diff options
| author | hathach <[email protected]> | 2026-07-24 16:20:13 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2026-07-24 16:20:13 +0700 |
| commit | d3eaeb06e04519b480637f6e7cb007a3de08d923 (patch) | |
| tree | 97373bb1cea44d7107905b8af1bbf134ce11a735 /hw | |
| parent | c962a0bf62f53d7bee42db7ff3bcd8f07ec23daa (diff) | |
imxrt: hold EVKB Ethernet PHY in reset while tracing, 50 MHz trace pin
Fresh bring-up pass on mimxrt1170_evkb: holding the 100M RTL8201 in reset
(ENET_RST_B = GPIO_LPSR_04) stops its RMII lines driving against the
shared trace pads and doubles the clean trace-pin rate to 50 MHz
(100 MHz CSTRACE root; 133 MHz root is marginal, stock 132 corrupts).
Validated 3x 8 s TinyUSB captures at 11.46M fetches. D1-D3 remain silent
in every configuration - the welded R1882-R1884 are electrically open;
reflow is the remaining step to width 4. Board notes gain JP4 (must be
shorted for an external probe on J58).
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/bsp/imxrt/family.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index e3ef6233c..1b1a1f1d8 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -131,6 +131,13 @@ static void trace_etm_init(void) { // breaks ETM trace - switch the pad to GPIO (MIMXRT1170-EVKB HUG 3.2) IOMUXC_SetPinMux(IOMUXC_GPIO_LPSR_10_GPIO12_IO10, 0U); + // Hold the 100M Ethernet PHY (RTL8201) in reset: its RMII lines are + // hardwired to the trace pads and drive against the stream at speed + // (ENET_RST_B = GPIO_LPSR_04) + IOMUXC_SetPinMux(IOMUXC_GPIO_LPSR_04_GPIO12_IO04, 0U); + GPIO12->GDIR |= (1U << 4); + GPIO12->DR &= ~(1U << 4); + // TRACE0-3 + TRACE_CLK on GPIO_DISP_B2_02..06, fast slew + high drive IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01, 0U); @@ -143,9 +150,11 @@ static void trace_etm_init(void) { IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03, IOMUXC_SW_PAD_CTL_PAD_DSE_MASK); IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK, IOMUXC_SW_PAD_CTL_PAD_DSE_MASK); - // 50 MHz CSTRACE root (OscRc400M/8) -> 25 MHz TRACE_CLK pin (= root/2) + // 100 MHz CSTRACE root (OscRc400M/4) -> 50 MHz TRACE_CLK pin (= root/2). + // With the PHY held in reset the CLK line is clean here; 133 MHz root + // (66 MHz pin) is marginal on this board, stock 132 MHz corrupts. CLOCK_SetRootClockMux(kCLOCK_Root_Cstrace, kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M); - CLOCK_SetRootClockDiv(kCLOCK_Root_Cstrace, 8); + CLOCK_SetRootClockDiv(kCLOCK_Root_Cstrace, 4); CLOCK_EnableClock(kCLOCK_Cstrace); // Enable the CM7 slave port on the platform trace funnel (E004_3000): the |