diff options
| author | Zixun LI <[email protected]> | 2026-03-12 10:55:18 +0100 |
|---|---|---|
| committer | Zixun LI <[email protected]> | 2026-03-12 10:55:18 +0100 |
| commit | e2884a1b88ce89b6e724e3d3b441b8ee1f83c06c (patch) | |
| tree | c322110908d4282ca7e37fe52dc9ce42be15b073 /hw | |
| parent | c06dc871d651ddaf756afdc59ed148c4b1af314d (diff) | |
| parent | ac61a5b176b44db503d8bcc287a622463b65e48e (diff) | |
Merge branch 'master' into ncm_restart
Diffstat (limited to 'hw')
215 files changed, 15501 insertions, 7416 deletions
diff --git a/hw/bsp/BoardPresets.json b/hw/bsp/BoardPresets.json index fabbeed93..ea6317771 100644 --- a/hw/bsp/BoardPresets.json +++ b/hw/bsp/BoardPresets.json @@ -91,6 +91,18 @@ "inherits": "default" }, { + "name": "at_start_f455", + "inherits": "default" + }, + { + "name": "at_start_f456", + "inherits": "default" + }, + { + "name": "at_start_f457", + "inherits": "default" + }, + { "name": "atsamd21_xpro", "inherits": "default" }, @@ -371,10 +383,6 @@ "inherits": "default" }, { - "name": "metro_m7_1011_sd", - "inherits": "default" - }, - { "name": "mimxrt1010_evk", "inherits": "default" }, @@ -1012,6 +1020,21 @@ "configurePreset": "at_start_f437" }, { + "name": "at_start_f455", + "description": "Build preset for the at_start_f455 board", + "configurePreset": "at_start_f455" + }, + { + "name": "at_start_f456", + "description": "Build preset for the at_start_f456 board", + "configurePreset": "at_start_f456" + }, + { + "name": "at_start_f457", + "description": "Build preset for the at_start_f457 board", + "configurePreset": "at_start_f457" + }, + { "name": "atsamd21_xpro", "description": "Build preset for the atsamd21_xpro board", "configurePreset": "atsamd21_xpro" @@ -1407,11 +1430,6 @@ "configurePreset": "metro_m7_1011" }, { - "name": "metro_m7_1011_sd", - "description": "Build preset for the metro_m7_1011_sd board", - "configurePreset": "metro_m7_1011_sd" - }, - { "name": "mimxrt1010_evk", "description": "Build preset for the mimxrt1010_evk board", "configurePreset": "mimxrt1010_evk" @@ -2288,6 +2306,45 @@ ] }, { + "name": "at_start_f455", + "steps": [ + { + "type": "configure", + "name": "at_start_f455" + }, + { + "type": "build", + "name": "at_start_f455" + } + ] + }, + { + "name": "at_start_f456", + "steps": [ + { + "type": "configure", + "name": "at_start_f456" + }, + { + "type": "build", + "name": "at_start_f456" + } + ] + }, + { + "name": "at_start_f457", + "steps": [ + { + "type": "configure", + "name": "at_start_f457" + }, + { + "type": "build", + "name": "at_start_f457" + } + ] + }, + { "name": "atsamd21_xpro", "steps": [ { @@ -3315,19 +3372,6 @@ ] }, { - "name": "metro_m7_1011_sd", - "steps": [ - { - "type": "configure", - "name": "metro_m7_1011_sd" - }, - { - "type": "build", - "name": "metro_m7_1011_sd" - } - ] - }, - { "name": "mimxrt1010_evk", "steps": [ { diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c index a6c2217fe..b7dbcbd98 100644 --- a/hw/bsp/at32f402_405/family.c +++ b/hw/bsp/at32f402_405/family.c @@ -258,7 +258,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) { system_ticks++; } - uint32_t board_millis(void) + uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f403a_407/family.c b/hw/bsp/at32f403a_407/family.c index dd9b85dc5..d4a7e446d 100644 --- a/hw/bsp/at32f403a_407/family.c +++ b/hw/bsp/at32f403a_407/family.c @@ -250,7 +250,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f413/family.c b/hw/bsp/at32f413/family.c index bdaed523c..adf29e097 100644 --- a/hw/bsp/at32f413/family.c +++ b/hw/bsp/at32f413/family.c @@ -250,7 +250,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f415/family.c b/hw/bsp/at32f415/family.c index 2fbd4c821..b592bf6c5 100644 --- a/hw/bsp/at32f415/family.c +++ b/hw/bsp/at32f415/family.c @@ -246,7 +246,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f423/family.c b/hw/bsp/at32f423/family.c index f30c6a83f..71cb559dc 100644 --- a/hw/bsp/at32f423/family.c +++ b/hw/bsp/at32f423/family.c @@ -250,7 +250,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f425/family.c b/hw/bsp/at32f425/family.c index 4ff4c8d6a..7f443509e 100644 --- a/hw/bsp/at32f425/family.c +++ b/hw/bsp/at32f425/family.c @@ -254,7 +254,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c index 01dd429f8..6c6bc4d72 100644 --- a/hw/bsp/at32f435_437/family.c +++ b/hw/bsp/at32f435_437/family.c @@ -320,7 +320,7 @@ volatile uint32_t system_ticks = 0; void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } void SVC_Handler(void) { diff --git a/hw/bsp/at32f45x/family.c b/hw/bsp/at32f45x/family.c index 0593e5115..fa0c1139f 100644 --- a/hw/bsp/at32f45x/family.c +++ b/hw/bsp/at32f45x/family.c @@ -227,7 +227,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 483d9dc28..71c209950 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -161,10 +161,6 @@ void board_putchar(int c) { (void) sys_write(0, (const char*)&c, 1); } -uint32_t tusb_time_millis_api(void) { - return board_millis(); -} - //-------------------------------------------------------------------- // FreeRTOS hooks //-------------------------------------------------------------------- @@ -255,3 +251,53 @@ void vApplicationSetupTimerInterrupt(void) { #endif #endif + +//-------------------------------------------------------------------- +// ThreadX hooks for ARM Cortex-M +//-------------------------------------------------------------------- +#if CFG_TUSB_OS == OPT_OS_THREADX && defined(__ARM_ARCH) + +#include "tx_api.h" +#include "tx_initialize.h" + +// Newlib linker symbol: end of statically allocated RAM (start of heap) +extern ULONG _end; + +// CMSIS standard variable for system clock frequency +extern uint32_t SystemCoreClock; + +// Cortex-M SysTick registers (fixed addresses on all Cortex-M) +#define _TX_SYST_CSR (*((volatile uint32_t *)0xE000E010U)) +#define _TX_SYST_RVR (*((volatile uint32_t *)0xE000E014U)) +#define _TX_SYST_CVR (*((volatile uint32_t *)0xE000E018U)) +// SCB->SHP[10] = PendSV priority, [11] = SysTick priority (byte access at SCB base + 0xD22) +#define _TX_SCB_SHPR3 (*((volatile uint32_t *)0xE000ED20U)) + +VOID _tx_initialize_low_level(VOID) { + // Set the first available memory address for tx_application_define + _tx_initialize_unused_memory = (VOID *)(&_end); + + // Configure SysTick for ThreadX tick rate: enable with processor clock + interrupt + _TX_SYST_RVR = (SystemCoreClock / TX_TIMER_TICKS_PER_SECOND) - 1u; + _TX_SYST_CVR = 0u; + _TX_SYST_CSR = 0x07u; // CLKSOURCE=1, TICKINT=1, ENABLE=1 + + // SHPR3 bits[31:24] = SysTick priority, bits[23:16] = PendSV priority + // PendSV must be lowest priority (0xFF). SysTick must be higher than PendSV (0x40) + // so SysTick can preempt the PendSV scheduler idle loop (__tx_ts_wait) to tick the timer. + _TX_SCB_SHPR3 = (_TX_SCB_SHPR3 & 0x0000FFFFU) | 0x40FF0000U; +} + +// Weak callback for board-specific SysTick work (e.g. HAL_IncTick on STM32) +void osal_threadx_tick_cb(void); +TU_ATTR_WEAK void osal_threadx_tick_cb(void) { } + +// SysTick drives the ThreadX timer tick +extern void _tx_timer_interrupt(void); +void SysTick_Handler(void); +void SysTick_Handler(void) { + osal_threadx_tick_cb(); + _tx_timer_interrupt(); +} + +#endif diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h index 606ac484f..4487871eb 100644 --- a/hw/bsp/board_api.h +++ b/hw/bsp/board_api.h @@ -98,43 +98,6 @@ int board_uart_read(uint8_t *buf, int len); // Send characters to UART. Return number of sent bytes int board_uart_write(void const *buf, int len); -#if CFG_TUSB_OS == OPT_OS_NONE -// Get current milliseconds, must be implemented when no RTOS is used -uint32_t board_millis(void); - -#elif CFG_TUSB_OS == OPT_OS_FREERTOS -static inline uint32_t board_millis(void) { - return ( ( ((uint64_t) xTaskGetTickCount()) * 1000) / configTICK_RATE_HZ ); -} - -#elif CFG_TUSB_OS == OPT_OS_MYNEWT -static inline uint32_t board_millis(void) { - return os_time_ticks_to_ms32( os_time_get() ); -} - -#elif CFG_TUSB_OS == OPT_OS_PICO -#include "pico/time.h" -static inline uint32_t board_millis(void) { - return to_ms_since_boot(get_absolute_time()); -} - -#elif CFG_TUSB_OS == OPT_OS_RTTHREAD -static inline uint32_t board_millis(void) { - return (((uint64_t)rt_tick_get()) * 1000 / RT_TICK_PER_SECOND); -} - -#elif CFG_TUSB_OS == OPT_OS_CUSTOM -// Implement your own board_millis() in any of .c file -uint32_t board_millis(void); - -#elif CFG_TUSB_OS == OPT_OS_ZEPHYR -static inline uint32_t board_millis(void) { - return k_uptime_get_32(); -} -#else - #error "board_millis() is not implemented for this OS" -#endif - //--------------------------------------------------------------------+ // Helper functions //--------------------------------------------------------------------+ @@ -175,8 +138,8 @@ static inline size_t board_usb_get_serial(uint16_t desc_str1[], size_t max_chars // TODO remove static inline void board_delay(uint32_t ms) { - uint32_t start_ms = board_millis(); - while ( board_millis() - start_ms < ms ) { + uint32_t start_ms = tusb_time_millis_api(); + while ( tusb_time_millis_api() - start_ms < ms ) { // take chance to run usb background #if CFG_TUD_ENABLED tud_task(); diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c index f8f3b0b70..399397bb4 100644 --- a/hw/bsp/broadcom_32bit/family.c +++ b/hw/bsp/broadcom_32bit/family.c @@ -146,7 +146,7 @@ void TIMER_1_IRQHandler(void) { SYSTMR->CS_b.M1 = 1; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c index f8f3b0b70..399397bb4 100644 --- a/hw/bsp/broadcom_64bit/family.c +++ b/hw/bsp/broadcom_64bit/family.c @@ -146,7 +146,7 @@ void TIMER_1_IRQHandler(void) { SYSTMR->CS_b.M1 = 1; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c index 15ff4b8ee..ff24cfe89 100644 --- a/hw/bsp/brtmm90x/family.c +++ b/hw/bsp/brtmm90x/family.c @@ -234,7 +234,7 @@ int board_uart_write(void const *buf, int len) } // Get current milliseconds -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { uint32_t safe_ms; diff --git a/hw/bsp/ch32f20x/family.c b/hw/bsp/ch32f20x/family.c index 7eae62fa4..dd84b7c77 100644 --- a/hw/bsp/ch32f20x/family.c +++ b/hw/bsp/ch32f20x/family.c @@ -101,7 +101,7 @@ void SysTick_Handler(void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/ch32v10x/family.c b/hw/bsp/ch32v10x/family.c index dfc041462..344dcaf0b 100644 --- a/hw/bsp/ch32v10x/family.c +++ b/hw/bsp/ch32v10x/family.c @@ -61,7 +61,7 @@ static uint32_t SysTick_Config(uint32_t ticks) { return 0; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c index 690acee1e..4c22450f9 100644 --- a/hw/bsp/ch32v20x/family.c +++ b/hw/bsp/ch32v20x/family.c @@ -85,7 +85,7 @@ static uint32_t SysTick_Config(uint32_t ticks) { return 0; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/ch32v30x/family.c b/hw/bsp/ch32v30x/family.c index c694f1a08..6295f7723 100644 --- a/hw/bsp/ch32v30x/family.c +++ b/hw/bsp/ch32v30x/family.c @@ -144,7 +144,7 @@ __attribute__((interrupt)) void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/cxd56/family.c b/hw/bsp/cxd56/family.c index a8e2fd52b..fd92bb9d9 100644 --- a/hw/bsp/cxd56/family.c +++ b/hw/bsp/cxd56/family.c @@ -96,7 +96,7 @@ int board_uart_write(void const *buf, int len) } // Get current milliseconds -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { struct timespec tp; diff --git a/hw/bsp/da1469x/family.c b/hw/bsp/da1469x/family.c index a64ffce67..a4f7f2e8d 100644 --- a/hw/bsp/da1469x/family.c +++ b/hw/bsp/da1469x/family.c @@ -140,7 +140,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/efm32/family.c b/hw/bsp/efm32/family.c index 39166bc4d..d318e20d6 100644 --- a/hw/bsp/efm32/family.c +++ b/hw/bsp/efm32/family.c @@ -689,7 +689,7 @@ void SysTick_Handler(void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake index fe4db4fc1..455ca90a1 100644 --- a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake @@ -1,2 +1,3 @@ # Apply board specific content here set(IDF_TARGET "esp32p4") +list(APPEND SDKCONFIG_DEFAULTS "${CMAKE_CURRENT_LIST_DIR}/sdkconfig.defaults") diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/sdkconfig.defaults b/hw/bsp/espressif/boards/espressif_p4_function_ev/sdkconfig.defaults new file mode 100644 index 000000000..6b0a548f6 --- /dev/null +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y +CONFIG_ESP32P4_REV_MIN_1=y diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index a837417f4..04d8a4001 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -50,7 +50,7 @@ static void max3421_init(void); #endif #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32H4, OPT_MCU_ESP32P4) -static bool usb_init(void); +static bool usb_init(uint8_t rhport, bool is_host); #endif //--------------------------------------------------------------------+ @@ -90,8 +90,14 @@ void board_init(void) { gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT); gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY); -#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4) - usb_init(); +#if CONFIG_USB_OTG_SUPPORTED + #if CFG_TUD_ENABLED + usb_init(BOARD_TUD_RHPORT, false); + #endif + + #if CFG_TUH_ENABLED + usb_init(BOARD_TUH_RHPORT, true); + #endif #endif #ifdef HIL_TS3USB30_MODE_PIN @@ -179,24 +185,30 @@ void board_reset_to_bootloader(void) { static usb_phy_handle_t phy_hdl; -bool usb_init(void) { +bool usb_init(uint8_t rhport, bool is_host) { + (void) rhport; // Configure USB PHY usb_phy_config_t phy_conf = { .controller = USB_PHY_CTRL_OTG, +#if defined(CONFIG_SOC_USB_UTMI_PHY_NUM) && CONFIG_SOC_USB_UTMI_PHY_NUM > 0 + .target = USB_PHY_TARGET_UTMI, +#else .target = USB_PHY_TARGET_INT, +#endif // maybe we can use USB_OTG_MODE_DEFAULT and switch using dwc2 driver -#if CFG_TUD_ENABLED - .otg_mode = USB_OTG_MODE_DEVICE, -#elif CFG_TUH_ENABLED - .otg_mode = USB_OTG_MODE_HOST, -#endif + .otg_mode = is_host ? USB_OTG_MODE_HOST : USB_OTG_MODE_DEVICE, // https://github.com/hathach/tinyusb/issues/2943#issuecomment-2601888322 // Set speed to undefined (auto-detect) to avoid timinng/racing issue with S3 with host such as macOS .otg_speed = USB_PHY_SPEED_UNDEFINED, }; - usb_new_phy(&phy_conf, &phy_hdl); + esp_err_t const err = usb_new_phy(&phy_conf, &phy_hdl); + if (err != ESP_OK) { + printf("usb_new_phy failed: %s\r\n", esp_err_to_name(err)); + phy_hdl = NULL; + return false; + } return true; } @@ -351,5 +363,4 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx ESP_ERROR_CHECK(spi_device_transmit(max3421_spi, &xact)); return true; } - #endif diff --git a/hw/bsp/f1c100s/family.c b/hw/bsp/f1c100s/family.c index 9e864363f..1e71333d4 100644 --- a/hw/bsp/f1c100s/family.c +++ b/hw/bsp/f1c100s/family.c @@ -79,7 +79,7 @@ int board_uart_write(void const* buf, int len) { #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 699afda92..5d21b4f79 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -105,6 +105,12 @@ set(WARN_FLAGS_GNU ) set(WARN_FLAGS_Clang ${WARN_FLAGS_GNU}) +set(WARN_FLAGS_IAR + --warnings_are_errors + --diag_suppress=Pa089 + --diag_suppress=Pe236 + ) + # Optimization if (NOT DEFINED CMAKE_BUILD_TYPE OR CMAKE_BUILD_TYPE STREQUAL "") set(CMAKE_BUILD_TYPE MinSizeRel CACHE STRING "Build type" FORCE) @@ -238,7 +244,7 @@ function(family_add_bloaty TARGET) COMMAND ${BLOATY_EXE} ${OPTION_LIST} $<TARGET_FILE:${TARGET}> VERBATIM) - set_property(TARGET ${TARGET}-bloaty PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-bloaty PROPERTY FOLDER ${TARGET}-group) # post build # add_custom_command(TARGET ${TARGET} POST_BUILD # COMMAND ${BLOATY_EXE} --csv ${OPTION_LIST} $<TARGET_FILE:${TARGET}> > ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}_bloaty.csv @@ -259,7 +265,7 @@ function(family_add_linkermap TARGET) VERBATIM ) - set_property(TARGET ${TARGET}-linkermap PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-linkermap PROPERTY FOLDER ${TARGET}-group) # post build add_custom_command(TARGET ${TARGET} POST_BUILD @@ -339,7 +345,7 @@ echo \"$MEMBROWSE_CMD\"") COMMAND ${CMAKE_COMMAND} -E env MEMBROWSE_UPLOAD=0 bash -lc "${MEMBROWSE_PREPARE_CMD}; eval \"$MEMBROWSE_CMD\"" VERBATIM ) - set_property(TARGET ${TARGET}-membrowse PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-membrowse PROPERTY FOLDER ${TARGET}-group) add_custom_target(${TARGET}-membrowse-upload COMMAND ${CMAKE_COMMAND} -E env MEMBROWSE_UPLOAD=1 bash -lc "${MEMBROWSE_PREPARE_CMD}; eval \"$MEMBROWSE_CMD\"" @@ -351,7 +357,7 @@ echo \"$MEMBROWSE_CMD\"") endif () add_dependencies(examples-membrowse-upload ${TARGET}-membrowse-upload) - set_property(TARGET ${TARGET}-membrowse-upload PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-membrowse-upload PROPERTY FOLDER ${TARGET}-group) endif () endfunction() @@ -380,6 +386,26 @@ function(family_add_rtos TARGET RTOS) target_link_libraries(${TARGET} PUBLIC freertos_kernel) target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_FREERTOS) + elseif (RTOS STREQUAL "threadx") + if (NOT TARGET threadx) + # Derive THREADX_ARCH from CMAKE_SYSTEM_CPU if not explicitly set + if (NOT DEFINED THREADX_ARCH) + string(REPLACE "-" "_" THREADX_ARCH ${CMAKE_SYSTEM_CPU}) + endif () + # Derive THREADX_TOOLCHAIN from TOOLCHAIN if not explicitly set + if (NOT DEFINED THREADX_TOOLCHAIN) + if (TOOLCHAIN STREQUAL "iar") + set(THREADX_TOOLCHAIN "iar") + elseif (TOOLCHAIN STREQUAL "clang") + set(THREADX_TOOLCHAIN "ac6") + else () + set(THREADX_TOOLCHAIN "gnu") + endif () + endif () + add_subdirectory(${TOP}/lib/threadx ${CMAKE_BINARY_DIR}/lib/threadx) + endif () + target_link_libraries(${TARGET} PUBLIC threadx) + target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_THREADX) elseif (RTOS STREQUAL "zephyr") target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_ZEPHYR) target_include_directories(${TARGET} PUBLIC ${ZEPHYR_BASE}/include) @@ -447,6 +473,7 @@ function(family_configure_common TARGET RTOS) target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") endif () elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_compile_options(${TARGET} PRIVATE $<$<OR:$<COMPILE_LANGUAGE:C>,$<COMPILE_LANGUAGE:CXX>>:${WARN_FLAGS_IAR}>) target_link_options(${TARGET} PUBLIC "LINKER:--map=$<TARGET_FILE:${TARGET}>.map") if (IAR_CSTAT) @@ -602,7 +629,7 @@ exit" VERBATIM ) - set_property(TARGET ${NAME_TARGET}-jlink PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${NAME_TARGET}-jlink PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -617,7 +644,7 @@ function(family_flash_stlink TARGET) COMMAND ${STM32_PROGRAMMER_CLI} --connect port=swd --write $<TARGET_FILE:${TARGET}> --go ) - set_property(TARGET ${TARGET}-stlink PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-stlink PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -632,7 +659,7 @@ function(family_flash_stflash TARGET) COMMAND ${ST_FLASH} write $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin 0x8000000 ) - set_property(TARGET ${TARGET}-stflash PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-stflash PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -660,7 +687,7 @@ function(family_flash_openocd TARGET) VERBATIM ) - set_property(TARGET ${TARGET}-openocd PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-openocd PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -723,7 +750,7 @@ function(family_flash_wlink_rs TARGET) COMMAND ${WLINK_RS} flash $<TARGET_FILE:${TARGET}> ) - set_property(TARGET ${TARGET}-wlink-rs PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-wlink-rs PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -738,7 +765,7 @@ function(family_flash_pyocd TARGET) COMMAND ${PYOCD} flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}> ) - set_property(TARGET ${TARGET}-pyocd PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-pyocd PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -748,7 +775,7 @@ function(family_flash_uf2 TARGET FAMILY_ID) DEPENDS ${TARGET} COMMAND python ${UF2CONV_PY} -f ${FAMILY_ID} --deploy $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.uf2 ) - set_property(TARGET ${TARGET}-uf2 PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-uf2 PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -764,7 +791,7 @@ function(family_flash_teensy TARGET) COMMAND ${TEENSY_CLI} --mcu=${TEENSY_MCU} -w -s $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex ) - set_property(TARGET ${TARGET}-teensy PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-teensy PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -784,7 +811,7 @@ function(family_flash_nxplink TARGET) COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}> ) - set_property(TARGET ${TARGET}-nxplink PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-nxplink PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -799,7 +826,7 @@ function(family_flash_dfu_util TARGET OPTION) VERBATIM ) - set_property(TARGET ${TARGET}-dfu-util PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-dfu-util PROPERTY FOLDER ${TARGET}-group) endfunction() function(family_flash_msp430flasher TARGET) @@ -816,7 +843,7 @@ function(family_flash_msp430flasher TARGET) ${MSP430FLASHER} -w $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex -z [VCC] ) - set_property(TARGET ${TARGET}-msp430flasher PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-msp430flasher PROPERTY FOLDER ${TARGET}-group) endfunction() function(family_flash_uniflash TARGET) @@ -832,7 +859,7 @@ function(family_flash_uniflash TARGET) VERBATIM ) - set_property(TARGET ${TARGET}-uniflash PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-uniflash PROPERTY FOLDER ${TARGET}-group) endfunction() #---------------------------------- diff --git a/hw/bsp/fomu/family.c b/hw/bsp/fomu/family.c index 9d7977bea..cf04a1f6f 100644 --- a/hw/bsp/fomu/family.c +++ b/hw/bsp/fomu/family.c @@ -117,7 +117,7 @@ int board_uart_write(void const * buf, int len) } #if CFG_TUSB_OS == OPT_OS_NONE -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c index 9d15755fc..4c1099317 100644 --- a/hw/bsp/gd32vf103/family.c +++ b/hw/bsp/gd32vf103/family.c @@ -179,7 +179,7 @@ void eclic_mtip_handler(void) { system_ticks++; SysTick_Reload(TIMER_TICKS); } -uint32_t board_millis(void) { return system_ticks; } +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif #ifdef USE_FULL_ASSERT diff --git a/hw/bsp/hpmicro/family.c b/hw/bsp/hpmicro/family.c index ffec2523a..a80a8d913 100644 --- a/hw/bsp/hpmicro/family.c +++ b/hw/bsp/hpmicro/family.c @@ -108,7 +108,7 @@ int board_uart_write(void const *buf, int len) { #if CFG_TUSB_OS == OPT_OS_NONE // Get current milliseconds, must be implemented when no RTOS is used -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return (hpm_csr_get_core_cycle() / clock_get_core_clock_ticks_per_ms()); } diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake index 99681ab12..63b2a120a 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1010) set(MCU_VARIANT MIMXRT1011) set(JLINK_DEVICE MIMXRT1011xxx5A) diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.mk b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk index b845194c2..229b5c18c 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board.mk +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY +MCU_FAMILY = RT1010 MCU_VARIANT = MIMXRT1011 # LD file with uf2 diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/ozone/metro_m7_1011_sd.jdebug b/hw/bsp/imxrt/boards/metro_m7_1011/ozone/metro_m7_1011.jdebug index 90f9b77e5..90f9b77e5 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/ozone/metro_m7_1011_sd.jdebug +++ b/hw/bsp/imxrt/boards/metro_m7_1011/ozone/metro_m7_1011.jdebug diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.cmake b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.cmake deleted file mode 100644 index 99681ab12..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.cmake +++ /dev/null @@ -1,15 +0,0 @@ -set(MCU_VARIANT MIMXRT1011) - -set(JLINK_DEVICE MIMXRT1011xxx5A) -set(PYOCD_TARGET mimxrt1010) -set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010) - -function(update_board TARGET) - target_sources(${TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c - ) - target_compile_definitions(${TARGET} PUBLIC - CPU_MIMXRT1011DAE5A - CFG_EXAMPLE_VIDEO_READONLY - ) -endfunction() diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h deleted file mode 100644 index 8f100284a..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - name: Adafruit Metro M7 1011 SD - url: https://www.adafruit.com/product/5600 -*/ - -#ifndef BOARD_METRO_M7_1011_SD_H_ -#define BOARD_METRO_M7_1011_SD_H_ - -// required since iMXRT MCUX-SDK include this file for board size -#define BOARD_FLASH_SIZE (8*1024*1024) - -// LED: IOMUXC_GPIO_03_GPIOMUX_IO03 -#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL -#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL -#define LED_STATE_ON 1 - -// D8 as button: GPIO8 -#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_PERIPHERAL -#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_CHANNEL -#define BUTTON_STATE_ACTIVE 0 - -// UART: IOMUXC_GPIO_09_LPUART1_RXD, IOMUXC_GPIO_10_LPUART1_TXD -#define UART_PORT LPUART1 -#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT - -static inline void BOARD_ConfigMPU(void) { -} - -#endif diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.mk b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.mk deleted file mode 100644 index b845194c2..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.mk +++ /dev/null @@ -1,17 +0,0 @@ -CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY -MCU_VARIANT = MIMXRT1011 - -# LD file with uf2 -LD_FILE = $(BOARD_PATH)/$(BOARD).ld - -# For flash-jlink target -JLINK_DEVICE = MIMXRT1011xxx5A - -# For flash-pyocd target -PYOCD_TARGET = mimxrt1010 - -# flash using pyocd -flash: flash-uf2 -flash-uf2: $(BUILD)/$(PROJECT).uf2 - @echo copying $< - @$(CP) $< /media/$(USER)/METROM7BOOT diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.c b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.c deleted file mode 100644 index 1b28b668a..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * How to setup clock using clock driver functions: - * - * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. - * - * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. - * - * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. - * - * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. - * - * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. - * - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v11.0 -processor: MIMXRT1011xxxxx -package_id: MIMXRT1011DAE5A -mcu_data: ksdk2_0 -processor_version: 13.0.2 -board: MIMXRT1010-EVK - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "clock_config.h" -#include "fsl_iomuxc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: ADC_ALT_CLK.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz} -- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -- {id: USBPHY_CLK.outFreq, value: 480 MHz} -settings: -- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true} -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} -- {id: CCM.IPG_PODF.scale, value: '4'} -- {id: CCM.LPSPI_PODF.scale, value: '5'} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK} -- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} -- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} -- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} -- {id: CCM_ANALOG.PLL2.denom, value: '1'} -- {id: CCM_ANALOG.PLL2.num, value: '0'} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} -- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} -- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -sources: -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = - { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = - { - .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { - } - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Xbar1); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 0); - CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0); -#endif - /* Disable ADC_ACLK_EN clock gate. */ - CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK; - /* Set ADC_ACLK_PODF. */ - CLOCK_SetDiv(kCLOCK_AdcDiv, 11); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 0); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); -#endif - /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */ - /* Set Pll3 SW clock source to use the USB1 PLL output. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Set safe value of the AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 1); - /* Set periph clock2 clock source to use the PLL3_SW_CLK. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.h deleted file mode 100644 index 119fd94bd..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.h +++ /dev/null @@ -1,97 +0,0 @@ -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL - -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.c b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.c deleted file mode 100644 index aa38e02dc..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.c +++ /dev/null @@ -1,108 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Pins v13.1 -processor: MIMXRT1011xxxxx -package_id: MIMXRT1011DAE5A -mcu_data: ksdk2_0 -processor_version: 13.0.2 -board: MIMXRT1010-EVK -external_user_signals: {} -pin_labels: -- {pin_num: '1', pin_signal: GPIO_11, label: GPIO_11, identifier: GPIO_11} -- {pin_num: '70', pin_signal: GPIO_SD_05} -- {pin_num: '10', pin_signal: GPIO_03, label: 'SAI1_RXD0/U10[16]', identifier: LED;USER_LED} -- {pin_num: '4', pin_signal: GPIO_08, label: 'SAI1_MCLK/U10[11]', identifier: USER_BUTTON} -- {pin_num: '79', pin_signal: GPIO_13, label: 'USB_OTG1_ID/J9[4]/Q9[2]', identifier: TRACE1} -power_domains: {NVCC_GPIO: '3.3'} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -#include "fsl_common.h" -#include "fsl_iomuxc.h" -#include "fsl_gpio.h" -#include "pin_mux.h" - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitBootPins - * Description : Calls initialization functions. - * - * END ****************************************************************************************************************/ -void BOARD_InitBootPins(void) { - BOARD_InitPins(); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPins: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09} - - {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10} - - {pin_num: '10', peripheral: GPIO1, signal: 'gpiomux_io, 03', pin_signal: GPIO_03, identifier: USER_LED, direction: OUTPUT} - - {pin_num: '79', peripheral: ARM, signal: 'TRACE, 1', pin_signal: GPIO_13, speed: MHZ_200} - - {pin_num: '80', peripheral: ARM, signal: 'TRACE, 2', pin_signal: GPIO_12, speed: MHZ_200} - - {pin_num: '58', peripheral: ARM, signal: arm_trace_clk, pin_signal: GPIO_AD_02, speed: MHZ_200} - - {pin_num: '1', peripheral: ARM, signal: 'TRACE, 3', pin_signal: GPIO_11, speed: MHZ_200} - - {pin_num: '60', peripheral: ARM, signal: 'TRACE, 0', pin_signal: GPIO_AD_00, speed: MHZ_200} - - {pin_num: '4', peripheral: GPIO1, signal: 'gpiomux_io, 08', pin_signal: GPIO_08, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_100K_Ohm} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - /* GPIO configuration of USER_LED on GPIO_03 (pin 10) */ - gpio_pin_config_t USER_LED_config = { - .direction = kGPIO_DigitalOutput, - .outputLogic = 0U, - .interruptMode = kGPIO_NoIntmode - }; - /* Initialize GPIO functionality on GPIO_03 (pin 10) */ - GPIO_PinInit(GPIO1, 3U, &USER_LED_config); - - /* GPIO configuration of USER_BUTTON on GPIO_08 (pin 4) */ - gpio_pin_config_t USER_BUTTON_config = { - .direction = kGPIO_DigitalInput, - .outputLogic = 0U, - .interruptMode = kGPIO_NoIntmode - }; - /* Initialize GPIO functionality on GPIO_08 (pin 4) */ - GPIO_PinInit(GPIO1, 8U, &USER_BUTTON_config); - - IOMUXC_SetPinMux(IOMUXC_GPIO_03_GPIOMUX_IO03, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_08_GPIOMUX_IO08, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_11_ARM_TRACE3, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_12_ARM_TRACE2, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_13_ARM_TRACE1, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0U); - IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & - (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK))) - | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U) - ); - IOMUXC_SetPinConfig(IOMUXC_GPIO_08_GPIOMUX_IO08, 0xB0A0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_11_ARM_TRACE3, 0x10E0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_12_ARM_TRACE2, 0x10E0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_13_ARM_TRACE1, 0x10E0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0x10E0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0x10E0U); -} - -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.h deleted file mode 100644 index 42c256745..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.h +++ /dev/null @@ -1,110 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _PIN_MUX_H_ -#define _PIN_MUX_H_ - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/*! @brief Direction type */ -typedef enum _pin_mux_direction -{ - kPIN_MUX_DirectionInput = 0U, /* Input direction */ - kPIN_MUX_DirectionOutput = 1U, /* Output direction */ - kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ -} pin_mux_direction_t; - -/*! - * @addtogroup pin_mux - * @{ - */ - -/*********************************************************************************************************************** - * API - **********************************************************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Calls initialization functions. - * - */ -void BOARD_InitBootPins(void); - -#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x08U /*!< Select GPIO1 or GPIO2: affected bits mask */ - -/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */ -/* Routed pin properties */ -#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_UART1_RXD_SIGNAL RXD /*!< Signal name */ - -/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */ -/* Routed pin properties */ -#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_UART1_TXD_SIGNAL TXD /*!< Signal name */ - -/* GPIO_03 (number 10), SAI1_RXD0/U10[16] */ -/* Routed pin properties */ -#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITPINS_USER_LED_SIGNAL gpiomux_io /*!< Signal name */ -#define BOARD_INITPINS_USER_LED_CHANNEL 3U /*!< Signal channel */ - -/* GPIO_13 (number 79), USB_OTG1_ID/J9[4]/Q9[2] */ -/* Routed pin properties */ -#define BOARD_INITPINS_TRACE1_PERIPHERAL ARM /*!< Peripheral name */ -#define BOARD_INITPINS_TRACE1_SIGNAL TRACE /*!< Signal name */ -#define BOARD_INITPINS_TRACE1_CHANNEL 1U /*!< Signal channel */ - -/* GPIO_12 (number 80), USB_OTG1_OC/U7[A2] */ -/* Routed pin properties */ -#define BOARD_INITPINS_USB_OTG1_OC_PERIPHERAL ARM /*!< Peripheral name */ -#define BOARD_INITPINS_USB_OTG1_OC_SIGNAL TRACE /*!< Signal name */ -#define BOARD_INITPINS_USB_OTG1_OC_CHANNEL 2U /*!< Signal channel */ - -/* GPIO_AD_02 (number 58), ADC12_2/J26[12]/J56[16] */ -/* Routed pin properties */ -#define BOARD_INITPINS_ADC12_2_PERIPHERAL ARM /*!< Peripheral name */ -#define BOARD_INITPINS_ADC12_2_SIGNAL arm_trace_clk /*!< Signal name */ - -/* GPIO_11 (number 1), GPIO_11 */ -/* Routed pin properties */ -#define BOARD_INITPINS_GPIO_11_PERIPHERAL ARM /*!< Peripheral name */ -#define BOARD_INITPINS_GPIO_11_SIGNAL TRACE /*!< Signal name */ -#define BOARD_INITPINS_GPIO_11_CHANNEL 3U /*!< Signal channel */ - -/* GPIO_AD_00 (number 60), USB_OTG1_PWR */ -/* Routed pin properties */ -#define BOARD_INITPINS_USB_OTG1_PWR_PERIPHERAL ARM /*!< Peripheral name */ -#define BOARD_INITPINS_USB_OTG1_PWR_SIGNAL TRACE /*!< Signal name */ -#define BOARD_INITPINS_USB_OTG1_PWR_CHANNEL 0U /*!< Signal channel */ - -/* GPIO_08 (number 4), SAI1_MCLK/U10[11] */ -/* Routed pin properties */ -#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpiomux_io /*!< Signal name */ -#define BOARD_INITPINS_USER_BUTTON_CHANNEL 8U /*!< Signal channel */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitPins(void); - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif /* _PIN_MUX_H_ */ - -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.c b/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.c deleted file mode 100644 index 752a65629..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "evkmimxrt1010_flexspi_nor_config.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_board" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -const flexspi_nor_config_t qspiflash_config = { - .memConfig = - { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = 16u * 1024u * 1024u, - .lookupTable = - { - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 24), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 64u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.h deleted file mode 100644 index bb5a64448..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ -#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ - -#include <stdint.h> -#include <stdbool.h> -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* FLEXSPI memory config block related definitions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related definitions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_120MHz = 7, - kFlexSpiSerialClk_133MHz = 8, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.ld b/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.ld deleted file mode 100644 index 960fc6891..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.ld +++ /dev/null @@ -1,270 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1011CAE4A -** MIMXRT1011DAE5A -** -** Compiler: GNU C Compiler -** Reference manual: IMXRT1010RM Rev.0, 09/2019 -** Version: rev. 1.0, 2019-08-01 -** Build: b210709 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: [email protected] -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; -VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0; - -/* Specify the memory areas */ -MEMORY -{ - m_flash_config (RX) : ORIGIN = 0x60000400, LENGTH = 0x00000C00 - m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 - - m_interrupts (RX) : ORIGIN = 0x6000C000, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = 0x6000C400, LENGTH = (8*1024*1024 - 0xC400) - m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00008000 - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000 - m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00010000 -} - -/* Define output sections */ -SECTIONS -{ - __NCACHE_REGION_START = ORIGIN(m_data2); - __NCACHE_REGION_SIZE = 0; - - .flash_config : - { - . = ALIGN(4); - __FLASH_BASE = .; - KEEP(* (.boot_hdr.conf)) /* flash config section */ - . = ALIGN(4); - } > m_flash_config - - ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config); - - .ivt : AT(ivt_begin) - { - . = ALIGN(4); - KEEP(* (.boot_hdr.ivt)) /* ivt section */ - KEEP(* (.boot_hdr.boot_data)) /* boot section */ - KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ - . = ALIGN(4); - } > m_ivt - - /* The startup code goes first into internal RAM */ - .interrupts : - { - __VECTOR_TABLE = .; - __Vectors = .; - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal RAM */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .interrupts_ram : - { - . = ALIGN(4); - __VECTOR_RAM__ = .; - __interrupts_ram_start__ = .; /* Create a global symbol at data start */ - *(.m_interrupts_ram) /* This is a user defined section */ - . += VECTOR_RAM_SIZE; - . = ALIGN(4); - __interrupts_ram_end__ = .; /* Define a global symbol at data end */ - } > m_data - - __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); - __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(m_usb_dma_init_data) - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - *(DataQuickAccess) /* quick access data section */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */ - - .ram_function : AT(__ram_function_flash_start) - { - . = ALIGN(32); - __ram_function_start__ = .; - *(CodeQuickAccess) - . = ALIGN(128); - __ram_function_end__ = .; - } > m_qacode - - __NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); - .ncache.init : AT(__NDATA_ROM) - { - __noncachedata_start__ = .; /* create a global symbol at ncache data start */ - *(NonCacheable.init) - . = ALIGN(4); - __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_data - . = __noncachedata_init_end__; - .ncache : - { - *(NonCacheable) - . = ALIGN(4); - __noncachedata_end__ = .; /* define a global symbol at ncache data end */ - } > m_data - - __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(m_usb_dma_noninit_data) - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex b/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex deleted file mode 100644 index 7aab59a68..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex +++ /dev/null @@ -1,431 +0,0 @@ -<?xml version="1.0" encoding= "UTF-8" ?> -<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> - <common> - <processor>MIMXRT1011xxxxx</processor> - <package>MIMXRT1011DAE5A</package> - <board>MIMXRT1010-EVK</board> - <board_revision>A</board_revision> - <mcu_data>ksdk2_0</mcu_data> - <cores selected="core0"> - <core name="Cortex-M7F" id="core0" description="M7 core"/> - </cores> - <description></description> - </common> - <preferences> - <validate_boot_init_only>true</validate_boot_init_only> - <generate_extended_information>false</generate_extended_information> - <generate_code_modified_registers_only>false</generate_code_modified_registers_only> - <update_include_paths>true</update_include_paths> - <generate_registers_defines>false</generate_registers_defines> - </preferences> - <tools> - <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> - <generated_project_files> - <file path="board/pin_mux.c" update_enabled="true"/> - <file path="board/pin_mux.h" update_enabled="true"/> - </generated_project_files> - <pins_profile> - <processor_version>13.0.2</processor_version> - <pin_labels> - <pin_label pin_num="1" pin_signal="GPIO_11" label="GPIO_11" identifier="GPIO_11"/> - <pin_label pin_num="70" pin_signal="GPIO_SD_05" label=""/> - <pin_label pin_num="10" pin_signal="GPIO_03" label="SAI1_RXD0/U10[16]" identifier="LED;USER_LED"/> - <pin_label pin_num="4" pin_signal="GPIO_08" label="SAI1_MCLK/U10[11]" identifier="USER_BUTTON"/> - <pin_label pin_num="79" pin_signal="GPIO_13" label="USB_OTG1_ID/J9[4]/Q9[2]" identifier="TRACE1"/> - </pin_labels> - <external_user_signals> - <properties/> - </external_user_signals> - <power_domains> - <power_domain name="NVCC_GPIO" value="3.3"/> - </power_domains> - </pins_profile> - <functions_list> - <function name="BOARD_InitPins"> - <description>Configures pin routing and optionally pin electrical features.</description> - <options> - <callFromInitBoot>true</callFromInitBoot> - <coreID>core0</coreID> - <enableClock>true</enableClock> - </options> - <dependencies> - <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> - <feature name="initialized" evaluation="equal"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> - <feature name="initialized" evaluation="equal"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="Peripheral" resourceId="GPIO1" description="Peripheral GPIO1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> - <feature name="initialized" evaluation="equal"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> - <feature name="enabled" evaluation="equal" configuration="core0"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> - <feature name="enabled" evaluation="equal" configuration="core0"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> - <feature name="enabled" evaluation="equal" configuration="core0"> - <data>true</data> - </feature> - </dependency> - </dependencies> - <pins> - <pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/> - <pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/> - <pin peripheral="GPIO1" signal="gpiomux_io, 03" pin_num="10" pin_signal="GPIO_03"> - <pin_features> - <pin_feature name="identifier" value="USER_LED"/> - <pin_feature name="direction" value="OUTPUT"/> - </pin_features> - </pin> - <pin peripheral="ARM" signal="TRACE, 1" pin_num="79" pin_signal="GPIO_13"> - <pin_features> - <pin_feature name="speed" value="MHZ_200"/> - </pin_features> - </pin> - <pin peripheral="ARM" signal="TRACE, 2" pin_num="80" pin_signal="GPIO_12"> - <pin_features> - <pin_feature name="speed" value="MHZ_200"/> - </pin_features> - </pin> - <pin peripheral="ARM" signal="arm_trace_clk" pin_num="58" pin_signal="GPIO_AD_02"> - <pin_features> - <pin_feature name="speed" value="MHZ_200"/> - </pin_features> - </pin> - <pin peripheral="ARM" signal="TRACE, 3" pin_num="1" pin_signal="GPIO_11"> - <pin_features> - <pin_feature name="speed" value="MHZ_200"/> - </pin_features> - </pin> - <pin peripheral="ARM" signal="TRACE, 0" pin_num="60" pin_signal="GPIO_AD_00"> - <pin_features> - <pin_feature name="speed" value="MHZ_200"/> - </pin_features> - </pin> - <pin peripheral="GPIO1" signal="gpiomux_io, 08" pin_num="4" pin_signal="GPIO_08"> - <pin_features> - <pin_feature name="direction" value="INPUT"/> - <pin_feature name="pull_keeper_select" value="Pull"/> - <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> - </pin_features> - </pin> - </pins> - </function> - </functions_list> - </pins> - <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> - <generated_project_files> - <file path="board/clock_config.c" update_enabled="true"/> - <file path="board/clock_config.h" update_enabled="true"/> - </generated_project_files> - <clocks_profile> - <processor_version>13.0.2</processor_version> - </clocks_profile> - <clock_configurations> - <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> - <description></description> - <options/> - <dependencies> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="routed" evaluation=""> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="direction" evaluation=""> - <data>INPUT</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="routed" evaluation=""> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="direction" evaluation=""> - <data>OUTPUT</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="routed" evaluation=""> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="direction" evaluation=""> - <data>INPUT</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="routed" evaluation=""> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="direction" evaluation=""> - <data>OUTPUT</data> - </feature> - </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> - <feature name="enabled" evaluation="equal" configuration="core0"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> - <feature name="enabled" evaluation="equal" configuration="core0"> - <data>true</data> - </feature> - </dependency> - </dependencies> - <clock_sources> - <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> - </clock_sources> - <clock_outputs> - <clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/> - <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> - <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> - <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> - <clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/> - <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/> - <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> - <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> - <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> - <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> - <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/> - <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> - <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> - <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/> - <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> - <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> - <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> - <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> - <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> - <clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> - </clock_outputs> - <clock_settings> - <setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/> - <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> - <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/> - <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/> - <setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/> - <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> - <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/> - <setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/> - <setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/> - <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/> - <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/> - <setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/> - <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> - <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> - <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> - <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> - <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> - <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> - <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> - <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/> - <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> - <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> - <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> - <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/> - <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> - <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> - <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> - </clock_settings> - <called_from_default_init>true</called_from_default_init> - </clock_configuration> - </clock_configurations> - </clocks> - <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> - <generated_project_files/> - <dcdx_profile> - <processor_version>0.0.0</processor_version> - </dcdx_profile> - <dcdx_configurations/> - </dcdx> - <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true"> - <generated_project_files/> - <peripherals_profile> - <processor_version>13.0.2</processor_version> - </peripherals_profile> - <functional_groups> - <functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0"> - <description></description> - <options/> - <dependencies/> - <instances> - <instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> - <config_set name="main" quick_selection="qs_interrupt"> - <setting name="clockSource" value="Lpi2cClock"/> - <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/> - </config_set> - <config_set name="interrupt_vector"/> - <config_set name="master" quick_selection="qs_master_transfer"> - <setting name="mode" value="transfer"/> - <struct name="config"> - <setting name="enableMaster" value="true"/> - <setting name="enableDoze" value="true"/> - <setting name="debugEnable" value="false"/> - <setting name="ignoreAck" value="false"/> - <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/> - <setting name="baudRate_Hz" value="100000"/> - <setting name="busIdleTimeout_ns" value="0"/> - <setting name="pinLowTimeout_ns" value="0"/> - <setting name="sdaGlitchFilterWidth_ns" value="0"/> - <setting name="sclGlitchFilterWidth_ns" value="0"/> - <struct name="hostRequest"> - <setting name="enable" value="false"/> - <setting name="source" value="kLPI2C_HostRequestExternalPin"/> - <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/> - </struct> - <set name="edmaRequestSources"> - <selected/> - </set> - </struct> - <struct name="transfer"> - <setting name="blocking" value="false"/> - <setting name="enable_custom_handle" value="false"/> - <struct name="callback"> - <setting name="name" value=""/> - <setting name="userData" value=""/> - </struct> - <set name="flags"> - <selected/> - </set> - <setting name="slaveAddress" value="0"/> - <setting name="direction" value="kLPI2C_Write"/> - <setting name="subaddress" value="0"/> - <setting name="subaddressSize" value="1"/> - <setting name="blocking_buffer" value="false"/> - <setting name="enable_custom_buffer" value="false"/> - <setting name="dataSize" value="1"/> - </struct> - </config_set> - </instance> - <instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> - <config_set name="lpuartConfig_t" quick_selection="QuickSelection1"> - <struct name="lpuartConfig"> - <setting name="clockSource" value="LpuartClock"/> - <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/> - <setting name="baudRate_Bps" value="115200"/> - <setting name="parityMode" value="kLPUART_ParityDisabled"/> - <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> - <setting name="isMsb" value="false"/> - <setting name="stopBitCount" value="kLPUART_OneStopBit"/> - <setting name="enableMatchAddress1" value="false"/> - <setting name="matchAddress1" value="0"/> - <setting name="enableMatchAddress2" value="false"/> - <setting name="matchAddress2" value="0"/> - <setting name="txFifoWatermark" value="0"/> - <setting name="rxFifoWatermark" value="1"/> - <setting name="enableRxRTS" value="false"/> - <setting name="enableTxCTS" value="false"/> - <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> - <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> - <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> - <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> - <setting name="enableTx" value="true"/> - <setting name="enableRx" value="true"/> - </struct> - </config_set> - </instance> - <instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> - <config_set name="fsl_gpio"> - <setting name="enable_irq_comb_0_15" value="false"/> - <struct name="gpio_interrupt_comb_0_15"> - <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/> - <setting name="enable_interrrupt" value="enabled"/> - <setting name="enable_priority" value="false"/> - <setting name="priority" value="0"/> - <setting name="enable_custom_name" value="false"/> - </struct> - </config_set> - </instance> - <instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> - <config_set name="fsl_gpio"> - <setting name="enable_irq_comb_0_15" value="false"/> - <struct name="gpio_interrupt_comb_0_15"> - <setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/> - <setting name="enable_interrrupt" value="enabled"/> - <setting name="enable_priority" value="false"/> - <setting name="priority" value="0"/> - <setting name="enable_custom_name" value="false"/> - </struct> - <setting name="enable_irq_comb_16_31" value="false"/> - <struct name="gpio_interrupt_comb_16_31"> - <setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/> - <setting name="enable_interrrupt" value="enabled"/> - <setting name="enable_priority" value="false"/> - <setting name="priority" value="0"/> - <setting name="enable_custom_name" value="false"/> - </struct> - </config_set> - </instance> - <instance name="NVIC" uuid="2a54e709-5718-4b89-8b7b-71cefb418658" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> - <config_set name="nvic"> - <array name="interrupt_table"/> - <array name="interrupts"/> - </config_set> - </instance> - </instances> - </functional_group> - </functional_groups> - <components> - <component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system"> - <config_set_global name="global_system_definitions"> - <setting name="user_definitions" value=""/> - <setting name="user_includes" value=""/> - </config_set_global> - </component> - <component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg"> - <config_set_global name="global_messages"/> - </component> - <component name="gpio_adapter_common" uuid="27e43a4b-bddb-4db2-8f6b-3f6a73008a27" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> - <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> - </component> - <component name="generic_uart" uuid="c946fe99-5d76-4cca-8be0-dea3c7861b68" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> - <config_set_global name="global_uart"/> - </component> - <component name="generic_can" uuid="c18a4299-93be-44e8-b563-3985b3e264c5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> - <config_set_global name="global_can"/> - </component> - <component name="uart_cmsis_common" uuid="6149366a-a07f-40a7-8909-00ba459085a7" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> - <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> - </component> - <component name="generic_enet" uuid="15cc4d18-2002-44a4-b7e7-f681a046f26c" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> - <config_set_global name="global_enet"/> - </component> - </components> - </periphs> - <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> - <generated_project_files/> - <tee_profile> - <processor_version>0.0.0</processor_version> - </tee_profile> - </tee> - </tools> -</configuration> diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake index 99681ab12..63b2a120a 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1010) set(MCU_VARIANT MIMXRT1011) set(JLINK_DEVICE MIMXRT1011xxx5A) diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk index 488a56fdc..c5521faf5 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY +MCU_FAMILY = RT1010 MCU_VARIANT = MIMXRT1011 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake index becad46d4..5661bb3e6 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1015) set(MCU_VARIANT MIMXRT1015) set(JLINK_DEVICE MIMXRT1015DAF5A) diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk index 20c697ea1..062929902 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1015DAF5A -DCFG_EXAMPLE_VIDEO_READONLY +MCU_FAMILY = RT1015 MCU_VARIANT = MIMXRT1015 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake index 39c94147c..6b95dfb65 100644 --- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1020) set(MCU_VARIANT MIMXRT1021) set(JLINK_DEVICE MIMXRT1021xxx5A) diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk index e269c8ac5..b3976b356 100644 --- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1021DAG5A +MCU_FAMILY = RT1020 MCU_VARIANT = MIMXRT1021 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake index 45487d148..10669b32d 100644 --- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1020) set(MCU_VARIANT MIMXRT1024) set(JLINK_DEVICE MIMXRT1024xxx5A) diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk index 3c325cc93..83448c399 100644 --- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1024DAG5A +MCU_FAMILY = RT1020 MCU_VARIANT = MIMXRT1024 # warnings caused by mcu driver diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake index 1aee75b0d..70050dd16 100644 --- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1050) set(MCU_VARIANT MIMXRT1052) set(JLINK_DEVICE MIMXRT1052xxxxB) diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk index 60aa1e28f..9331eba94 100644 --- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1052DVL6B +MCU_FAMILY = RT1050 MCU_VARIANT = MIMXRT1052 JLINK_DEVICE = MIMXRT1052xxxxB diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake index f70a5f923..865695894 100644 --- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1060) set(MCU_VARIANT MIMXRT1062) set(JLINK_DEVICE MIMXRT1062xxx6A) diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk index 0317ee452..79d15880b 100644 --- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1062DVL6A +MCU_FAMILY = RT1060 MCU_VARIANT = MIMXRT1062 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake index cd75c5227..b23fee3c4 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1064) set(MCU_VARIANT MIMXRT1064) set(JLINK_DEVICE MIMXRT1064xxx6A) diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk index ddde419ae..3a65a3d89 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1064DVL6A +MCU_FAMILY = RT1064 MCU_VARIANT = MIMXRT1064 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake index d5629f8ba..dc3b8ed44 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake @@ -1,9 +1,10 @@ +set(MCU_FAMILY RT1170) set(MCU_VARIANT MIMXRT1176) if (M4 STREQUAL "1") set(MCU_CORE _cm4) set(JLINK_CORE _M4) - set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_ram.ld) + set(LD_FILE_GNU ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_ram.ld) set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") else () set(MCU_CORE _cm7) diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk index 8270ae587..3f07e28fc 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk @@ -1,3 +1,4 @@ +MCU_FAMILY = RT1170 MCU_VARIANT = MIMXRT1176 ifeq ($(M4), 1) diff --git a/hw/bsp/imxrt/boards/teensy_40/board.cmake b/hw/bsp/imxrt/boards/teensy_40/board.cmake index 41fdc78f5..55dd29897 100644 --- a/hw/bsp/imxrt/boards/teensy_40/board.cmake +++ b/hw/bsp/imxrt/boards/teensy_40/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1060) set(MCU_VARIANT MIMXRT1062) set(JLINK_DEVICE MIMXRT1062xxx6A) diff --git a/hw/bsp/imxrt/boards/teensy_40/board.mk b/hw/bsp/imxrt/boards/teensy_40/board.mk index 45ca0fb6e..e7f75fcae 100644 --- a/hw/bsp/imxrt/boards/teensy_40/board.mk +++ b/hw/bsp/imxrt/boards/teensy_40/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1062DVL6A +MCU_FAMILY = RT1060 MCU_VARIANT = MIMXRT1062 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/teensy_41/board.cmake b/hw/bsp/imxrt/boards/teensy_41/board.cmake index 0fd8d528e..e8398fdbe 100644 --- a/hw/bsp/imxrt/boards/teensy_41/board.cmake +++ b/hw/bsp/imxrt/boards/teensy_41/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1060) set(MCU_VARIANT MIMXRT1062) set(JLINK_DEVICE MIMXRT1062xxx6A) diff --git a/hw/bsp/imxrt/boards/teensy_41/board.mk b/hw/bsp/imxrt/boards/teensy_41/board.mk index 45ca0fb6e..e7f75fcae 100644 --- a/hw/bsp/imxrt/boards/teensy_41/board.mk +++ b/hw/bsp/imxrt/boards/teensy_41/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1062DVL6A +MCU_FAMILY = RT1060 MCU_VARIANT = MIMXRT1062 # For flash-jlink target diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index d54b41bdb..c1ee34b1a 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -239,7 +239,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index d946b591d..009b15da3 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -1,7 +1,8 @@ include_guard() -set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) -set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +set(MCUX_CORE ${TOP}/hw/mcu/nxp/mcuxsdk-core) +set(MCUX_DEVICES ${TOP}/hw/mcu/nxp/mcux-devices-rt) +set(CMSIS_DIR ${TOP}/lib/CMSIS_6) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -15,19 +16,29 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "") +# XIP boot files: some devices reference RT1052's xip (see each device's xip/CMakeLists.txt) +if (MCU_FAMILY STREQUAL "RT1064") + set(XIP_DIR ${MCUX_DEVICES}/RT1064/MIMXRT1064/xip) +elseif (MCU_FAMILY STREQUAL "RT1170") + set(XIP_DIR ${MCUX_DEVICES}/RT1170/MIMXRT1176/xip) +else() + # RT1010, RT1015, RT1020, RT1050, RT1060 all use RT1052's xip + set(XIP_DIR ${MCUX_DEVICES}/RT1050/MIMXRT1052/xip) +endif() + #------------------------------------ # Startup & Linker script #------------------------------------ if (NOT DEFINED LD_FILE_GNU) -set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.ld) +set(LD_FILE_GNU ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) if (NOT DEFINED LD_FILE_IAR) -set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.icf) +set(LD_FILE_IAR ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/iar/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.icf) endif () -set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S) -set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/startup_${MCU_VARIANT_WITH_CORE}.s) +set(STARTUP_FILE_GNU ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S) +set(STARTUP_FILE_IAR ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/iar/startup_${MCU_VARIANT_WITH_CORE}.s) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) #------------------------------------ @@ -37,23 +48,26 @@ function(family_add_board BOARD_TARGET) add_library(${BOARD_TARGET} STATIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/pin_mux.c - ${SDK_DIR}/drivers/common/fsl_common.c - ${SDK_DIR}/drivers/common/fsl_common_arm.c - ${SDK_DIR}/drivers/igpio/fsl_gpio.c - ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c - ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c - ${SDK_DIR}/drivers/ocotp/fsl_ocotp.c - ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT_WITH_CORE}.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c + # mcuxsdk-core drivers + ${MCUX_CORE}/drivers/common/fsl_common.c + ${MCUX_CORE}/drivers/common/fsl_common_arm.c + ${MCUX_CORE}/drivers/igpio/fsl_gpio.c + ${MCUX_CORE}/drivers/lpspi/fsl_lpspi.c + ${MCUX_CORE}/drivers/lpuart/fsl_lpuart.c + ${MCUX_CORE}/drivers/ocotp/fsl_ocotp.c + # device specific + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/system_${MCU_VARIANT_WITH_CORE}.c + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/fsl_clock.c ) - # Optional drivers: only available for some mcus: rt1160, rt1170 - set(OPTIONAL_DRIVER fsl_dcdc.c fsl_pmu.c fsl_anatop_ai.c) - foreach(FILE IN LISTS OPTIONAL_DRIVER) - if(EXISTS ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/${FILE}) - target_sources(${BOARD_TARGET} PRIVATE ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/${FILE}) - endif() - endforeach() + # Additional drivers in subdirectories (RT1170 power/anatop_ai) + if (MCU_FAMILY STREQUAL "RT1170") + target_sources(${BOARD_TARGET} PRIVATE + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/power/fsl_dcdc.c + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/power/fsl_pmu.c + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/anatop_ai/fsl_anatop_ai.c + ) + endif() if (NOT M4 STREQUAL "1") target_compile_definitions(${BOARD_TARGET} PUBLIC @@ -66,15 +80,27 @@ function(family_add_board BOARD_TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board ${CMSIS_DIR}/CMSIS/Core/Include - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/igpio - ${SDK_DIR}/drivers/lpspi - ${SDK_DIR}/drivers/lpuart - ${SDK_DIR}/drivers/ocotp + # device specific + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT} + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers + ${MCUX_DEVICES}/${MCU_FAMILY}/periph + # mcuxsdk-core drivers + ${MCUX_CORE}/drivers/common + ${MCUX_CORE}/drivers/igpio + ${MCUX_CORE}/drivers/lpspi + ${MCUX_CORE}/drivers/lpuart + ${MCUX_CORE}/drivers/ocotp ) + # Include power/anatop_ai driver directories if they exist + foreach(SUBDIR power anatop_ai) + if(EXISTS ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/${SUBDIR}) + target_include_directories(${BOARD_TARGET} PUBLIC + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/${SUBDIR} + ) + endif() + endforeach() + update_board(${BOARD_TARGET}) endfunction() @@ -91,13 +117,14 @@ function(family_configure_example TARGET RTOS) ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c ${TOP}/src/portable/ehci/ehci.c - ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c + ${XIP_DIR}/fsl_flexspi_nor_boot.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ) target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ${XIP_DIR} ) target_compile_definitions(${TARGET} PUBLIC __START=main # required with -nostartfiles diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk index 42000671d..59735670a 100644 --- a/hw/bsp/imxrt/family.mk +++ b/hw/bsp/imxrt/family.mk @@ -1,11 +1,22 @@ UF2_FAMILY_ID = 0x4fb2d5bd -SDK_DIR = hw/mcu/nxp/mcux-sdk +MCUX_CORE = hw/mcu/nxp/mcuxsdk-core +MCUX_DEVICES = hw/mcu/nxp/mcux-devices-rt include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m7 MCU_VARIANT_WITH_CORE = ${MCU_VARIANT}${MCU_CORE} -MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT) +MCU_DIR = $(MCUX_DEVICES)/$(MCU_FAMILY)/$(MCU_VARIANT) + +# XIP boot files: some devices reference RT1052's xip (see each device's xip/CMakeLists.txt) +ifeq ($(MCU_FAMILY),RT1064) + XIP_DIR = $(MCUX_DEVICES)/RT1064/MIMXRT1064/xip +else ifeq ($(MCU_FAMILY),RT1170) + XIP_DIR = $(MCUX_DEVICES)/RT1170/MIMXRT1176/xip +else + # RT1010, RT1015, RT1020, RT1050, RT1060 all use RT1052's xip + XIP_DIR = $(MCUX_DEVICES)/RT1050/MIMXRT1052/xip +endif CFLAGS += \ -D__START=main \ @@ -48,32 +59,36 @@ SRC_C += \ ${BOARD_PATH}/board/clock_config.c \ ${BOARD_PATH}/board/pin_mux.c \ $(MCU_DIR)/system_$(MCU_VARIANT_WITH_CORE).c \ - $(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \ + $(XIP_DIR)/fsl_flexspi_nor_boot.c \ $(MCU_DIR)/drivers/fsl_clock.c \ - $(SDK_DIR)/drivers/common/fsl_common.c \ - $(SDK_DIR)/drivers/common/fsl_common_arm.c \ - $(SDK_DIR)/drivers/igpio/fsl_gpio.c \ - $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c \ - $(SDK_DIR)/drivers/ocotp/fsl_ocotp.c \ + $(MCUX_CORE)/drivers/common/fsl_common.c \ + $(MCUX_CORE)/drivers/common/fsl_common_arm.c \ + $(MCUX_CORE)/drivers/igpio/fsl_gpio.c \ + $(MCUX_CORE)/drivers/lpuart/fsl_lpuart.c \ + $(MCUX_CORE)/drivers/ocotp/fsl_ocotp.c \ -# Optional drivers: only available for some mcus: rt1160, rt1170 -ifneq (,$(wildcard ${TOP}/${MCU_DIR}/drivers/fsl_dcdc.c)) +# Optional drivers: RT1170 power/anatop_ai subdirectories +ifneq (,$(wildcard ${TOP}/${MCU_DIR}/drivers/power/fsl_dcdc.c)) SRC_C += \ - ${MCU_DIR}/drivers/fsl_dcdc.c \ - ${MCU_DIR}/drivers/fsl_pmu.c \ - ${MCU_DIR}/drivers/fsl_anatop_ai.c + ${MCU_DIR}/drivers/power/fsl_dcdc.c \ + ${MCU_DIR}/drivers/power/fsl_pmu.c \ + ${MCU_DIR}/drivers/anatop_ai/fsl_anatop_ai.c +INC += \ + $(TOP)/$(MCU_DIR)/drivers/power \ + $(TOP)/$(MCU_DIR)/drivers/anatop_ai endif INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/lib/CMSIS_6/CMSIS/Core/Include \ $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/project_template \ $(TOP)/$(MCU_DIR)/drivers \ - $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/igpio \ - $(TOP)/$(SDK_DIR)/drivers/lpuart \ - $(TOP)/$(SDK_DIR)/drivers/ocotp \ + $(TOP)/$(MCUX_DEVICES)/$(MCU_FAMILY)/periph \ + $(TOP)/$(MCUX_CORE)/drivers/common \ + $(TOP)/$(MCUX_CORE)/drivers/igpio \ + $(TOP)/$(MCUX_CORE)/drivers/lpuart \ + $(TOP)/$(MCUX_CORE)/drivers/ocotp \ + $(TOP)/$(XIP_DIR) \ SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT_WITH_CORE).S diff --git a/hw/bsp/kinetis_k/family.c b/hw/bsp/kinetis_k/family.c index 98ef52739..1505defe0 100644 --- a/hw/bsp/kinetis_k/family.c +++ b/hw/bsp/kinetis_k/family.c @@ -143,7 +143,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/kinetis_k32l2/family.c b/hw/bsp/kinetis_k32l2/family.c index 2062b8b18..ec8dc6ecf 100644 --- a/hw/bsp/kinetis_k32l2/family.c +++ b/hw/bsp/kinetis_k32l2/family.c @@ -148,7 +148,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/kinetis_kl/family.c b/hw/bsp/kinetis_kl/family.c index c257f4b2b..f89434d06 100644 --- a/hw/bsp/kinetis_kl/family.c +++ b/hw/bsp/kinetis_kl/family.c @@ -142,7 +142,7 @@ void SysTick_Handler(void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc11/family.c b/hw/bsp/lpc11/family.c index c9f18bd2f..76c2bd17c 100644 --- a/hw/bsp/lpc11/family.c +++ b/hw/bsp/lpc11/family.c @@ -130,7 +130,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc13/family.c b/hw/bsp/lpc13/family.c index e212c6a63..8513f4df4 100644 --- a/hw/bsp/lpc13/family.c +++ b/hw/bsp/lpc13/family.c @@ -83,7 +83,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c index 5f22df175..0d092d3a9 100644 --- a/hw/bsp/lpc15/family.c +++ b/hw/bsp/lpc15/family.c @@ -140,7 +140,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc17/family.c b/hw/bsp/lpc17/family.c index ba59fccca..f398f7e3c 100644 --- a/hw/bsp/lpc17/family.c +++ b/hw/bsp/lpc17/family.c @@ -145,7 +145,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c index 6c02c711f..2043cef99 100644 --- a/hw/bsp/lpc18/family.c +++ b/hw/bsp/lpc18/family.c @@ -143,7 +143,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc40/family.c b/hw/bsp/lpc40/family.c index 5ea95e9b8..237cd996b 100644 --- a/hw/bsp/lpc40/family.c +++ b/hw/bsp/lpc40/family.c @@ -156,7 +156,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c index f440fb119..56834a1b0 100644 --- a/hw/bsp/lpc43/family.c +++ b/hw/bsp/lpc43/family.c @@ -185,8 +185,10 @@ void board_init(void) */ Chip_USB1_Init(); +#ifdef _BOARD_EA4357_H // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board) Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7); +#endif #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0 // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low. @@ -257,7 +259,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake index 1f549bf50..6e632d266 100644 --- a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake +++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake @@ -7,7 +7,4 @@ function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CPU_LPC51U68JBD64 ) - target_link_libraries(${TARGET} PUBLIC - ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower.a - ) endfunction() diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk index 5627cb024..072037e90 100644 --- a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk +++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk @@ -1,4 +1,4 @@ -MCU = LPC51U68 +MCU_VARIANT = LPC51U68 CFLAGS += \ -DCPU_LPC51U68JBD64 \ diff --git a/hw/bsp/lpc51/family.c b/hw/bsp/lpc51/family.c index bec86f87f..847972350 100644 --- a/hw/bsp/lpc51/family.c +++ b/hw/bsp/lpc51/family.c @@ -122,7 +122,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake index 1823b64fc..00c6731ae 100644 --- a/hw/bsp/lpc51/family.cmake +++ b/hw/bsp/lpc51/family.cmake @@ -1,7 +1,8 @@ include_guard() -set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) -set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +set(MCUX_DIR ${TOP}/hw/mcu/nxp/mcuxsdk-core) +set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-devices-lpc) +set(CMSIS_DIR ${TOP}/lib/CMSIS_6) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -16,41 +17,52 @@ set(FAMILY_MCUS LPC51 CACHE INTERNAL "") # Startup & Linker script #------------------------------------ if (NOT DEFINED LD_FILE_GNU) -set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}_flash.ld) + set(LD_FILE_GNU ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/gcc/${MCU_VARIANT}_flash.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) + if (NOT DEFINED STARTUP_FILE_GNU) -set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S) + set(STARTUP_FILE_GNU ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S) endif () set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) +if (NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/iar/${MCU_VARIANT}_flash.icf) +endif () + +if (NOT DEFINED STARTUP_FILE_IAR) + set(STARTUP_FILE_IAR ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/iar/startup_${MCU_VARIANT}.s) +endif () + #------------------------------------ # Board Target #------------------------------------ function(family_add_board BOARD_TARGET) add_library(${BOARD_TARGET} STATIC # driver - ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c - ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c - ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c + ${MCUX_DIR}/drivers/lpc_gpio/fsl_gpio.c + ${MCUX_DIR}/drivers/flexcomm/fsl_flexcomm.c + ${MCUX_DIR}/drivers/flexcomm/usart/fsl_usart.c # mcu - ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c + ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/system_${MCU_VARIANT}.c + ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers/fsl_clock.c + ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers/fsl_power.c + ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers/fsl_reset.c ) target_include_directories(${BOARD_TARGET} PUBLIC ${TOP}/lib/sct_neopixel # driver - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/flexcomm - ${SDK_DIR}/drivers/lpc_iocon - ${SDK_DIR}/drivers/lpc_gpio - ${SDK_DIR}/drivers/lpuart + ${MCUX_DIR}/drivers/common + ${MCUX_DIR}/drivers/common + ${MCUX_DIR}/drivers/flexcomm + ${MCUX_DIR}/drivers/flexcomm/usart + ${MCUX_DIR}/drivers/lpc_iocon + ${MCUX_DIR}/drivers/lpc_gpio # mcu - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ${SDK_DIR}/LPC51U68/${MCU_VARIANT} + ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers ${CMSIS_DIR}/CMSIS/Core/Include + ${SDK_DIR}/LPC51U68/periph ) target_compile_definitions(${BOARD_TARGET} PUBLIC CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\) diff --git a/hw/bsp/lpc51/family.mk b/hw/bsp/lpc51/family.mk index 91d1261cb..34987d183 100644 --- a/hw/bsp/lpc51/family.mk +++ b/hw/bsp/lpc51/family.mk @@ -1,8 +1,7 @@ -SDK_DIR = hw/mcu/nxp/mcux-sdk - include $(TOP)/$(BOARD_PATH)/board.mk -MCU_DIR = $(SDK_DIR)/devices/$(MCU) CPU_CORE ?= cortex-m0plus +MCUX_DIR = /hw/mcu/nxp/mcuxsdk-core +SDK_DIR = /hw/mcu/nxp/mcux-devices-lpc CFLAGS += \ -flto \ @@ -18,29 +17,28 @@ LDFLAGS_GCC += \ --specs=nosys.specs --specs=nano.specs \ # All source paths should be relative to the top level. -LD_FILE = $(MCU_DIR)/gcc/$(MCU)_flash.ld +LD_FILE = $(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/gcc/$(MCU_VARIANT)_flash.ld SRC_C += \ src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \ - $(MCU_DIR)/system_$(MCU).c \ - $(MCU_DIR)/drivers/fsl_clock.c \ - $(MCU_DIR)/drivers/fsl_power.c \ - $(MCU_DIR)/drivers/fsl_reset.c \ - $(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \ - $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ - $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/system_$(MCU_VARIANT).c \ + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers/fsl_clock.c \ + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers/fsl_power.c \ + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers/fsl_reset.c \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_gpio/fsl_gpio.c \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/fsl_flexcomm.c \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart/fsl_usart.c \ INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/drivers \ - $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/flexcomm \ - $(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \ - $(TOP)/$(SDK_DIR)/drivers/lpc_iocon \ - $(TOP)/$(SDK_DIR)/drivers/lpc_gpio - -SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_6/CMSIS/Core/Include \ + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT) \ + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers \ + $(TOP)/$(SDK_DIR)/LPC51U68/periph \ + $(TOP)/$(MCUX_DIR)/drivers/common \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_iocon \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_gpio -LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a +SRC_S += $(TOP)$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/gcc/startup_$(MCU_VARIANT).S diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake index c0bbeecd5..b306f885a 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake +++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake @@ -6,10 +6,8 @@ set(PYOCD_TARGET LPC54114) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54114J256_cm4_flash.ld) -# Device port default to PORT1 Highspeed -if (NOT DEFINED PORT) - set(PORT 1) -endif() +# Only Port 0 Full-Speed +set(RHPORT_DEVICE 0) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h index c43ca9d7d..1158d0675 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h @@ -36,6 +36,18 @@ extern "C" { #endif +// IOCON pin mux +#define IOCON_PIO_DIGITAL_EN 0x80u // Enables digital function +#define IOCON_PIO_FUNC0 0x00u +#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1 +#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7 +#define IOCON_PIO_INPFILT_OFF 0x0100u // Input filter disabled +#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted +#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function +#define IOCON_PIO_MODE_PULLUP 0x10u +#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled +#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled + // LED #define LED_PORT 0 #define LED_PIN 29 diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake index f0715fa12..aea608e60 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake +++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake @@ -8,8 +8,11 @@ set(NXPLINK_DEVICE LPC54608:LPCXpresso54608) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54608J512_flash.ld) # Device port default to PORT1 Highspeed -if (NOT DEFINED PORT) - set(PORT 1) +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) endif() function(update_board TARGET) diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h index e985e97e0..7a5cbea87 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h @@ -36,6 +36,18 @@ extern "C" { #endif +// IOCON pin mux +#define IOCON_PIO_DIGITAL_EN 0x0100u // Enables digital function +#define IOCON_PIO_FUNC0 0x00u +#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1 +#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7 +#define IOCON_PIO_INPFILT_OFF 0x0200u // Input filter disabled +#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted +#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function +#define IOCON_PIO_MODE_PULLUP 0x10u +#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled +#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled + // LED #define LED_PORT 2 #define LED_PIN 2 @@ -54,6 +66,15 @@ // USB0 VBUS #define USB0_VBUS_PINMUX 0, 22, IOCON_PIO_DIG_FUNC7_EN +// Power switch +#define USBFS_POWER_PORT 4 +#define USBFS_POWER_PIN 7 +#define USBFS_POWER_STATE_ON 0 + +#define USBHS_POWER_PORT 4 +#define USBHS_POWER_PIN 9 +#define USBHS_POWER_STATE_ON 0 + // XTAL //#define XTAL0_CLK_HZ (16 * 1000 * 1000U) diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake index 1dea6f353..b0d0d404f 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake +++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake @@ -8,8 +8,11 @@ set(NXPLINK_DEVICE LPC54628:LPCXpresso54628) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54628J512_flash.ld) # Device port default to PORT1 Highspeed -if (NOT DEFINED PORT) - set(PORT 1) +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) endif() function(update_board TARGET) diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h index 837d26aef..5c858ed99 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h @@ -36,6 +36,18 @@ extern "C" { #endif +// IOCON pin mux +#define IOCON_PIO_DIGITAL_EN 0x0100u // Enables digital function +#define IOCON_PIO_FUNC0 0x00u +#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1 +#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7 +#define IOCON_PIO_INPFILT_OFF 0x0200u // Input filter disabled +#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted +#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function +#define IOCON_PIO_MODE_PULLUP 0x10u +#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled +#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled + // LED #define LED_PORT 2 #define LED_PIN 2 diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c index 7bb73afbc..806bd53dc 100644 --- a/hw/bsp/lpc54/family.c +++ b/hw/bsp/lpc54/family.c @@ -41,18 +41,6 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -// IOCON pin mux -#define IOCON_PIO_DIGITAL_EN 0x80u // Enables digital function -#define IOCON_PIO_FUNC0 0x00u -#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1 -#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7 -#define IOCON_PIO_INPFILT_OFF 0x0100u // Input filter disabled -#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted -#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function -#define IOCON_PIO_MODE_PULLUP 0x10u -#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled -#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled - // Digital pin function n enabled #define IOCON_PIO_DIG_FUNC0_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC0) #define IOCON_PIO_DIG_FUNC1_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC1) @@ -149,37 +137,71 @@ void board_init(void) { USART_Init(UART_DEV, &uart_config, 12000000); #endif - // USB - IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX); - #if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT // LPC546xx and LPC540xx has OTG 1 FS + 1 HS rhports - #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0 + #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0) + /* PORT0 PIN22 configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX); + // Port0 is Full Speed POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*< Turn on USB Phy */ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - /*According to reference manual, device mode setting has to be set by access usb host register */ - CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */ - USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK; - CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */ + if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) { + /*According to reference manual, device mode setting has to be set by access usb host register */ + CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */ + USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK; + CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */ + + CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq()); + } else { + #ifdef USBFS_POWER_PORT + /* Configure USB0 Power Switch Pin */ + IOCON_PinMuxSet(IOCON, USBFS_POWER_PORT, USBFS_POWER_PIN, IOCON_PIO_DIG_FUNC0_EN); - CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq()); + gpio_pin_config_t const power_pin_config = {kGPIO_DigitalOutput, USBFS_POWER_STATE_ON}; + GPIO_PinInit(GPIO, USBFS_POWER_PORT, USBFS_POWER_PIN, &power_pin_config); + #endif + CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq()); + USBFSH->PORTMODE &= ~USBFSH_PORTMODE_DEV_ENABLE_MASK; + } #endif - #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1 - // Port1 is High Speed - POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); + #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1) + // Port1 is High Speed + + /* Turn on USB1 Phy */ + POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); - /*According to reference manual, device mode setting has to be set by access usb host register */ - CLOCK_EnableClock(kCLOCK_Usbh1); /* enable usb1 host clock */ + /* reset the IP to make sure it's in reset state. */ + RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn); + + if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) { + /* According to reference manual, device mode setting has to be set by access usb host register */ + CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock + + USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; - CLOCK_DisableClock(kCLOCK_Usbh1); /* enable usb1 host clock */ + CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock + /* enable USB Device clock */ CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUsbPll, 0U); + } else { + #ifdef USBHS_POWER_PORT + /* Configure USB1 Power Switch Pin */ + IOCON_PinMuxSet(IOCON, USBHS_POWER_PORT, USBHS_POWER_PIN, IOCON_PIO_DIG_FUNC0_EN); + + gpio_pin_config_t const power_pin_config = {kGPIO_DigitalOutput, USBHS_POWER_STATE_ON}; + GPIO_PinInit(GPIO, USBHS_POWER_PORT, USBHS_POWER_PIN, &power_pin_config); + #endif + CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 0U); + } #endif #else + IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX); // LPC5411x series only has full speed device POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); // Turn on USB Phy CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */ @@ -217,7 +239,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake index c6145bd41..ebc0689fd 100644 --- a/hw/bsp/lpc54/family.cmake +++ b/hw/bsp/lpc54/family.cmake @@ -12,13 +12,29 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS LPC54 CACHE INTERNAL "") -if (NOT DEFINED PORT) - set(PORT 0) -endif() +# ---------------------- +# Port & Speed Selection +# ---------------------- -# Host port will be the other port if available -set(HOST_PORT $<NOT:${PORT}>) +# default device port to USB1 highspeed, host to USB0 fullspeed +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 1) +endif () + +# port 0 is fullspeed, port 1 is highspeed +set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) + +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) #------------------------------------ # Startup & Linker script #------------------------------------ @@ -26,11 +42,20 @@ if (NOT DEFINED LD_FILE_GNU) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) + if (NOT DEFINED STARTUP_FILE_GNU) set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) endif () set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) +if (NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/iar/${MCU_CORE}_flash.icf) +endif () + +if (NOT DEFINED STARTUP_FILE_IAR) + set(STARTUP_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/iar/startup_${MCU_CORE}.s) +endif () + #------------------------------------ # Board Target #------------------------------------ @@ -64,24 +89,23 @@ function(family_add_board BOARD_TARGET) ) target_compile_definitions(${BOARD_TARGET} PUBLIC CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\) - BOARD_TUD_RHPORT=${PORT} - BOARD_TUH_RHPORT=${HOST_PORT} + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} __STARTUP_CLEAR_BSS ) - # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM - if (PORT EQUAL 1) + # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM + if (RHPORT_DEVICE EQUAL 1) target_compile_definitions(${BOARD_TARGET} PUBLIC - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED - CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) + [=[CFG_TUD_MEM_SECTION=__attribute__((section("m_usb_global")))]=] ) - else () + endif () + if (RHPORT_HOST EQUAL 1) target_compile_definitions(${BOARD_TARGET} PUBLIC - BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED - BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED - CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) - #CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) + [=[CFG_TUH_MEM_SECTION=__attribute__((section("m_usb_global")))]=] + CFG_TUH_USBIP_IP3516=1 ) endif () @@ -107,11 +131,23 @@ function(family_configure_example TARGET RTOS) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) + if (RHPORT_HOST EQUAL 0) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/ohci/ohci.c + ) + elseif (RHPORT_HOST EQUAL 1) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c + ) + endif () + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" --specs=nosys.specs --specs=nano.specs -nostartfiles + "LINKER:--defsym=__stack_size__=0x1000" + "LINKER:--defsym=__heap_size__=0" ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${TARGET} PUBLIC @@ -120,6 +156,8 @@ function(family_configure_example TARGET RTOS) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${TARGET} PUBLIC "LINKER:--config=${LD_FILE_IAR}" + "LINKER:--config_def=__stack_size__=0x1000" + "LINKER:--config_def=__heap_size__=0" ) endif () diff --git a/hw/bsp/lpc54/iar/LPC54608_flash.icf b/hw/bsp/lpc54/iar/LPC54608_flash.icf new file mode 100644 index 000000000..408ab90ed --- /dev/null +++ b/hw/bsp/lpc54/iar/LPC54608_flash.icf @@ -0,0 +1,84 @@ +/* +** ################################################################### +** Processors: LPC54608J512BD208 +** LPC54608J512ET180 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017 +** Version: rev. 1.2, 2017-06-08 +** Build: b241125 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: [email protected] +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0007FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x20027FFF; + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40101FFF; + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; diff --git a/hw/bsp/lpc54/iar/LPC54628_flash.icf b/hw/bsp/lpc54/iar/LPC54628_flash.icf new file mode 100644 index 000000000..cc6615bd6 --- /dev/null +++ b/hw/bsp/lpc54/iar/LPC54628_flash.icf @@ -0,0 +1,82 @@ +/* +** ################################################################### +** Processor: LPC54628J512ET180 +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017 +** Version: rev. 1.2, 2017-06-08 +** Build: b241125 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: [email protected] +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0007FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x20027FFF; + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40101FFF; + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; diff --git a/hw/bsp/lpc54/iar/startup_LPC54608.s b/hw/bsp/lpc54/iar/startup_LPC54608.s new file mode 100644 index 000000000..05c4350e5 --- /dev/null +++ b/hw/bsp/lpc54/iar/startup_LPC54608.s @@ -0,0 +1,654 @@ +; ------------------------------------------------------------------------- +; @file: startup_LPC54608.s +; @purpose: CMSIS Cortex-M4 Core Device Startup File +; LPC54608 +; @version: 2.0 +; @date: 2024-10-29 +; @build: b250521 +; ------------------------------------------------------------------------- +; +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2025 NXP +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0xFFFFFFFF ;ECRP + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD WDT_BOD_IRQHandler ;Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ;DMA controller + DCD GINT0_IRQHandler ;GPIO group 0 + DCD GINT1_IRQHandler ;GPIO group 1 + DCD PIN_INT0_IRQHandler ;Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ;Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ;Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ;Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ;Micro-tick Timer + DCD MRT0_IRQHandler ;Multi-rate timer + DCD CTIMER0_IRQHandler ;Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ;Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ;SCTimer/PWM + DCD CTIMER3_IRQHandler ;Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ;Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ;Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ;Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ;Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ;Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ;Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ;Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ;Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD ADC0_SEQA_IRQHandler ;ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ;ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ;ADC0 threshold compare and error. + DCD DMIC0_IRQHandler ;Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ;Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ;USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ;USB device + DCD RTC_IRQHandler ;RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ;Reserved interrupt + DCD Reserved47_IRQHandler ;Reserved interrupt + DCD PIN_INT4_IRQHandler ;Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ;Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ;Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ;Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ;Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ;Standard counter/timer CTIMER4 + DCD RIT_IRQHandler ;Repetitive Interrupt Timer + DCD SPIFI0_IRQHandler ;SPI flash interface + DCD FLEXCOMM8_IRQHandler ;Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM9_IRQHandler ;Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) + DCD SDIO_IRQHandler ;SD/MMC + DCD CAN0_IRQ0_IRQHandler ;CAN0 interrupt0 + DCD CAN0_IRQ1_IRQHandler ;CAN0 interrupt1 + DCD CAN1_IRQ0_IRQHandler ;CAN1 interrupt0 + DCD CAN1_IRQ1_IRQHandler ;CAN1 interrupt1 + DCD USB1_IRQHandler ;USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ;USB1 activity + DCD ETHERNET_IRQHandler ;Ethernet + DCD ETHERNET_PMT_IRQHandler ;Ethernet power management interrupt + DCD ETHERNET_MACLP_IRQHandler ;Ethernet MAC interrupt + DCD EEPROM_IRQHandler ;EEPROM interrupt + DCD LCD_IRQHandler ;LCD interrupt + DCD SHA_IRQHandler ;SHA interrupt + DCD SMARTCARD0_IRQHandler ;Smart card 0 interrupt + DCD SMARTCARD1_IRQHandler ;Smart card 1 interrupt +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + MOVS r0,#56 + LDR r1, =0x40000220 + STR r0, [r1] ;Enable SRAM clock used by Stack + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_SEQA_IRQHandler + PUBWEAK ADC0_SEQA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQA_IRQHandler + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_SEQB_IRQHandler + PUBWEAK ADC0_SEQB_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQB_IRQHandler + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_THCMP_IRQHandler + PUBWEAK ADC0_THCMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_THCMP_IRQHandler + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + + PUBWEAK DMIC0_IRQHandler + PUBWEAK DMIC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMIC0_IRQHandler + LDR R0, =DMIC0_DriverIRQHandler + BX R0 + + PUBWEAK HWVAD0_IRQHandler + PUBWEAK HWVAD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HWVAD0_IRQHandler + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + + PUBWEAK Reserved46_IRQHandler + PUBWEAK Reserved46_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved46_IRQHandler + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + + PUBWEAK Reserved47_IRQHandler + PUBWEAK Reserved47_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved47_IRQHandler + LDR R0, =Reserved47_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT4_IRQHandler + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT5_IRQHandler + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT6_IRQHandler + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK PIN_INT7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT7_IRQHandler + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + + PUBWEAK RIT_IRQHandler + PUBWEAK RIT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RIT_IRQHandler + LDR R0, =RIT_DriverIRQHandler + BX R0 + + PUBWEAK SPIFI0_IRQHandler + PUBWEAK SPIFI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPIFI0_IRQHandler + LDR R0, =SPIFI0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM8_IRQHandler + PUBWEAK FLEXCOMM8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM8_IRQHandler + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM9_IRQHandler + PUBWEAK FLEXCOMM9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM9_IRQHandler + LDR R0, =FLEXCOMM9_DriverIRQHandler + BX R0 + + PUBWEAK SDIO_IRQHandler + PUBWEAK SDIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SDIO_IRQHandler + LDR R0, =SDIO_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_IRQ0_IRQHandler + PUBWEAK CAN0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ0_IRQHandler + LDR R0, =CAN0_IRQ0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_IRQ1_IRQHandler + PUBWEAK CAN0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ1_IRQHandler + LDR R0, =CAN0_IRQ1_DriverIRQHandler + BX R0 + + PUBWEAK CAN1_IRQ0_IRQHandler + PUBWEAK CAN1_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ0_IRQHandler + LDR R0, =CAN1_IRQ0_DriverIRQHandler + BX R0 + + PUBWEAK CAN1_IRQ1_IRQHandler + PUBWEAK CAN1_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ1_IRQHandler + LDR R0, =CAN1_IRQ1_DriverIRQHandler + BX R0 + + PUBWEAK USB1_IRQHandler + PUBWEAK USB1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_IRQHandler + LDR R0, =USB1_DriverIRQHandler + BX R0 + + PUBWEAK USB1_NEEDCLK_IRQHandler + PUBWEAK USB1_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_NEEDCLK_IRQHandler + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_IRQHandler + PUBWEAK ETHERNET_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_IRQHandler + LDR R0, =ETHERNET_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_PMT_IRQHandler + PUBWEAK ETHERNET_PMT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_PMT_IRQHandler + LDR R0, =ETHERNET_PMT_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_MACLP_IRQHandler + PUBWEAK ETHERNET_MACLP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_MACLP_IRQHandler + LDR R0, =ETHERNET_MACLP_DriverIRQHandler + BX R0 + + PUBWEAK EEPROM_IRQHandler + PUBWEAK EEPROM_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EEPROM_IRQHandler + LDR R0, =EEPROM_DriverIRQHandler + BX R0 + + PUBWEAK LCD_IRQHandler + PUBWEAK LCD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LCD_IRQHandler + LDR R0, =LCD_DriverIRQHandler + BX R0 + + PUBWEAK SHA_IRQHandler + PUBWEAK SHA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SHA_IRQHandler + LDR R0, =SHA_DriverIRQHandler + BX R0 + + PUBWEAK SMARTCARD0_IRQHandler + PUBWEAK SMARTCARD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD0_IRQHandler + LDR R0, =SMARTCARD0_DriverIRQHandler + BX R0 + + PUBWEAK SMARTCARD1_IRQHandler + PUBWEAK SMARTCARD1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD1_IRQHandler + LDR R0, =SMARTCARD1_DriverIRQHandler + BX R0 + +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +DMIC0_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +Reserved47_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +RIT_DriverIRQHandler +SPIFI0_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler +FLEXCOMM9_DriverIRQHandler +SDIO_DriverIRQHandler +CAN0_IRQ0_DriverIRQHandler +CAN0_IRQ1_DriverIRQHandler +CAN1_IRQ0_DriverIRQHandler +CAN1_IRQ1_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +ETHERNET_DriverIRQHandler +ETHERNET_PMT_DriverIRQHandler +ETHERNET_MACLP_DriverIRQHandler +EEPROM_DriverIRQHandler +LCD_DriverIRQHandler +SHA_DriverIRQHandler +SMARTCARD0_DriverIRQHandler +SMARTCARD1_DriverIRQHandler +DefaultISR + B . + + END diff --git a/hw/bsp/lpc54/iar/startup_LPC54628.s b/hw/bsp/lpc54/iar/startup_LPC54628.s new file mode 100644 index 000000000..fec5f7fca --- /dev/null +++ b/hw/bsp/lpc54/iar/startup_LPC54628.s @@ -0,0 +1,654 @@ +; ------------------------------------------------------------------------- +; @file: startup_LPC54628.s +; @purpose: CMSIS Cortex-M4 Core Device Startup File +; LPC54628 +; @version: 2.0 +; @date: 2024-10-29 +; @build: b250521 +; ------------------------------------------------------------------------- +; +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2025 NXP +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0xFFFFFFFF ;ECRP + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD WDT_BOD_IRQHandler ;Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ;DMA controller + DCD GINT0_IRQHandler ;GPIO group 0 + DCD GINT1_IRQHandler ;GPIO group 1 + DCD PIN_INT0_IRQHandler ;Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ;Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ;Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ;Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ;Micro-tick Timer + DCD MRT0_IRQHandler ;Multi-rate timer + DCD CTIMER0_IRQHandler ;Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ;Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ;SCTimer/PWM + DCD CTIMER3_IRQHandler ;Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ;Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ;Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ;Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ;Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ;Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ;Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ;Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ;Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD ADC0_SEQA_IRQHandler ;ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ;ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ;ADC0 threshold compare and error. + DCD DMIC0_IRQHandler ;Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ;Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ;USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ;USB device + DCD RTC_IRQHandler ;RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ;Reserved interrupt + DCD Reserved47_IRQHandler ;Reserved interrupt + DCD PIN_INT4_IRQHandler ;Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ;Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ;Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ;Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ;Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ;Standard counter/timer CTIMER4 + DCD RIT_IRQHandler ;Repetitive Interrupt Timer + DCD SPIFI0_IRQHandler ;SPI flash interface + DCD FLEXCOMM8_IRQHandler ;Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM9_IRQHandler ;Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) + DCD SDIO_IRQHandler ;SD/MMC + DCD CAN0_IRQ0_IRQHandler ;CAN0 interrupt0 + DCD CAN0_IRQ1_IRQHandler ;CAN0 interrupt1 + DCD CAN1_IRQ0_IRQHandler ;CAN1 interrupt0 + DCD CAN1_IRQ1_IRQHandler ;CAN1 interrupt1 + DCD USB1_IRQHandler ;USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ;USB1 activity + DCD ETHERNET_IRQHandler ;Ethernet + DCD ETHERNET_PMT_IRQHandler ;Ethernet power management interrupt + DCD ETHERNET_MACLP_IRQHandler ;Ethernet MAC interrupt + DCD EEPROM_IRQHandler ;EEPROM interrupt + DCD LCD_IRQHandler ;LCD interrupt + DCD SHA_IRQHandler ;SHA interrupt + DCD SMARTCARD0_IRQHandler ;Smart card 0 interrupt + DCD SMARTCARD1_IRQHandler ;Smart card 1 interrupt +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + MOVS r0,#56 + LDR r1, =0x40000220 + STR r0, [r1] ;Enable SRAM clock used by Stack + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_SEQA_IRQHandler + PUBWEAK ADC0_SEQA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQA_IRQHandler + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_SEQB_IRQHandler + PUBWEAK ADC0_SEQB_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQB_IRQHandler + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_THCMP_IRQHandler + PUBWEAK ADC0_THCMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_THCMP_IRQHandler + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + + PUBWEAK DMIC0_IRQHandler + PUBWEAK DMIC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMIC0_IRQHandler + LDR R0, =DMIC0_DriverIRQHandler + BX R0 + + PUBWEAK HWVAD0_IRQHandler + PUBWEAK HWVAD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HWVAD0_IRQHandler + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + + PUBWEAK Reserved46_IRQHandler + PUBWEAK Reserved46_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved46_IRQHandler + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + + PUBWEAK Reserved47_IRQHandler + PUBWEAK Reserved47_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved47_IRQHandler + LDR R0, =Reserved47_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT4_IRQHandler + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT5_IRQHandler + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT6_IRQHandler + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK PIN_INT7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT7_IRQHandler + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + + PUBWEAK RIT_IRQHandler + PUBWEAK RIT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RIT_IRQHandler + LDR R0, =RIT_DriverIRQHandler + BX R0 + + PUBWEAK SPIFI0_IRQHandler + PUBWEAK SPIFI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPIFI0_IRQHandler + LDR R0, =SPIFI0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM8_IRQHandler + PUBWEAK FLEXCOMM8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM8_IRQHandler + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM9_IRQHandler + PUBWEAK FLEXCOMM9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM9_IRQHandler + LDR R0, =FLEXCOMM9_DriverIRQHandler + BX R0 + + PUBWEAK SDIO_IRQHandler + PUBWEAK SDIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SDIO_IRQHandler + LDR R0, =SDIO_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_IRQ0_IRQHandler + PUBWEAK CAN0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ0_IRQHandler + LDR R0, =CAN0_IRQ0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_IRQ1_IRQHandler + PUBWEAK CAN0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ1_IRQHandler + LDR R0, =CAN0_IRQ1_DriverIRQHandler + BX R0 + + PUBWEAK CAN1_IRQ0_IRQHandler + PUBWEAK CAN1_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ0_IRQHandler + LDR R0, =CAN1_IRQ0_DriverIRQHandler + BX R0 + + PUBWEAK CAN1_IRQ1_IRQHandler + PUBWEAK CAN1_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ1_IRQHandler + LDR R0, =CAN1_IRQ1_DriverIRQHandler + BX R0 + + PUBWEAK USB1_IRQHandler + PUBWEAK USB1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_IRQHandler + LDR R0, =USB1_DriverIRQHandler + BX R0 + + PUBWEAK USB1_NEEDCLK_IRQHandler + PUBWEAK USB1_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_NEEDCLK_IRQHandler + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_IRQHandler + PUBWEAK ETHERNET_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_IRQHandler + LDR R0, =ETHERNET_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_PMT_IRQHandler + PUBWEAK ETHERNET_PMT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_PMT_IRQHandler + LDR R0, =ETHERNET_PMT_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_MACLP_IRQHandler + PUBWEAK ETHERNET_MACLP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_MACLP_IRQHandler + LDR R0, =ETHERNET_MACLP_DriverIRQHandler + BX R0 + + PUBWEAK EEPROM_IRQHandler + PUBWEAK EEPROM_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EEPROM_IRQHandler + LDR R0, =EEPROM_DriverIRQHandler + BX R0 + + PUBWEAK LCD_IRQHandler + PUBWEAK LCD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LCD_IRQHandler + LDR R0, =LCD_DriverIRQHandler + BX R0 + + PUBWEAK SHA_IRQHandler + PUBWEAK SHA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SHA_IRQHandler + LDR R0, =SHA_DriverIRQHandler + BX R0 + + PUBWEAK SMARTCARD0_IRQHandler + PUBWEAK SMARTCARD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD0_IRQHandler + LDR R0, =SMARTCARD0_DriverIRQHandler + BX R0 + + PUBWEAK SMARTCARD1_IRQHandler + PUBWEAK SMARTCARD1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD1_IRQHandler + LDR R0, =SMARTCARD1_DriverIRQHandler + BX R0 + +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +DMIC0_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +Reserved47_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +RIT_DriverIRQHandler +SPIFI0_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler +FLEXCOMM9_DriverIRQHandler +SDIO_DriverIRQHandler +CAN0_IRQ0_DriverIRQHandler +CAN0_IRQ1_DriverIRQHandler +CAN1_IRQ0_DriverIRQHandler +CAN1_IRQ1_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +ETHERNET_DriverIRQHandler +ETHERNET_PMT_DriverIRQHandler +ETHERNET_MACLP_DriverIRQHandler +EEPROM_DriverIRQHandler +LCD_DriverIRQHandler +SHA_DriverIRQHandler +SMARTCARD0_DriverIRQHandler +SMARTCARD1_DriverIRQHandler +DefaultISR + B . + + END diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.h b/hw/bsp/lpc55/boards/double_m33_express/board.h index dc11e47fc..fec7e9067 100644 --- a/hw/bsp/lpc55/boards/double_m33_express/board.h +++ b/hw/bsp/lpc55/boards/double_m33_express/board.h @@ -37,26 +37,17 @@ #endif // LED -#define LED_PORT 0 -#define LED_PIN 1 +#define LED_PORT BOARD_INITLEDSPINS_LED_PORT +#define LED_PIN BOARD_INITLEDSPINS_LED_PIN #define LED_STATE_ON 1 // WAKE button -#define BUTTON_PORT 0 -#define BUTTON_PIN 5 +#define BUTTON_PORT BOARD_INITBUTTONSPINS_S1_PORT +#define BUTTON_PIN BOARD_INITBUTTONSPINS_S1_PIN #define BUTTON_STATE_ACTIVE 0 -// Number of neopixels -#define NEOPIXEL_NUMBER 2 -#define NEOPIXEL_PORT 0 -#define NEOPIXEL_PIN 27 -#define NEOPIXEL_CH 6 -#define NEOPIXEL_TYPE 0 - // UART #define UART_DEV USART0 -#define UART_RX_PINMUX 0U, 29U, IOCON_PIO_DIG_FUNC1_EN -#define UART_TX_PINMUX 0U, 30U, IOCON_PIO_DIG_FUNC1_EN // XTAL #define XTAL0_CLK_HZ (16 * 1000 * 1000U) diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.mk b/hw/bsp/lpc55/boards/double_m33_express/board.mk index d28700ca7..c0282686f 100644 --- a/hw/bsp/lpc55/boards/double_m33_express/board.mk +++ b/hw/bsp/lpc55/boards/double_m33_express/board.mk @@ -1,10 +1,17 @@ MCU_VARIANT = LPC55S69 MCU_CORE = LPC55S69_cm33_core0 -PORT ?= 1 +RHPORT_DEVICE ?= 1 CFLAGS += -DCPU_LPC55S69JBD100_cm33_core0 LD_FILE = $(BOARD_PATH)/LPC55S69_cm33_core0_uf2.ld +SRC_C += \ + $(TOP)/$(BOARD_PATH)/board/clock_config.c \ + $(TOP)/$(BOARD_PATH)/board/pin_mux.c \ + $(TOP)/$(BOARD_PATH)/board/peripherals.c + +INC += $(TOP)/$(BOARD_PATH)/board + JLINK_DEVICE = LPC55S69 PYOCD_TARGET = LPC55S69 diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.c b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.c new file mode 100644 index 000000000..99a738f18 --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.c @@ -0,0 +1,328 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: FXCOM0_clock.outFreq, value: 48 MHz} +- {id: System_clock.outFreq, value: 144 MHz} +- {id: USB0_clock.outFreq, value: 48 MHz} +- {id: USB1_PHY_clock.outFreq, value: 16 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: PLL1_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_PLL_USB_OUT, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV} +- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0DIV.scale, value: '2'} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL1M_MULT.scale, value: '18'} +- {id: SYSCON.PLL1_PDEC.scale, value: '2'} +- {id: SYSCON.USB0CLKDIV.scale, value: '3'} +- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; /* Enable clk_in to HS USB */ + + POWER_SetVoltageForFreq(144000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(144000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up PLL1 */ + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(1U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(18U), + .pllRate = 144000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + /*!< Set up dividers */ + #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4) + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #else + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #endif + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false); /*!< Set USB0CLKDIV divider to value 3 */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true); /*!< Reset PLL0DIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false); /*!< Set PLL0DIV divider to value 2 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */ + CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK); /*!< Switch USB0_CLK to MAIN_CLK */ + CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0); /*!< Switch FLEXCOMM0 to PLL0_DIV */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.h b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.h new file mode 100644 index 000000000..9112ede78 --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.h @@ -0,0 +1,290 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK 96000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK 100000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK 48000000UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK 144000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK 48000000UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK 16000000UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.c b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.c new file mode 100644 index 000000000..890a20fc6 --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.c @@ -0,0 +1,160 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v15.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 +functionalGroups: +- name: BOARD_InitPeripherals_cm33_core0 + UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1 + called_from_default_init: true + selectedCore: cm33_core0 +- name: BOARD_InitPeripherals_cm33_core1 + UUID: e2041cd4-ebb6-45a5-807f-e0c2dc047d48 + selectedCore: cm33_core1 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + - global_init: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'uart_cmsis_common' +- type_id: 'uart_cmsis_common' +- global_USART_CMSIS_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'gpio_adapter_common' +- type_id: 'gpio_adapter_common' +- global_gpio_adapter_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals_cm33_core0 functional group + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * DEBUG_UART initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'DEBUG_UART' +- type: 'flexcomm_usart' +- mode: 'polling' +- custom_name_enabled: 'true' +- type_id: 'flexcomm_usart_2.2.0' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'FLEXCOMM0' +- config_sets: + - usartConfig_t: + - usartConfig: + - clockSource: 'FXCOMFunctionClock' + - clockSourceFreq: 'ClocksTool_DefaultInit' + - baudRate_Bps: '115200' + - syncMode: 'kUSART_SyncModeDisabled' + - parityMode: 'kUSART_ParityDisabled' + - stopBitCount: 'kUSART_OneStopBit' + - bitCountPerChar: 'kUSART_8BitsPerChar' + - loopback: 'false' + - txWatermark: 'kUSART_TxFifo0' + - rxWatermark: 'kUSART_RxFifo1' + - enableRx: 'true' + - enableTx: 'true' + - clockPolarity: 'kUSART_RxSampleOnFallingEdge' + - enableContinuousSCLK: 'false' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const usart_config_t DEBUG_UART_config = { + .baudRate_Bps = 115200UL, + .syncMode = kUSART_SyncModeDisabled, + .parityMode = kUSART_ParityDisabled, + .stopBitCount = kUSART_OneStopBit, + .bitCountPerChar = kUSART_8BitsPerChar, + .loopback = false, + .txWatermark = kUSART_TxFifo0, + .rxWatermark = kUSART_RxFifo1, + .enableRx = true, + .enableTx = true, + .enableMode32k = false, + .clockPolarity = kUSART_RxSampleOnFallingEdge, + .enableContinuousSCLK = false +}; + +static void DEBUG_UART_init(void) { + /* Reset FLEXCOMM device */ + RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); + USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE); +} + +/*********************************************************************************************************************** + * NVIC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'NVIC' +- type: 'nvic' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'nvic' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'NVIC' +- config_sets: + - nvic: + - interrupt_table: [] + - interrupts: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void NVIC_init(void) { +} */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals_cm33_core0(void) +{ + /* Initialize components */ + DEBUG_UART_init(); +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals_cm33_core0(); +} diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.h b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.h new file mode 100644 index 000000000..fc4d72c33 --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.h @@ -0,0 +1,57 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_usart.h" +#include "fsl_clock.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals_cm33_core0 functional group */ +/* Definition of peripheral ID */ +#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0) +/* Definition of the clock source frequency */ +#define DEBUG_UART_CLOCK_SOURCE 48000000UL + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern const usart_config_t DEBUG_UART_config; + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals_cm33_core0(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.c b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.c new file mode 100644 index 000000000..16e112dfc --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.c @@ -0,0 +1,736 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 +pin_labels: +- {pin_num: '7', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, label: 'P18[2]/SD1_CLK', identifier: LED} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitDEBUG_UARTPins(); + BOARD_InitUSBPins(); + BOARD_InitLEDsPins(); + BOARD_InitBUTTONsPins(); + BOARD_InitPins_Core0(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitDEBUG_UARTPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX); + + const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitSWD_DEBUGPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT0 PIN10 (coords: 21) is configured as SWO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO); + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + else + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } + else + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitUSBPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP} + - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM} + - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM} + - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP} + - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS} + - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp} + - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, + mode: pullUp} + - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp} + - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitUSBPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitUSBPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */ + IOCON_PIO_FUNC7 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS); + + IOCON->PIO[0][28] = ((IOCON->PIO[0][28] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][12] = ((IOCON->PIO[1][12] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][29] = ((IOCON->PIO[1][29] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][30] = ((IOCON->PIO[1][30] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '7', peripheral: GPIO, signal: 'PIO0, 1', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, direction: OUTPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitLEDsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + gpio_pin_config_t LED_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO0_1 (pin 7) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_GPIO, BOARD_INITLEDSPINS_LED_PORT, BOARD_INITLEDSPINS_LED_PIN, &LED_config); + + IOCON->PIO[0][1] = ((IOCON->PIO[0][1] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT01 (pin 7) is configured as PIO0_1. */ + | IOCON_PIO_FUNC(PIO0_1_FUNC_ALT0) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_1_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitBUTTONsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + gpio_pin_config_t S1_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO0_5 (pin 88) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S1_GPIO, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, &S1_config); + + const uint32_t S1 = (/* Pin is configured as PIO0_5 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN5 (coords: 88) is configured as PIO0_5 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, S1); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins_Core0: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins_Core0 + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitPins_Core0(void) +{ +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitI2SPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled, + open_drain: disabled} + - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, + identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitI2SPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitI2SPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */ + IOCON_PIO_FUNC1 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK); + + const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS); + + const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX); + + const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK); + + const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX); + + const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); + + const uint32_t MCLK = (/* Pin is configured as MCLK */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN31 (coords: 91) is configured as MCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitACCELPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitACCELPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitACCELPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t ACCL_INTR_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_19 (pin 58) */ + GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config); + + const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */ + IOCON_PIO_FUNC0 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.h b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.h new file mode 100644 index 000000000..33f000d0a --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.h @@ -0,0 +1,383 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U) +/* @} */ + +/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_ASW_DIS_EN 0x00u /*!<@brief Analog switch is closed (enabled), only for A0 version */ +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U) +/* @} */ + +/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U) +/* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Enables digital function */ +#define IOCON_PIO_DIGITAL_EN 0x0100u +/*! + * @brief Selects pin function 7 */ +#define IOCON_PIO_FUNC7 0x07u +/*! + * @brief Input function is not inverted */ +#define IOCON_PIO_INV_DI 0x00u +/*! + * @brief No addition pin function */ +#define IOCON_PIO_MODE_INACT 0x00u +/*! + * @brief Open drain is disabled */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u +/*! + * @brief Standard mode, output slew rate control is enabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_28_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 7. */ +#define PIO0_28_FUNC_ALT7 0x07u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO0_28_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_12_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_12_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_12_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_29_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_29_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_29_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_30_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_30_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_30_MODE_PULL_UP 0x02u + +/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS + @{ */ +#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U /*!<@brief PORT pin number */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define PIO0_1_DIGIMODE_DIGITAL 0x01u /*!<@brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_1_FUNC_ALT0 0x00u /*!<@brief Selects pin function.: Alternative connection 0. */ + +/*! @name PIO0_1 (number 7), P18[2]/SD1_CLK + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_INIT_GPIO_VALUE 0U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_GPIO_PIN_MASK (1U << 1U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_PIN 1U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_PIN_MASK (1U << 1U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1 + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S1_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S1_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_PIN 5U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S1_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC2 0x02u /*!<@brief Selects pin function 2 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO + @{ */ +#define BOARD_INITI2SPINS_MCLK_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_MCLK_PIN 31U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */ +#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/double_m33_express/double_m33_express.mex b/hw/bsp/lpc55/boards/double_m33_express/double_m33_express.mex new file mode 100644 index 000000000..47d0909d6 --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/double_m33_express.mex @@ -0,0 +1,1283 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="LPCXpresso55S69" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="acf73d26-2bf9-4855-b3be-26068672d98a" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>LPC55S69</processor> + <package>LPC55S69JBD100</package> + <board>LPCXpresso55S69</board> + <board_revision>A2</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="cm33_core0"> + <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/> + <core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <custom_copyright> + <text>/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +</text> + <enabled>true</enabled> + </custom_copyright> + <update_include_paths>true</update_include_paths> + <enable_parallel_routing>true</enable_parallel_routing> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>25.09.10</processor_version> + <pin_labels> + <pin_label pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1" label="P18[2]/SD1_CLK" identifier="LED"/> + </pin_labels> + </pins_profile> + <functions_list> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSWD_DEBUGPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9"> + <pin_features> + <pin_feature name="mode" value="pullDown"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="DEBUG_SWD_SWO"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitUSBPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/> + <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/> + <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/> + <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/> + <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/> + <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitLEDsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO0, 1" pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitBUTTONsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/> + </pins> + </function> + <function name="BOARD_InitPins_Core0"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitPins_Core1"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core1</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core1"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitI2SPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="FC6_I2S_CLK"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitACCELPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>25.09.10</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources/> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings/> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/> + <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/> + <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="PLL1_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/> + <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/> + <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/> + <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/> + <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/> + <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true"> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.2.0</data> + </feature> + </dependency> + <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>25.09.10</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals_cm33_core0" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + </dependencies> + <instances> + <instance name="ACCEL" uuid="b999c56a-0d01-4089-9311-9224db5272f4" type="flexcomm_i2c" type_id="flexcomm_i2c_2.3.0" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_i2c" quick_selection="QS_I2C_Master"> + <setting name="i2c_mode" value="kI2C_Master"/> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="i2c_master_config"> + <setting name="enableMaster" value="true"/> + <setting name="baudRate_Bps" value="100000"/> + <setting name="enableTimeout" value="false"/> + <setting name="timeout_Ms" value="35"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="9fb0504c-6159-43e2-98bb-51d75f06133a" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="usartConfig_t"> + <struct name="usartConfig"> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="syncMode" value="kUSART_SyncModeDisabled"/> + <setting name="parityMode" value="kUSART_ParityDisabled"/> + <setting name="stopBitCount" value="kUSART_OneStopBit"/> + <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/> + <setting name="loopback" value="false"/> + <setting name="txWatermark" value="kUSART_TxFifo0"/> + <setting name="rxWatermark" value="kUSART_RxFifo1"/> + <setting name="enableRx" value="true"/> + <setting name="enableTx" value="true"/> + <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/> + <setting name="enableContinuousSCLK" value="false"/> + </struct> + </config_set> + </instance> + <instance name="LEDS" uuid="f5ad3a56-404b-44cb-8abc-7b25b5551d33" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="SW" uuid="d57ddfca-dc72-486c-a145-c7a2ab1e1a66" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="NVIC" uuid="56761ad9-9b77-4074-917d-de0fde10cd48" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + <functional_group name="BOARD_InitPeripherals_cm33_core1" uuid="e2041cd4-ebb6-45a5-807f-e0c2dc047d48" called_from_default_init="false" id_prefix="" core="cm33_core1"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="NVIC_2" uuid="db546092-4c45-40af-938a-8cc58edd1c4f" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="905d2747-654a-47d9-91f9-81a5c6f9c407" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + <setting name="global_init" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="64cbcd7c-424d-4baf-9681-a60878969fb6" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="generic_can" uuid="b9b018dd-ef4e-41f6-b456-f91b855cb391" type_id="generic_can"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="bafa6375-9184-4272-8102-06ea086041d7" type_id="uart_cmsis_common"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="1710dc7f-381f-4b37-8f78-0fd2f923b3ac" type_id="generic_uart"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_enet" uuid="c7fc4395-b141-4b13-a326-4145e765b2b7" type_id="generic_enet"> + <config_set_global name="global_enet"/> + </component> + <component name="gpio_adapter_common" uuid="b6ee89c2-4c58-4181-94dc-af13d8ae8ea5" type_id="gpio_adapter_common"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + </components> + </periphs> + <tee name="TEE" version="10.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + <tool_options> + <option id="_output_type_" value="c_code"/> + <option id="_legacy_source_names_" value="yes"/> + </tool_options> + </tee_profile> + <functional_group name="BOARD_InitTrustZone" called_from_default_init="true" id_prefix="" prefix_user_defined="true"> + <description></description> + <options/> + <ahb> + <relative_region start="0" size="655360" security="s_priv" memory="PROGRAM_FLASH"/> + <relative_region start="0" size="131072" security="s_priv" memory="BootROM"/> + <relative_region start="0" size="32768" security="s_priv" memory="SRAMX"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM0"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM1"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM2"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM3"/> + <relative_region start="0" size="16384" security="s_priv" memory="SRAM4"/> + <relative_region start="0" size="16384" security="s_priv" memory="AHBperipherals_port10_ahb_secure_ctrl_area"/> + <relative_region start="0" size="16384" security="s_priv" memory="USB_RAM"/> + <masters> + <master id="HASH" security="ns_user"/> + <master id="MCM33C" security="ns_user"/> + <master id="MCM33S" security="ns_user"/> + <master id="PQ" security="ns_user"/> + <master id="SDIO" security="ns_user"/> + <master id="SDMA0" security="ns_user"/> + <master id="SDMA1" security="ns_user"/> + <master id="USBFSD" security="ns_user"/> + <master id="USBFSH" security="ns_user"/> + </masters> + <peripherals> + <peripheral id="ADC0" security="s_priv"/> + <peripheral id="AHB_SECURE_CTRL" security="s_priv"/> + <peripheral id="ANACTRL" security="s_priv"/> + <peripheral id="CASPER" security="s_priv"/> + <peripheral id="CRC_ENGINE" security="s_priv"/> + <peripheral id="CTIMER0" security="s_priv"/> + <peripheral id="CTIMER1" security="s_priv"/> + <peripheral id="CTIMER2" security="s_priv"/> + <peripheral id="CTIMER3" security="s_priv"/> + <peripheral id="CTIMER4" security="s_priv"/> + <peripheral id="DBGMAILBOX" security="s_priv"/> + <peripheral id="DMA0" security="s_priv"/> + <peripheral id="DMA1" security="s_priv"/> + <peripheral id="FLASH" security="s_priv"/> + <peripheral id="FLEXCOMM0" security="s_priv"/> + <peripheral id="FLEXCOMM1" security="s_priv"/> + <peripheral id="FLEXCOMM2" security="s_priv"/> + <peripheral id="FLEXCOMM3" security="s_priv"/> + <peripheral id="FLEXCOMM4" security="s_priv"/> + <peripheral id="FLEXCOMM5" security="s_priv"/> + <peripheral id="FLEXCOMM6" security="s_priv"/> + <peripheral id="FLEXCOMM7" security="s_priv"/> + <peripheral id="GINT0" security="s_priv"/> + <peripheral id="GINT1" security="s_priv"/> + <peripheral id="GPIO" security="s_priv"/> + <peripheral id="HASHCRYPT" security="s_priv"/> + <peripheral id="INPUTMUX" security="s_priv"/> + <peripheral id="IOCON" security="s_priv"/> + <peripheral id="MAILBOX" security="s_priv"/> + <peripheral id="MRT0" security="s_priv"/> + <peripheral id="OSTIMER" security="s_priv"/> + <peripheral id="PINT" security="s_priv"/> + <peripheral id="PLU" security="s_priv"/> + <peripheral id="PMC" security="s_priv"/> + <peripheral id="POWERQUAD" security="s_priv"/> + <peripheral id="PRINCE" security="s_priv"/> + <peripheral id="PUF" security="s_priv"/> + <peripheral id="RNG" security="s_priv"/> + <peripheral id="RTC" security="s_priv"/> + <peripheral id="SCT0" security="s_priv"/> + <peripheral id="SDIF" security="s_priv"/> + <peripheral id="SECGPIO" security="s_priv"/> + <peripheral id="SECPINT" security="s_priv"/> + <peripheral id="SPI8" security="s_priv"/> + <peripheral id="SYSCON" security="s_priv"/> + <peripheral id="SYSCTL" security="s_priv"/> + <peripheral id="USB0" security="s_priv"/> + <peripheral id="USBFSH" security="s_priv"/> + <peripheral id="USBHSD" security="s_priv"/> + <peripheral id="USBHSH" security="s_priv"/> + <peripheral id="USBPHY" security="s_priv"/> + <peripheral id="UTICK0" security="s_priv"/> + <peripheral id="WWDT" security="s_priv"/> + </peripherals> + <interrupts> + <masking> + <interrupt id="acmp_capt_irq" masked="Masked"/> + <interrupt id="adc_irq" masked="Masked"/> + <interrupt id="casper_irq" masked="Masked"/> + <interrupt id="ctimer0_irq" masked="Masked"/> + <interrupt id="ctimer1_irq" masked="Masked"/> + <interrupt id="ctimer2_irq" masked="Masked"/> + <interrupt id="ctimer3_irq" masked="Masked"/> + <interrupt id="ctimer4_irq" masked="Masked"/> + <interrupt id="flexcomm0_irq" masked="Masked"/> + <interrupt id="flexcomm1_irq" masked="Masked"/> + <interrupt id="flexcomm2_irq" masked="Masked"/> + <interrupt id="flexcomm3_irq" masked="Masked"/> + <interrupt id="flexcomm4_irq" masked="Masked"/> + <interrupt id="flexcomm5_irq" masked="Masked"/> + <interrupt id="flexcomm6_irq" masked="Masked"/> + <interrupt id="flexcomm7_irq" masked="Masked"/> + <interrupt id="global_irq0" masked="Masked"/> + <interrupt id="global_irq1" masked="Masked"/> + <interrupt id="lspi_hs_irq" masked="Masked"/> + <interrupt id="mailbox_irq" masked="Masked"/> + <interrupt id="mrt_irq" masked="Masked"/> + <interrupt id="os_event_irq" masked="Masked"/> + <interrupt id="pin_int4" masked="Masked"/> + <interrupt id="pin_int5" masked="Masked"/> + <interrupt id="pin_int6" masked="Masked"/> + <interrupt id="pin_int7" masked="Masked"/> + <interrupt id="pin_irq0" masked="Masked"/> + <interrupt id="pin_irq1" masked="Masked"/> + <interrupt id="pin_irq2" masked="Masked"/> + <interrupt id="pin_irq3" masked="Masked"/> + <interrupt id="plu_irq" masked="Masked"/> + <interrupt id="pq_irq" masked="Masked"/> + <interrupt id="qddkey_irq" masked="Masked"/> + <interrupt id="rtc_irq" masked="Masked"/> + <interrupt id="sct_irq" masked="Masked"/> + <interrupt id="sdio_irq" masked="Masked"/> + <interrupt id="sdma0_irq" masked="Masked"/> + <interrupt id="sdma1_irq" masked="Masked"/> + <interrupt id="sec_hypervisor_call_irq" masked="Masked"/> + <interrupt id="sec_int0" masked="Masked"/> + <interrupt id="sec_int1" masked="Masked"/> + <interrupt id="sec_vio_irq" masked="Masked"/> + <interrupt id="sha_irq" masked="Masked"/> + <interrupt id="sys_irq" masked="Masked"/> + <interrupt id="usb0_irq" masked="Masked"/> + <interrupt id="usb0_needclk_irq" masked="Masked"/> + <interrupt id="usb1_irq" masked="Masked"/> + <interrupt id="usb1_needclk_irq" masked="Masked"/> + <interrupt id="usb1_utmi_irq" masked="Masked"/> + <interrupt id="utick_irq" masked="Masked"/> + </masking> + <security> + <interrupt id="acmp_capt_irq" secure="Secure"/> + <interrupt id="adc_irq" secure="Secure"/> + <interrupt id="casper_irq" secure="Secure"/> + <interrupt id="ctimer0_irq" secure="Secure"/> + <interrupt id="ctimer1_irq" secure="Secure"/> + <interrupt id="ctimer2_irq" secure="Secure"/> + <interrupt id="ctimer3_irq" secure="Secure"/> + <interrupt id="ctimer4_irq" secure="Secure"/> + <interrupt id="flexcomm0_irq" secure="Secure"/> + <interrupt id="flexcomm1_irq" secure="Secure"/> + <interrupt id="flexcomm2_irq" secure="Secure"/> + <interrupt id="flexcomm3_irq" secure="Secure"/> + <interrupt id="flexcomm4_irq" secure="Secure"/> + <interrupt id="flexcomm5_irq" secure="Secure"/> + <interrupt id="flexcomm6_irq" secure="Secure"/> + <interrupt id="flexcomm7_irq" secure="Secure"/> + <interrupt id="global_irq0" secure="Secure"/> + <interrupt id="global_irq1" secure="Secure"/> + <interrupt id="lspi_hs_irq" secure="Secure"/> + <interrupt id="mailbox_irq" secure="Secure"/> + <interrupt id="mrt_irq" secure="Secure"/> + <interrupt id="os_event_irq" secure="Secure"/> + <interrupt id="pin_int4" secure="Secure"/> + <interrupt id="pin_int5" secure="Secure"/> + <interrupt id="pin_int6" secure="Secure"/> + <interrupt id="pin_int7" secure="Secure"/> + <interrupt id="pin_irq0" secure="Secure"/> + <interrupt id="pin_irq1" secure="Secure"/> + <interrupt id="pin_irq2" secure="Secure"/> + <interrupt id="pin_irq3" secure="Secure"/> + <interrupt id="plu_irq" secure="Secure"/> + <interrupt id="pq_irq" secure="Secure"/> + <interrupt id="qddkey_irq" secure="Secure"/> + <interrupt id="rtc_irq" secure="Secure"/> + <interrupt id="sct_irq" secure="Secure"/> + <interrupt id="sdio_irq" secure="Secure"/> + <interrupt id="sdma0_irq" secure="Secure"/> + <interrupt id="sdma1_irq" secure="Secure"/> + <interrupt id="sec_hypervisor_call_irq" secure="Secure"/> + <interrupt id="sec_int0" secure="Secure"/> + <interrupt id="sec_int1" secure="Secure"/> + <interrupt id="sec_vio_irq" secure="Secure"/> + <interrupt id="sha_irq" secure="Secure"/> + <interrupt id="sys_irq" secure="Secure"/> + <interrupt id="usb0_irq" secure="Secure"/> + <interrupt id="usb0_needclk_irq" secure="Secure"/> + <interrupt id="usb1_irq" secure="Secure"/> + <interrupt id="usb1_needclk_irq" secure="Secure"/> + <interrupt id="usb1_utmi_irq" secure="Secure"/> + <interrupt id="utick_irq" secure="Secure"/> + </security> + </interrupts> + <ports> + <port id="pio0"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + <port id="pio1"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + </ports> + </ahb> + <saus> + <sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false"> + <region start="0" size="268435456" security="ns" enabled="true" index="0"/> + <region start="536870912" size="3221225472" security="ns" enabled="true" index="1"/> + <region start="0" size="32" security="ns" enabled="false" index="2"/> + <region start="0" size="32" security="ns" enabled="false" index="3"/> + <region start="0" size="32" security="ns" enabled="false" index="4"/> + <region start="0" size="32" security="ns" enabled="false" index="5"/> + <region start="0" size="32" security="ns" enabled="false" index="6"/> + <region start="0" size="32" security="ns" enabled="false" index="7"/> + </sau> + </saus> + <global_options> + <option id="AIRCR_PRIS" value="no"/> + <option id="AIRCR_BFHFNMINS" value="no"/> + <option id="AIRCR_SYSRESETREQS" value="no"/> + <option id="SCR_SLEEPDEEPS" value="no"/> + <option id="SHCSR_SECUREFAULTENA" value="no"/> + <option id="CPACR_CP0" value="3"/> + <option id="CPACR_CP1" value="3"/> + <option id="CPACR_CP2" value="0"/> + <option id="CPACR_CP3" value="0"/> + <option id="CPACR_CP4" value="0"/> + <option id="CPACR_CP5" value="0"/> + <option id="CPACR_CP6" value="0"/> + <option id="CPACR_CP7" value="0"/> + <option id="CPACR_CP10" value="3"/> + <option id="CPACR_CP11" value="3"/> + <option id="NSACR_CP0" value="yes"/> + <option id="NSACR_CP1" value="yes"/> + <option id="NSACR_CP2" value="no"/> + <option id="NSACR_CP3" value="no"/> + <option id="NSACR_CP4" value="no"/> + <option id="NSACR_CP5" value="no"/> + <option id="NSACR_CP6" value="no"/> + <option id="NSACR_CP7" value="no"/> + <option id="NSACR_CP10" value="yes"/> + <option id="NSACR_CP11" value="yes"/> + <option id="CPPWR_SU0" value="no"/> + <option id="CPPWR_SUS0" value="no"/> + <option id="CPPWR_SU1" value="no"/> + <option id="CPPWR_SUS1" value="no"/> + <option id="CPPWR_SU2" value="no"/> + <option id="CPPWR_SUS2" value="no"/> + <option id="CPPWR_SU3" value="no"/> + <option id="CPPWR_SUS3" value="no"/> + <option id="CPPWR_SU4" value="no"/> + <option id="CPPWR_SUS4" value="no"/> + <option id="CPPWR_SU5" value="no"/> + <option id="CPPWR_SUS5" value="no"/> + <option id="CPPWR_SU6" value="no"/> + <option id="CPPWR_SUS6" value="no"/> + <option id="CPPWR_SU7" value="no"/> + <option id="CPPWR_SUS7" value="no"/> + <option id="CPPWR_SU10" value="no"/> + <option id="CPPWR_SUS10" value="no"/> + <option id="CPPWR_SU11" value="no"/> + <option id="CPPWR_SUS11" value="no"/> + <option id="SEC_GPIO_MASK0_LOCK" value="no"/> + <option id="SEC_GPIO_MASK1_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/> + <option id="MASTER_SEC_LEVEL_LOCK" value="no"/> + <option id="CPU0_LOCK_NS_VTOR" value="no"/> + <option id="CPU0_LOCK_NS_MPU" value="no"/> + <option id="CPU0_LOCK_S_VTAIRCR" value="no"/> + <option id="CPU0_LOCK_S_MPU" value="no"/> + <option id="CPU0_LOCK_SAU" value="no"/> + <option id="CPU0_LOCK_REG_LOCK" value="no"/> + <option id="CPU1_LOCK_NS_VTOR" value="no"/> + <option id="CPU1_LOCK_NS_MPU" value="no"/> + <option id="CPU1_LOCK_REG_LOCK" value="no"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/> + <option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="yes"/> + </global_options> + <mpus> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + </mpus> + </functional_group> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/LPCXpresso55S28.mex b/hw/bsp/lpc55/boards/lpcxpresso55s28/LPCXpresso55S28.mex new file mode 100644 index 000000000..cc59745f9 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/LPCXpresso55S28.mex @@ -0,0 +1,856 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="LPCXpresso55S28" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="485a5299-e2fe-41ab-bc43-80d8d2a4ae02" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>LPC55S28</processor> + <package>LPC55S28JBD100</package> + <board>LPCXpresso55S28</board> + <board_revision>A2</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="cm33_core0"> + <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <custom_copyright> + <text>/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +</text> + <enabled>true</enabled> + </custom_copyright> + <update_include_paths>true</update_include_paths> + <enable_parallel_routing>true</enable_parallel_routing> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>25.09.10</processor_version> + <external_user_signals> + <properties/> + </external_user_signals> + </pins_profile> + <functions_list> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSWD_DEBUGPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9"> + <pin_features> + <pin_feature name="mode" value="pullDown"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="DEBUG_SWD_SWO"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitUSBPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/> + <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/> + <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/> + <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/> + <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/> + <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitLEDsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO1, 4" pin_num="1" pin_signal="PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 6" pin_num="5" pin_signal="PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 7" pin_num="9" pin_signal="PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitBUTTONsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 18" pin_num="64" pin_signal="PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 9" pin_num="10" pin_signal="PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/> + </pins> + </function> + <function name="BOARD_InitPins_Core0"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitI2SPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="FC6_I2S_CLK"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitACCELPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>25.09.10</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources/> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL1_Mode" value="Normal" locked="false"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/> + <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="SYSTICK0_clock.outFreq" value="144 MHz" locked="false" accuracy=""/> + <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/> + <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="PLL1_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/> + <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/> + <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/> + <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/> + <setting id="SYSCON.SYSTICKCLKSEL0.sel" value="SYSCON.SYSTICKCLKDIV0" locked="false"/> + <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/> + <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>N/A</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true"> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.2.0</data> + </feature> + </dependency> + <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>25.09.10</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + </dependencies> + <instances> + <instance name="DEBUG_UART" uuid="30367b6e-4b43-4345-bc10-e4052723fa66" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="usartConfig_t"> + <struct name="usartConfig"> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="syncMode" value="kUSART_SyncModeDisabled"/> + <setting name="parityMode" value="kUSART_ParityDisabled"/> + <setting name="stopBitCount" value="kUSART_OneStopBit"/> + <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/> + <setting name="loopback" value="false"/> + <setting name="txWatermark" value="kUSART_TxFifo0"/> + <setting name="rxWatermark" value="kUSART_RxFifo1"/> + <setting name="enableRx" value="true"/> + <setting name="enableTx" value="true"/> + <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/> + <setting name="enableContinuousSCLK" value="false"/> + </struct> + </config_set> + </instance> + <instance name="ACCEL" uuid="796441cb-6cbf-48af-8003-54caaeb9a132" type="flexcomm_i2c" type_id="flexcomm_i2c_2.0.1" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_i2c" quick_selection="QS_I2C_Master"> + <setting name="i2c_mode" value="kI2C_Master"/> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="i2c_master_config"> + <setting name="enableMaster" value="true"/> + <setting name="baudRate_Bps" value="100000"/> + <setting name="enableTimeout" value="false"/> + </struct> + </config_set> + </instance> + <instance name="SW" uuid="723cdb07-2d95-4daf-94b4-1dfaf0ce6c04" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="LEDS" uuid="7ec70f15-5deb-44fa-b8cf-2d12230a37ac" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="NVIC" uuid="d00e8bd3-19f3-445c-9444-103d6461e0d1" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="4e239a4c-f368-4554-b66e-d1af6e8b1f5d" type_id="system_54b53072540eeeb8f8e9343e71f28176"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + <setting name="global_init" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="7bbbd3b5-f7c2-4cb2-8b95-c037fdaf8e02" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7"> + <config_set_global name="global_messages"/> + </component> + <component name="generic_can" uuid="1560ea56-1bfb-4123-a192-daeeed8f2a1d" type_id="generic_can"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="4305ffdd-d7f2-418a-b81b-8a042e7e4c75" type_id="uart_cmsis_common"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="fe22d2c9-7984-4e79-a7b1-8d26fad750be" type_id="generic_uart"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_enet" uuid="f5a27f2d-a41b-4143-ad53-b9ee09903619" type_id="generic_enet"> + <config_set_global name="global_enet"/> + </component> + <component name="gpio_adapter_common" uuid="03fd1bc8-0fd6-4b47-a53c-1c40e2aa781e" type_id="gpio_adapter_common"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + </components> + </periphs> + <tee name="TEE" version="10.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>N/A</processor_version> + </tee_profile> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake index d935b70e6..b3d6ec722 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake @@ -1,10 +1,17 @@ set(MCU_VARIANT LPC55S28) set(MCU_CORE LPC55S28) +set(MCU_DRIVER_VARIANT LPC55S69) set(JLINK_DEVICE LPC55S28) +set(JLINK_OPTION "-USB 000727031389") + set(PYOCD_TARGET LPC55S28) set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28) +# device fullspeed, host highspeed +set(RHPORT_DEVICE 0) +set(RHPORT_HOST 1) + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CPU_LPC55S28JBD100 diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h index 907aee6a4..c8d3a2b8f 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h @@ -36,20 +36,18 @@ extern "C" { #endif -// LED -#define LED_PORT 1 -#define LED_PIN 6 +// LED: use red LED from generated pin_mux +#define LED_PORT BOARD_INITLEDSPINS_LED_RED_PORT +#define LED_PIN BOARD_INITLEDSPINS_LED_RED_PIN #define LED_STATE_ON 0 -// WAKE button -#define BUTTON_PORT 1 -#define BUTTON_PIN 18 +// WAKE button: use S2 from generated pin_mux +#define BUTTON_PORT BOARD_INITBUTTONSPINS_S2_PORT +#define BUTTON_PIN BOARD_INITBUTTONSPINS_S2_PIN #define BUTTON_STATE_ACTIVE 0 // UART #define UART_DEV USART0 -#define UART_RX_PINMUX 0, 29, IOCON_PIO_DIG_FUNC1_EN -#define UART_TX_PINMUX 0, 30, IOCON_PIO_DIG_FUNC1_EN // XTAL #define XTAL0_CLK_HZ (16 * 1000 * 1000U) diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk index ec0828e41..db2e11fd7 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk @@ -1,9 +1,20 @@ MCU_VARIANT = LPC55S28 MCU_CORE = LPC55S28 -PORT ?= 1 +MCU_DRIVER_VARIANT = LPC55S69 + +# device fullspeed, host highspeed +RHPORT_DEVICE ?= 0 +RHPORT_HOST ?= 1 CFLAGS += -DCPU_LPC55S28JBD100 +SRC_C += \ + $(TOP)/$(BOARD_PATH)/board/clock_config.c \ + $(TOP)/$(BOARD_PATH)/board/pin_mux.c \ + $(TOP)/$(BOARD_PATH)/board/peripherals.c + +INC += $(TOP)/$(BOARD_PATH)/board + JLINK_DEVICE = LPC55S28 PYOCD_TARGET = LPC55S28 diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.c b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.c new file mode 100644 index 000000000..c1e8e0575 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.c @@ -0,0 +1,335 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: LPC55S28 +package_id: LPC55S28JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S28 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} +settings: +- {id: PLL1_Mode, value: Normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: FXCOM0_clock.outFreq, value: 48 MHz} +- {id: SYSTICK0_clock.outFreq, value: 144 MHz} +- {id: System_clock.outFreq, value: 144 MHz} +- {id: USB0_clock.outFreq, value: 48 MHz} +- {id: USB1_PHY_clock.outFreq, value: 16 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: PLL1_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_PLL_USB_OUT, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV} +- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0DIV.scale, value: '2'} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL1M_MULT.scale, value: '18'} +- {id: SYSCON.PLL1_PDEC.scale, value: '2'} +- {id: SYSCON.SYSTICKCLKSEL0.sel, value: SYSCON.SYSTICKCLKDIV0} +- {id: SYSCON.USB0CLKDIV.scale, value: '3'} +- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; /* Enable clk_in to HS USB */ + + POWER_SetVoltageForFreq(144000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(144000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up PLL1 */ + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(1U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(18U), + .pllRate = 144000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk0, 0U, true); /*!< Reset SYSTICKCLKDIV0 divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk0, 1U, false); /*!< Set SYSTICKCLKDIV0 divider to value 1 */ + #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4) + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #else + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #endif + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false); /*!< Set USB0CLKDIV divider to value 3 */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true); /*!< Reset PLL0DIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false); /*!< Set PLL0DIV divider to value 2 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */ + CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK); /*!< Switch USB0_CLK to MAIN_CLK */ + CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0); /*!< Switch FLEXCOMM0 to PLL0_DIV */ + CLOCK_AttachClk(kSYSTICK_DIV0_to_SYSTICK0); /*!< Switch SYSTICK0 to SYSTICK_DIV0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.h new file mode 100644 index 000000000..fdd472793 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.h @@ -0,0 +1,286 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK 96000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK 100000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK 48000000UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK 144000000UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK 144000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK 48000000UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK 16000000UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.c b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.c new file mode 100644 index 000000000..f3b986b6c --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.c @@ -0,0 +1,157 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v15.0 +processor: LPC55S28 +package_id: LPC55S28JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S28 +functionalGroups: +- name: BOARD_InitPeripherals + UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1 + called_from_default_init: true + selectedCore: cm33_core0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system_54b53072540eeeb8f8e9343e71f28176' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + - global_init: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'uart_cmsis_common' +- type_id: 'uart_cmsis_common' +- global_USART_CMSIS_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'gpio_adapter_common' +- type_id: 'gpio_adapter_common' +- global_gpio_adapter_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals functional group + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * DEBUG_UART initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'DEBUG_UART' +- type: 'flexcomm_usart' +- mode: 'polling' +- custom_name_enabled: 'true' +- type_id: 'flexcomm_usart_2.2.0' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'FLEXCOMM0' +- config_sets: + - usartConfig_t: + - usartConfig: + - clockSource: 'FXCOMFunctionClock' + - clockSourceFreq: 'ClocksTool_DefaultInit' + - baudRate_Bps: '115200' + - syncMode: 'kUSART_SyncModeDisabled' + - parityMode: 'kUSART_ParityDisabled' + - stopBitCount: 'kUSART_OneStopBit' + - bitCountPerChar: 'kUSART_8BitsPerChar' + - loopback: 'false' + - txWatermark: 'kUSART_TxFifo0' + - rxWatermark: 'kUSART_RxFifo1' + - enableRx: 'true' + - enableTx: 'true' + - clockPolarity: 'kUSART_RxSampleOnFallingEdge' + - enableContinuousSCLK: 'false' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const usart_config_t DEBUG_UART_config = { + .baudRate_Bps = 115200UL, + .syncMode = kUSART_SyncModeDisabled, + .parityMode = kUSART_ParityDisabled, + .stopBitCount = kUSART_OneStopBit, + .bitCountPerChar = kUSART_8BitsPerChar, + .loopback = false, + .txWatermark = kUSART_TxFifo0, + .rxWatermark = kUSART_RxFifo1, + .enableRx = true, + .enableTx = true, + .enableMode32k = false, + .clockPolarity = kUSART_RxSampleOnFallingEdge, + .enableContinuousSCLK = false +}; + +static void DEBUG_UART_init(void) { + /* Reset FLEXCOMM device */ + RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); + USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE); +} + +/*********************************************************************************************************************** + * NVIC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'NVIC' +- type: 'nvic' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'nvic' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'NVIC' +- config_sets: + - nvic: + - interrupt_table: [] + - interrupts: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void NVIC_init(void) { +} */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals(void) +{ + /* Initialize components */ + DEBUG_UART_init(); +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals(); +} diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.h new file mode 100644 index 000000000..3f498f4af --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.h @@ -0,0 +1,57 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_usart.h" +#include "fsl_clock.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals functional group */ +/* Definition of peripheral ID */ +#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0) +/* Definition of the clock source frequency */ +#define DEBUG_UART_CLOCK_SOURCE 48000000UL + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern const usart_config_t DEBUG_UART_config; + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.c b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.c new file mode 100644 index 000000000..924961d42 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.c @@ -0,0 +1,795 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: LPC55S28 +package_id: LPC55S28JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S28 +external_user_signals: {} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitDEBUG_UARTPins(); + BOARD_InitUSBPins(); + BOARD_InitLEDsPins(); + BOARD_InitBUTTONsPins(); + BOARD_InitPins_Core0(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitDEBUG_UARTPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX); + + const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitSWD_DEBUGPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT0 PIN10 (coords: 21) is configured as SWO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO); + + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitUSBPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP} + - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM} + - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM} + - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP} + - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS} + - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp} + - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp} + - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, + mode: pullUp} + - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitUSBPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitUSBPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */ + IOCON_PIO_FUNC7 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS); + + IOCON->PIO[0][28] = ((IOCON->PIO[0][28] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][12] = ((IOCON->PIO[1][12] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][29] = ((IOCON->PIO[1][29] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][30] = ((IOCON->PIO[1][30] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '1', peripheral: GPIO, signal: 'PIO1, 4', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '5', peripheral: GPIO, signal: 'PIO1, 6', pin_signal: PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '9', peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitLEDsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t LED_BLUE_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_4 (pin 1) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config); + + gpio_pin_config_t LED_RED_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_6 (pin 5) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config); + + gpio_pin_config_t LED_GREEN_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_7 (pin 9) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config); + + const uint32_t LED_BLUE = (/* Pin is configured as PIO1_4 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN4 (coords: 1) is configured as PIO1_4 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, LED_BLUE); + + const uint32_t LED_RED = (/* Pin is configured as PIO1_6 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN6 (coords: 5) is configured as PIO1_6 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, LED_RED); + + const uint32_t LED_GREEN = (/* Pin is configured as PIO1_7 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN7 (coords: 9) is configured as PIO1_7 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, LED_GREEN); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, direction: INPUT, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '10', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12, direction: INPUT, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitBUTTONsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t S1_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO0_5 (pin 88) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S1_GPIO, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, &S1_config); + + gpio_pin_config_t S3_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_9 (pin 10) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S3_GPIO, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, &S3_config); + + gpio_pin_config_t S2_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_18 (pin 64) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S2_GPIO, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, &S2_config); + + const uint32_t S1 = (/* Pin is configured as PIO0_5 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN5 (coords: 88) is configured as PIO0_5 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, S1); + + const uint32_t S2 = (/* Pin is configured as PIO1_18 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN18 (coords: 64) is configured as PIO1_18 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, S2); + + const uint32_t S3 = (/* Pin is configured as PIO1_9 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT1 PIN9 (coords: 10) is configured as PIO1_9 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, S3); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins_Core0: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins_Core0 + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitPins_Core0(void) +{ +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitI2SPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled, + open_drain: disabled} + - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, + identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitI2SPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitI2SPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */ + IOCON_PIO_FUNC1 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK); + + const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS); + + const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX); + + const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK); + + const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX); + + const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); + + const uint32_t MCLK = (/* Pin is configured as MCLK */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN31 (coords: 91) is configured as MCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitACCELPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitACCELPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitACCELPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t ACCL_INTR_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_19 (pin 58) */ + GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config); + + const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */ + IOCON_PIO_FUNC0 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.h new file mode 100644 index 000000000..2a99795ef --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.h @@ -0,0 +1,433 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U) +/* @} */ + +/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U) +/* @} */ + +/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U) +/* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Enables digital function */ +#define IOCON_PIO_DIGITAL_EN 0x0100u +/*! + * @brief Selects pin function 7 */ +#define IOCON_PIO_FUNC7 0x07u +/*! + * @brief Input function is not inverted */ +#define IOCON_PIO_INV_DI 0x00u +/*! + * @brief No addition pin function */ +#define IOCON_PIO_MODE_INACT 0x00u +/*! + * @brief Open drain is disabled */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u +/*! + * @brief Standard mode, output slew rate control is enabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_28_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 7. */ +#define PIO0_28_FUNC_ALT7 0x07u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO0_28_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_12_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_12_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_12_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_29_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_29_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_29_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_30_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_30_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_30_MODE_PULL_UP 0x02u + +/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS + @{ */ +#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U /*!<@brief PORT pin number */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_4 (number 1), R78/P18[5]/LEDR/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_BLUE_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 4U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_BLUE_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_BLUE_PIN 4U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 4U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_6 (number 5), R80/P18[9]/LEDB/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_RED_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_RED_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_RED_PIN 6U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 6U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_7 (number 9), R79/P18[7]/LEDG/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_GREEN_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 7U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_GREEN_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_GREEN_PIN 7U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 7U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1 + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S1_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S1_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_PIN 5U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S1_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_18 (number 64), S2/P18[16]/P24[2]/WAKE/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S2_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S2_GPIO_PIN_MASK (1U << 18U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S2_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S2_PIN 18U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S2_PIN_MASK (1U << 18U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_9 (number 10), S3/P18[1]/PIO1_9_GPIO_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S3_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S3_GPIO_PIN_MASK (1U << 9U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S3_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S3_PIN 9U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S3_PIN_MASK (1U << 9U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC2 0x02u /*!<@brief Selects pin function 2 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO + @{ */ +#define BOARD_INITI2SPINS_MCLK_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_MCLK_PIN 31U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */ +#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/LPCXpresso55S69.mex b/hw/bsp/lpc55/boards/lpcxpresso55s69/LPCXpresso55S69.mex new file mode 100644 index 000000000..9e31688b7 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/LPCXpresso55S69.mex @@ -0,0 +1,1329 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="LPCXpresso55S69" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="acf73d26-2bf9-4855-b3be-26068672d98a" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>LPC55S69</processor> + <package>LPC55S69JBD100</package> + <board>LPCXpresso55S69</board> + <board_revision>A2</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="cm33_core0"> + <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/> + <core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <custom_copyright> + <text>/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +</text> + <enabled>true</enabled> + </custom_copyright> + <update_include_paths>true</update_include_paths> + <enable_parallel_routing>true</enable_parallel_routing> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>25.09.10</processor_version> + </pins_profile> + <functions_list> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSWD_DEBUGPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9"> + <pin_features> + <pin_feature name="mode" value="pullDown"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="DEBUG_SWD_SWO"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitUSBPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/> + <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/> + <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/> + <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/> + <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/> + <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitLEDsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO1, 4" pin_num="1" pin_signal="PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 6" pin_num="5" pin_signal="PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 7" pin_num="9" pin_signal="PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitBUTTONsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 18" pin_num="64" pin_signal="PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 9" pin_num="10" pin_signal="PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/> + </pins> + </function> + <function name="BOARD_InitPins_Core0"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitPins_Core1"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core1</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core1"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitI2SPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="FC6_I2S_CLK"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitACCELPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>25.09.10</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources/> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings/> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/> + <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/> + <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="PLL1_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/> + <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/> + <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/> + <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/> + <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/> + <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true"> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.2.0</data> + </feature> + </dependency> + <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>25.09.10</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals_cm33_core0" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + </dependencies> + <instances> + <instance name="ACCEL" uuid="b999c56a-0d01-4089-9311-9224db5272f4" type="flexcomm_i2c" type_id="flexcomm_i2c_2.3.0" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_i2c" quick_selection="QS_I2C_Master"> + <setting name="i2c_mode" value="kI2C_Master"/> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="i2c_master_config"> + <setting name="enableMaster" value="true"/> + <setting name="baudRate_Bps" value="100000"/> + <setting name="enableTimeout" value="false"/> + <setting name="timeout_Ms" value="35"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="9fb0504c-6159-43e2-98bb-51d75f06133a" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="usartConfig_t"> + <struct name="usartConfig"> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="syncMode" value="kUSART_SyncModeDisabled"/> + <setting name="parityMode" value="kUSART_ParityDisabled"/> + <setting name="stopBitCount" value="kUSART_OneStopBit"/> + <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/> + <setting name="loopback" value="false"/> + <setting name="txWatermark" value="kUSART_TxFifo0"/> + <setting name="rxWatermark" value="kUSART_RxFifo1"/> + <setting name="enableRx" value="true"/> + <setting name="enableTx" value="true"/> + <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/> + <setting name="enableContinuousSCLK" value="false"/> + </struct> + </config_set> + </instance> + <instance name="LEDS" uuid="f5ad3a56-404b-44cb-8abc-7b25b5551d33" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="SW" uuid="d57ddfca-dc72-486c-a145-c7a2ab1e1a66" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="NVIC" uuid="56761ad9-9b77-4074-917d-de0fde10cd48" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + <functional_group name="BOARD_InitPeripherals_cm33_core1" uuid="e2041cd4-ebb6-45a5-807f-e0c2dc047d48" called_from_default_init="false" id_prefix="" core="cm33_core1"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="NVIC_2" uuid="db546092-4c45-40af-938a-8cc58edd1c4f" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="905d2747-654a-47d9-91f9-81a5c6f9c407" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + <setting name="global_init" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="64cbcd7c-424d-4baf-9681-a60878969fb6" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="generic_can" uuid="b9b018dd-ef4e-41f6-b456-f91b855cb391" type_id="generic_can"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="bafa6375-9184-4272-8102-06ea086041d7" type_id="uart_cmsis_common"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="1710dc7f-381f-4b37-8f78-0fd2f923b3ac" type_id="generic_uart"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_enet" uuid="c7fc4395-b141-4b13-a326-4145e765b2b7" type_id="generic_enet"> + <config_set_global name="global_enet"/> + </component> + <component name="gpio_adapter_common" uuid="b6ee89c2-4c58-4181-94dc-af13d8ae8ea5" type_id="gpio_adapter_common"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + </components> + </periphs> + <tee name="TEE" version="10.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + <tool_options> + <option id="_output_type_" value="c_code"/> + <option id="_legacy_source_names_" value="yes"/> + </tool_options> + </tee_profile> + <functional_group name="BOARD_InitTrustZone" called_from_default_init="true" id_prefix="" prefix_user_defined="true"> + <description></description> + <options/> + <ahb> + <relative_region start="0" size="655360" security="s_priv" memory="PROGRAM_FLASH"/> + <relative_region start="0" size="131072" security="s_priv" memory="BootROM"/> + <relative_region start="0" size="32768" security="s_priv" memory="SRAMX"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM0"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM1"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM2"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM3"/> + <relative_region start="0" size="16384" security="s_priv" memory="SRAM4"/> + <relative_region start="0" size="16384" security="s_priv" memory="AHBperipherals_port10_ahb_secure_ctrl_area"/> + <relative_region start="0" size="16384" security="s_priv" memory="USB_RAM"/> + <masters> + <master id="HASH" security="ns_user"/> + <master id="MCM33C" security="ns_user"/> + <master id="MCM33S" security="ns_user"/> + <master id="PQ" security="ns_user"/> + <master id="SDIO" security="ns_user"/> + <master id="SDMA0" security="ns_user"/> + <master id="SDMA1" security="ns_user"/> + <master id="USBFSD" security="ns_user"/> + <master id="USBFSH" security="ns_user"/> + </masters> + <peripherals> + <peripheral id="ADC0" security="s_priv"/> + <peripheral id="AHB_SECURE_CTRL" security="s_priv"/> + <peripheral id="ANACTRL" security="s_priv"/> + <peripheral id="CASPER" security="s_priv"/> + <peripheral id="CRC_ENGINE" security="s_priv"/> + <peripheral id="CTIMER0" security="s_priv"/> + <peripheral id="CTIMER1" security="s_priv"/> + <peripheral id="CTIMER2" security="s_priv"/> + <peripheral id="CTIMER3" security="s_priv"/> + <peripheral id="CTIMER4" security="s_priv"/> + <peripheral id="DBGMAILBOX" security="s_priv"/> + <peripheral id="DMA0" security="s_priv"/> + <peripheral id="DMA1" security="s_priv"/> + <peripheral id="FLASH" security="s_priv"/> + <peripheral id="FLEXCOMM0" security="s_priv"/> + <peripheral id="FLEXCOMM1" security="s_priv"/> + <peripheral id="FLEXCOMM2" security="s_priv"/> + <peripheral id="FLEXCOMM3" security="s_priv"/> + <peripheral id="FLEXCOMM4" security="s_priv"/> + <peripheral id="FLEXCOMM5" security="s_priv"/> + <peripheral id="FLEXCOMM6" security="s_priv"/> + <peripheral id="FLEXCOMM7" security="s_priv"/> + <peripheral id="GINT0" security="s_priv"/> + <peripheral id="GINT1" security="s_priv"/> + <peripheral id="GPIO" security="s_priv"/> + <peripheral id="HASHCRYPT" security="s_priv"/> + <peripheral id="INPUTMUX" security="s_priv"/> + <peripheral id="IOCON" security="s_priv"/> + <peripheral id="MAILBOX" security="s_priv"/> + <peripheral id="MRT0" security="s_priv"/> + <peripheral id="OSTIMER" security="s_priv"/> + <peripheral id="PINT" security="s_priv"/> + <peripheral id="PLU" security="s_priv"/> + <peripheral id="PMC" security="s_priv"/> + <peripheral id="POWERQUAD" security="s_priv"/> + <peripheral id="PRINCE" security="s_priv"/> + <peripheral id="PUF" security="s_priv"/> + <peripheral id="RNG" security="s_priv"/> + <peripheral id="RTC" security="s_priv"/> + <peripheral id="SCT0" security="s_priv"/> + <peripheral id="SDIF" security="s_priv"/> + <peripheral id="SECGPIO" security="s_priv"/> + <peripheral id="SECPINT" security="s_priv"/> + <peripheral id="SPI8" security="s_priv"/> + <peripheral id="SYSCON" security="s_priv"/> + <peripheral id="SYSCTL" security="s_priv"/> + <peripheral id="USB0" security="s_priv"/> + <peripheral id="USBFSH" security="s_priv"/> + <peripheral id="USBHSD" security="s_priv"/> + <peripheral id="USBHSH" security="s_priv"/> + <peripheral id="USBPHY" security="s_priv"/> + <peripheral id="UTICK0" security="s_priv"/> + <peripheral id="WWDT" security="s_priv"/> + </peripherals> + <interrupts> + <masking> + <interrupt id="acmp_capt_irq" masked="Masked"/> + <interrupt id="adc_irq" masked="Masked"/> + <interrupt id="casper_irq" masked="Masked"/> + <interrupt id="ctimer0_irq" masked="Masked"/> + <interrupt id="ctimer1_irq" masked="Masked"/> + <interrupt id="ctimer2_irq" masked="Masked"/> + <interrupt id="ctimer3_irq" masked="Masked"/> + <interrupt id="ctimer4_irq" masked="Masked"/> + <interrupt id="flexcomm0_irq" masked="Masked"/> + <interrupt id="flexcomm1_irq" masked="Masked"/> + <interrupt id="flexcomm2_irq" masked="Masked"/> + <interrupt id="flexcomm3_irq" masked="Masked"/> + <interrupt id="flexcomm4_irq" masked="Masked"/> + <interrupt id="flexcomm5_irq" masked="Masked"/> + <interrupt id="flexcomm6_irq" masked="Masked"/> + <interrupt id="flexcomm7_irq" masked="Masked"/> + <interrupt id="global_irq0" masked="Masked"/> + <interrupt id="global_irq1" masked="Masked"/> + <interrupt id="lspi_hs_irq" masked="Masked"/> + <interrupt id="mailbox_irq" masked="Masked"/> + <interrupt id="mrt_irq" masked="Masked"/> + <interrupt id="os_event_irq" masked="Masked"/> + <interrupt id="pin_int4" masked="Masked"/> + <interrupt id="pin_int5" masked="Masked"/> + <interrupt id="pin_int6" masked="Masked"/> + <interrupt id="pin_int7" masked="Masked"/> + <interrupt id="pin_irq0" masked="Masked"/> + <interrupt id="pin_irq1" masked="Masked"/> + <interrupt id="pin_irq2" masked="Masked"/> + <interrupt id="pin_irq3" masked="Masked"/> + <interrupt id="plu_irq" masked="Masked"/> + <interrupt id="pq_irq" masked="Masked"/> + <interrupt id="qddkey_irq" masked="Masked"/> + <interrupt id="rtc_irq" masked="Masked"/> + <interrupt id="sct_irq" masked="Masked"/> + <interrupt id="sdio_irq" masked="Masked"/> + <interrupt id="sdma0_irq" masked="Masked"/> + <interrupt id="sdma1_irq" masked="Masked"/> + <interrupt id="sec_hypervisor_call_irq" masked="Masked"/> + <interrupt id="sec_int0" masked="Masked"/> + <interrupt id="sec_int1" masked="Masked"/> + <interrupt id="sec_vio_irq" masked="Masked"/> + <interrupt id="sha_irq" masked="Masked"/> + <interrupt id="sys_irq" masked="Masked"/> + <interrupt id="usb0_irq" masked="Masked"/> + <interrupt id="usb0_needclk_irq" masked="Masked"/> + <interrupt id="usb1_irq" masked="Masked"/> + <interrupt id="usb1_needclk_irq" masked="Masked"/> + <interrupt id="usb1_utmi_irq" masked="Masked"/> + <interrupt id="utick_irq" masked="Masked"/> + </masking> + <security> + <interrupt id="acmp_capt_irq" secure="Secure"/> + <interrupt id="adc_irq" secure="Secure"/> + <interrupt id="casper_irq" secure="Secure"/> + <interrupt id="ctimer0_irq" secure="Secure"/> + <interrupt id="ctimer1_irq" secure="Secure"/> + <interrupt id="ctimer2_irq" secure="Secure"/> + <interrupt id="ctimer3_irq" secure="Secure"/> + <interrupt id="ctimer4_irq" secure="Secure"/> + <interrupt id="flexcomm0_irq" secure="Secure"/> + <interrupt id="flexcomm1_irq" secure="Secure"/> + <interrupt id="flexcomm2_irq" secure="Secure"/> + <interrupt id="flexcomm3_irq" secure="Secure"/> + <interrupt id="flexcomm4_irq" secure="Secure"/> + <interrupt id="flexcomm5_irq" secure="Secure"/> + <interrupt id="flexcomm6_irq" secure="Secure"/> + <interrupt id="flexcomm7_irq" secure="Secure"/> + <interrupt id="global_irq0" secure="Secure"/> + <interrupt id="global_irq1" secure="Secure"/> + <interrupt id="lspi_hs_irq" secure="Secure"/> + <interrupt id="mailbox_irq" secure="Secure"/> + <interrupt id="mrt_irq" secure="Secure"/> + <interrupt id="os_event_irq" secure="Secure"/> + <interrupt id="pin_int4" secure="Secure"/> + <interrupt id="pin_int5" secure="Secure"/> + <interrupt id="pin_int6" secure="Secure"/> + <interrupt id="pin_int7" secure="Secure"/> + <interrupt id="pin_irq0" secure="Secure"/> + <interrupt id="pin_irq1" secure="Secure"/> + <interrupt id="pin_irq2" secure="Secure"/> + <interrupt id="pin_irq3" secure="Secure"/> + <interrupt id="plu_irq" secure="Secure"/> + <interrupt id="pq_irq" secure="Secure"/> + <interrupt id="qddkey_irq" secure="Secure"/> + <interrupt id="rtc_irq" secure="Secure"/> + <interrupt id="sct_irq" secure="Secure"/> + <interrupt id="sdio_irq" secure="Secure"/> + <interrupt id="sdma0_irq" secure="Secure"/> + <interrupt id="sdma1_irq" secure="Secure"/> + <interrupt id="sec_hypervisor_call_irq" secure="Secure"/> + <interrupt id="sec_int0" secure="Secure"/> + <interrupt id="sec_int1" secure="Secure"/> + <interrupt id="sec_vio_irq" secure="Secure"/> + <interrupt id="sha_irq" secure="Secure"/> + <interrupt id="sys_irq" secure="Secure"/> + <interrupt id="usb0_irq" secure="Secure"/> + <interrupt id="usb0_needclk_irq" secure="Secure"/> + <interrupt id="usb1_irq" secure="Secure"/> + <interrupt id="usb1_needclk_irq" secure="Secure"/> + <interrupt id="usb1_utmi_irq" secure="Secure"/> + <interrupt id="utick_irq" secure="Secure"/> + </security> + </interrupts> + <ports> + <port id="pio0"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + <port id="pio1"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + </ports> + </ahb> + <saus> + <sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false"> + <region start="0" size="268435456" security="ns" enabled="true" index="0"/> + <region start="536870912" size="3221225472" security="ns" enabled="true" index="1"/> + <region start="0" size="32" security="ns" enabled="false" index="2"/> + <region start="0" size="32" security="ns" enabled="false" index="3"/> + <region start="0" size="32" security="ns" enabled="false" index="4"/> + <region start="0" size="32" security="ns" enabled="false" index="5"/> + <region start="0" size="32" security="ns" enabled="false" index="6"/> + <region start="0" size="32" security="ns" enabled="false" index="7"/> + </sau> + </saus> + <global_options> + <option id="AIRCR_PRIS" value="no"/> + <option id="AIRCR_BFHFNMINS" value="no"/> + <option id="AIRCR_SYSRESETREQS" value="no"/> + <option id="SCR_SLEEPDEEPS" value="no"/> + <option id="SHCSR_SECUREFAULTENA" value="no"/> + <option id="CPACR_CP0" value="3"/> + <option id="CPACR_CP1" value="3"/> + <option id="CPACR_CP2" value="0"/> + <option id="CPACR_CP3" value="0"/> + <option id="CPACR_CP4" value="0"/> + <option id="CPACR_CP5" value="0"/> + <option id="CPACR_CP6" value="0"/> + <option id="CPACR_CP7" value="0"/> + <option id="CPACR_CP10" value="3"/> + <option id="CPACR_CP11" value="3"/> + <option id="NSACR_CP0" value="yes"/> + <option id="NSACR_CP1" value="yes"/> + <option id="NSACR_CP2" value="no"/> + <option id="NSACR_CP3" value="no"/> + <option id="NSACR_CP4" value="no"/> + <option id="NSACR_CP5" value="no"/> + <option id="NSACR_CP6" value="no"/> + <option id="NSACR_CP7" value="no"/> + <option id="NSACR_CP10" value="yes"/> + <option id="NSACR_CP11" value="yes"/> + <option id="CPPWR_SU0" value="no"/> + <option id="CPPWR_SUS0" value="no"/> + <option id="CPPWR_SU1" value="no"/> + <option id="CPPWR_SUS1" value="no"/> + <option id="CPPWR_SU2" value="no"/> + <option id="CPPWR_SUS2" value="no"/> + <option id="CPPWR_SU3" value="no"/> + <option id="CPPWR_SUS3" value="no"/> + <option id="CPPWR_SU4" value="no"/> + <option id="CPPWR_SUS4" value="no"/> + <option id="CPPWR_SU5" value="no"/> + <option id="CPPWR_SUS5" value="no"/> + <option id="CPPWR_SU6" value="no"/> + <option id="CPPWR_SUS6" value="no"/> + <option id="CPPWR_SU7" value="no"/> + <option id="CPPWR_SUS7" value="no"/> + <option id="CPPWR_SU10" value="no"/> + <option id="CPPWR_SUS10" value="no"/> + <option id="CPPWR_SU11" value="no"/> + <option id="CPPWR_SUS11" value="no"/> + <option id="SEC_GPIO_MASK0_LOCK" value="no"/> + <option id="SEC_GPIO_MASK1_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/> + <option id="MASTER_SEC_LEVEL_LOCK" value="no"/> + <option id="CPU0_LOCK_NS_VTOR" value="no"/> + <option id="CPU0_LOCK_NS_MPU" value="no"/> + <option id="CPU0_LOCK_S_VTAIRCR" value="no"/> + <option id="CPU0_LOCK_S_MPU" value="no"/> + <option id="CPU0_LOCK_SAU" value="no"/> + <option id="CPU0_LOCK_REG_LOCK" value="no"/> + <option id="CPU1_LOCK_NS_VTOR" value="no"/> + <option id="CPU1_LOCK_NS_MPU" value="no"/> + <option id="CPU1_LOCK_REG_LOCK" value="no"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/> + <option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="yes"/> + </global_options> + <mpus> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + </mpus> + </functional_group> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake index f46775b27..59f7d6329 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake @@ -2,9 +2,15 @@ set(MCU_VARIANT LPC55S69) set(MCU_CORE LPC55S69_cm33_core0) set(JLINK_DEVICE LPC55S69_M33_0) +set(JLINK_OPTION "-USB 000727648789") + set(PYOCD_TARGET LPC55S69) set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69) +# device highspeed, host fullspeed +set(RHPORT_DEVICE 1) +set(RHPORT_HOST 0) + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CPU_LPC55S69JBD100_cm33_core0 diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h index e18d5bbad..3b81411a1 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h @@ -36,20 +36,18 @@ extern "C" { #endif -// LED -#define LED_PORT 1 -#define LED_PIN 6 +// LED: use red LED from generated pin_mux +#define LED_PORT BOARD_INITLEDSPINS_LED_RED_PORT +#define LED_PIN BOARD_INITLEDSPINS_LED_RED_PIN #define LED_STATE_ON 0 -// WAKE button -#define BUTTON_PORT 1 -#define BUTTON_PIN 18 +// WAKE button: use S2 from generated pin_mux +#define BUTTON_PORT BOARD_INITBUTTONSPINS_S2_PORT +#define BUTTON_PIN BOARD_INITBUTTONSPINS_S2_PIN #define BUTTON_STATE_ACTIVE 0 // UART #define UART_DEV USART0 -#define UART_RX_PINMUX 0, 29, IOCON_PIO_DIG_FUNC1_EN -#define UART_TX_PINMUX 0, 30, IOCON_PIO_DIG_FUNC1_EN // XTAL #define XTAL0_CLK_HZ (16 * 1000 * 1000U) diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk index 73edc88a9..e92c46f05 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk @@ -1,9 +1,19 @@ MCU_VARIANT = LPC55S69 MCU_CORE = LPC55S69_cm33_core0 -PORT ?= 1 + +# device highspeed, host fullspeed +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 CFLAGS += -DCPU_LPC55S69JBD100_cm33_core0 +SRC_C += \ + $(TOP)/$(BOARD_PATH)/board/clock_config.c \ + $(TOP)/$(BOARD_PATH)/board/pin_mux.c \ + $(TOP)/$(BOARD_PATH)/board/peripherals.c + +INC += $(TOP)/$(BOARD_PATH)/board + JLINK_DEVICE = LPC55S69 PYOCD_TARGET = LPC55S69 diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.c b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.c new file mode 100644 index 000000000..99a738f18 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.c @@ -0,0 +1,328 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: FXCOM0_clock.outFreq, value: 48 MHz} +- {id: System_clock.outFreq, value: 144 MHz} +- {id: USB0_clock.outFreq, value: 48 MHz} +- {id: USB1_PHY_clock.outFreq, value: 16 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: PLL1_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_PLL_USB_OUT, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV} +- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0DIV.scale, value: '2'} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL1M_MULT.scale, value: '18'} +- {id: SYSCON.PLL1_PDEC.scale, value: '2'} +- {id: SYSCON.USB0CLKDIV.scale, value: '3'} +- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; /* Enable clk_in to HS USB */ + + POWER_SetVoltageForFreq(144000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(144000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up PLL1 */ + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(1U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(18U), + .pllRate = 144000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + /*!< Set up dividers */ + #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4) + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #else + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #endif + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false); /*!< Set USB0CLKDIV divider to value 3 */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true); /*!< Reset PLL0DIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false); /*!< Set PLL0DIV divider to value 2 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */ + CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK); /*!< Switch USB0_CLK to MAIN_CLK */ + CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0); /*!< Switch FLEXCOMM0 to PLL0_DIV */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.h new file mode 100644 index 000000000..9112ede78 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.h @@ -0,0 +1,290 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK 96000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK 100000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK 48000000UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK 144000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK 48000000UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK 16000000UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.c b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.c new file mode 100644 index 000000000..890a20fc6 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.c @@ -0,0 +1,160 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v15.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 +functionalGroups: +- name: BOARD_InitPeripherals_cm33_core0 + UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1 + called_from_default_init: true + selectedCore: cm33_core0 +- name: BOARD_InitPeripherals_cm33_core1 + UUID: e2041cd4-ebb6-45a5-807f-e0c2dc047d48 + selectedCore: cm33_core1 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + - global_init: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'uart_cmsis_common' +- type_id: 'uart_cmsis_common' +- global_USART_CMSIS_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'gpio_adapter_common' +- type_id: 'gpio_adapter_common' +- global_gpio_adapter_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals_cm33_core0 functional group + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * DEBUG_UART initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'DEBUG_UART' +- type: 'flexcomm_usart' +- mode: 'polling' +- custom_name_enabled: 'true' +- type_id: 'flexcomm_usart_2.2.0' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'FLEXCOMM0' +- config_sets: + - usartConfig_t: + - usartConfig: + - clockSource: 'FXCOMFunctionClock' + - clockSourceFreq: 'ClocksTool_DefaultInit' + - baudRate_Bps: '115200' + - syncMode: 'kUSART_SyncModeDisabled' + - parityMode: 'kUSART_ParityDisabled' + - stopBitCount: 'kUSART_OneStopBit' + - bitCountPerChar: 'kUSART_8BitsPerChar' + - loopback: 'false' + - txWatermark: 'kUSART_TxFifo0' + - rxWatermark: 'kUSART_RxFifo1' + - enableRx: 'true' + - enableTx: 'true' + - clockPolarity: 'kUSART_RxSampleOnFallingEdge' + - enableContinuousSCLK: 'false' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const usart_config_t DEBUG_UART_config = { + .baudRate_Bps = 115200UL, + .syncMode = kUSART_SyncModeDisabled, + .parityMode = kUSART_ParityDisabled, + .stopBitCount = kUSART_OneStopBit, + .bitCountPerChar = kUSART_8BitsPerChar, + .loopback = false, + .txWatermark = kUSART_TxFifo0, + .rxWatermark = kUSART_RxFifo1, + .enableRx = true, + .enableTx = true, + .enableMode32k = false, + .clockPolarity = kUSART_RxSampleOnFallingEdge, + .enableContinuousSCLK = false +}; + +static void DEBUG_UART_init(void) { + /* Reset FLEXCOMM device */ + RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); + USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE); +} + +/*********************************************************************************************************************** + * NVIC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'NVIC' +- type: 'nvic' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'nvic' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'NVIC' +- config_sets: + - nvic: + - interrupt_table: [] + - interrupts: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void NVIC_init(void) { +} */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals_cm33_core0(void) +{ + /* Initialize components */ + DEBUG_UART_init(); +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals_cm33_core0(); +} diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.h new file mode 100644 index 000000000..fc4d72c33 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.h @@ -0,0 +1,57 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_usart.h" +#include "fsl_clock.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals_cm33_core0 functional group */ +/* Definition of peripheral ID */ +#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0) +/* Definition of the clock source frequency */ +#define DEBUG_UART_CLOCK_SOURCE 48000000UL + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern const usart_config_t DEBUG_UART_config; + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals_cm33_core0(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.c b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.c new file mode 100644 index 000000000..979e7d065 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.c @@ -0,0 +1,860 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitDEBUG_UARTPins(); + BOARD_InitUSBPins(); + BOARD_InitLEDsPins(); + BOARD_InitBUTTONsPins(); + BOARD_InitPins_Core0(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitDEBUG_UARTPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX); + + const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitSWD_DEBUGPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT0 PIN10 (coords: 21) is configured as SWO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO); + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + else + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } + else + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitUSBPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP} + - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM} + - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM} + - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP} + - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS} + - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp} + - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, + mode: pullUp} + - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp} + - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitUSBPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitUSBPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */ + IOCON_PIO_FUNC7 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS); + + IOCON->PIO[0][28] = ((IOCON->PIO[0][28] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][12] = ((IOCON->PIO[1][12] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][29] = ((IOCON->PIO[1][29] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][30] = ((IOCON->PIO[1][30] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '1', peripheral: GPIO, signal: 'PIO1, 4', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '5', peripheral: GPIO, signal: 'PIO1, 6', pin_signal: PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '9', peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitLEDsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t LED_BLUE_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_4 (pin 1) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config); + + gpio_pin_config_t LED_RED_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_6 (pin 5) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config); + + gpio_pin_config_t LED_GREEN_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_7 (pin 9) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config); + + const uint32_t LED_BLUE = (/* Pin is configured as PIO1_4 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN4 (coords: 1) is configured as PIO1_4 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, LED_BLUE); + + const uint32_t LED_RED = (/* Pin is configured as PIO1_6 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN6 (coords: 5) is configured as PIO1_6 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, LED_RED); + + const uint32_t LED_GREEN = (/* Pin is configured as PIO1_7 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN7 (coords: 9) is configured as PIO1_7 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, LED_GREEN); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, direction: INPUT, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '10', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12, direction: INPUT, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitBUTTONsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t S1_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO0_5 (pin 88) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S1_GPIO, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, &S1_config); + + gpio_pin_config_t S3_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_9 (pin 10) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S3_GPIO, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, &S3_config); + + gpio_pin_config_t S2_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_18 (pin 64) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S2_GPIO, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, &S2_config); + + const uint32_t S1 = (/* Pin is configured as PIO0_5 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN5 (coords: 88) is configured as PIO0_5 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, S1); + + const uint32_t S2 = (/* Pin is configured as PIO1_18 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN18 (coords: 64) is configured as PIO1_18 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, S2); + + if (Chip_GetVersion()==1) + { + const uint32_t S3 = (/* Pin is configured as PIO1_9 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT1 PIN9 (coords: 10) is configured as PIO1_9 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, S3); + } + else + { + const uint32_t S3 = (/* Pin is configured as PIO1_9 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT1 PIN9 (coords: 10) is configured as PIO1_9 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, S3); + } +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins_Core0: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins_Core0 + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitPins_Core0(void) +{ +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitI2SPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled, + open_drain: disabled} + - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, + identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitI2SPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitI2SPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */ + IOCON_PIO_FUNC1 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK); + + const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS); + + const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX); + + const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK); + + const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX); + + const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); + + const uint32_t MCLK = (/* Pin is configured as MCLK */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN31 (coords: 91) is configured as MCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitACCELPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitACCELPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitACCELPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t ACCL_INTR_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_19 (pin 58) */ + GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config); + + const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */ + IOCON_PIO_FUNC0 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.h new file mode 100644 index 000000000..3925c937a --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.h @@ -0,0 +1,435 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U) +/* @} */ + +/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_ASW_DIS_EN 0x00u /*!<@brief Analog switch is closed (enabled), only for A0 version */ +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U) +/* @} */ + +/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U) +/* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Enables digital function */ +#define IOCON_PIO_DIGITAL_EN 0x0100u +/*! + * @brief Selects pin function 7 */ +#define IOCON_PIO_FUNC7 0x07u +/*! + * @brief Input function is not inverted */ +#define IOCON_PIO_INV_DI 0x00u +/*! + * @brief No addition pin function */ +#define IOCON_PIO_MODE_INACT 0x00u +/*! + * @brief Open drain is disabled */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u +/*! + * @brief Standard mode, output slew rate control is enabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_28_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 7. */ +#define PIO0_28_FUNC_ALT7 0x07u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO0_28_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_12_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_12_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_12_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_29_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_29_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_29_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_30_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_30_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_30_MODE_PULL_UP 0x02u + +/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS + @{ */ +#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U /*!<@brief PORT pin number */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_4 (number 1), R78/P18[5]/LEDR/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_BLUE_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 4U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_BLUE_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_BLUE_PIN 4U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 4U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_6 (number 5), R80/P18[9]/LEDB/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_RED_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_RED_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_RED_PIN 6U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 6U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_7 (number 9), R79/P18[7]/LEDG/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_GREEN_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 7U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_GREEN_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_GREEN_PIN 7U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 7U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DIS_EN 0x00u /*!<@brief Analog switch is closed (enabled), only for A0 version */ +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1 + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S1_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S1_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_PIN 5U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S1_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_18 (number 64), S2/P18[16]/P24[2]/WAKE/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S2_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S2_GPIO_PIN_MASK (1U << 18U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S2_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S2_PIN 18U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S2_PIN_MASK (1U << 18U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_9 (number 10), S3/P18[1]/PIO1_9_GPIO_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S3_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S3_GPIO_PIN_MASK (1U << 9U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S3_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S3_PIN 9U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S3_PIN_MASK (1U << 9U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC2 0x02u /*!<@brief Selects pin function 2 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO + @{ */ +#define BOARD_INITI2SPINS_MCLK_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_MCLK_PIN 31U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */ +#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/mcu_link/board.cmake b/hw/bsp/lpc55/boards/mcu_link/board.cmake index fd7cb6de6..bbaaf6648 100644 --- a/hw/bsp/lpc55/boards/mcu_link/board.cmake +++ b/hw/bsp/lpc55/boards/mcu_link/board.cmake @@ -7,8 +7,6 @@ set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC - CPU_LPC55S69JBD100_cm33_core0 - # port 1 is highspeed - # BOARD_TUD_RHPORT=1 + CPU_LPC55S69JBD64_cm33_core0 ) endfunction() diff --git a/hw/bsp/lpc55/boards/mcu_link/board.h b/hw/bsp/lpc55/boards/mcu_link/board.h index 1d71b3e79..d3c133f40 100644 --- a/hw/bsp/lpc55/boards/mcu_link/board.h +++ b/hw/bsp/lpc55/boards/mcu_link/board.h @@ -37,19 +37,17 @@ #endif // LED -#define LED_PORT 0 -#define LED_PIN 5 +#define LED_PORT BOARD_INITLEDSPINS_LED_PORT +#define LED_PIN BOARD_INITLEDSPINS_LED_PIN #define LED_STATE_ON 0 // WAKE button (Dummy, use unused pin -#define BUTTON_PORT 0 -#define BUTTON_PIN 30 +#define BUTTON_PORT BOARD_INITBUTTONSPINS_BUTTON_PORT +#define BUTTON_PIN BOARD_INITBUTTONSPINS_BUTTON_PIN #define BUTTON_STATE_ACTIVE 0 // UART #define UART_DEV USART0 -#define UART_RX_PINMUX 0, 24, IOCON_PIO_DIG_FUNC1_EN -#define UART_TX_PINMUX 0, 25, IOCON_PIO_DIG_FUNC1_EN // XTAL #define XTAL0_CLK_HZ (16 * 1000 * 1000U) diff --git a/hw/bsp/lpc55/boards/mcu_link/board.mk b/hw/bsp/lpc55/boards/mcu_link/board.mk index ceb1d0ebc..4f686a88f 100644 --- a/hw/bsp/lpc55/boards/mcu_link/board.mk +++ b/hw/bsp/lpc55/boards/mcu_link/board.mk @@ -1,9 +1,16 @@ MCU_VARIANT = LPC55S69 MCU_CORE = LPC55S69_cm33_core0 -PORT ?= 1 +RHPORT_DEVICE ?= 1 CFLAGS += -DCPU_LPC55S69JBD64_cm33_core0 +SRC_C += \ + $(TOP)/$(BOARD_PATH)/board/clock_config.c \ + $(TOP)/$(BOARD_PATH)/board/pin_mux.c \ + $(TOP)/$(BOARD_PATH)/board/peripherals.c + +INC += $(TOP)/$(BOARD_PATH)/board + JLINK_DEVICE = LPC55S69 PYOCD_TARGET = LPC55S69 diff --git a/hw/bsp/lpc55/boards/mcu_link/board/clock_config.c b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.c new file mode 100644 index 000000000..99a738f18 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.c @@ -0,0 +1,328 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: FXCOM0_clock.outFreq, value: 48 MHz} +- {id: System_clock.outFreq, value: 144 MHz} +- {id: USB0_clock.outFreq, value: 48 MHz} +- {id: USB1_PHY_clock.outFreq, value: 16 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: PLL1_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_PLL_USB_OUT, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV} +- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0DIV.scale, value: '2'} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL1M_MULT.scale, value: '18'} +- {id: SYSCON.PLL1_PDEC.scale, value: '2'} +- {id: SYSCON.USB0CLKDIV.scale, value: '3'} +- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; /* Enable clk_in to HS USB */ + + POWER_SetVoltageForFreq(144000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(144000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up PLL1 */ + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(1U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(18U), + .pllRate = 144000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + /*!< Set up dividers */ + #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4) + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #else + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #endif + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false); /*!< Set USB0CLKDIV divider to value 3 */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true); /*!< Reset PLL0DIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false); /*!< Set PLL0DIV divider to value 2 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */ + CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK); /*!< Switch USB0_CLK to MAIN_CLK */ + CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0); /*!< Switch FLEXCOMM0 to PLL0_DIV */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} diff --git a/hw/bsp/lpc55/boards/mcu_link/board/clock_config.h b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.h new file mode 100644 index 000000000..9112ede78 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.h @@ -0,0 +1,290 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK 96000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK 100000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK 48000000UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK 144000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK 48000000UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK 16000000UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/lpc55/boards/mcu_link/board/peripherals.c b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.c new file mode 100644 index 000000000..890a20fc6 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.c @@ -0,0 +1,160 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v15.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 +functionalGroups: +- name: BOARD_InitPeripherals_cm33_core0 + UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1 + called_from_default_init: true + selectedCore: cm33_core0 +- name: BOARD_InitPeripherals_cm33_core1 + UUID: e2041cd4-ebb6-45a5-807f-e0c2dc047d48 + selectedCore: cm33_core1 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + - global_init: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'uart_cmsis_common' +- type_id: 'uart_cmsis_common' +- global_USART_CMSIS_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'gpio_adapter_common' +- type_id: 'gpio_adapter_common' +- global_gpio_adapter_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals_cm33_core0 functional group + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * DEBUG_UART initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'DEBUG_UART' +- type: 'flexcomm_usart' +- mode: 'polling' +- custom_name_enabled: 'true' +- type_id: 'flexcomm_usart_2.2.0' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'FLEXCOMM0' +- config_sets: + - usartConfig_t: + - usartConfig: + - clockSource: 'FXCOMFunctionClock' + - clockSourceFreq: 'ClocksTool_DefaultInit' + - baudRate_Bps: '115200' + - syncMode: 'kUSART_SyncModeDisabled' + - parityMode: 'kUSART_ParityDisabled' + - stopBitCount: 'kUSART_OneStopBit' + - bitCountPerChar: 'kUSART_8BitsPerChar' + - loopback: 'false' + - txWatermark: 'kUSART_TxFifo0' + - rxWatermark: 'kUSART_RxFifo1' + - enableRx: 'true' + - enableTx: 'true' + - clockPolarity: 'kUSART_RxSampleOnFallingEdge' + - enableContinuousSCLK: 'false' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const usart_config_t DEBUG_UART_config = { + .baudRate_Bps = 115200UL, + .syncMode = kUSART_SyncModeDisabled, + .parityMode = kUSART_ParityDisabled, + .stopBitCount = kUSART_OneStopBit, + .bitCountPerChar = kUSART_8BitsPerChar, + .loopback = false, + .txWatermark = kUSART_TxFifo0, + .rxWatermark = kUSART_RxFifo1, + .enableRx = true, + .enableTx = true, + .enableMode32k = false, + .clockPolarity = kUSART_RxSampleOnFallingEdge, + .enableContinuousSCLK = false +}; + +static void DEBUG_UART_init(void) { + /* Reset FLEXCOMM device */ + RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); + USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE); +} + +/*********************************************************************************************************************** + * NVIC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'NVIC' +- type: 'nvic' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'nvic' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'NVIC' +- config_sets: + - nvic: + - interrupt_table: [] + - interrupts: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void NVIC_init(void) { +} */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals_cm33_core0(void) +{ + /* Initialize components */ + DEBUG_UART_init(); +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals_cm33_core0(); +} diff --git a/hw/bsp/lpc55/boards/mcu_link/board/peripherals.h b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.h new file mode 100644 index 000000000..fc4d72c33 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.h @@ -0,0 +1,57 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_usart.h" +#include "fsl_clock.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals_cm33_core0 functional group */ +/* Definition of peripheral ID */ +#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0) +/* Definition of the clock source frequency */ +#define DEBUG_UART_CLOCK_SOURCE 48000000UL + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern const usart_config_t DEBUG_UART_config; + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals_cm33_core0(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.c b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.c new file mode 100644 index 000000000..a673302e5 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.c @@ -0,0 +1,839 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 +expansion_headers: +- id: lpc_style_arduino + name: LPCXpresso V3 (Arduino compatible) + connectors: + - id: C1 + name: P16 + pins: + - {id: 8, name: 3.3V, external_signal_types: power_supply_3.3V} + - {id: 10, name: RESET, pin_num: '32', pin_signal: RESETN} + - {id: 12, name: 3.3V, external_signal_types: power_supply_3.3V} + - {id: 14, name: 5V, external_signal_types: power_supply_5V} + - {id: 16, name: GND, external_signal_types: ground} + - {id: 18, name: GND, external_signal_types: ground} + - {id: 20, name: 5V, external_signal_types: power_supply_5V} + - id: C2 + name: P17 + pins: + - {id: 1, name: D15, pin_num: '4', pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2} + - {id: 3, name: D14, pin_num: '30', pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3} + - {id: 5, name: 3.3V, external_signal_types: power_supply_3.3V} + - {id: 6, pin_num: '93', pin_signal: PIO1_11/FC1_TXD_SCL_MISO_WS/CT_INP5/USB0_VBUS} + - {id: 7, name: GND, external_signal_types: ground} + - {id: 8, pin_num: '88', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5} + - {id: 9, name: D13, pin_num: '61', pin_signal: PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5} + - {id: 10, pin_num: '74', pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS} + - {id: 11, name: D12, pin_num: '62', pin_signal: PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6} + - {id: 12, pin_num: '90', pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19} + - {id: 13, name: D11, pin_num: '60', pin_signal: PIO0_26/FC2_RXD_SDA_MOSI_DATA/CLKOUT/CT_INP14/SCT0_OUT5/USB0_IDVALUE/FC0_SCK/HS_SPI_MOSI/SECURE_GPIO0_26} + - {id: 14, pin_num: '76', pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21} + - {id: 15, name: D10, pin_num: '59', pin_signal: PIO1_1/FC3_RXD_SDA_MOSI_DATA/CT_INP3/SCT_GPI5/HS_SPI_SSEL1/USB1_OVERCURRENTN/PLU_OUT4} + - {id: 16, pin_num: '85', pin_signal: PIO1_27/FC2_RTS_SCL_SSEL1/SD0_D4/CTIMER0_MAT3/CLKOUT/PLU_IN4} + - {id: 17, name: D9, pin_num: '31', pin_signal: PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0} + - {id: 18, pin_num: '73', pin_signal: PIO1_28/FC7_SCK/SD0_D5/CT_INP2/PLU_IN3} + - {id: 19, name: D8, pin_num: '24', pin_signal: PIO1_8/FC0_CTS_SDA_SSEL0/SD0_CLK/SCT0_OUT1/FC4_SSEL2/ADC0_4} + - {id: 20, pin_num: '2', pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N} + - id: C3 + name: P18 + pins: + - {id: 1, name: D7, pin_num: '10', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12} + - {id: 2, pin_num: '7', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1} + - {id: 3, name: D6, pin_num: '40', pin_signal: PIO1_10/FC1_RXD_SDA_MOSI_DATA/CTIMER1_MAT0/SCT0_OUT3} + - {id: 4, pin_num: '57', pin_signal: PIO1_14/UTICK_CAP2/CTIMER1_MAT2/FC5_CTS_SDA_SSEL0/USB0_LEDN/SD1_CMD/ACMP0_D} + - {id: 5, name: D5, pin_num: '1', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A} + - {id: 6, pin_num: '77', pin_signal: PIO1_25/FC2_TXD_SCL_MISO_WS/SCT0_OUT2/SD1_D0/UTICK_CAP0/PLU_CLKIN} + - {id: 7, name: D4-LED_GREEN, pin_num: '9', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4} + - {id: 8, pin_num: '42', pin_signal: PIO1_23/FC2_SCK/SCT0_OUT0/SD1_D3/FC3_SSEL2/PLU_OUT5} + - {id: 10, pin_num: '3', pin_signal: PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6} + - {id: 11, name: D2, pin_num: '22', pin_signal: PIO0_15/FC6_CTS_SDA_SSEL0/UTICK_CAP2/CT_INP16/SCT0_OUT2/SD0_WR_PRT/SECURE_GPIO0_15/ADC0_2} + - {id: 12, pin_num: '82', pin_signal: PIO1_15/UTICK_CAP3/CT_INP7/FC5_RTS_SCL_SSEL1/FC4_RTS_SCL_SSEL1/SD1_D2} + - {id: 13, name: D1, pin_num: '27', pin_signal: PIO0_27/FC2_TXD_SCL_MISO_WS/CTIMER3_MAT2/SCT0_OUT6/FC7_RXD_SDA_MOSI_DATA/PLU_OUT0/SECURE_GPIO0_27} + - {id: 14, pin_num: '58', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF} + - {id: 15, name: D0, pin_num: '3', pin_signal: PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6} + - {id: 16, pin_num: '64', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0} + - {id: 17, pin_num: '87', pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD} + - {id: 18, pin_num: '68', pin_signal: PIO1_26/FC2_CTS_SDA_SSEL0/SCT0_OUT3/CT_INP3/UTICK_CAP1/HS_SPI_SSEL3/PLU_IN5} + - {id: 19, pin_num: '43', pin_signal: PIO1_17/FC6_RTS_SCL_SSEL1/SCT0_OUT4/SD1_CARD_INT_N/SD1_CARD_DET_N} + - {id: 20, pin_num: '56', pin_signal: PIO0_18/FC4_CTS_SDA_SSEL0/SD0_WR_PRT/CTIMER1_MAT0/SCT0_OUT1/PLU_IN3/SECURE_GPIO0_18/ACMP0_C} + - id: C4 + name: P19 + pins: + - {id: 2, name: A0, pin_num: '14', pin_signal: PIO0_16/FC4_TXD_SCL_MISO_WS/CLKOUT/CT_INP4/SECURE_GPIO0_16/ADC0_8} + - {id: 4, name: A1, pin_num: '20', pin_signal: PIO0_23/MCLK/CTIMER1_MAT2/CTIMER3_MAT3/SCT0_OUT4/FC0_CTS_SDA_SSEL0/SD1_D1/SECURE_GPIO0_23/ADC0_0} + - {id: 6, name: A2, pin_num: '54', pin_signal: PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A} + - {id: 7, pin_num: '91', pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0} + - {id: 8, name: A3, pin_num: '91', pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0} + - {id: 9, pin_num: '71', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13} + - {id: 10, name: A4, pin_num: '71', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13} + - {id: 11, pin_num: '72', pin_signal: PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14} + - {id: 12, name: A5, pin_num: '72', pin_signal: PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14} +pin_labels: +- {pin_num: '7', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, label: 'P18[2]/SD1_CLK', identifier: LED_RED} +- {pin_num: '88', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, label: 'S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1', + identifier: LED} +- {pin_num: '11', pin_signal: PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11, label: 'U20[2]/SD0_D3', identifier: BUTTON} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitDEBUG_UARTPins(); + BOARD_InitUSBPins(); + BOARD_InitLEDsPins(); + BOARD_InitBUTTONsPins(); + BOARD_InitPins_Core0(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitDEBUG_UARTPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX); + + const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitSWD_DEBUGPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT0 PIN10 (coords: 21) is configured as SWO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO); + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + else + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } + else + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitUSBPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP} + - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM} + - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM} + - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP} + - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS} + - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp} + - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, + mode: pullUp} + - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp} + - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitUSBPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitUSBPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */ + IOCON_PIO_FUNC7 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS); + + IOCON->PIO[0][28] = ((IOCON->PIO[0][28] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][12] = ((IOCON->PIO[1][12] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][29] = ((IOCON->PIO[1][29] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][30] = ((IOCON->PIO[1][30] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: OUTPUT, + gpio_init_state: 'true', mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitLEDsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + gpio_pin_config_t LED_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO0_5 (pin 88) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_GPIO, BOARD_INITLEDSPINS_LED_PORT, BOARD_INITLEDSPINS_LED_PIN, &LED_config); + + IOCON->PIO[0][5] = ((IOCON->PIO[0][5] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT05 (pin 88) is configured as PIO0_5. */ + | IOCON_PIO_FUNC(PIO0_5_FUNC_ALT0) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO0_5_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_5_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN} + - {pin_num: '11', peripheral: GPIO, signal: 'PIO1, 0', pin_signal: PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11, direction: INPUT, mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitBUTTONsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t BUTTON_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_0 (pin 11) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_BUTTON_GPIO, BOARD_INITBUTTONSPINS_BUTTON_PORT, BOARD_INITBUTTONSPINS_BUTTON_PIN, &BUTTON_config); + + if (Chip_GetVersion()==1) + { + IOCON->PIO[1][0] = ((IOCON->PIO[1][0] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT10 (pin 11) is configured as PIO1_0. */ + | IOCON_PIO_FUNC(PIO1_0_FUNC_ALT0) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_0_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_0_DIGIMODE_DIGITAL)); + } + else + { + IOCON->PIO[1][0] = ((IOCON->PIO[1][0] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT10 (pin 11) is configured as PIO1_0. */ + | IOCON_PIO_FUNC(PIO1_0_FUNC_ALT0) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_0_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_0_DIGIMODE_DIGITAL)); + } +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins_Core0: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins_Core0 + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitPins_Core0(void) +{ +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitI2SPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled, + open_drain: disabled} + - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, + identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitI2SPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitI2SPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */ + IOCON_PIO_FUNC1 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK); + + const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS); + + const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX); + + const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK); + + const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX); + + const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); + + const uint32_t MCLK = (/* Pin is configured as MCLK */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN31 (coords: 91) is configured as MCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitACCELPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitACCELPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitACCELPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t ACCL_INTR_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_19 (pin 58) */ + GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config); + + const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */ + IOCON_PIO_FUNC0 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.h b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.h new file mode 100644 index 000000000..3e14d6baf --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.h @@ -0,0 +1,393 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U) +/* @} */ + +/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_ASW_DIS_EN 0x00u /*!<@brief Analog switch is closed (enabled), only for A0 version */ +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U) +/* @} */ + +/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U) +/* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Enables digital function */ +#define IOCON_PIO_DIGITAL_EN 0x0100u +/*! + * @brief Selects pin function 7 */ +#define IOCON_PIO_FUNC7 0x07u +/*! + * @brief Input function is not inverted */ +#define IOCON_PIO_INV_DI 0x00u +/*! + * @brief No addition pin function */ +#define IOCON_PIO_MODE_INACT 0x00u +/*! + * @brief Open drain is disabled */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u +/*! + * @brief Standard mode, output slew rate control is enabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_28_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 7. */ +#define PIO0_28_FUNC_ALT7 0x07u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO0_28_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_12_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_12_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_12_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_29_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_29_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_29_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_30_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_30_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_30_MODE_PULL_UP 0x02u + +/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS + @{ */ +#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U /*!<@brief PORT pin number */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_5_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO0_5_FUNC_ALT0 0x00u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO0_5_MODE_PULL_UP 0x02u + +/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1 + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_PIN 5U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_0_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO1_0_FUNC_ALT0 0x00u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_0_MODE_PULL_UP 0x02u + +/*! @name PIO1_0 (number 11), U20[2]/SD0_D3 + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_BUTTON_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_BUTTON_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_BUTTON_PIN 0U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_BUTTON_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC2 0x02u /*!<@brief Selects pin function 2 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO + @{ */ +#define BOARD_INITI2SPINS_MCLK_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_MCLK_PIN 31U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */ +#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/mcu_link/mcu_link.mex b/hw/bsp/lpc55/boards/mcu_link/mcu_link.mex new file mode 100644 index 000000000..c78dba808 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/mcu_link.mex @@ -0,0 +1,1354 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="LPCXpresso55S69" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="acf73d26-2bf9-4855-b3be-26068672d98a" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>LPC55S69</processor> + <package>LPC55S69JBD100</package> + <board>LPCXpresso55S69</board> + <board_revision>A2</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="cm33_core0"> + <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/> + <core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <custom_copyright> + <text>/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +</text> + <enabled>true</enabled> + </custom_copyright> + <update_include_paths>true</update_include_paths> + <enable_parallel_routing>true</enable_parallel_routing> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>25.09.10</processor_version> + <pin_labels> + <pin_label pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1" label="P18[2]/SD1_CLK" identifier="LED_RED"/> + <pin_label pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5" label="S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1" identifier="LED"/> + <pin_label pin_num="11" pin_signal="PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11" label="U20[2]/SD0_D3" identifier="BUTTON"/> + </pin_labels> + <expansion_headers> + <expansion_header id="lpc_style_arduino" name="LPCXpresso V3 (Arduino compatible)"> + <connectors> + <connector id="C1" name="P16"> + <pins> + <pin id="8" external_signal_types="power_supply_3.3V" name="3.3V"/> + <pin id="10" pin_num="32" pin_signal="RESETN" name="RESET"/> + <pin id="12" external_signal_types="power_supply_3.3V" name="3.3V"/> + <pin id="14" external_signal_types="power_supply_5V" name="5V"/> + <pin id="16" external_signal_types="ground" name="GND"/> + <pin id="18" external_signal_types="ground" name="GND"/> + <pin id="20" external_signal_types="power_supply_5V" name="5V"/> + </pins> + </connector> + <connector id="C2" name="P17"> + <pins> + <pin id="1" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2" name="D15"/> + <pin id="3" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3" name="D14"/> + <pin id="5" external_signal_types="power_supply_3.3V" name="3.3V"/> + <pin id="6" pin_num="93" pin_signal="PIO1_11/FC1_TXD_SCL_MISO_WS/CT_INP5/USB0_VBUS"/> + <pin id="7" external_signal_types="ground" name="GND"/> + <pin id="8" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5"/> + <pin id="9" pin_num="61" pin_signal="PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5" name="D13"/> + <pin id="10" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS"/> + <pin id="11" pin_num="62" pin_signal="PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6" name="D12"/> + <pin id="12" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19"/> + <pin id="13" pin_num="60" pin_signal="PIO0_26/FC2_RXD_SDA_MOSI_DATA/CLKOUT/CT_INP14/SCT0_OUT5/USB0_IDVALUE/FC0_SCK/HS_SPI_MOSI/SECURE_GPIO0_26" name="D11"/> + <pin id="14" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21"/> + <pin id="15" pin_num="59" pin_signal="PIO1_1/FC3_RXD_SDA_MOSI_DATA/CT_INP3/SCT_GPI5/HS_SPI_SSEL1/USB1_OVERCURRENTN/PLU_OUT4" name="D10"/> + <pin id="16" pin_num="85" pin_signal="PIO1_27/FC2_RTS_SCL_SSEL1/SD0_D4/CTIMER0_MAT3/CLKOUT/PLU_IN4"/> + <pin id="17" pin_num="31" pin_signal="PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0" name="D9"/> + <pin id="18" pin_num="73" pin_signal="PIO1_28/FC7_SCK/SD0_D5/CT_INP2/PLU_IN3"/> + <pin id="19" pin_num="24" pin_signal="PIO1_8/FC0_CTS_SDA_SSEL0/SD0_CLK/SCT0_OUT1/FC4_SSEL2/ADC0_4" name="D8"/> + <pin id="20" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N"/> + </pins> + </connector> + <connector id="C3" name="P18"> + <pins> + <pin id="1" pin_num="10" pin_signal="PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12" name="D7"/> + <pin id="2" pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1"/> + <pin id="3" pin_num="40" pin_signal="PIO1_10/FC1_RXD_SDA_MOSI_DATA/CTIMER1_MAT0/SCT0_OUT3" name="D6"/> + <pin id="4" pin_num="57" pin_signal="PIO1_14/UTICK_CAP2/CTIMER1_MAT2/FC5_CTS_SDA_SSEL0/USB0_LEDN/SD1_CMD/ACMP0_D"/> + <pin id="5" pin_num="1" pin_signal="PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A" name="D5"/> + <pin id="6" pin_num="77" pin_signal="PIO1_25/FC2_TXD_SCL_MISO_WS/SCT0_OUT2/SD1_D0/UTICK_CAP0/PLU_CLKIN"/> + <pin id="7" pin_num="9" pin_signal="PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4" name="D4-LED_GREEN"/> + <pin id="8" pin_num="42" pin_signal="PIO1_23/FC2_SCK/SCT0_OUT0/SD1_D3/FC3_SSEL2/PLU_OUT5"/> + <pin id="10" pin_num="3" pin_signal="PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6"/> + <pin id="11" pin_num="22" pin_signal="PIO0_15/FC6_CTS_SDA_SSEL0/UTICK_CAP2/CT_INP16/SCT0_OUT2/SD0_WR_PRT/SECURE_GPIO0_15/ADC0_2" name="D2"/> + <pin id="12" pin_num="82" pin_signal="PIO1_15/UTICK_CAP3/CT_INP7/FC5_RTS_SCL_SSEL1/FC4_RTS_SCL_SSEL1/SD1_D2"/> + <pin id="13" pin_num="27" pin_signal="PIO0_27/FC2_TXD_SCL_MISO_WS/CTIMER3_MAT2/SCT0_OUT6/FC7_RXD_SDA_MOSI_DATA/PLU_OUT0/SECURE_GPIO0_27" name="D1"/> + <pin id="14" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF"/> + <pin id="15" pin_num="3" pin_signal="PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6" name="D0"/> + <pin id="16" pin_num="64" pin_signal="PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0"/> + <pin id="17" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD"/> + <pin id="18" pin_num="68" pin_signal="PIO1_26/FC2_CTS_SDA_SSEL0/SCT0_OUT3/CT_INP3/UTICK_CAP1/HS_SPI_SSEL3/PLU_IN5"/> + <pin id="19" pin_num="43" pin_signal="PIO1_17/FC6_RTS_SCL_SSEL1/SCT0_OUT4/SD1_CARD_INT_N/SD1_CARD_DET_N"/> + <pin id="20" pin_num="56" pin_signal="PIO0_18/FC4_CTS_SDA_SSEL0/SD0_WR_PRT/CTIMER1_MAT0/SCT0_OUT1/PLU_IN3/SECURE_GPIO0_18/ACMP0_C"/> + </pins> + </connector> + <connector id="C4" name="P19"> + <pins> + <pin id="2" pin_num="14" pin_signal="PIO0_16/FC4_TXD_SCL_MISO_WS/CLKOUT/CT_INP4/SECURE_GPIO0_16/ADC0_8" name="A0"/> + <pin id="4" pin_num="20" pin_signal="PIO0_23/MCLK/CTIMER1_MAT2/CTIMER3_MAT3/SCT0_OUT4/FC0_CTS_SDA_SSEL0/SD1_D1/SECURE_GPIO0_23/ADC0_0" name="A1"/> + <pin id="6" pin_num="54" pin_signal="PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A" name="A2"/> + <pin id="7" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0"/> + <pin id="8" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0" name="A3"/> + <pin id="9" pin_num="71" pin_signal="PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13"/> + <pin id="10" pin_num="71" pin_signal="PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13" name="A4"/> + <pin id="11" pin_num="72" pin_signal="PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14"/> + <pin id="12" pin_num="72" pin_signal="PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14" name="A5"/> + </pins> + </connector> + </connectors> + </expansion_header> + </expansion_headers> + </pins_profile> + <functions_list> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSWD_DEBUGPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9"> + <pin_features> + <pin_feature name="mode" value="pullDown"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="DEBUG_SWD_SWO"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitUSBPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/> + <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/> + <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/> + <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/> + <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/> + <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitLEDsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitBUTTONsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/> + <pin peripheral="GPIO" signal="PIO1, 0" pin_num="11" pin_signal="PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitPins_Core0"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitPins_Core1"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core1</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core1"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitI2SPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="FC6_I2S_CLK"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitACCELPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>25.09.10</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources/> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings/> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/> + <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/> + <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="PLL1_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/> + <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/> + <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/> + <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/> + <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/> + <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true"> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.2.0</data> + </feature> + </dependency> + <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>25.09.10</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals_cm33_core0" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + </dependencies> + <instances> + <instance name="ACCEL" uuid="b999c56a-0d01-4089-9311-9224db5272f4" type="flexcomm_i2c" type_id="flexcomm_i2c_2.3.0" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_i2c" quick_selection="QS_I2C_Master"> + <setting name="i2c_mode" value="kI2C_Master"/> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="i2c_master_config"> + <setting name="enableMaster" value="true"/> + <setting name="baudRate_Bps" value="100000"/> + <setting name="enableTimeout" value="false"/> + <setting name="timeout_Ms" value="35"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="9fb0504c-6159-43e2-98bb-51d75f06133a" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="usartConfig_t"> + <struct name="usartConfig"> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="syncMode" value="kUSART_SyncModeDisabled"/> + <setting name="parityMode" value="kUSART_ParityDisabled"/> + <setting name="stopBitCount" value="kUSART_OneStopBit"/> + <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/> + <setting name="loopback" value="false"/> + <setting name="txWatermark" value="kUSART_TxFifo0"/> + <setting name="rxWatermark" value="kUSART_RxFifo1"/> + <setting name="enableRx" value="true"/> + <setting name="enableTx" value="true"/> + <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/> + <setting name="enableContinuousSCLK" value="false"/> + </struct> + </config_set> + </instance> + <instance name="LEDS" uuid="f5ad3a56-404b-44cb-8abc-7b25b5551d33" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="SW" uuid="d57ddfca-dc72-486c-a145-c7a2ab1e1a66" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="NVIC" uuid="56761ad9-9b77-4074-917d-de0fde10cd48" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + <functional_group name="BOARD_InitPeripherals_cm33_core1" uuid="e2041cd4-ebb6-45a5-807f-e0c2dc047d48" called_from_default_init="false" id_prefix="" core="cm33_core1"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="NVIC_2" uuid="db546092-4c45-40af-938a-8cc58edd1c4f" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="905d2747-654a-47d9-91f9-81a5c6f9c407" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + <setting name="global_init" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="64cbcd7c-424d-4baf-9681-a60878969fb6" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="generic_can" uuid="b9b018dd-ef4e-41f6-b456-f91b855cb391" type_id="generic_can"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="bafa6375-9184-4272-8102-06ea086041d7" type_id="uart_cmsis_common"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="1710dc7f-381f-4b37-8f78-0fd2f923b3ac" type_id="generic_uart"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_enet" uuid="c7fc4395-b141-4b13-a326-4145e765b2b7" type_id="generic_enet"> + <config_set_global name="global_enet"/> + </component> + <component name="gpio_adapter_common" uuid="b6ee89c2-4c58-4181-94dc-af13d8ae8ea5" type_id="gpio_adapter_common"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + </components> + </periphs> + <tee name="TEE" version="10.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + <tool_options> + <option id="_output_type_" value="c_code"/> + <option id="_legacy_source_names_" value="yes"/> + </tool_options> + </tee_profile> + <functional_group name="BOARD_InitTrustZone" called_from_default_init="true" id_prefix="" prefix_user_defined="true"> + <description></description> + <options/> + <ahb> + <relative_region start="0" size="655360" security="s_priv" memory="PROGRAM_FLASH"/> + <relative_region start="0" size="131072" security="s_priv" memory="BootROM"/> + <relative_region start="0" size="32768" security="s_priv" memory="SRAMX"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM0"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM1"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM2"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM3"/> + <relative_region start="0" size="16384" security="s_priv" memory="SRAM4"/> + <relative_region start="0" size="16384" security="s_priv" memory="AHBperipherals_port10_ahb_secure_ctrl_area"/> + <relative_region start="0" size="16384" security="s_priv" memory="USB_RAM"/> + <masters> + <master id="HASH" security="ns_user"/> + <master id="MCM33C" security="ns_user"/> + <master id="MCM33S" security="ns_user"/> + <master id="PQ" security="ns_user"/> + <master id="SDIO" security="ns_user"/> + <master id="SDMA0" security="ns_user"/> + <master id="SDMA1" security="ns_user"/> + <master id="USBFSD" security="ns_user"/> + <master id="USBFSH" security="ns_user"/> + </masters> + <peripherals> + <peripheral id="ADC0" security="s_priv"/> + <peripheral id="AHB_SECURE_CTRL" security="s_priv"/> + <peripheral id="ANACTRL" security="s_priv"/> + <peripheral id="CASPER" security="s_priv"/> + <peripheral id="CRC_ENGINE" security="s_priv"/> + <peripheral id="CTIMER0" security="s_priv"/> + <peripheral id="CTIMER1" security="s_priv"/> + <peripheral id="CTIMER2" security="s_priv"/> + <peripheral id="CTIMER3" security="s_priv"/> + <peripheral id="CTIMER4" security="s_priv"/> + <peripheral id="DBGMAILBOX" security="s_priv"/> + <peripheral id="DMA0" security="s_priv"/> + <peripheral id="DMA1" security="s_priv"/> + <peripheral id="FLASH" security="s_priv"/> + <peripheral id="FLEXCOMM0" security="s_priv"/> + <peripheral id="FLEXCOMM1" security="s_priv"/> + <peripheral id="FLEXCOMM2" security="s_priv"/> + <peripheral id="FLEXCOMM3" security="s_priv"/> + <peripheral id="FLEXCOMM4" security="s_priv"/> + <peripheral id="FLEXCOMM5" security="s_priv"/> + <peripheral id="FLEXCOMM6" security="s_priv"/> + <peripheral id="FLEXCOMM7" security="s_priv"/> + <peripheral id="GINT0" security="s_priv"/> + <peripheral id="GINT1" security="s_priv"/> + <peripheral id="GPIO" security="s_priv"/> + <peripheral id="HASHCRYPT" security="s_priv"/> + <peripheral id="INPUTMUX" security="s_priv"/> + <peripheral id="IOCON" security="s_priv"/> + <peripheral id="MAILBOX" security="s_priv"/> + <peripheral id="MRT0" security="s_priv"/> + <peripheral id="OSTIMER" security="s_priv"/> + <peripheral id="PINT" security="s_priv"/> + <peripheral id="PLU" security="s_priv"/> + <peripheral id="PMC" security="s_priv"/> + <peripheral id="POWERQUAD" security="s_priv"/> + <peripheral id="PRINCE" security="s_priv"/> + <peripheral id="PUF" security="s_priv"/> + <peripheral id="RNG" security="s_priv"/> + <peripheral id="RTC" security="s_priv"/> + <peripheral id="SCT0" security="s_priv"/> + <peripheral id="SDIF" security="s_priv"/> + <peripheral id="SECGPIO" security="s_priv"/> + <peripheral id="SECPINT" security="s_priv"/> + <peripheral id="SPI8" security="s_priv"/> + <peripheral id="SYSCON" security="s_priv"/> + <peripheral id="SYSCTL" security="s_priv"/> + <peripheral id="USB0" security="s_priv"/> + <peripheral id="USBFSH" security="s_priv"/> + <peripheral id="USBHSD" security="s_priv"/> + <peripheral id="USBHSH" security="s_priv"/> + <peripheral id="USBPHY" security="s_priv"/> + <peripheral id="UTICK0" security="s_priv"/> + <peripheral id="WWDT" security="s_priv"/> + </peripherals> + <interrupts> + <masking> + <interrupt id="acmp_capt_irq" masked="Masked"/> + <interrupt id="adc_irq" masked="Masked"/> + <interrupt id="casper_irq" masked="Masked"/> + <interrupt id="ctimer0_irq" masked="Masked"/> + <interrupt id="ctimer1_irq" masked="Masked"/> + <interrupt id="ctimer2_irq" masked="Masked"/> + <interrupt id="ctimer3_irq" masked="Masked"/> + <interrupt id="ctimer4_irq" masked="Masked"/> + <interrupt id="flexcomm0_irq" masked="Masked"/> + <interrupt id="flexcomm1_irq" masked="Masked"/> + <interrupt id="flexcomm2_irq" masked="Masked"/> + <interrupt id="flexcomm3_irq" masked="Masked"/> + <interrupt id="flexcomm4_irq" masked="Masked"/> + <interrupt id="flexcomm5_irq" masked="Masked"/> + <interrupt id="flexcomm6_irq" masked="Masked"/> + <interrupt id="flexcomm7_irq" masked="Masked"/> + <interrupt id="global_irq0" masked="Masked"/> + <interrupt id="global_irq1" masked="Masked"/> + <interrupt id="lspi_hs_irq" masked="Masked"/> + <interrupt id="mailbox_irq" masked="Masked"/> + <interrupt id="mrt_irq" masked="Masked"/> + <interrupt id="os_event_irq" masked="Masked"/> + <interrupt id="pin_int4" masked="Masked"/> + <interrupt id="pin_int5" masked="Masked"/> + <interrupt id="pin_int6" masked="Masked"/> + <interrupt id="pin_int7" masked="Masked"/> + <interrupt id="pin_irq0" masked="Masked"/> + <interrupt id="pin_irq1" masked="Masked"/> + <interrupt id="pin_irq2" masked="Masked"/> + <interrupt id="pin_irq3" masked="Masked"/> + <interrupt id="plu_irq" masked="Masked"/> + <interrupt id="pq_irq" masked="Masked"/> + <interrupt id="qddkey_irq" masked="Masked"/> + <interrupt id="rtc_irq" masked="Masked"/> + <interrupt id="sct_irq" masked="Masked"/> + <interrupt id="sdio_irq" masked="Masked"/> + <interrupt id="sdma0_irq" masked="Masked"/> + <interrupt id="sdma1_irq" masked="Masked"/> + <interrupt id="sec_hypervisor_call_irq" masked="Masked"/> + <interrupt id="sec_int0" masked="Masked"/> + <interrupt id="sec_int1" masked="Masked"/> + <interrupt id="sec_vio_irq" masked="Masked"/> + <interrupt id="sha_irq" masked="Masked"/> + <interrupt id="sys_irq" masked="Masked"/> + <interrupt id="usb0_irq" masked="Masked"/> + <interrupt id="usb0_needclk_irq" masked="Masked"/> + <interrupt id="usb1_irq" masked="Masked"/> + <interrupt id="usb1_needclk_irq" masked="Masked"/> + <interrupt id="usb1_utmi_irq" masked="Masked"/> + <interrupt id="utick_irq" masked="Masked"/> + </masking> + <security> + <interrupt id="acmp_capt_irq" secure="Secure"/> + <interrupt id="adc_irq" secure="Secure"/> + <interrupt id="casper_irq" secure="Secure"/> + <interrupt id="ctimer0_irq" secure="Secure"/> + <interrupt id="ctimer1_irq" secure="Secure"/> + <interrupt id="ctimer2_irq" secure="Secure"/> + <interrupt id="ctimer3_irq" secure="Secure"/> + <interrupt id="ctimer4_irq" secure="Secure"/> + <interrupt id="flexcomm0_irq" secure="Secure"/> + <interrupt id="flexcomm1_irq" secure="Secure"/> + <interrupt id="flexcomm2_irq" secure="Secure"/> + <interrupt id="flexcomm3_irq" secure="Secure"/> + <interrupt id="flexcomm4_irq" secure="Secure"/> + <interrupt id="flexcomm5_irq" secure="Secure"/> + <interrupt id="flexcomm6_irq" secure="Secure"/> + <interrupt id="flexcomm7_irq" secure="Secure"/> + <interrupt id="global_irq0" secure="Secure"/> + <interrupt id="global_irq1" secure="Secure"/> + <interrupt id="lspi_hs_irq" secure="Secure"/> + <interrupt id="mailbox_irq" secure="Secure"/> + <interrupt id="mrt_irq" secure="Secure"/> + <interrupt id="os_event_irq" secure="Secure"/> + <interrupt id="pin_int4" secure="Secure"/> + <interrupt id="pin_int5" secure="Secure"/> + <interrupt id="pin_int6" secure="Secure"/> + <interrupt id="pin_int7" secure="Secure"/> + <interrupt id="pin_irq0" secure="Secure"/> + <interrupt id="pin_irq1" secure="Secure"/> + <interrupt id="pin_irq2" secure="Secure"/> + <interrupt id="pin_irq3" secure="Secure"/> + <interrupt id="plu_irq" secure="Secure"/> + <interrupt id="pq_irq" secure="Secure"/> + <interrupt id="qddkey_irq" secure="Secure"/> + <interrupt id="rtc_irq" secure="Secure"/> + <interrupt id="sct_irq" secure="Secure"/> + <interrupt id="sdio_irq" secure="Secure"/> + <interrupt id="sdma0_irq" secure="Secure"/> + <interrupt id="sdma1_irq" secure="Secure"/> + <interrupt id="sec_hypervisor_call_irq" secure="Secure"/> + <interrupt id="sec_int0" secure="Secure"/> + <interrupt id="sec_int1" secure="Secure"/> + <interrupt id="sec_vio_irq" secure="Secure"/> + <interrupt id="sha_irq" secure="Secure"/> + <interrupt id="sys_irq" secure="Secure"/> + <interrupt id="usb0_irq" secure="Secure"/> + <interrupt id="usb0_needclk_irq" secure="Secure"/> + <interrupt id="usb1_irq" secure="Secure"/> + <interrupt id="usb1_needclk_irq" secure="Secure"/> + <interrupt id="usb1_utmi_irq" secure="Secure"/> + <interrupt id="utick_irq" secure="Secure"/> + </security> + </interrupts> + <ports> + <port id="pio0"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + <port id="pio1"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + </ports> + </ahb> + <saus> + <sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false"> + <region start="0" size="268435456" security="ns" enabled="true" index="0"/> + <region start="536870912" size="3221225472" security="ns" enabled="true" index="1"/> + <region start="0" size="32" security="ns" enabled="false" index="2"/> + <region start="0" size="32" security="ns" enabled="false" index="3"/> + <region start="0" size="32" security="ns" enabled="false" index="4"/> + <region start="0" size="32" security="ns" enabled="false" index="5"/> + <region start="0" size="32" security="ns" enabled="false" index="6"/> + <region start="0" size="32" security="ns" enabled="false" index="7"/> + </sau> + </saus> + <global_options> + <option id="AIRCR_PRIS" value="no"/> + <option id="AIRCR_BFHFNMINS" value="no"/> + <option id="AIRCR_SYSRESETREQS" value="no"/> + <option id="SCR_SLEEPDEEPS" value="no"/> + <option id="SHCSR_SECUREFAULTENA" value="no"/> + <option id="CPACR_CP0" value="3"/> + <option id="CPACR_CP1" value="3"/> + <option id="CPACR_CP2" value="0"/> + <option id="CPACR_CP3" value="0"/> + <option id="CPACR_CP4" value="0"/> + <option id="CPACR_CP5" value="0"/> + <option id="CPACR_CP6" value="0"/> + <option id="CPACR_CP7" value="0"/> + <option id="CPACR_CP10" value="3"/> + <option id="CPACR_CP11" value="3"/> + <option id="NSACR_CP0" value="yes"/> + <option id="NSACR_CP1" value="yes"/> + <option id="NSACR_CP2" value="no"/> + <option id="NSACR_CP3" value="no"/> + <option id="NSACR_CP4" value="no"/> + <option id="NSACR_CP5" value="no"/> + <option id="NSACR_CP6" value="no"/> + <option id="NSACR_CP7" value="no"/> + <option id="NSACR_CP10" value="yes"/> + <option id="NSACR_CP11" value="yes"/> + <option id="CPPWR_SU0" value="no"/> + <option id="CPPWR_SUS0" value="no"/> + <option id="CPPWR_SU1" value="no"/> + <option id="CPPWR_SUS1" value="no"/> + <option id="CPPWR_SU2" value="no"/> + <option id="CPPWR_SUS2" value="no"/> + <option id="CPPWR_SU3" value="no"/> + <option id="CPPWR_SUS3" value="no"/> + <option id="CPPWR_SU4" value="no"/> + <option id="CPPWR_SUS4" value="no"/> + <option id="CPPWR_SU5" value="no"/> + <option id="CPPWR_SUS5" value="no"/> + <option id="CPPWR_SU6" value="no"/> + <option id="CPPWR_SUS6" value="no"/> + <option id="CPPWR_SU7" value="no"/> + <option id="CPPWR_SUS7" value="no"/> + <option id="CPPWR_SU10" value="no"/> + <option id="CPPWR_SUS10" value="no"/> + <option id="CPPWR_SU11" value="no"/> + <option id="CPPWR_SUS11" value="no"/> + <option id="SEC_GPIO_MASK0_LOCK" value="no"/> + <option id="SEC_GPIO_MASK1_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/> + <option id="MASTER_SEC_LEVEL_LOCK" value="no"/> + <option id="CPU0_LOCK_NS_VTOR" value="no"/> + <option id="CPU0_LOCK_NS_MPU" value="no"/> + <option id="CPU0_LOCK_S_VTAIRCR" value="no"/> + <option id="CPU0_LOCK_S_MPU" value="no"/> + <option id="CPU0_LOCK_SAU" value="no"/> + <option id="CPU0_LOCK_REG_LOCK" value="no"/> + <option id="CPU1_LOCK_NS_VTOR" value="no"/> + <option id="CPU1_LOCK_NS_MPU" value="no"/> + <option id="CPU1_LOCK_REG_LOCK" value="no"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/> + <option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="yes"/> + </global_options> + <mpus> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + </mpus> + </functional_group> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c index ad0e502b5..b5d097234 100644 --- a/hw/bsp/lpc55/family.c +++ b/hw/bsp/lpc55/family.c @@ -33,9 +33,12 @@ #include "fsl_device_registers.h" #include "fsl_gpio.h" #include "fsl_power.h" -#include "fsl_iocon.h" #include "fsl_usart.h" +#include "board/pin_mux.h" +#include "board/clock_config.h" +#include "board/peripherals.h" + #ifdef NEOPIXEL_PIN #include "fsl_sctimer.h" #include "sct_neopixel.h" @@ -45,23 +48,6 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -// IOCON pin mux -#define IOCON_PIO_DIGITAL_EN 0x0100u // Enables digital function -#define IOCON_PIO_FUNC0 0x00u // Selects pin function 0 -#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1 -#define IOCON_PIO_FUNC4 0x04u // Selects pin function 4 -#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7 -#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted -#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function -#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled -#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled -#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ - -#define IOCON_PIO_DIG_FUNC0_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC0) // Digital pin function 0 enabled -#define IOCON_PIO_DIG_FUNC1_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC1) // Digital pin function 1 enabled -#define IOCON_PIO_DIG_FUNC4_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC4) // Digital pin function 2 enabled -#define IOCON_PIO_DIG_FUNC7_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC7) // Digital pin function 2 enabled - //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -73,74 +59,12 @@ void USB1_IRQHandler(void) { tusb_int_handler(1, true); } -/**************************************************************** -name: BOARD_BootClockPLL100M -outputs: -- {id: System_clock.outFreq, value: 100 MHz} -settings: -- {id: PLL0_Mode, value: Normal} -- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} -- {id: ENABLE_CLKIN_ENA, value: Enabled} -- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} -- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} -- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} -- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} -- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} -- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} -sources: -- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} -- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} -******************************************************************/ -void BOARD_BootClockPLL100M(void) -{ - /*!< Set up the clock sources */ - /*!< Configure FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ - - CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ - - /*!< Configure XTAL32M */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ - CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up PLL */ - CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ - POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - const pll_setup_t pll0Setup = { - .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), - .pllndec = SYSCON_PLL0NDEC_NDIV(4U), - .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), - .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, - .pllRate = 100000000U, - .flags = PLL_SETUPFLAG_WAITLOCK - }; - CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ - - /*< Set SystemCoreClock variable. */ - SystemCoreClock = 100000000U; -} - void board_init(void) { - // Enable IOCON clock - CLOCK_EnableClock(kCLOCK_Iocon); + BOARD_InitBootPins(); + BOARD_InitBootClocks(); + BOARD_InitBootPeripherals(); - // Init 100 MHz clock - BOARD_BootClockPLL100M(); + board_led_write(0); #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer @@ -155,54 +79,8 @@ void board_init(void) { NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif - // Init all GPIO ports - GPIO_PortInit(GPIO, 0); - GPIO_PortInit(GPIO, 1); - - // LED - IOCON_PinMuxSet(IOCON, LED_PORT, LED_PIN, IOCON_PIO_DIG_FUNC0_EN); - gpio_pin_config_t const led_config = {kGPIO_DigitalOutput, 1}; - GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config); - - board_led_write(0); - -#ifdef NEOPIXEL_PIN - // Neopixel - static uint32_t pixelData[NEOPIXEL_NUMBER]; - IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN); - - sctpix_init(NEOPIXEL_TYPE); - sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER); - sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010); - sctpix_show(); -#endif - - // Button - IOCON_PinMuxSet(IOCON, BUTTON_PORT, BUTTON_PIN, IOCON_PIO_DIG_FUNC0_EN); - gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0}; - GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config); - -#ifdef UART_DEV - // UART - IOCON_PinMuxSet(IOCON, UART_RX_PINMUX); - IOCON_PinMuxSet(IOCON, UART_TX_PINMUX); - - // Enable UART when debug log is on - CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); - usart_config_t uart_config; - USART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - USART_Init(UART_DEV, &uart_config, 12000000); -#endif - #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0) - /* PORT0 PIN22 configured as USB0_VBUS */ - IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN); // Port0 is Full Speed - NVIC_ClearPendingIRQ(USB0_IRQn); NVIC_ClearPendingIRQ(USB0_NEEDCLK_IRQn); @@ -227,36 +105,6 @@ void board_init(void) { /* enable USB Device clock */ CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); } else { - const uint32_t port1_pin12_config = (/* Pin is configured as USB0_PORTPWRN */ - IOCON_PIO_FUNC4 | - /* Selects pull-up function */ - IOCON_PIO_MODE_PULLUP | - /* Standard mode, output slew rate control is enabled */ - IOCON_PIO_SLEW_STANDARD | - /* Input function is not inverted */ - IOCON_PIO_INV_DI | - /* Enables digital function */ - IOCON_PIO_DIGITAL_EN | - /* Open drain is disabled */ - IOCON_PIO_OPENDRAIN_DI); - /* PORT1 PIN12 (coords: 67) is configured as USB0_PORTPWRN */ - IOCON_PinMuxSet(IOCON, 1U, 12U, port1_pin12_config); - - const uint32_t port0_pin28_config = (/* Pin is configured as USB0_OVERCURRENTN */ - IOCON_PIO_FUNC7 | - /* Selects pull-up function */ - IOCON_PIO_MODE_PULLUP | - /* Standard mode, output slew rate control is enabled */ - IOCON_PIO_SLEW_STANDARD | - /* Input function is not inverted */ - IOCON_PIO_INV_DI | - /* Enables digital function */ - IOCON_PIO_DIGITAL_EN | - /* Open drain is disabled */ - IOCON_PIO_OPENDRAIN_DI); - /* PORT0 PIN28 (coords: 66) is configured as USB0_OVERCURRENTN */ - IOCON_PinMuxSet(IOCON, 0U, 28U, port0_pin28_config); - CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbfsSrcPll1, 48000000U); USBFSH->PORTMODE &= ~USBFSH_PORTMODE_DEV_ENABLE_MASK; } @@ -274,18 +122,21 @@ void board_init(void) { RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn); RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn); - /* According to reference manual, device mode setting has to be set by access usb host register */ - CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock + if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) { + /* According to reference manual, device mode setting has to be set by access usb host register */ + CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock - USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control - USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; + USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control + USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; - CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock + CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock + /* enable USB Device clock */ + CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U); + } else { + CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUnused, 0U); + } - /* enable USB Device clock */ CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, XTAL0_CLK_HZ); - CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U); - CLOCK_EnableClock(kCLOCK_UsbRam1); // Enable PHY support for Low speed device + LS via FS Hub USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; @@ -296,11 +147,9 @@ void board_init(void) { USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK; USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK; - // TX Timing -// uint32_t phytx = USBPHY->TX; -// phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK); -// phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06); -// USBPHY->TX = phytx; + // PHY Tx calibration + USBPHY->TX = ((USBPHY->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(0x05U) | USBPHY_TX_TXCAL45DP(0x0AU) | USBPHY_TX_TXCAL45DM(0x0AU))); ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer) ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0)); @@ -314,17 +163,6 @@ void board_init(void) { void board_led_write(bool state) { GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); - -#ifdef NEOPIXEL_PIN - if (state) { - sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010); - } else { - sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010); - } - sctpix_show(); -#endif } uint32_t board_button_read(void) { @@ -350,7 +188,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index 1f18f9bad..2dc1c33f3 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -1,7 +1,8 @@ include_guard() -set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) -set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +set(MCUX_DIR ${TOP}/hw/mcu/nxp/mcuxsdk-core) +set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-devices-lpc/LPC5500) +set(CMSIS_DIR ${TOP}/lib/CMSIS_6) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -40,43 +41,60 @@ cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_ # Startup & Linker script #------------------------------------ if (NOT DEFINED LD_FILE_GNU) - set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) + set(LD_FILE_GNU ${SDK_DIR}/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) if (NOT DEFINED STARTUP_FILE_GNU) - set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) + set(STARTUP_FILE_GNU ${SDK_DIR}/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) endif () set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) +if (NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${SDK_DIR}/${MCU_VARIANT}/iar/${MCU_CORE}_flash.icf) +endif () + +if (NOT DEFINED STARTUP_FILE_IAR) + set(STARTUP_FILE_IAR ${SDK_DIR}/${MCU_VARIANT}/iar/startup_${MCU_CORE}.s) +endif () + #------------------------------------ # Board Target #------------------------------------ function(family_add_board BOARD_TARGET) + # Some variants (e.g. LPC55S28) share drivers with another variant (e.g. LPC55S69) + if (NOT DEFINED MCU_DRIVER_VARIANT) + set(MCU_DRIVER_VARIANT ${MCU_VARIANT}) + endif () + add_library(${BOARD_TARGET} STATIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/pin_mux.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/peripherals.c # driver - ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c - ${SDK_DIR}/drivers/common/fsl_common_arm.c - ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c - ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c + ${MCUX_DIR}/drivers/lpc_gpio/fsl_gpio.c + ${MCUX_DIR}/drivers/common/fsl_common_arm.c + ${MCUX_DIR}/drivers/flexcomm/fsl_flexcomm.c + ${MCUX_DIR}/drivers/flexcomm/usart/fsl_usart.c # mcu - ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c + ${SDK_DIR}/${MCU_VARIANT}/system_${MCU_CORE}.c + ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers/fsl_clock.c + ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers/fsl_power.c + ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers/fsl_reset.c ) target_include_directories(${BOARD_TARGET} PUBLIC ${TOP}/lib/sct_neopixel # driver - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/flexcomm - ${SDK_DIR}/drivers/flexcomm/usart - ${SDK_DIR}/drivers/lpc_iocon - ${SDK_DIR}/drivers/lpc_gpio - ${SDK_DIR}/drivers/sctimer + ${MCUX_DIR}/drivers/common + ${MCUX_DIR}/drivers/flexcomm + ${MCUX_DIR}/drivers/flexcomm/usart + ${MCUX_DIR}/drivers/lpc_iocon + ${MCUX_DIR}/drivers/lpc_gpio + ${MCUX_DIR}/drivers/sctimer # mcu - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ${SDK_DIR}/${MCU_VARIANT} + ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers + ${SDK_DIR}/periph ${CMSIS_DIR}/CMSIS/Core/Include ) target_compile_definitions(${BOARD_TARGET} PUBLIC @@ -91,11 +109,13 @@ function(family_add_board BOARD_TARGET) # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM if (RHPORT_DEVICE EQUAL 1) target_compile_definitions(${BOARD_TARGET} PUBLIC - CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) + [=[CFG_TUD_MEM_SECTION=__attribute__((section("m_usb_global")))]=] ) - elseif (RHPORT_HOST EQUAL 1) + endif () + if (RHPORT_HOST EQUAL 1) target_compile_definitions(${BOARD_TARGET} PUBLIC - CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) + [=[CFG_TUH_MEM_SECTION=__attribute__((section("m_usb_global")))]=] + CFG_TUH_USBIP_IP3516=1 ) endif () @@ -114,9 +134,19 @@ function(family_configure_example TARGET RTOS) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c ${TOP}/lib/sct_neopixel/sct_neopixel.c ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - ${TOP}/src/portable/ohci/ohci.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ) + + if (RHPORT_HOST EQUAL 0) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/ohci/ohci.c + ) + elseif (RHPORT_HOST EQUAL 1) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c + ) + endif () + target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ @@ -128,6 +158,8 @@ function(family_configure_example TARGET RTOS) "LINKER:--script=${LD_FILE_GNU}" --specs=nosys.specs --specs=nano.specs -nostartfiles + "LINKER:--defsym=__stack_size__=0x1000" + "LINKER:--defsym=__heap_size__=0" ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${TARGET} PUBLIC @@ -136,6 +168,8 @@ function(family_configure_example TARGET RTOS) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${TARGET} PUBLIC "LINKER:--config=${LD_FILE_IAR}" + "LINKER:--config_def=__stack_size__=0x1000" + "LINKER:--config_def=__heap_size__=0" ) endif () diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk index fadf852cd..2fc76ed50 100644 --- a/hw/bsp/lpc55/family.mk +++ b/hw/bsp/lpc55/family.mk @@ -1,28 +1,41 @@ UF2_FAMILY_ID = 0x2abc77ec -SDK_DIR = hw/mcu/nxp/mcux-sdk include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m33 -MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT) +MCUX_DIR = hw/mcu/nxp/mcuxsdk-core +SDK_DIR = hw/mcu/nxp/mcux-devices-lpc -# Default to Highspeed PORT1 -PORT ?= 1 +# Some variants (e.g. LPC55S28) share drivers with another variant (e.g. LPC55S69) +MCU_DRIVER_VARIANT ?= $(MCU_VARIANT) + +# Default device port to USB1 highspeed, host to USB0 fullspeed +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 CFLAGS += \ -flto \ -D__STARTUP_CLEAR_BSS \ -DCFG_TUSB_MCU=OPT_MCU_LPC55XX \ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \ - -DBOARD_TUD_RHPORT=$(PORT) \ + -DBOARD_TUD_RHPORT=$(RHPORT_DEVICE) \ + -DBOARD_TUH_RHPORT=$(RHPORT_HOST) \ -ifeq ($(PORT), 1) - $(info "PORT1 High Speed") +# port 0 is fullspeed, port 1 is highspeed +ifeq ($(RHPORT_DEVICE), 1) CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + # Port1 controller can only access USB_SRAM + CFLAGS += -DCFG_TUD_MEM_SECTION='__attribute__((section("m_usb_global")))' +else + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED +endif - # LPC55 Highspeed Port1 can only write to USB_SRAM region - CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))' +ifeq ($(RHPORT_HOST), 1) + CFLAGS += -DBOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED + CFLAGS += -DCFG_TUH_MEM_SECTION='__attribute__((section("m_usb_global")))' + CFLAGS += -DCFG_TUH_USBIP_IP3516=1 + SRC_C += $(TOP)/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c else - $(info "PORT0 Full Speed") + CFLAGS += -DBOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED endif # mcu driver cause following warnings @@ -31,33 +44,36 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=float-equal LDFLAGS_GCC += \ -nostartfiles \ --specs=nosys.specs --specs=nano.specs \ + -Wl,--defsym=__stack_size__=0x1000 \ + -Wl,--defsym=__heap_size__=0 \ # All source paths should be relative to the top level. -LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_CORE)_flash.ld +LD_FILE ?= $(SDK_DIR)/LPC5500/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld SRC_C += \ - src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \ - $(MCU_DIR)/system_$(MCU_CORE).c \ - $(MCU_DIR)/drivers/fsl_clock.c \ - $(MCU_DIR)/drivers/fsl_power.c \ - $(MCU_DIR)/drivers/fsl_reset.c \ - $(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \ - $(SDK_DIR)/drivers/common/fsl_common_arm.c \ - $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ - $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \ - lib/sct_neopixel/sct_neopixel.c + $(TOP)/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_VARIANT)/system_$(MCU_CORE).c \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers/fsl_clock.c \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers/fsl_power.c \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers/fsl_reset.c \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_gpio/fsl_gpio.c \ + $(TOP)/$(MCUX_DIR)/drivers/common/fsl_common_arm.c \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/fsl_flexcomm.c \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart/fsl_usart.c \ + $(TOP)/lib/sct_neopixel/sct_neopixel.c INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/sct_neopixel \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/drivers \ - $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \ - $(TOP)/$(SDK_DIR)/drivers/flexcomm/ \ - $(TOP)/$(SDK_DIR)/drivers/lpc_iocon \ - $(TOP)/$(SDK_DIR)/drivers/lpc_gpio \ - $(TOP)/$(SDK_DIR)/drivers/sctimer + $(TOP)/lib/CMSIS_6/CMSIS/Core/Include \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_VARIANT) \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers \ + $(TOP)/$(SDK_DIR)/LPC5500/periph \ + $(TOP)/$(MCUX_DIR)/drivers/common \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/ \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_iocon \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_gpio \ + $(TOP)/$(MCUX_DIR)/drivers/sctimer -SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S +SRC_S += $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S diff --git a/hw/bsp/maxim/family.c b/hw/bsp/maxim/family.c index 7ad7d6ff9..6ef4c12c1 100644 --- a/hw/bsp/maxim/family.c +++ b/hw/bsp/maxim/family.c @@ -202,7 +202,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake index e6619992f..f0bf9510b 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake @@ -1,4 +1,5 @@ set(MCU_VARIANT MCXA153) +set(MCU_FAMILY MCXA) set(MCU_CORE MCXA153) set(JLINK_DEVICE MCXA153_M33) @@ -15,10 +16,10 @@ function(update_board TARGET) CFG_EXAMPLE_VIDEO_READONLY ) target_sources(${TARGET} PRIVATE - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/clock_config.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/pin_mux.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c ) target_include_directories(${TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board + ${SDK_DIR}/${MCU_FAMILY}/periph ) endfunction() diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk index 34558b43e..caa2e5a3b 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk @@ -1,4 +1,5 @@ MCU_VARIANT = MCXA153 +MCU_FAMILY = MCXA MCU_CORE = MCXA153 PORT = 0 @@ -9,11 +10,11 @@ CFLAGS += \ -DCFG_EXAMPLE_VIDEO_READONLY SRC_C += \ - ${BOARD_PATH}/board/clock_config.c \ - ${BOARD_PATH}/board/pin_mux.c + ${BOARD_PATH}/clock_config.c \ + ${BOARD_PATH}/pin_mux.c INC += \ - $(TOP)/$(BOARD_PATH)/board + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph JLINK_DEVICE = MCXA153 PYOCD_TARGET = MCXA153 diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c index 599110d7a..599110d7a 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.c +++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h index d609eb468..d609eb468 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h +++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c index 58b0f47e9..58b0f47e9 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c +++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h index 4a42f266d..4a42f266d 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h +++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake index a6aa6c2e4..0d8ec3229 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake +++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake @@ -1,4 +1,5 @@ set(MCU_VARIANT MCXA156) +set(MCU_FAMILY MCXA) set(MCU_CORE MCXA156) set(JLINK_DEVICE MCXA156_M33) @@ -18,4 +19,7 @@ function(update_board TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c ) + target_include_directories(${TARGET} PUBLIC + ${SDK_DIR}/${MCU_FAMILY}/periph1 + ) endfunction() diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.mk b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk index d4a59b32a..9d24b5fab 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa156/board.mk +++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk @@ -1,4 +1,5 @@ MCU_VARIANT = MCXA156 +MCU_FAMILY = MCXA MCU_CORE = MCXA156 PORT = 0 @@ -7,6 +8,9 @@ CFLAGS += \ -DCPU_MCXA156VLH \ -DCFG_TUSB_MCU=OPT_MCU_MCXA15 \ +INC += \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph1 + JLINK_DEVICE = MCXA156 PYOCD_TARGET = MCXA156 diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake index 8c3280743..3bf7851bd 100644 --- a/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake +++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake @@ -1,4 +1,5 @@ set(MCU_VARIANT MCXN947) +set(MCU_FAMILY MCXN) set(MCU_CORE MCXN947_cm33_core0) set(JLINK_DEVICE MCXN947_M33_0) @@ -18,4 +19,7 @@ function(update_board TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c ) + target_include_directories(${TARGET} PUBLIC + ${SDK_DIR}/${MCU_FAMILY}/periph + ) endfunction() diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.mk b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk index 22fefd79b..ee1c94f94 100644 --- a/hw/bsp/mcx/boards/frdm_mcxn947/board.mk +++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk @@ -1,4 +1,5 @@ MCU_VARIANT = MCXN947 +MCU_FAMILY = MCXN MCU_CORE = MCXN947_cm33_core0 PORT ?= 1 @@ -7,6 +8,9 @@ CFLAGS += \ -DCPU_MCXN947VDF_cm33_core0 \ -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \ +INC += \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph + JLINK_DEVICE = MCXN947_M33_0 PYOCD_TARGET = MCXN947 diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake index 8c3280743..3bf7851bd 100644 --- a/hw/bsp/mcx/boards/mcxn947brk/board.cmake +++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake @@ -1,4 +1,5 @@ set(MCU_VARIANT MCXN947) +set(MCU_FAMILY MCXN) set(MCU_CORE MCXN947_cm33_core0) set(JLINK_DEVICE MCXN947_M33_0) @@ -18,4 +19,7 @@ function(update_board TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c ) + target_include_directories(${TARGET} PUBLIC + ${SDK_DIR}/${MCU_FAMILY}/periph + ) endfunction() diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk index 22fefd79b..ee1c94f94 100644 --- a/hw/bsp/mcx/boards/mcxn947brk/board.mk +++ b/hw/bsp/mcx/boards/mcxn947brk/board.mk @@ -1,4 +1,5 @@ MCU_VARIANT = MCXN947 +MCU_FAMILY = MCXN MCU_CORE = MCXN947_cm33_core0 PORT ?= 1 @@ -7,6 +8,9 @@ CFLAGS += \ -DCPU_MCXN947VDF_cm33_core0 \ -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \ +INC += \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph + JLINK_DEVICE = MCXN947_M33_0 PYOCD_TARGET = MCXN947 diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c index 3b91678b1..a3969c217 100644 --- a/hw/bsp/mcx/family.c +++ b/hw/bsp/mcx/family.c @@ -219,7 +219,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index d062cec16..89e2aadf2 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -1,7 +1,8 @@ include_guard() -set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) -set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +set(MCUX_DIR ${TOP}/hw/mcu/nxp/mcuxsdk-core) +set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-devices-mcx) +set(CMSIS_DIR ${TOP}/lib/CMSIS_6) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -26,46 +27,55 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL # Startup & Linker script #------------------------------------ if (NOT DEFINED LD_FILE_GNU) -set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) + set(LD_FILE_GNU ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) + if (NOT DEFINED STARTUP_FILE_GNU) -set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) + set(STARTUP_FILE_GNU ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) endif() set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) +if (NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/iar/${MCU_CORE}_flash.icf) +endif () + +if (NOT DEFINED STARTUP_FILE_IAR) + set(STARTUP_FILE_IAR ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/iar/startup_${MCU_CORE}.s) +endif () + #------------------------------------ # Board Target #------------------------------------ function(family_add_board BOARD_TARGET) add_library(${BOARD_TARGET} STATIC # driver - ${SDK_DIR}/drivers/gpio/fsl_gpio.c - ${SDK_DIR}/drivers/common/fsl_common_arm.c - ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c + ${MCUX_DIR}/drivers/gpio/fsl_gpio.c + ${MCUX_DIR}/drivers/common/fsl_common_arm.c + ${MCUX_DIR}/drivers/lpuart/fsl_lpuart.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc/fsl_spc.c # mcu - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c - ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c + ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/system_${MCU_CORE}.c + ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/fsl_clock.c + ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/fsl_reset.c ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMSIS_DIR}/CMSIS/Core/Include - ${SDK_DIR}/drivers/gpio/ - ${SDK_DIR}/drivers/lpuart - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/port + ${MCUX_DIR}/drivers/gpio/ + ${MCUX_DIR}/drivers/lpuart + ${MCUX_DIR}/drivers/common + ${MCUX_DIR}/drivers/port ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT} + ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers ) if (${FAMILY_MCUS} STREQUAL "MCXN9") target_sources(${BOARD_TARGET} PRIVATE - ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c + ${MCUX_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c ) target_include_directories(${BOARD_TARGET} PUBLIC - ${SDK_DIR}/drivers/lpflexcomm + ${MCUX_DIR}/drivers/lpflexcomm ) elseif(${FAMILY_MCUS} STREQUAL "MCXA15") endif() @@ -100,7 +110,8 @@ function(family_configure_example TARGET RTOS) target_link_options(${TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" --specs=nosys.specs --specs=nano.specs - #-nostartfiles + "LINKER:--defsym=__stack_size__=0x1000" + "LINKER:--defsym=__heap_size__=0" ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${TARGET} PUBLIC @@ -109,6 +120,8 @@ function(family_configure_example TARGET RTOS) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${TARGET} PUBLIC "LINKER:--config=${LD_FILE_IAR}" + "LINKER:--config_def=__stack_size__=0x1000" + "LINKER:--config_def=__heap_size__=0" ) endif () diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk index 4321e654a..3d63eb238 100644 --- a/hw/bsp/mcx/family.mk +++ b/hw/bsp/mcx/family.mk @@ -1,7 +1,9 @@ UF2_FAMILY_ID = 0x2abc77ec -SDK_DIR = hw/mcu/nxp/mcux-sdk include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m33 +MCUX_DIR = hw/mcu/nxp/mcuxsdk-core +SDK_DIR = hw/mcu/nxp/mcux-devices-mcx # Default to Highspeed PORT1 PORT ?= 1 @@ -13,10 +15,13 @@ CFLAGS += \ # mcu driver cause following warnings CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration -Wno-error=redundant-decls -LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs +LDFLAGS_GCC += \ + --specs=nosys.specs --specs=nano.specs \ + -Wl,--defsym=__stack_size__=0x1000 \ + -Wl,--defsym=__heap_size__=0 \ # All source paths should be relative to the top level. -LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld +LD_FILE ?= $(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS ifeq ($(PORT), 1) @@ -30,17 +35,17 @@ else endif SRC_C += \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \ - ${SDK_DIR}/drivers/gpio/fsl_gpio.c \ - ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c \ - ${SDK_DIR}/drivers/common/fsl_common_arm.c\ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/system_$(MCU_CORE).c \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers/fsl_clock.c \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers/fsl_reset.c \ + $(TOP)/$(MCUX_DIR)/drivers/gpio/fsl_gpio.c \ + $(TOP)/$(MCUX_DIR)/drivers/lpuart/fsl_lpuart.c \ + $(TOP)/$(MCUX_DIR)/drivers/common/fsl_common_arm.c \ hw/bsp/mcx/drivers/spc/fsl_spc.c # fsl_lpflexcomm for MCXN9 ifeq ($(MCU_VARIANT), MCXN947) - SRC_C += ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c + SRC_C += $(MCUX_DIR)/drivers/lpflexcomm/fsl_lpflexcomm.c endif # fsl_spc for MCXNA15 @@ -50,15 +55,15 @@ endif INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \ - $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \ - $(TOP)/$(SDK_DIR)/drivers/ \ - $(TOP)/$(SDK_DIR)/drivers/lpuart \ - $(TOP)/$(SDK_DIR)/drivers/lpflexcomm \ - $(TOP)/$(SDK_DIR)/drivers/common\ - $(TOP)/$(SDK_DIR)/drivers/gpio\ - $(TOP)/$(SDK_DIR)/drivers/port\ + $(TOP)/lib/CMSIS_6/CMSIS/Core/Include \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT) \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers \ + $(TOP)/$(MCUX_DIR)/drivers/ \ + $(TOP)/$(MCUX_DIR)/drivers/lpuart \ + $(TOP)/$(MCUX_DIR)/drivers/lpflexcomm \ + $(TOP)/$(MCUX_DIR)/drivers/common \ + $(TOP)/$(MCUX_DIR)/drivers/gpio \ + $(TOP)/$(MCUX_DIR)/drivers/port \ $(TOP)/hw/bsp/mcx/drivers/spc -SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S +SRC_S += $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S diff --git a/hw/bsp/mm32/family.c b/hw/bsp/mm32/family.c index 663c30818..330b01f6d 100644 --- a/hw/bsp/mm32/family.c +++ b/hw/bsp/mm32/family.c @@ -175,7 +175,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/msp430/family.c b/hw/bsp/msp430/family.c index 390a9915e..413ad7db6 100644 --- a/hw/bsp/msp430/family.c +++ b/hw/bsp/msp430/family.c @@ -102,10 +102,10 @@ static void SystemClock_Config(void) // VUSB enabled automatically. // Wait two milliseconds to stabilize, per manual recommendation. - uint32_t ms_elapsed = board_millis(); + uint32_t ms_elapsed = tusb_time_millis_api(); do { - while((board_millis() - ms_elapsed) < 2); + while((tusb_time_millis_api() - ms_elapsed) < 2); }while(!(USBPWRCTL & USBBGVBV)); // USB uses XT2 (4 MHz) directly. Enable the PLL. @@ -113,11 +113,11 @@ static void SystemClock_Config(void) USBPLLCTL |= (UPFDEN | UPLLEN); // Wait until PLL locks. Check every 2ms, per manual. - ms_elapsed = board_millis(); + ms_elapsed = tusb_time_millis_api(); do { USBPLLIR &= ~USBOOLIFG; - while((board_millis() - ms_elapsed) < 2); + while((tusb_time_millis_api() - ms_elapsed) < 2); }while(USBPLLIR & USBOOLIFG); USBKEYPID = 0; @@ -207,7 +207,7 @@ void TIMER0_A0_ISR (void) { // TAxCCR0 CCIFG resets itself as soon as interrupt is invoked. } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { uint32_t systick_mirror; diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c index 0e1b0528a..90eb945f4 100644 --- a/hw/bsp/msp432e4/family.c +++ b/hw/bsp/msp432e4/family.c @@ -202,7 +202,7 @@ void SysTick_Handler(void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index ee3ac61e2..04bfbf320 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -296,7 +296,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/nuc100_120/family.c b/hw/bsp/nuc100_120/family.c index 752af2a56..cfe60121c 100644 --- a/hw/bsp/nuc100_120/family.c +++ b/hw/bsp/nuc100_120/family.c @@ -87,7 +87,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/nuc121_125/family.c b/hw/bsp/nuc121_125/family.c index 089855207..dce5b4d62 100644 --- a/hw/bsp/nuc121_125/family.c +++ b/hw/bsp/nuc121_125/family.c @@ -86,7 +86,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/nuc126/family.c b/hw/bsp/nuc126/family.c index f992fcab4..3343064e5 100644 --- a/hw/bsp/nuc126/family.c +++ b/hw/bsp/nuc126/family.c @@ -111,7 +111,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/nuc505/family.c b/hw/bsp/nuc505/family.c index 00ed92310..f1a77e4a5 100644 --- a/hw/bsp/nuc505/family.c +++ b/hw/bsp/nuc505/family.c @@ -88,7 +88,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/pic32mz/family.c b/hw/bsp/pic32mz/family.c index da97f67a9..2bfc876e1 100644 --- a/hw/bsp/pic32mz/family.c +++ b/hw/bsp/pic32mz/family.c @@ -106,7 +106,7 @@ TU_ATTR_WEAK int board_uart_write(void const * buf, int len) } #if CFG_TUSB_OS == OPT_OS_NONE -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { // COUNTER is system clock (200MHz / 2 = 100MHz) convert to ms) return _CP0_GET_COUNT() / (100000000 / 1000); diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 1f75b47c1..f371e694b 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -169,7 +169,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index a51b3f758..adb58449d 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -370,7 +370,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx }else if (rx_buf == NULL) { ret = spi_write_blocking(MAX3421_SPI, tx_buf, xfer_bytes); }else { - ret = spi_write_read_blocking(spi0, tx_buf, rx_buf, xfer_bytes); + ret = spi_write_read_blocking(MAX3421_SPI, tx_buf, rx_buf, xfer_bytes); } return ret == (int) xfer_bytes; diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 82d0034a1..e31abe50b 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -98,6 +98,7 @@ target_sources(tinyusb_device_base INTERFACE ${TOP}/src/class/mtp/mtp_device.c ${TOP}/src/class/net/ecm_rndis_device.c ${TOP}/src/class/net/ncm_device.c + ${TOP}/src/class/printer/printer_device.c ${TOP}/src/class/usbtmc/usbtmc_device.c ${TOP}/src/class/vendor/vendor_device.c ${TOP}/src/class/video/video_device.c diff --git a/hw/bsp/rw61x/family.c b/hw/bsp/rw61x/family.c index 265d5fcc0..fcc7fb262 100644 --- a/hw/bsp/rw61x/family.c +++ b/hw/bsp/rw61x/family.c @@ -128,7 +128,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c index 26ad4a6aa..e5b24bf69 100644 --- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c +++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c @@ -248,7 +248,7 @@ void INT_Excep_CMT0_CMI0(void) ++system_ticks; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c index 66a319541..d5c2de05a 100644 --- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c +++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c @@ -299,7 +299,7 @@ void INT_Excep_CMT0_CMI0(void) ++system_ticks; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/samd11/family.c b/hw/bsp/samd11/family.c index 6cbf02412..bccbac8ea 100644 --- a/hw/bsp/samd11/family.c +++ b/hw/bsp/samd11/family.c @@ -155,7 +155,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/samd2x_l2x/family.c b/hw/bsp/samd2x_l2x/family.c index a2dc8a8d4..737219b6c 100644 --- a/hw/bsp/samd2x_l2x/family.c +++ b/hw/bsp/samd2x_l2x/family.c @@ -361,7 +361,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/samd5x_e5x/family.c b/hw/bsp/samd5x_e5x/family.c index 5a7105894..c008b9719 100644 --- a/hw/bsp/samd5x_e5x/family.c +++ b/hw/bsp/samd5x_e5x/family.c @@ -210,7 +210,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/same7x/boards/same70_qmtech/board.cmake b/hw/bsp/same7x/boards/same70_qmtech/board.cmake index cde4c3da6..fc2071b3a 100644 --- a/hw/bsp/same7x/boards/same70_qmtech/board.cmake +++ b/hw/bsp/same7x/boards/same70_qmtech/board.cmake @@ -1,5 +1,8 @@ -set(JLINK_DEVICE SAME70N19B) -set(LD_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/same70q21b_flash.ld) +set(JLINK_DEVICE ATSAME70N19B) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/same70n19b_flash.ld) + +# N19B and Q21B share the same vector table / startup code +set(STARTUP_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/startup_same70q21b.c) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/same7x/boards/same70_qmtech/board.mk b/hw/bsp/same7x/boards/same70_qmtech/board.mk index 09ae98860..4ad8212a8 100644 --- a/hw/bsp/same7x/boards/same70_qmtech/board.mk +++ b/hw/bsp/same7x/boards/same70_qmtech/board.mk @@ -1,3 +1,6 @@ CFLAGS += -D__SAME70N19B__ -JLINK_DEVICE = SAME70N19B +LD_FILE = $(BOARD_PATH)/same70n19b_flash.ld +STARTUP_FILE = $(SDK_DIR)/same70b/gcc/gcc/startup_same70q21b.c + +JLINK_DEVICE = ATSAME70N19B diff --git a/hw/bsp/same7x/boards/same70_xplained/board.cmake b/hw/bsp/same7x/boards/same70_xplained/board.cmake index b226b6c4f..f762464a6 100644 --- a/hw/bsp/same7x/boards/same70_xplained/board.cmake +++ b/hw/bsp/same7x/boards/same70_xplained/board.cmake @@ -1,5 +1,9 @@ -set(JLINK_DEVICE SAME70Q21B) +set(JLINK_DEVICE ATSAME70Q21B) set(LD_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/same70q21b_flash.ld) +set(LD_FILE_IAR ${TOP}/hw/mcu/microchip/same70/same70b/iar/config/linker/Microchip/atsame70q21b/flash.icf) + +set(STARTUP_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/startup_same70q21b.c) +set(STARTUP_FILE_IAR ${TOP}/hw/mcu/microchip/same70/same70b/iar/iar/startup_same70q21b.c) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/same7x/boards/same70_xplained/board.mk b/hw/bsp/same7x/boards/same70_xplained/board.mk index ca23a9be5..231d5d770 100644 --- a/hw/bsp/same7x/boards/same70_xplained/board.mk +++ b/hw/bsp/same7x/boards/same70_xplained/board.mk @@ -1,3 +1,6 @@ CFLAGS += -D__SAME70Q21B__ -JLINK_DEVICE = SAME70Q21B +LD_FILE = $(SDK_DIR)/same70b/gcc/gcc/same70q21b_flash.ld +STARTUP_FILE = $(SDK_DIR)/same70b/gcc/gcc/startup_same70q21b.c + +JLINK_DEVICE = ATSAME70Q21B diff --git a/hw/bsp/same7x/family.c b/hw/bsp/same7x/family.c index 6feefa3b5..61c1792d1 100644 --- a/hw/bsp/same7x/family.c +++ b/hw/bsp/same7x/family.c @@ -42,56 +42,15 @@ static inline void board_vbus_set(uint8_t rhport, bool state); void _init(void); #include "board.h" -#ifndef LED_STATE_ON - #define LED_STATE_ON 1 -#endif - -#ifndef LED_PORT_CLOCK - #define LED_PORT_CLOCK ID_PIOA -#endif - -#ifndef BUTTON_PORT_CLOCK - #define BUTTON_PORT_CLOCK ID_PIOA -#endif - -#ifndef UART_PORT_CLOCK - #define UART_PORT_CLOCK ID_USART1 -#endif - -#ifndef BOARD_USART - #define BOARD_USART USART1 -#endif - -#ifndef BOARD_UART_DESCRIPTOR - #define BOARD_UART_DESCRIPTOR edbg_com -#endif - -#ifndef BOARD_UART_BUFFER - #define BOARD_UART_BUFFER edbg_com_buffer -#endif - -#ifndef BUTTON_STATE_ACTIVE - #define BUTTON_STATE_ACTIVE 0 -#endif - -#ifndef UART_TX_FUNCTION - #define UART_TX_FUNCTION MUX_PB4D_USART1_TXD1 -#endif - -#ifndef UART_RX_FUNCTION - #define UART_RX_FUNCTION MUX_PA21A_USART1_RXD1 -#endif - #ifndef UART_BUFFER_SIZE #define UART_BUFFER_SIZE 64 #endif #define LED_STATE_OFF (1 - LED_STATE_ON) -static struct usart_async_descriptor BOARD_UART_DESCRIPTOR; -static uint8_t BOARD_UART_BUFFER[UART_BUFFER_SIZE]; +static struct usart_async_descriptor edbg_com; +static uint8_t edbg_com_buffer[UART_BUFFER_SIZE]; static volatile bool uart_busy = false; - static void tx_complete_cb(const struct usart_async_descriptor *const io_descr) { (void) io_descr; uart_busy = false; @@ -121,10 +80,10 @@ void board_init(void) { gpio_set_pin_function(UART_RX_PIN, UART_RX_FUNCTION); gpio_set_pin_function(UART_TX_PIN, UART_TX_FUNCTION); - usart_async_init(&BOARD_UART_DESCRIPTOR, BOARD_USART, BOARD_UART_BUFFER, sizeof(BOARD_UART_BUFFER), _usart_get_usart_async()); - usart_async_set_baud_rate(&BOARD_UART_DESCRIPTOR, CFG_BOARD_UART_BAUDRATE); - usart_async_register_callback(&BOARD_UART_DESCRIPTOR, USART_ASYNC_TXC_CB, tx_complete_cb); - usart_async_enable(&BOARD_UART_DESCRIPTOR); + usart_async_init(&edbg_com, BOARD_USART, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async()); + usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE); + usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_complete_cb); + usart_async_enable(&edbg_com); #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer (SystemCoreClock may not be correct after init) @@ -181,10 +140,40 @@ int board_uart_write(void const *buf, int len) { while (uart_busy) {} uart_busy = true; - io_write(&BOARD_UART_DESCRIPTOR.io, buf, len); + io_write(&edbg_com.io, buf, len); return len; } +// Read 128-bit unique ID via EFC STUI/SPUI commands +// Must run from RAM since STUI remaps flash to the unique ID +__attribute__((noinline)) TU_ATTR_SECTION(.ramfunc) static void read_unique_id(uint32_t uid[4]) { + // Wait for flash to be ready + while (!(EFC->EEFC_FSR & EEFC_FSR_FRDY)) {} + + // Issue Start Read Unique Identifier command + EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_STUI; + while (EFC->EEFC_FSR & EEFC_FSR_FRDY) {} + + // Read 128-bit unique ID from flash base address + const volatile uint32_t *flash = (const volatile uint32_t *) IFLASH_ADDR; + for (int i = 0; i < 4; i++) { + uid[i] = flash[i]; + } + + // Issue Stop Read Unique Identifier command + EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SPUI; + while (!(EFC->EEFC_FSR & EEFC_FSR_FRDY)) {} +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + const size_t uid_len = 16; + if (max_len < uid_len) { + return 0; + } + read_unique_id((uint32_t *)(uintptr_t) id); + return uid_len; +} + #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; @@ -192,7 +181,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/same7x/family.cmake b/hw/bsp/same7x/family.cmake index a9c9de413..63726a8e5 100644 --- a/hw/bsp/same7x/family.cmake +++ b/hw/bsp/same7x/family.cmake @@ -13,7 +13,6 @@ set(FAMILY_MCUS SAMX7X CACHE INTERNAL "") #------------------------------------ # Startup & Linker script #------------------------------------ -set(STARTUP_FILE_GNU ${SDK_DIR}/same70b/gcc/gcc/startup_same70q21b.c) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) set(LD_FILE_Clang ${LD_FILE_GNU}) @@ -47,12 +46,9 @@ function(family_add_board BOARD_TARGET) update_board(${BOARD_TARGET}) - target_compile_options(${BOARD_TARGET} PUBLIC - -Wno-error=unused-parameter - -Wno-error=cast-align - -Wno-error=redundant-decls - -Wno-error=cast-qual - ) + if (TOOLCHAIN STREQUAL "gcc" OR TOOLCHAIN STREQUAL "clang") + set_target_properties(${BOARD_TARGET} PROPERTIES COMPILE_FLAGS -Wno-error=cast-qual) + endif () endfunction() #------------------------------------ @@ -89,9 +85,13 @@ function(family_configure_example TARGET RTOS) "LINKER:--config=${LD_FILE_IAR}" ) endif () - set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES - SKIP_LINTING ON - COMPILE_OPTIONS -w) + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang") + # ignore hal error + set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + PROPERTIES + SKIP_LINTING ON + COMPILE_OPTIONS -w) + endif() family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) diff --git a/hw/bsp/same7x/family.mk b/hw/bsp/same7x/family.mk index c8fa74d71..19e119625 100644 --- a/hw/bsp/same7x/family.mk +++ b/hw/bsp/same7x/family.mk @@ -21,11 +21,9 @@ CFLAGS_SKIP += -Wcast-qual LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs # All source paths should be relative to the top level. -LD_FILE = $(SDK_DIR)/same70b/gcc/gcc/same70q21b_flash.ld - SRC_C += \ src/portable/microchip/samx7x/dcd_samx7x.c \ - $(SDK_DIR)/same70b/gcc/gcc/startup_same70q21b.c \ + $(STARTUP_FILE) \ $(SDK_DIR)/same70b/gcc/system_same70q21b.c \ $(SDK_DIR)/hpl/core/hpl_init.c \ $(SDK_DIR)/hpl/usart/hpl_usart.c \ @@ -48,9 +46,6 @@ INC += \ $(TOP)/$(SDK_DIR)/hri \ $(TOP)/$(SDK_DIR)/CMSIS/Core/Include -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7 - # For flash-jlink target flash: $(BUILD)/$(PROJECT).bin edbg --verbose -t same70 -pv -f $< diff --git a/hw/bsp/samg/family.c b/hw/bsp/samg/family.c index 5c5fc3c14..b27134305 100644 --- a/hw/bsp/samg/family.c +++ b/hw/bsp/samg/family.c @@ -148,7 +148,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32c0/family.c b/hw/bsp/stm32c0/family.c index e2ba47f45..e20c0ee15 100644 --- a/hw/bsp/stm32c0/family.c +++ b/hw/bsp/stm32c0/family.c @@ -173,7 +173,7 @@ void SysTick_Handler(void) { HAL_IncTick(); } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c index b99b0a8cc..5a35a3e50 100644 --- a/hw/bsp/stm32f0/family.c +++ b/hw/bsp/stm32f0/family.c @@ -160,7 +160,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c index 3147061cf..78a425453 100644 --- a/hw/bsp/stm32f1/family.c +++ b/hw/bsp/stm32f1/family.c @@ -148,12 +148,12 @@ void board_init(void) { #ifdef USB_CONNECT_PIN void dcd_disconnect(uint8_t rhport) { (void)rhport; - HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, 1-USB_CONNECT_STATE); + HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, (GPIO_PinState)(1 - USB_CONNECT_STATE)); } void dcd_connect(uint8_t rhport) { (void)rhport; - HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, USB_CONNECT_STATE); + HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, (GPIO_PinState)USB_CONNECT_STATE); } #endif @@ -202,7 +202,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32f2/family.c b/hw/bsp/stm32f2/family.c index f95128040..f1fd4ddb2 100644 --- a/hw/bsp/stm32f2/family.c +++ b/hw/bsp/stm32f2/family.c @@ -35,7 +35,7 @@ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ void OTG_FS_IRQHandler(void) { - tud_int_handler(0); + tusb_int_handler(0, true); } //--------------------------------------------------------------------+ @@ -145,7 +145,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32f3/family.c b/hw/bsp/stm32f3/family.c index 95bcc7882..fde1e9f6d 100644 --- a/hw/bsp/stm32f3/family.c +++ b/hw/bsp/stm32f3/family.c @@ -156,7 +156,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h deleted file mode 100644 index b892df3b6..000000000 --- a/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,491 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED - -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_EXTI_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)12000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -/* Copied over manually- STM32Cube didn't generate these for some reason. */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848_PHY_ADDRESS Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) - -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h deleted file mode 100644 index b892df3b6..000000000 --- a/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,491 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED - -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_EXTI_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)12000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -/* Copied over manually- STM32Cube didn't generate these for some reason. */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848_PHY_ADDRESS Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) - -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h deleted file mode 100644 index 16f081cfb..000000000 --- a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (25000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h deleted file mode 100644 index e24e782ea..000000000 --- a/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h deleted file mode 100644 index e24e782ea..000000000 --- a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake index d16db508f..f54807c2a 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake @@ -6,5 +6,6 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F411CEUx_FLASH.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F411xE + HSE_VALUE=25000000 ) endfunction() diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk index 7af7ca47c..c45aba79b 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -DSTM32F411xE +CFLAGS += -DSTM32F411xE -DHSE_VALUE=25000000 # GCC SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h deleted file mode 100644 index 16f081cfb..000000000 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (25000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h deleted file mode 100644 index e24e782ea..000000000 --- a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h deleted file mode 100644 index e24e782ea..000000000 --- a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h deleted file mode 100644 index e24e782ea..000000000 --- a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h deleted file mode 100644 index 7bbd6b54f..000000000 --- a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,486 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* LAN8742A_PHY_ADDRESS Address*/ -#define LAN8742A_PHY_ADDRESS 0U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -#define PHY_ISFR ((uint16_t)0x001DU) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c index f0e9620f2..665ea114a 100644 --- a/hw/bsp/stm32f4/family.c +++ b/hw/bsp/stm32f4/family.c @@ -251,7 +251,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk index c3c41dc3f..f3e74ecea 100644 --- a/hw/bsp/stm32f4/family.mk +++ b/hw/bsp/stm32f4/family.mk @@ -71,6 +71,7 @@ SRC_C += \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c INC += \ + $(TOP)/hw/bsp/stm32$(ST_FAMILY) \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(ST_CMSIS)/Include \ diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index d8f0da201..ce9049abe 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -312,7 +312,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c index 4b175b0ec..b25897264 100644 --- a/hw/bsp/stm32g0/family.c +++ b/hw/bsp/stm32g0/family.c @@ -181,7 +181,7 @@ void SysTick_Handler(void) { HAL_IncTick(); } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index d8afa0f95..2e13a1d4b 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -211,7 +211,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32h5/family.c b/hw/bsp/stm32h5/family.c index fdb12e44f..1e8acd502 100644 --- a/hw/bsp/stm32h5/family.c +++ b/hw/bsp/stm32h5/family.c @@ -207,7 +207,7 @@ void SysTick_Handler(void) { HAL_IncTick(); } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h index 44ca58dc5..d2f61a5ce 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h @@ -120,13 +120,13 @@ static inline void SystemClock_Config(void) { // From H743 eval manual ETM can only work at 50 MHz clock by default because ETM signals // are shared with other peripherals. Trace CLK = PLL1R. RCC_OscInitStruct.PLL.PLLM = 5; - RCC_OscInitStruct.PLL.PLLN = 160; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 4; - RCC_OscInitStruct.PLL.PLLR = 6; // Trace clock is 400/6 = 66.67 MHz (larger than 50 MHz but work well) + RCC_OscInitStruct.PLL.PLLN = 160; // May reduce to 100/200 Mhz when tracing to avoid overflowing trace buffer + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = RCC_OscInitStruct.PLL.PLLN/10; // Trace clock is limit to 50 Mhz to meet board requirement + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; RCC_OscInitStruct.PLL.PLLFRACN = 0; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; HAL_RCC_OscConfig(&RCC_OscInitStruct); diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc index 0e5a4cc00..a2e11012f 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc +++ b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc @@ -193,8 +193,8 @@ Mcu.PinsNb=169 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32H743XIHx -MxCube.Version=6.10.0 -MxDb.Version=DB.6.0.100 +MxCube.Version=6.12.1 +MxDb.Version=DB.6.0.121 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false NVIC.ForceEnableDMAVector=true @@ -880,12 +880,12 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32H743XIHx -ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.0 +ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.2 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=false +ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=2 ProjectManager.MainLocation=Src ProjectManager.NoMain=false @@ -933,8 +933,8 @@ RCC.DIVQ1Freq_Value=200000000 RCC.DIVQ2Freq_Value=50390625 RCC.DIVQ3=7 RCC.DIVQ3Freq_Value=48000000 -RCC.DIVR1=6 -RCC.DIVR1Freq_Value=133333333.33333333 +RCC.DIVR1=8 +RCC.DIVR1Freq_Value=100000000 RCC.DIVR2Freq_Value=50390625 RCC.DIVR3Freq_Value=168000000 RCC.EnbaleCSS=true @@ -979,7 +979,7 @@ RCC.SYSCLKFreq_VALUE=400000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.Tim1OutputFreq_Value=200000000 RCC.Tim2OutputFreq_Value=200000000 -RCC.TraceFreq_Value=133333333.33333333 +RCC.TraceFreq_Value=100000000 RCC.USART16Freq_Value=100000000 RCC.USART234578Freq_Value=100000000 RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3 diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug index 0ab078319..32a8155c1 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug +++ b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug @@ -9,6 +9,10 @@ ********************************************************************** */ void OnProjectLoad (void) { + Project.SetTraceSource ("Trace Pins"); + Project.SetTraceTiming (100, 100, 100, 100); + Project.SetSWO (0); + Edit.SysVar (VAR_TRACE_CORE_CLOCK, 200000000); Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M7F.svd"); Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd"); Project.AddSvdFile ("./STM32H743.svd"); @@ -18,12 +22,8 @@ void OnProjectLoad (void) { Project.SetTargetIF ("SWD"); Project.SetTIFSpeed ("50 MHz"); - Project.SetTraceSource ("Trace Pins"); - Project.SetTracePortWidth (4); - // timing delay for trace pins in pico seconds, default is 2 nano seconds - Project.SetTraceTiming (100, 100, 100, 100); - File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-stm32h743eval/cdc_msc.elf"); + // File.Open ("../../../../../../examples/cmake-build-stm32h743eval_host1/host/cdc_msc_hid/cdc_msc_hid.elf"); } /********************************************************************* diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index a320a7e72..c94c2e755 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -139,6 +139,10 @@ void board_init(void) { #endif NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + +#elif CFG_TUSB_OS == OPT_OS_THREADX + // Disable SysTick before kernel entry; _tx_initialize_low_level() will re-configure it + SysTick->CTRL &= ~1UL; #endif GPIO_InitTypeDef GPIO_InitStruct; @@ -295,10 +299,15 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } +#elif CFG_TUSB_OS == OPT_OS_THREADX +// Keep HAL_GetTick() working for HAL functions called from board_init() +void osal_threadx_tick_cb(void) { + HAL_IncTick(); +} #endif void HardFault_Handler(void) { diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h index 16c2fd335..4b8564709 100644 --- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h @@ -62,7 +62,7 @@ static board_pindef_t board_pindef[] = { { // Button .port = GPIOC, .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0 }, - .active_state = 1 + .active_state = 0 }, { // UART TX .port = GPIOD, diff --git a/hw/bsp/stm32h7rs/family.c b/hw/bsp/stm32h7rs/family.c index 2cc39b7ac..3bf75ba97 100644 --- a/hw/bsp/stm32h7rs/family.c +++ b/hw/bsp/stm32h7rs/family.c @@ -468,7 +468,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c index 6aeab1259..7fd076dbd 100644 --- a/hw/bsp/stm32l0/family.c +++ b/hw/bsp/stm32l0/family.c @@ -123,7 +123,8 @@ void board_init(void) { //--------------------------------------------------------------------+ void board_led_write(bool state) { - HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); + GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON)); + HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state); } uint32_t board_button_read(void) { @@ -168,7 +169,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c index 65f6b9ab3..c87b643b8 100644 --- a/hw/bsp/stm32l4/family.c +++ b/hw/bsp/stm32l4/family.c @@ -231,7 +231,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32n6/family.c b/hw/bsp/stm32n6/family.c index c839e6b3e..4354616c3 100644 --- a/hw/bsp/stm32n6/family.c +++ b/hw/bsp/stm32n6/family.c @@ -366,7 +366,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32u0/family.c b/hw/bsp/stm32u0/family.c index 50b513d8f..0f91d1f30 100644 --- a/hw/bsp/stm32u0/family.c +++ b/hw/bsp/stm32u0/family.c @@ -174,7 +174,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c index dfcf5c537..55ca25d58 100644 --- a/hw/bsp/stm32u5/family.c +++ b/hw/bsp/stm32u5/family.c @@ -270,7 +270,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c index 153d10a09..de503c072 100644 --- a/hw/bsp/stm32wb/family.c +++ b/hw/bsp/stm32wb/family.c @@ -174,7 +174,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32wba/family.c b/hw/bsp/stm32wba/family.c index d05415755..878355b48 100644 --- a/hw/bsp/stm32wba/family.c +++ b/hw/bsp/stm32wba/family.c @@ -175,7 +175,10 @@ void board_init(void) { #endif // USB_OTG_HS } -void board_led_write(bool state) { HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); } +void board_led_write(bool state) { + GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON)); + HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state); +} uint32_t board_button_read(void) { return HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN) == BUTTON_STATE_ACTIVE; } @@ -198,7 +201,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { return system_ticks; } +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif void HardFault_Handler(void) { asm( "bkpt 1" ); } diff --git a/hw/bsp/tm4c/family.c b/hw/bsp/tm4c/family.c index ae7f22f00..503d0a8c9 100644 --- a/hw/bsp/tm4c/family.c +++ b/hw/bsp/tm4c/family.c @@ -211,7 +211,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c index 6fef53025..d0acd04cb 100644 --- a/hw/bsp/xmc4000/family.c +++ b/hw/bsp/xmc4000/family.c @@ -147,7 +147,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } |