Revert "Merge branch 'hathach:master' into MCX"

This reverts commit 6afd4a57896f9c9e794de3ab6eabc73d18be4bd0, reversing
changes made to 5c14bd13da211ff2679115b0dba96ac80c1a516c.

10 files changed, 8 insertions, 994 deletions

diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
index c4dc65b63..f69700139 100644
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
@@ -8,6 +8,9 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld
 
+SRC_C += \
+	$(MCU_DIR)/project_template/clock_config.c \
+
 # For flash-jlink target
 JLINK_DEVICE = K32L2A41xxxxA
 
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c
deleted file mode 100644
index 2814efc86..000000000
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * Copyright 2019 ,2021 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
- *    Note: The clock could not be set when it is being used as system clock.
- *    In default out of reset, the CPU is clocked from FIRC(IRC48M),
- *    so before setting FIRC, change to use another available clock source.
- *
- * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
- *
- * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
- *    Wait until the system clock source is changed to target source.
- *
- * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
- *    corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
- *    Supported run mode and clock restrictions could be found in Reference Manual.
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v7.0
-processor: K32L2A41xxxxA
-package_id: K32L2A41VLL1A
-mcu_data: ksdk2_0
-processor_version: 9.0.0
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "fsl_smc.h"
-#include "clock_config.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define SCG_CLKOUTCNFG_SIRC                               2U  /*!< SCG CLKOUT clock select: Slow IRC */
-#define SCG_SOSC_DISABLE                                  0U  /*!< System OSC disabled */
-#define SCG_SPLL_DISABLE                                  0U  /*!< System PLL disabled */
-#define SCG_SYS_OSC_CAP_0P                                0U  /*!< Oscillator 0pF capacitor load */
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-/*FUNCTION**********************************************************************
- *
- * Function Name : CLOCK_CONFIG_SetScgOutSel
- * Description   : Set the SCG clock out select (CLKOUTSEL).
- * Param setting : The selected clock source.
- *
- *END**************************************************************************/
-static void CLOCK_CONFIG_SetScgOutSel(uint8_t setting)
-{
-     SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
-}
-
-/*FUNCTION**********************************************************************
- *
- * Function Name : CLOCK_CONFIG_FircSafeConfig
- * Description   : This function is used to safely configure FIRC clock.
- *                 In default out of reset, the CPU is clocked from FIRC(IRC48M).
- *                 Before setting FIRC, change to use SIRC as system clock,
- *                 then configure FIRC. After FIRC is set, change back to use FIRC
- *                 in case SIRC need to be configured.
- * Param fircConfig  : FIRC configuration.
- *
- *END**************************************************************************/
-static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
-{
-    scg_sys_clk_config_t curConfig;
-    const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
-                                             .div1 = kSCG_AsyncClkDisable,
-                                             .div3 = kSCG_AsyncClkDivBy2,
-                                             .range = kSCG_SircRangeHigh};
-    scg_sys_clk_config_t sysClkSafeConfigSource = {
-         .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-         .reserved1 = 0,
-         .reserved2 = 0,
-         .reserved3 = 0,
-#endif
-         .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-         .reserved4 = 0,
-#endif
-         .src = kSCG_SysClkSrcSirc,    /* System clock source */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-         .reserved5 = 0,
-#endif
-    };
-    /* Init Sirc. */
-    CLOCK_InitSirc(&scgSircConfig);
-    /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
-    CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
-    /* Wait for clock source switch finished. */
-    do
-    {
-         CLOCK_GetCurSysClkConfig(&curConfig);
-    } while (curConfig.src != sysClkSafeConfigSource.src);
-
-    /* Init Firc. */
-    CLOCK_InitFirc(fircConfig);
-    /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
-    sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
-    CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
-    /* Wait for clock source switch finished. */
-    do
-    {
-         CLOCK_GetCurSysClkConfig(&curConfig);
-    } while (curConfig.src != sysClkSafeConfigSource.src);
-}
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockRUN();
-}
-
-/*******************************************************************************
- ********************** Configuration BOARD_BootClockRUN ***********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockRUN
-called_from_default_init: true
-outputs:
-- {id: Core_clock.outFreq, value: 48 MHz}
-- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
-- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
-- {id: SIRCDIV3_CLK.outFreq, value: 4 MHz}
-- {id: SIRC_CLK.outFreq, value: 8 MHz}
-- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
-- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
-- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
-- {id: Slow_clock.outFreq, value: 24 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
-- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
-- {id: SCG.SIRCDIV3.scale, value: '2', locked: true}
-- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
-- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
-sources:
-- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockRUN configuration
- ******************************************************************************/
-const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
-    {
-        .divSlow = kSCG_SysClkDivBy2,             /* Slow Clock Divider: divided by 2 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved1 = 0,
-        .reserved2 = 0,
-        .reserved3 = 0,
-#endif
-        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved4 = 0,
-#endif
-        .src = kSCG_SysClkSrcFirc,                /* Fast IRC is selected as System Clock Source */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved5 = 0,
-#endif
-    };
-const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
-    {
-        .freq = 32768U,                           /* System Oscillator frequency: 32768Hz */
-        .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
-        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDivBy1,              /* System OSC Clock Divider 3: divided by 1 */
-        .capLoad = SCG_SYS_OSC_CAP_0P,            /* Oscillator capacity load: 0pF */
-        .workMode = kSCG_SysOscModeOscLowPower,   /* Oscillator low power */
-    };
-const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
-    {
-        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
-        .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDivBy2,              /* Slow IRC Clock Divider 3: divided by 2 */
-        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
-    };
-const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
-    {
-        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
-        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
-        .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
-        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
-        .trimConfig = NULL,                       /* Fast IRC Trim disabled */
-    };
-const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN =
-    {
-        .enableMode = SCG_SPLL_DISABLE,           /* System PLL disabled */
-        .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 3: Clock output is disabled */
-        .src = kSCG_SysPllSrcSysOsc,              /* System PLL clock source is System OSC */
-        .prediv = 0,                              /* Divided by 1 */
-        .mult = 0,                                /* Multiply Factor is 16 */
-    };
-/*******************************************************************************
- * Code for BOARD_BootClockRUN configuration
- ******************************************************************************/
-void BOARD_BootClockRUN(void)
-{
-    scg_sys_clk_config_t curConfig;
-
-    /* Init SOSC according to board configuration. */
-    CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
-    /* Set the XTAL0 frequency based on board settings. */
-    CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
-    /* Init FIRC. */
-    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
-    /* Init SIRC. */
-    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
-    /* Set SCG to FIRC mode. */
-    CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
-    /* Wait for clock source switch finished. */
-    do
-    {
-         CLOCK_GetCurSysClkConfig(&curConfig);
-    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockHSRUN **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockHSRUN
-outputs:
-- {id: CLKOUT.outFreq, value: 8 MHz}
-- {id: Core_clock.outFreq, value: 96 MHz, locked: true, accuracy: '0.001'}
-- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
-- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
-- {id: PLLDIV1_CLK.outFreq, value: 96 MHz}
-- {id: PLLDIV3_CLK.outFreq, value: 96 MHz}
-- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
-- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
-- {id: SIRC_CLK.outFreq, value: 8 MHz}
-- {id: SOSCDIV1_CLK.outFreq, value: 32.768 kHz}
-- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
-- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
-- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
-- {id: Slow_clock.outFreq, value: 24 MHz, locked: true, accuracy: '0.001'}
-- {id: System_clock.outFreq, value: 96 MHz}
-settings:
-- {id: SCGMode, value: SPLL}
-- {id: powerMode, value: HSRUN}
-- {id: CLKOUTConfig, value: 'yes'}
-- {id: SCG.DIVSLOW.scale, value: '4'}
-- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
-- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
-- {id: SCG.PREDIV.scale, value: '4'}
-- {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
-- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
-- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
-- {id: SCG.SOSCDIV1.scale, value: '1', locked: true}
-- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
-- {id: SCG.SPLLDIV1.scale, value: '1', locked: true}
-- {id: SCG.SPLLDIV3.scale, value: '1', locked: true}
-- {id: SCG.SPLLSRCSEL.sel, value: SCG.FIRC}
-- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
-- {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
-sources:
-- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockHSRUN configuration
- ******************************************************************************/
-const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
-    {
-        .divSlow = kSCG_SysClkDivBy4,             /* Slow Clock Divider: divided by 4 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved1 = 0,
-        .reserved2 = 0,
-        .reserved3 = 0,
-#endif
-        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved4 = 0,
-#endif
-        .src = kSCG_SysClkSrcSysPll,              /* System PLL is selected as System Clock Source */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved5 = 0,
-#endif
-    };
-const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
-    {
-        .freq = 32768U,                           /* System Oscillator frequency: 32768Hz */
-        .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
-        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDivBy1,              /* System OSC Clock Divider 1: divided by 1 */
-        .div3 = kSCG_AsyncClkDivBy1,              /* System OSC Clock Divider 3: divided by 1 */
-        .capLoad = SCG_SYS_OSC_CAP_0P,            /* Oscillator capacity load: 0pF */
-        .workMode = kSCG_SysOscModeOscLowPower,   /* Oscillator low power */
-    };
-const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
-    {
-        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
-        .div1 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 1: divided by 1 */
-        .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
-        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
-    };
-const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
-    {
-        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
-        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
-        .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
-        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
-        .trimConfig = NULL,                       /* Fast IRC Trim disabled */
-    };
-const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN =
-    {
-        .enableMode = kSCG_SysPllEnable,          /* Enable SPLL clock */
-        .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDivBy1,              /* System PLL Clock Divider 1: divided by 1 */
-        .div3 = kSCG_AsyncClkDivBy1,              /* System PLL Clock Divider 3: divided by 1 */
-        .src = kSCG_SysPllSrcFirc,                /* System PLL clock source is Fast IRC */
-        .prediv = 3,                              /* Divided by 4 */
-        .mult = 0,                                /* Multiply Factor is 16 */
-    };
-/*******************************************************************************
- * Code for BOARD_BootClockHSRUN configuration
- ******************************************************************************/
-void BOARD_BootClockHSRUN(void)
-{
-    scg_sys_clk_config_t curConfig;
-
-    /* Init SOSC according to board configuration. */
-    CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
-    /* Set the XTAL0 frequency based on board settings. */
-    CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
-    /* Init FIRC. */
-    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
-    /* Init SIRC. */
-    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
-    /* Init SysPll. */
-    CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN);
-    /* Set HSRUN power mode. */
-    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
-    SMC_SetPowerModeHsrun(SMC);
-    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
-    {
-    }
-
-    /* Set SCG to SPLL mode. */
-    CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
-    /* Wait for clock source switch finished. */
-    do
-    {
-         CLOCK_GetCurSysClkConfig(&curConfig);
-    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
-    /* Set SCG CLKOUT selection. */
-    CLOCK_CONFIG_SetScgOutSel(SCG_CLKOUTCNFG_SIRC);
-}
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockVLPR ***********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockVLPR
-outputs:
-- {id: Core_clock.outFreq, value: 8 MHz, locked: true, accuracy: '0.001'}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: SIRC_CLK.outFreq, value: 8 MHz}
-- {id: Slow_clock.outFreq, value: 1 MHz, locked: true, accuracy: '0.001'}
-- {id: System_clock.outFreq, value: 8 MHz}
-settings:
-- {id: SCGMode, value: SIRC}
-- {id: powerMode, value: VLPR}
-- {id: SCG.DIVSLOW.scale, value: '8'}
-- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
-- {id: SCG_FIRCCSR_FIRCLPEN_CFG, value: Enabled}
-sources:
-- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
-    {
-        .divSlow = kSCG_SysClkDivBy8,             /* Slow Clock Divider: divided by 8 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved1 = 0,
-        .reserved2 = 0,
-        .reserved3 = 0,
-#endif
-        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved4 = 0,
-#endif
-        .src = kSCG_SysClkSrcSirc,                /* Slow IRC is selected as System Clock Source */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved5 = 0,
-#endif
-    };
-const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
-    {
-        .freq = 0U,                               /* System Oscillator frequency: 0Hz */
-        .enableMode = SCG_SOSC_DISABLE,           /* System OSC disabled */
-        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 3: Clock output is disabled */
-        .capLoad = SCG_SYS_OSC_CAP_0P,            /* Oscillator capacity load: 0pF */
-        .workMode = kSCG_SysOscModeExt,           /* Use external clock */
-    };
-const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
-    {
-        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
-        .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 3: Clock output is disabled */
-        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
-    };
-const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
-    {
-        .enableMode = kSCG_FircEnable | kSCG_FircEnableInLowPower,/* Enable FIRC clock, Enable FIRC in low power mode */
-        .div1 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 3: Clock output is disabled */
-        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
-        .trimConfig = NULL,                       /* Fast IRC Trim disabled */
-    };
-const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockVLPR =
-    {
-        .enableMode = SCG_SPLL_DISABLE,           /* System PLL disabled */
-        .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 3: Clock output is disabled */
-        .src = kSCG_SysPllSrcSysOsc,              /* System PLL clock source is System OSC */
-        .prediv = 0,                              /* Divided by 1 */
-        .mult = 0,                                /* Multiply Factor is 16 */
-    };
-/*******************************************************************************
- * Code for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-void BOARD_BootClockVLPR(void)
-{
-    /* Init FIRC. */
-    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockVLPR);
-    /* Init SIRC. */
-    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
-    /* Allow SMC all power modes. */
-    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
-    /* Set VLPR power mode. */
-    SMC_SetPowerModeVlpr(SMC);
-    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
-    {
-    }
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
-}
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h
deleted file mode 100644
index c01d5e03c..000000000
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright 2019 ,2021 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                            32768U  /*!< Board xtal0 frequency in Hz */
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************** Configuration BOARD_BootClockRUN ***********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockRUN configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKRUN_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
-
-/*! @brief SCG set for BOARD_BootClockRUN configuration.
- */
-extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
-/*! @brief System OSC set for BOARD_BootClockRUN configuration.
- */
-extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
-/*! @brief SIRC set for BOARD_BootClockRUN configuration.
- */
-extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
-/*! @brief FIRC set for BOARD_BootClockRUN configuration.
- */
-extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
-extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockRUN;
-/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
- */
-
-/*******************************************************************************
- * API for BOARD_BootClockRUN configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockRUN(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockHSRUN **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockHSRUN configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK            96000000U  /*!< Core clock frequency: 96000000Hz */
-
-/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
- */
-extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
-/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
- */
-extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
-/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
- */
-extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
-/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
- */
-extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
-extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockHSRUN;
-/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
- */
-
-/*******************************************************************************
- * API for BOARD_BootClockHSRUN configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockHSRUN(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockVLPR ***********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              8000000U  /*!< Core clock frequency: 8000000Hz */
-
-/*! @brief SCG set for BOARD_BootClockVLPR configuration.
- */
-extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
-/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
- */
-extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
-/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
- */
-extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
-/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
- */
-extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
-extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockVLPR;
-/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
- */
-
-/*******************************************************************************
- * API for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockVLPR(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
index 9cf36c500..82456b721 100644
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
@@ -8,6 +8,9 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
 
+SRC_C += \
+	$(MCU_DIR)/project_template/clock_config.c \
+
 # For flash-jlink target
 JLINK_DEVICE = K32L2B31xxxxA
 
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
deleted file mode 100644
index e74000827..000000000
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2019 ,2021 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
- *    and flash clock are in allowed range during clock mode switch.
- *
- * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
- *
- * 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
- *
- * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v7.0
-processor: K32L2B31xxxxA
-package_id: K32L2B31VLH0A
-mcu_data: ksdk2_0
-processor_version: 9.0.0
-board: FRDM-K32L2B
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "fsl_smc.h"
-#include "clock_config.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
-#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
-#define SIM_OSC32KSEL_OSC32KCLK_CLK                       0U  /*!< OSC32KSEL select: OSC32KCLK clock */
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockRUN();
-}
-
-/*******************************************************************************
- ********************** Configuration BOARD_BootClockRUN ***********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockRUN
-called_from_default_init: true
-outputs:
-- {id: Bus_clock.outFreq, value: 24 MHz}
-- {id: Core_clock.outFreq, value: 48 MHz}
-- {id: Flash_clock.outFreq, value: 24 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: MCGIRCLK.outFreq, value: 8 MHz}
-- {id: MCGPCLK.outFreq, value: 48 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-settings:
-- {id: MCGMode, value: HIRC}
-- {id: MCG.CLKS.sel, value: MCG.HIRC}
-- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
-- {id: MCG_C2_RANGE0_CFG, value: Very_high}
-- {id: MCG_MC_HIRCEN_CFG, value: Enabled}
-- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
-- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
-- {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
-- {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
-- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
-- {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
-- {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
-- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
-- {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
-- {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
-sources:
-- {id: MCG.HIRC.outFreq, value: 48 MHz}
-- {id: OSC.OSC.outFreq, value: 32 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockRUN configuration
- ******************************************************************************/
-const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN =
-    {
-        .outSrc = kMCGLITE_ClkSrcHirc,            /* MCGOUTCLK source is HIRC */
-        .irclkEnableMode = kMCGLITE_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
-        .ircs = kMCGLITE_Lirc8M,                  /* Slow internal reference (LIRC) 8 MHz clock selected */
-        .fcrdiv = kMCGLITE_LircDivBy1,            /* Low-frequency Internal Reference Clock Divider: divided by 1 */
-        .lircDiv2 = kMCGLITE_LircDivBy1,          /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
-        .hircEnableInNotHircMode = true,          /* HIRC source is enabled */
-    };
-const sim_clock_config_t simConfig_BOARD_BootClockRUN =
-    {
-        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
-        .clkdiv1 = 0x10000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
-    };
-const osc_config_t oscConfig_BOARD_BootClockRUN =
-    {
-        .freq = 0U,                               /* Oscillator frequency: 0Hz */
-        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
-        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
-        .oscerConfig =
-            {
-                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
-            }
-    };
-
-/*******************************************************************************
- * Code for BOARD_BootClockRUN configuration
- ******************************************************************************/
-void BOARD_BootClockRUN(void)
-{
-    /* Set the system clock dividers in SIM to safe value. */
-    CLOCK_SetSimSafeDivs();
-    /* Set MCG to HIRC mode. */
-    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
-    /* Set the clock configuration in SIM module. */
-    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockVLPR ***********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockVLPR
-outputs:
-- {id: Bus_clock.outFreq, value: 1 MHz}
-- {id: Core_clock.outFreq, value: 2 MHz}
-- {id: Flash_clock.outFreq, value: 1 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: MCGIRCLK.outFreq, value: 2 MHz}
-- {id: System_clock.outFreq, value: 2 MHz}
-settings:
-- {id: MCGMode, value: LIRC2M}
-- {id: powerMode, value: VLPR}
-- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
-- {id: RTCCLKOUTConfig, value: 'yes'}
-- {id: SIM.OUTDIV4.scale, value: '2', locked: true}
-- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
-sources:
-- {id: MCG.LIRC.outFreq, value: 2 MHz}
-- {id: OSC.OSC.outFreq, value: 32.768 kHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR =
-    {
-        .outSrc = kMCGLITE_ClkSrcLirc,            /* MCGOUTCLK source is LIRC */
-        .irclkEnableMode = kMCGLITE_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
-        .ircs = kMCGLITE_Lirc2M,                  /* Slow internal reference (LIRC) 2 MHz clock selected */
-        .fcrdiv = kMCGLITE_LircDivBy1,            /* Low-frequency Internal Reference Clock Divider: divided by 1 */
-        .lircDiv2 = kMCGLITE_LircDivBy1,          /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
-        .hircEnableInNotHircMode = false,         /* HIRC source is not enabled */
-    };
-const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
-    {
-        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
-        .clkdiv1 = 0x10000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
-    };
-const osc_config_t oscConfig_BOARD_BootClockVLPR =
-    {
-        .freq = 0U,                               /* Oscillator frequency: 0Hz */
-        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
-        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
-        .oscerConfig =
-            {
-                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
-            }
-    };
-
-/*******************************************************************************
- * Code for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-void BOARD_BootClockVLPR(void)
-{
-    /* Set the system clock dividers in SIM to safe value. */
-    CLOCK_SetSimSafeDivs();
-    /* Set MCG to LIRC2M mode. */
-    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
-    /* Set the clock configuration in SIM module. */
-    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
-    /* Set VLPR power mode. */
-    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
-#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
-    SMC_SetPowerModeVlpr(SMC, false);
-#else
-    SMC_SetPowerModeVlpr(SMC);
-#endif
-    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
-    {
-    }
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
-}
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h
deleted file mode 100644
index 37328e7d8..000000000
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2019 ,2021 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************** Configuration BOARD_BootClockRUN ***********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockRUN configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKRUN_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
-
-/*! @brief MCG lite set for BOARD_BootClockRUN configuration.
- */
-extern const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN;
-/*! @brief SIM module set for BOARD_BootClockRUN configuration.
- */
-extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
-/*! @brief OSC set for BOARD_BootClockRUN configuration.
- */
-extern const osc_config_t oscConfig_BOARD_BootClockRUN;
-
-/*******************************************************************************
- * API for BOARD_BootClockRUN configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockRUN(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockVLPR ***********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              2000000U  /*!< Core clock frequency: 2000000Hz */
-
-/*! @brief MCG lite set for BOARD_BootClockVLPR configuration.
- */
-extern const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR;
-/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
- */
-extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
-/*! @brief OSC set for BOARD_BootClockVLPR configuration.
- */
-extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
-
-/*******************************************************************************
- * API for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockVLPR(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake
index 0fbc1d31f..ca5399a3a 100644
--- a/hw/bsp/nrf/boards/pca10095/board.cmake
+++ b/hw/bsp/nrf/boards/pca10095/board.cmake
@@ -1,9 +1,6 @@
 set(MCU_VARIANT nrf5340_application)
 set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
 
-# enable max3421 host driver for this board
-set(MAX3421_HOST 1)
-
 function(update_board TARGET)
   target_sources(${TARGET} PRIVATE
     ${NRFX_DIR}/drivers/src/nrfx_usbreg.c
diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h
index 7437dad48..ad3379bf6 100644
--- a/hw/bsp/nrf/boards/pca10095/board.h
+++ b/hw/bsp/nrf/boards/pca10095/board.h
@@ -42,8 +42,8 @@
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
-#define UART_RX_PIN           22
-#define UART_TX_PIN           20
+#define UART_RX_PIN           32
+#define UART_TX_PIN           33
 
 // SPI for USB host shield
 #define MAX3421_SCK_PIN  _PINNUM(1, 15)
diff --git a/hw/bsp/nrf/boards/pca10095/board.mk b/hw/bsp/nrf/boards/pca10095/board.mk
index 20580d619..9c4edbafc 100644
--- a/hw/bsp/nrf/boards/pca10095/board.mk
+++ b/hw/bsp/nrf/boards/pca10095/board.mk
@@ -2,9 +2,6 @@ CPU_CORE = cortex-m33
 MCU_VARIANT = nrf5340_application
 CFLAGS += -DNRF5340_XXAA -DNRF5340_XXAA_APPLICATION
 
-# enable max3421 host driver for this board
-MAX3421_HOST = 1
-
 LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf5340_xxaa_application.ld
 
 SRC_C += hw/mcu/nordic/nrfx/drivers/src/nrfx_usbreg.c
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 55119ef02..7a970f52e 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -76,7 +76,6 @@ enum {
   #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC
   #define VBUSDETECT_Msk USBREG_USBREGSTATUS_VBUSDETECT_Msk
   #define OUTPUTRDY_Msk USBREG_USBREGSTATUS_OUTPUTRDY_Msk
-  #define GPIOTE_IRQn GPIOTE1_IRQn
 #else
   #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_RC
   #define VBUSDETECT_Msk POWER_USBREGSTATUS_VBUSDETECT_Msk