Merge pull request #3294 from hathach/add-ohci-lpc55

try to enable ohci for lpc55 but not working, probably clock issue

9 files changed, 85 insertions, 51 deletions

diff --git a/hw/bsp/lpc17/family.cmake b/hw/bsp/lpc17/family.cmake
index 92bcbff21..919b8f3bc 100644
--- a/hw/bsp/lpc17/family.cmake
+++ b/hw/bsp/lpc17/family.cmake
@@ -69,7 +69,6 @@ function(family_configure_example TARGET RTOS)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
     ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
-    ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
     ${TOP}/src/portable/ohci/ohci.c
     )
 
diff --git a/hw/bsp/lpc17/family.mk b/hw/bsp/lpc17/family.mk
index e8d707ea5..f1ed1a7d0 100644
--- a/hw/bsp/lpc17/family.mk
+++ b/hw/bsp/lpc17/family.mk
@@ -20,7 +20,6 @@ LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
 
 SRC_C += \
 	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
 	src/portable/ohci/ohci.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \
diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake
index 211846444..01430bbb1 100644
--- a/hw/bsp/lpc40/family.cmake
+++ b/hw/bsp/lpc40/family.cmake
@@ -70,7 +70,6 @@ function(family_configure_example TARGET RTOS)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
     ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
-    ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
     ${TOP}/src/portable/ohci/ohci.c
     )
 
diff --git a/hw/bsp/lpc40/family.mk b/hw/bsp/lpc40/family.mk
index c72631235..c21923000 100644
--- a/hw/bsp/lpc40/family.mk
+++ b/hw/bsp/lpc40/family.mk
@@ -18,7 +18,6 @@ LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
 # All source paths should be relative to the top level.
 SRC_C += \
 	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
 	src/portable/ohci/ohci.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc40xx.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.cmake b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
index 3324ce888..186655b5a 100644
--- a/hw/bsp/lpc55/boards/double_m33_express/board.cmake
+++ b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
@@ -7,11 +7,6 @@ set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
 
-# Device port default to PORT1 Highspeed
-if (NOT DEFINED PORT)
-  set(PORT 1)
-endif()
-
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S69JBD100_cm33_core0
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
index b3d0c3349..d935b70e6 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
@@ -5,11 +5,6 @@ set(JLINK_DEVICE LPC55S28)
 set(PYOCD_TARGET LPC55S28)
 set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28)
 
-# Device port default to PORT1 Highspeed
-if (NOT DEFINED PORT)
-  set(PORT 1)
-endif()
-
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S28JBD100
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
index b52ec2f9d..f46775b27 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
@@ -5,11 +5,6 @@ set(JLINK_DEVICE LPC55S69_M33_0)
 set(PYOCD_TARGET LPC55S69)
 set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 
-# Device port default to PORT1 Highspeed
-if (NOT DEFINED PORT)
-  set(PORT 1)
-endif()
-
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S69JBD100_cm33_core0
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index f0ded96a7..f1ef58926 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -55,6 +55,7 @@
 #define IOCON_PIO_MODE_INACT     0x00u   // No addition pin function
 #define IOCON_PIO_OPENDRAIN_DI   0x00u   // Open drain is disabled
 #define IOCON_PIO_SLEW_STANDARD  0x00u   // Standard mode, output slew rate control is enabled
+#define IOCON_PIO_MODE_PULLUP    0x20u   /*!<@brief Selects pull-up function */
 
 #define IOCON_PIO_DIG_FUNC0_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC0) // Digital pin function 0 enabled
 #define IOCON_PIO_DIG_FUNC1_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC1) // Digital pin function 1 enabled
@@ -197,13 +198,14 @@ void board_init(void) {
   USART_Init(UART_DEV, &uart_config, 12000000);
 #endif
 
-  // USB VBUS
+#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0)
   /* PORT0 PIN22 configured as USB0_VBUS */
   IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
-
-#if defined(BOARD_TUD_RHPORT)  && BOARD_TUD_RHPORT == 0
   // Port0 is Full Speed
 
+  NVIC_ClearPendingIRQ(USB0_IRQn);
+  NVIC_ClearPendingIRQ(USB0_NEEDCLK_IRQn);
+
   /* Turn on USB0 Phy */
   POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
 
@@ -212,21 +214,55 @@ void board_init(void) {
   RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn);
   RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn);
 
-  // Enable USB Clock Adjustments to trim the FRO for the full speed controller
-  ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
-  CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
-  CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+  if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) {
+    // Enable USB Clock Adjustments to trim the FRO for the full speed controller
+    ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
+    CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+
+    /*According to reference manual, device mode setting has to be set by access usb host register */
+    CLOCK_EnableClock(kCLOCK_Usbhsl0);  // enable usb0 host clock
+    USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
+    CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
+    /* enable USB Device clock */
+    CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
+  } else {
+    const uint32_t port1_pin12_config = (/* Pin is configured as USB0_PORTPWRN */
+                                         IOCON_PIO_FUNC4 |
+                                         /* Selects pull-up function */
+                                         IOCON_PIO_MODE_PULLUP |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN12 (coords: 67) is configured as USB0_PORTPWRN */
+    IOCON_PinMuxSet(IOCON, 1U, 12U, port1_pin12_config);
 
-  /*According to reference manual, device mode setting has to be set by access usb host register */
-  CLOCK_EnableClock(kCLOCK_Usbhsl0);  // enable usb0 host clock
-  USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
-  CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
+    const uint32_t port0_pin28_config = (/* Pin is configured as USB0_OVERCURRENTN */
+                                         IOCON_PIO_FUNC7 |
+                                         /* Selects pull-up function */
+                                         IOCON_PIO_MODE_PULLUP |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN28 (coords: 66) is configured as USB0_OVERCURRENTN */
+    IOCON_PinMuxSet(IOCON, 0U, 28U, port0_pin28_config);
 
-  /* enable USB Device clock */
-  CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
+    CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbfsSrcPll1, 48000000U);
+    USBFSH->PORTMODE &= ~USBFSH_PORTMODE_DEV_ENABLE_MASK;
+  }
 #endif
 
-#if defined(BOARD_TUD_RHPORT)  && BOARD_TUD_RHPORT == 1
+#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
   // Port1 is High Speed
 
   /* Turn on USB1 Phy */
@@ -266,9 +302,9 @@ void board_init(void) {
 //  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
 //  USBPHY->TX = phytx;
 
-    ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer)
-    ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0));
-    ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
+  ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer)
+  ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0));
+  ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
 #endif
 }
 
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 3477d9f10..1f18f9bad 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -12,22 +12,40 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL
 
 set(FAMILY_MCUS LPC55 CACHE INTERNAL "")
 
-if (NOT DEFINED PORT)
-  set(PORT 0)
-endif()
+# ----------------------
+# Port & Speed Selection
+# ----------------------
 
-# Host port will be the other port if available
-set(HOST_PORT $<NOT:${PORT}>)
+# default device port to USB1 highspeed, host to USB0 fullspeed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif ()
+
+# port 0 is fullspeed, port 1 is highspeed
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
+
+cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
 
 #------------------------------------
 # Startup & Linker script
 #------------------------------------
 if (NOT DEFINED LD_FILE_GNU)
-set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+  set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
 endif ()
 set(LD_FILE_Clang ${LD_FILE_GNU})
+
 if (NOT DEFINED STARTUP_FILE_GNU)
-set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+  set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
 endif ()
 set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
 
@@ -63,22 +81,20 @@ function(family_add_board BOARD_TARGET)
     )
   target_compile_definitions(${BOARD_TARGET} PUBLIC
     CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
-    BOARD_TUD_RHPORT=${PORT}
-    BOARD_TUH_RHPORT=${HOST_PORT}
+    BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+    BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+    BOARD_TUH_RHPORT=${RHPORT_HOST}
+    BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
     __STARTUP_CLEAR_BSS
     )
 
   # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
-  if (PORT EQUAL 1)
+  if (RHPORT_DEVICE EQUAL 1)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
-      BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-      BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
       CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
       )
-  else ()
+  elseif (RHPORT_HOST EQUAL 1)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
-      BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
-      BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
       CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
       )
   endif ()
@@ -98,6 +114,7 @@ function(family_configure_example TARGET RTOS)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
     ${TOP}/lib/sct_neopixel/sct_neopixel.c
     ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    ${TOP}/src/portable/ohci/ohci.c
     ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     )
   target_include_directories(${TARGET} PUBLIC