Merge branch 'master' into fork/HiFiPhile/dcd_notif

4 files changed, 438 insertions, 242 deletions

diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index c18066f57..0e08b0acd 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _CH34X_H_
-#define _CH34X_H_
+#ifndef TUSB_CH34X_H
+#define TUSB_CH34X_H
 
 // There is no official documentation for the CH34x (CH340, CH341) chips. Reference can be found
 // - https://github.com/WCHSoftGroup/ch341ser_linux
@@ -34,51 +34,51 @@
 
 // set line_coding @ enumeration
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
+  #define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
 #else // this default is necessary to work properly
-#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+  #define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
 #endif
 
 // USB requests
-#define CH34X_REQ_READ_VERSION 0x5F // dec  95
-#define CH34X_REQ_WRITE_REG    0x9A // dec 154
-#define CH34X_REQ_READ_REG     0x95 // dec 149
-#define CH34X_REQ_SERIAL_INIT  0xA1 // dec 161
-#define CH34X_REQ_MODEM_CTRL   0xA4 // dev 164
+#define CH34X_REQ_READ_VERSION        0x5F // dec  95
+#define CH34X_REQ_WRITE_REG           0x9A // dec 154
+#define CH34X_REQ_READ_REG            0x95 // dec 149
+#define CH34X_REQ_SERIAL_INIT         0xA1 // dec 161
+#define CH34X_REQ_MODEM_CTRL          0xA4 // dev 164
 
 // registers
-#define CH34X_REG_BREAK        0x05
-#define CH34X_REG_PRESCALER    0x12
-#define CH34X_REG_DIVISOR      0x13
-#define CH34X_REG_LCR          0x18
-#define CH34X_REG_LCR2         0x25
-#define CH34X_REG_MCR_MSR      0x06
-#define CH34X_REG_MCR_MSR2     0x07
-#define CH34X_NBREAK_BITS      0x01
+#define CH34X_REG_BREAK               0x05
+#define CH34X_REG_PRESCALER           0x12
+#define CH34X_REG_DIVISOR             0x13
+#define CH34X_REG_LCR                 0x18
+#define CH34X_REG_LCR2                0x25
+#define CH34X_REG_MCR_MSR             0x06
+#define CH34X_REG_MCR_MSR2            0x07
+#define CH34X_NBREAK_BITS             0x01
 
-#define CH341_REG_0x0F         0x0F // undocumented register
-#define CH341_REG_0x2C         0x2C // undocumented register
-#define CH341_REG_0x27         0x27 // hardware flow control (cts/rts)
+#define CH341_REG_0x0F                0x0F // undocumented register
+#define CH341_REG_0x2C                0x2C // undocumented register
+#define CH341_REG_0x27                0x27 // hardware flow control (cts/rts)
 
-#define CH34X_REG16_DIVISOR_PRESCALER  TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
-#define CH32X_REG16_LCR2_LCR           TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR)
+#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
+#define CH32X_REG16_LCR2_LCR          TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR)
 
 // modem control bits
-#define CH34X_BIT_RTS ( 1 << 6 )
-#define CH34X_BIT_DTR ( 1 << 5 )
+#define CH34X_BIT_RTS                 (1 << 6)
+#define CH34X_BIT_DTR                 (1 << 5)
 
 // line control bits
-#define CH34X_LCR_ENABLE_RX    0x80
-#define CH34X_LCR_ENABLE_TX    0x40
-#define CH34X_LCR_MARK_SPACE   0x20
-#define CH34X_LCR_PAR_EVEN     0x10
-#define CH34X_LCR_ENABLE_PAR   0x08
-#define CH34X_LCR_PAR_MASK     0x38 // all parity bits
-#define CH34X_LCR_STOP_BITS_2  0x04
-#define CH34X_LCR_CS8          0x03
-#define CH34X_LCR_CS7          0x02
-#define CH34X_LCR_CS6          0x01
-#define CH34X_LCR_CS5          0x00
-#define CH34X_LCR_CS_MASK      0x03 // all CSx bits
+#define CH34X_LCR_ENABLE_RX           0x80
+#define CH34X_LCR_ENABLE_TX           0x40
+#define CH34X_LCR_MARK_SPACE          0x20
+#define CH34X_LCR_PAR_EVEN            0x10
+#define CH34X_LCR_ENABLE_PAR          0x08
+#define CH34X_LCR_PAR_MASK            0x38 // all parity bits
+#define CH34X_LCR_STOP_BITS_2         0x04
+#define CH34X_LCR_CS8                 0x03
+#define CH34X_LCR_CS7                 0x02
+#define CH34X_LCR_CS6                 0x01
+#define CH34X_LCR_CS5                 0x00
+#define CH34X_LCR_CS_MASK             0x03 // all CSx bits
 
-#endif /* _CH34X_H_ */
+#endif // TUSB_CH34X_H
diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h
index 2c749f522..a0eff9e40 100644
--- a/src/class/cdc/serial/cp210x.h
+++ b/src/class/cdc/serial/cp210x.h
@@ -28,9 +28,10 @@
 // Protocol details can be found at AN571: CP210x Virtual COM Port Interface
 // https://www.silabs.com/documents/public/application-notes/AN571.pdf
 
-#define TU_CP210X_VID 0x10C4
+// parts are overtaken from vendors driver
+// https://www.silabs.com/documents/public/software/cp210x-3.1.0.tar.gz
 
-/* Config request codes */
+// Config request codes
 #define CP210X_IFC_ENABLE      0x00
 #define CP210X_SET_BAUDDIV     0x01
 #define CP210X_GET_BAUDDIV     0x02
@@ -59,4 +60,55 @@
 #define CP210X_SET_BAUDRATE    0x1E
 #define CP210X_VENDOR_SPECIFIC 0xFF // GPIO, Recipient must be Device
 
+// SILABSER_IFC_ENABLE_REQUEST_CODE
+#define CP210X_UART_ENABLE              0x0001
+#define CP210X_UART_DISABLE             0x0000
+
+// SILABSER_SET_BAUDDIV_REQUEST_CODE
+#define CP210X_BAUD_RATE_GEN_FREQ     0x384000
+
+// SILABSER_SET_LINE_CTL_REQUEST_CODE
+#define CP210X_BITS_DATA_MASK           0x0f00
+#define CP210X_BITS_DATA_5              0x0500
+#define CP210X_BITS_DATA_6              0x0600
+#define CP210X_BITS_DATA_7              0x0700
+#define CP210X_BITS_DATA_8              0x0800
+#define CP210X_BITS_DATA_9              0x0900
+
+#define CP210X_BITS_PARITY_MASK         0x00f0
+#define CP210X_BITS_PARITY_NONE         0x0000
+#define CP210X_BITS_PARITY_ODD          0x0010
+#define CP210X_BITS_PARITY_EVEN         0x0020
+#define CP210X_BITS_PARITY_MARK         0x0030
+#define CP210X_BITS_PARITY_SPACE        0x0040
+
+#define CP210X_BITS_STOP_MASK           0x000f
+#define CP210X_BITS_STOP_1              0x0000
+#define CP210X_BITS_STOP_1_5            0x0001
+#define CP210X_BITS_STOP_2              0x0002
+
+// SILABSER_SET_BREAK_REQUEST_CODE
+#define CP210X_BREAK_ON                 0x0001
+#define CP210X_BREAK_OFF                0x0000
+
+// SILABSER_SET_MHS_REQUEST_CODE
+#define CP210X_MCR_DTR                  0x0001
+#define CP210X_MCR_RTS                  0x0002
+#define CP210X_MCR_ALL                  0x0003
+#define CP210X_MSR_CTS                  0x0010
+#define CP210X_MSR_DSR                  0x0020
+#define CP210X_MSR_RING                 0x0040
+#define CP210X_MSR_DCD                  0x0080
+#define CP210X_MSR_ALL                  0x00F0
+
+#define CP210X_CONTROL_WRITE_DTR        0x0100UL
+#define CP210X_CONTROL_WRITE_RTS        0x0200UL
+
+#define CP210X_LSR_BREAK                0x0001
+#define CP210X_LSR_FRAMING_ERROR        0x0002
+#define CP210X_LSR_HW_OVERRUN           0x0004
+#define CP210X_LSR_QUEUE_OVERRUN        0x0008
+#define CP210X_LSR_PARITY_ERROR         0x0010
+#define CP210X_LSR_ALL                  0x001F
+
 #endif //TUSB_CP210X_H
diff --git a/src/class/cdc/serial/ftdi_sio.h b/src/class/cdc/serial/ftdi_sio.h
index 0825f0719..8abf74f11 100644
--- a/src/class/cdc/serial/ftdi_sio.h
+++ b/src/class/cdc/serial/ftdi_sio.h
@@ -25,222 +25,207 @@
 #ifndef TUSB_FTDI_SIO_H
 #define TUSB_FTDI_SIO_H
 
-// VID for matching FTDI devices
-#define TU_FTDI_VID 0x0403
+#include <stdint.h>
 
 // Commands
-#define FTDI_SIO_RESET             	0    /* Reset the port */
-#define FTDI_SIO_MODEM_CTRL        	1    /* Set the modem control register */
-#define FTDI_SIO_SET_FLOW_CTRL     	2    /* Set flow control register */
-#define FTDI_SIO_SET_BAUD_RATE     	3    /* Set baud rate */
-#define FTDI_SIO_SET_DATA          	4    /* Set the data characteristics of the port */
-#define FTDI_SIO_GET_MODEM_STATUS  	5    /* Retrieve current value of modem status register */
-#define FTDI_SIO_SET_EVENT_CHAR    	6    /* Set the event character */
-#define FTDI_SIO_SET_ERROR_CHAR    	7    /* Set the error character */
-#define FTDI_SIO_SET_LATENCY_TIMER 	9    /* Set the latency timer */
-#define FTDI_SIO_GET_LATENCY_TIMER 	0x0a /* Get the latency timer */
-#define FTDI_SIO_SET_BITMODE       	0x0b /* Set bitbang mode */
-#define FTDI_SIO_READ_PINS         	0x0c /* Read immediate value of pins */
-#define FTDI_SIO_READ_EEPROM       	0x90 /* Read EEPROM */
+#define FTDI_SIO_RESET                0 // Reset the port
+#define FTDI_SIO_MODEM_CTRL           1 // Set the modem control register
+#define FTDI_SIO_SET_FLOW_CTRL        2 // Set flow control register
+#define FTDI_SIO_SET_BAUD_RATE        3 // Set baud rate
+#define FTDI_SIO_SET_DATA             4 // Set the data characteristics of the port
+#define FTDI_SIO_GET_MODEM_STATUS     5 // Retrieve current value of modem status register
+#define FTDI_SIO_SET_EVENT_CHAR       6 // Set the event character
+#define FTDI_SIO_SET_ERROR_CHAR       7 // Set the error character
+#define FTDI_SIO_SET_LATENCY_TIMER    9 // Set the latency timer
+#define FTDI_SIO_GET_LATENCY_TIMER   10 // Get the latency timer
+#define FTDI_SIO_SET_BITMODE         11 // Set bitbang mode
+#define FTDI_SIO_READ_PINS           12 // Read immediate value of pins
+#define FTDI_SIO_READ_EEPROM       0x90 // Read EEPROM
 
-/* FTDI_SIO_RESET */
-#define FTDI_SIO_RESET_SIO 0
-#define FTDI_SIO_RESET_PURGE_RX 1
-#define FTDI_SIO_RESET_PURGE_TX 2
+// Channel indices for FT2232, FT2232H and FT4232H devices
+#define CHANNEL_A 1
+#define CHANNEL_B 2
+#define CHANNEL_C 3
+#define CHANNEL_D 4
 
-/*
- * BmRequestType:  0100 0000B
- * bRequest:       FTDI_SIO_RESET
- * wValue:         Control Value
- *                   0 = Reset SIO
- *                   1 = Purge RX buffer
- *                   2 = Purge TX buffer
- * wIndex:         Port
- * wLength:        0
- * Data:           None
- *
- * The Reset SIO command has this effect:
- *
- *    Sets flow control set to 'none'
- *    Event char = $0D
- *    Event trigger = disabled
- *    Purge RX buffer
- *    Purge TX buffer
- *    Clear DTR
- *    Clear RTS
- *    baud and data format not reset
- *
- * The Purge RX and TX buffer commands affect nothing except the buffers
- *
-   */
+// Port Identifier Table
+#define PIT_DEFAULT  0 // SIOA
+#define PIT_SIOA     1 // SIOA
+// The device this driver is tested with one has only one port
+#define PIT_SIOB     2 // SIOB
+#define PIT_PARALLEL 3 // Parallel
 
-/* FTDI_SIO_MODEM_CTRL */
-/*
- * BmRequestType:   0100 0000B
- * bRequest:        FTDI_SIO_MODEM_CTRL
- * wValue:          ControlValue (see below)
- * wIndex:          Port
- * wLength:         0
- * Data:            None
- *
- * NOTE: If the device is in RTS/CTS flow control, the RTS set by this
- * command will be IGNORED without an error being returned
- * Also - you can not set DTR and RTS with one control message
- */
+// FTDI_SIO_RESET
+#define FTDI_SIO_RESET_REQUEST                    FTDI_SIO_RESET
+#define FTDI_SIO_RESET_REQUEST_TYPE               0x40
+#define FTDI_SIO_RESET_SIO                        0
+#define FTDI_SIO_RESET_PURGE_RX                   1
+#define FTDI_SIO_RESET_PURGE_TX                   2
 
-#define FTDI_SIO_SET_DTR_MASK 0x1
-#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1)
-#define FTDI_SIO_SET_DTR_LOW  ((FTDI_SIO_SET_DTR_MASK << 8) | 0)
-#define FTDI_SIO_SET_RTS_MASK 0x2
-#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2)
-#define FTDI_SIO_SET_RTS_LOW  ((FTDI_SIO_SET_RTS_MASK << 8) | 0)
+// FTDI_SIO_SET_BAUDRATE
+#define FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE        0x40
+#define FTDI_SIO_SET_BAUDRATE_REQUEST             3
 
-/*
- * ControlValue
- * B0    DTR state
- *          0 = reset
- *          1 = set
- * B1    RTS state
- *          0 = reset
- *          1 = set
- * B2..7 Reserved
- * B8    DTR state enable
- *          0 = ignore
- *          1 = use DTR state
- * B9    RTS state enable
- *          0 = ignore
- *          1 = use RTS state
- * B10..15 Reserved
- */
+enum ftdi_sio_baudrate {
+  ftdi_sio_b300 = 0,
+  ftdi_sio_b600 = 1,
+  ftdi_sio_b1200 = 2,
+  ftdi_sio_b2400 = 3,
+  ftdi_sio_b4800 = 4,
+  ftdi_sio_b9600 = 5,
+  ftdi_sio_b19200 = 6,
+  ftdi_sio_b38400 = 7,
+  ftdi_sio_b57600 = 8,
+  ftdi_sio_b115200 = 9
+};
 
-/* FTDI_SIO_SET_FLOW_CTRL */
-#define FTDI_SIO_DISABLE_FLOW_CTRL 0x0
-#define FTDI_SIO_RTS_CTS_HS (0x1 << 8)
-#define FTDI_SIO_DTR_DSR_HS (0x2 << 8)
-#define FTDI_SIO_XON_XOFF_HS (0x4 << 8)
+// FTDI_SIO_SET_DATA
+#define FTDI_SIO_SET_DATA_REQUEST                 FTDI_SIO_SET_DATA
+#define FTDI_SIO_SET_DATA_REQUEST_TYPE            0x40
+#define FTDI_SIO_SET_DATA_PARITY_NONE             (0x0 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_ODD              (0x1 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_EVEN             (0x2 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_MARK             (0x3 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_SPACE            (0x4 << 8)
+#define FTDI_SIO_SET_DATA_STOP_BITS_1             (0x0 << 11) // same coding as ACM
+#define FTDI_SIO_SET_DATA_STOP_BITS_15            (0x1 << 11) // 1.5 not supported, for future use?
+#define FTDI_SIO_SET_DATA_STOP_BITS_2             (0x2 << 11)
+#define FTDI_SIO_SET_BREAK                        (0x1 << 14)
 
-/*
- *   BmRequestType:  0100 0000b
- *   bRequest:       FTDI_SIO_SET_FLOW_CTRL
- *   wValue:         Xoff/Xon
- *   wIndex:         Protocol/Port - hIndex is protocol / lIndex is port
- *   wLength:        0
- *   Data:           None
- *
- * hIndex protocol is:
- *   B0 Output handshaking using RTS/CTS
- *       0 = disabled
- *       1 = enabled
- *   B1 Output handshaking using DTR/DSR
- *       0 = disabled
- *       1 = enabled
- *   B2 Xon/Xoff handshaking
- *       0 = disabled
- *       1 = enabled
- *
- * A value of zero in the hIndex field disables handshaking
- *
- * If Xon/Xoff handshaking is specified, the hValue field should contain the
- * XOFF character and the lValue field contains the XON character.
- */
+// FTDI_SIO_MODEM_CTRL
+#define FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE      0x40
+#define FTDI_SIO_SET_MODEM_CTRL_REQUEST           FTDI_SIO_MODEM_CTRL
 
-/* FTDI_SIO_SET_BAUD_RATE */
-/*
- * BmRequestType:  0100 0000B
- * bRequest:       FTDI_SIO_SET_BAUDRATE
- * wValue:         BaudDivisor value - see below
- * wIndex:         Port
- * wLength:        0
- * Data:           None
- * The BaudDivisor values are calculated as follows (too complicated):
- */
+#define FTDI_SIO_SET_DTR_MASK                     0x1UL
+#define FTDI_SIO_SET_DTR_HIGH                     ((FTDI_SIO_SET_DTR_MASK << 8) | 1UL)
+#define FTDI_SIO_SET_DTR_LOW                      ((FTDI_SIO_SET_DTR_MASK << 8) | 0UL)
+#define FTDI_SIO_SET_RTS_MASK                     0x2UL
+#define FTDI_SIO_SET_RTS_HIGH                     ((FTDI_SIO_SET_RTS_MASK << 8) | 2UL)
+#define FTDI_SIO_SET_RTS_LOW                      ((FTDI_SIO_SET_RTS_MASK << 8) | 0UL)
 
-/* FTDI_SIO_SET_DATA */
-#define FTDI_SIO_SET_DATA_PARITY_NONE	(0x0 << 8)
-#define FTDI_SIO_SET_DATA_PARITY_ODD	(0x1 << 8)
-#define FTDI_SIO_SET_DATA_PARITY_EVEN	(0x2 << 8)
-#define FTDI_SIO_SET_DATA_PARITY_MARK	(0x3 << 8)
-#define FTDI_SIO_SET_DATA_PARITY_SPACE	(0x4 << 8)
-#define FTDI_SIO_SET_DATA_STOP_BITS_1	(0x0 << 11)
-#define FTDI_SIO_SET_DATA_STOP_BITS_15	(0x1 << 11)
-#define FTDI_SIO_SET_DATA_STOP_BITS_2	(0x2 << 11)
-#define FTDI_SIO_SET_BREAK		(0x1 << 14)
+// FTDI_SIO_SET_FLOW_CTRL
+#define FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE       0x40
+#define FTDI_SIO_SET_FLOW_CTRL_REQUEST            FTDI_SIO_SET_FLOW_CTRL
+#define FTDI_SIO_DISABLE_FLOW_CTRL                0x0
+#define FTDI_SIO_RTS_CTS_HS                       (0x1 << 8)
+#define FTDI_SIO_DTR_DSR_HS                       (0x2 << 8)
+#define FTDI_SIO_XON_XOFF_HS                      (0x4 << 8)
 
-/*
- * BmRequestType:  0100 0000B
- * bRequest:       FTDI_SIO_SET_DATA
- * wValue:         Data characteristics (see below)
- * wIndex:         Port
- * wLength:        0
- * Data:           No
- *
- * Data characteristics
- *
- *   B0..7   Number of data bits
- *   B8..10  Parity
- *           0 = None
- *           1 = Odd
- *           2 = Even
- *           3 = Mark
- *           4 = Space
- *   B11..13 Stop Bits
- *           0 = 1
- *           1 = 1.5
- *           2 = 2
- *   B14
- *           1 = TX ON (break)
- *           0 = TX OFF (normal state)
- *   B15 Reserved
- *
- */
+// FTDI_SIO_GET_LATENCY_TIMER
+#define  FTDI_SIO_GET_LATENCY_TIMER_REQUEST       FTDI_SIO_GET_LATENCY_TIMER
+#define  FTDI_SIO_GET_LATENCY_TIMER_REQUEST_TYPE  0xC0
 
-/*
-* DATA FORMAT
-*
-* IN Endpoint
-*
-* The device reserves the first two bytes of data on this endpoint to contain
-* the current values of the modem and line status registers. In the absence of
-* data, the device generates a message consisting of these two status bytes
-  * every 40 ms
-  *
-  * Byte 0: Modem Status
-*
-* Offset	Description
-* B0	Reserved - must be 1
-* B1	Reserved - must be 0
-* B2	Reserved - must be 0
-* B3	Reserved - must be 0
-* B4	Clear to Send (CTS)
-* B5	Data Set Ready (DSR)
-* B6	Ring Indicator (RI)
-* B7	Receive Line Signal Detect (RLSD)
-*
-* Byte 1: Line Status
-*
-* Offset	Description
-* B0	Data Ready (DR)
-* B1	Overrun Error (OE)
-* B2	Parity Error (PE)
-* B3	Framing Error (FE)
-* B4	Break Interrupt (BI)
-* B5	Transmitter Holding Register (THRE)
-* B6	Transmitter Empty (TEMT)
-* B7	Error in RCVR FIFO
-*
-*/
-#define FTDI_RS0_CTS	(1 << 4)
-#define FTDI_RS0_DSR	(1 << 5)
-#define FTDI_RS0_RI	(1 << 6)
-#define FTDI_RS0_RLSD	(1 << 7)
+// FTDI_SIO_SET_LATENCY_TIMER
+#define  FTDI_SIO_SET_LATENCY_TIMER_REQUEST       FTDI_SIO_SET_LATENCY_TIMER
+#define  FTDI_SIO_SET_LATENCY_TIMER_REQUEST_TYPE  0x40
+
+// FTDI_SIO_SET_EVENT_CHAR
+#define  FTDI_SIO_SET_EVENT_CHAR_REQUEST          FTDI_SIO_SET_EVENT_CHAR
+#define  FTDI_SIO_SET_EVENT_CHAR_REQUEST_TYPE     0x40
+
+// FTDI_SIO_GET_MODEM_STATUS
+#define FTDI_SIO_GET_MODEM_STATUS_REQUEST_TYPE    0xc0
+#define FTDI_SIO_GET_MODEM_STATUS_REQUEST         FTDI_SIO_GET_MODEM_STATUS
+#define FTDI_SIO_CTS_MASK                         0x10
+#define FTDI_SIO_DSR_MASK                         0x20
+#define FTDI_SIO_RI_MASK                          0x40
+#define FTDI_SIO_RLSD_MASK                        0x80
+
+// FTDI_SIO_SET_BITMODE
+#define FTDI_SIO_SET_BITMODE_REQUEST_TYPE         0x40
+#define FTDI_SIO_SET_BITMODE_REQUEST              FTDI_SIO_SET_BITMODE
+
+// Possible bitmodes for FTDI_SIO_SET_BITMODE_REQUEST
+#define FTDI_SIO_BITMODE_RESET                    0x00
+#define FTDI_SIO_BITMODE_CBUS                     0x20
+
+// FTDI_SIO_READ_PINS
+#define FTDI_SIO_READ_PINS_REQUEST_TYPE           0xc0
+#define FTDI_SIO_READ_PINS_REQUEST                FTDI_SIO_READ_PINS
+
+// FTDI_SIO_READ_EEPROM
+#define FTDI_SIO_READ_EEPROM_REQUEST_TYPE         0xc0
+#define FTDI_SIO_READ_EEPROM_REQUEST              FTDI_SIO_READ_EEPROM
+
+#define FTDI_FTX_CBUS_MUX_GPIO    0x8
+#define FTDI_FT232R_CBUS_MUX_GPIO 0xa
+
+#define FTDI_RS0_CTS  (1 << 4)
+#define FTDI_RS0_DSR  (1 << 5)
+#define FTDI_RS0_RI   (1 << 6)
+#define FTDI_RS0_RLSD (1 << 7)
+
+#define FTDI_RS_DR    1
+#define FTDI_RS_OE    (1 << 1)
+#define FTDI_RS_PE    (1 << 2)
+#define FTDI_RS_FE    (1 << 3)
+#define FTDI_RS_BI    (1 << 4)
+#define FTDI_RS_THRE  (1 << 5)
+#define FTDI_RS_TEMT  (1 << 6)
+#define FTDI_RS_FIFO  (1 << 7)
+
+// chip types and names
+typedef enum ftdi_chip_type {
+  FTDI_SIO = 0,
+//  FTDI_FT232A,
+  FTDI_FT232B,
+  FTDI_FT2232C,
+  FTDI_FT232R,
+  FTDI_FT232H,
+  FTDI_FT2232H,
+  FTDI_FT4232H,
+  FTDI_FT4232HA,
+  FTDI_FT232HP,
+  FTDI_FT233HP,
+  FTDI_FT2232HP,
+  FTDI_FT2233HP,
+  FTDI_FT4232HP,
+  FTDI_FT4233HP,
+  FTDI_FTX,
+  FTDI_UNKNOWN
+} ftdi_chip_type_t;
+
+#define FTDI_CHIP_NAMES \
+  [FTDI_SIO]       = "SIO", /* the serial part of FT8U100AX */ \
+/*  [FTDI_FT232A]    = "FT232A", */ \
+  [FTDI_FT232B]    = "FT232B", \
+  [FTDI_FT2232C]   = "FT2232C/D", \
+  [FTDI_FT232R]    = "FT232R", \
+  [FTDI_FT232H]    = "FT232H", \
+  [FTDI_FT2232H]   = "FTDI_FT2232H", \
+  [FTDI_FT4232H]   = "FT4232H", \
+  [FTDI_FT4232HA]  = "FT4232HA", \
+  [FTDI_FT232HP]   = "FT232HP", \
+  [FTDI_FT233HP]   = "FT233HP", \
+  [FTDI_FT2232HP]  = "FT2232HP", \
+  [FTDI_FT2233HP]  = "FT2233HP", \
+  [FTDI_FT4232HP]  = "FT4232HP", \
+  [FTDI_FT4233HP]  = "FT4233HP", \
+  [FTDI_FTX]       = "FT-X", \
+  [FTDI_UNKNOWN]   = "UNKNOWN"
+
+// private interface data
+typedef struct ftdi_private {
+  ftdi_chip_type_t chip_type;
+  uint8_t channel;                  // channel index, or 0 for legacy types
+} ftdi_private_t;
+
+#define FTDI_OK           true
+#define FTDI_FAIL         false
+#define FTDI_NOT_POSSIBLE -1
+#define FTDI_REQUESTED    -2
 
-#define FTDI_RS_DR	1
-#define FTDI_RS_OE	(1<<1)
-#define FTDI_RS_PE	(1<<2)
-#define FTDI_RS_FE	(1<<3)
-#define FTDI_RS_BI	(1<<4)
-#define FTDI_RS_THRE	(1<<5)
-#define FTDI_RS_TEMT	(1<<6)
-#define FTDI_RS_FIFO	(1<<7)
+// division and round function overtaken from math.h
+#define DIV_ROUND_CLOSEST(x, divisor)(      \
+{             \
+  typeof(x) __x = x;        \
+  typeof(divisor) __d = divisor;      \
+  (((typeof(x))-1) > 0 ||       \
+   ((typeof(divisor))-1) > 0 ||     \
+   (((__x) > 0) == ((__d) > 0))) ?    \
+    (((__x) + ((__d) / 2)) / (__d)) : \
+    (((__x) - ((__d) / 2)) / (__d));  \
+}             \
+)
 
 #endif //TUSB_FTDI_SIO_H
diff --git a/src/class/cdc/serial/pl2303.h b/src/class/cdc/serial/pl2303.h
new file mode 100644
index 000000000..63910c7bb
--- /dev/null
+++ b/src/class/cdc/serial/pl2303.h
@@ -0,0 +1,159 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Heiko Kuester
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_PL2303_H
+#define TUSB_PL2303_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+// There is no official documentation for the PL2303 chips.
+// Reference can be found
+// - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/pl2303.h and
+//   https://github.com/torvalds/linux/blob/master/drivers/usb/serial/pl2303.c
+// - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uplcom.c
+
+// quirks
+#define PL2303_QUIRK_UART_STATE_IDX0      1
+#define PL2303_QUIRK_LEGACY               2
+#define PL2303_QUIRK_ENDPOINT_HACK        4
+
+// requests and bits
+#define PL2303_SET_LINE_REQUEST_TYPE      0x21    // class request host to device interface
+#define PL2303_SET_LINE_REQUEST           0x20    // dec 32
+
+#define PL2303_SET_CONTROL_REQUEST_TYPE   0x21    // class request host to device interface
+#define PL2303_SET_CONTROL_REQUEST        0x22    // dec 34
+#define PL2303_CONTROL_DTR                0x01    // dec 1
+#define PL2303_CONTROL_RTS                0x02    // dec 2
+
+#define PL2303_BREAK_REQUEST_TYPE         0x21    // class request host to device interface
+#define PL2303_BREAK_REQUEST              0x23    // dec 35
+#define PL2303_BREAK_ON                   0xffff
+#define PL2303_BREAK_OFF                  0x0000
+
+#define PL2303_GET_LINE_REQUEST_TYPE      0xa1    // class request device to host interface
+#define PL2303_GET_LINE_REQUEST           0x21    // dec 33
+
+#define PL2303_VENDOR_WRITE_REQUEST_TYPE  0x40    // vendor request host to device interface
+#define PL2303_VENDOR_WRITE_REQUEST       0x01    // dec 1
+#define PL2303_VENDOR_WRITE_NREQUEST      0x80    // dec 128
+
+#define PL2303_VENDOR_READ_REQUEST_TYPE   0xc0    // vendor request device to host interface
+#define PL2303_VENDOR_READ_REQUEST        0x01    // dec 1
+#define PL2303_VENDOR_READ_NREQUEST       0x81    // dec 129
+
+#define PL2303_UART_STATE_INDEX           8
+#define PL2303_UART_STATE_MSR_MASK        0x8b
+#define PL2303_UART_STATE_TRANSIENT_MASK  0x74
+#define PL2303_UART_DCD                   0x01
+#define PL2303_UART_DSR                   0x02
+#define PL2303_UART_BREAK_ERROR           0x04
+#define PL2303_UART_RING                  0x08
+#define PL2303_UART_FRAME_ERROR           0x10
+#define PL2303_UART_PARITY_ERROR          0x20
+#define PL2303_UART_OVERRUN_ERROR         0x40
+#define PL2303_UART_CTS                   0x80
+
+#define PL2303_FLOWCTRL_MASK              0xf0
+
+#define PL2303_CLEAR_HALT_REQUEST_TYPE    0x02    // standard request host to device endpoint
+
+// registers via vendor read/write requests
+#define PL2303_READ_TYPE_HX_STATUS        0x8080
+
+#define PL2303_HXN_RESET_REG              0x07
+#define PL2303_HXN_RESET_UPSTREAM_PIPE    0x02
+#define PL2303_HXN_RESET_DOWNSTREAM_PIPE  0x01
+
+#define PL2303_HXN_FLOWCTRL_REG           0x0a
+#define PL2303_HXN_FLOWCTRL_MASK          0x1c
+#define PL2303_HXN_FLOWCTRL_NONE          0x1c
+#define PL2303_HXN_FLOWCTRL_RTS_CTS       0x18
+#define PL2303_HXN_FLOWCTRL_XON_XOFF      0x0c
+
+// type data
+typedef enum pl2303_type {
+  PL2303_TYPE_H = 0, // 0
+  PL2303_TYPE_HX,    // 1
+  PL2303_TYPE_TA,    // 2
+  PL2303_TYPE_TB,    // 3
+  PL2303_TYPE_HXD,   // 4
+  PL2303_TYPE_HXN,   // 5
+  PL2303_TYPE_COUNT,
+  PL2303_TYPE_NEED_SUPPORTS_HX_STATUS,
+  PL2303_TYPE_UNKNOWN,
+} pl2303_type_t;
+
+typedef struct pl2303_type_data {
+  uint32_t max_baud_rate;
+  uint8_t  quirks;
+  uint8_t  no_autoxonxoff : 1;
+  uint8_t  no_divisors    : 1;
+  uint8_t  alt_divisors   : 1;
+} pl2303_type_data_t;
+
+#define PL2303_TYPE_DATA \
+  [PL2303_TYPE_H] = { \
+    .max_baud_rate = 1228800, .quirks = PL2303_QUIRK_LEGACY, \
+    .no_autoxonxoff = 1, .no_divisors = 0, .alt_divisors = 0 \
+  }, \
+  [PL2303_TYPE_HX] = { \
+    .max_baud_rate = 6000000, .quirks = 0, \
+    .no_autoxonxoff = 0, .no_divisors = 0, .alt_divisors = 0 \
+  }, \
+  [PL2303_TYPE_TA] = { \
+    .max_baud_rate = 6000000, .quirks = 0, \
+    .no_autoxonxoff = 0, .no_divisors = 0, .alt_divisors = 1 \
+  }, \
+  [PL2303_TYPE_TB] = { \
+    .max_baud_rate = 12000000, .quirks = 0, \
+    .no_autoxonxoff = 0, .no_divisors = 0, .alt_divisors = 1 \
+  }, \
+  [PL2303_TYPE_HXD] = { \
+    .max_baud_rate = 12000000, .quirks = 0, \
+    .no_autoxonxoff = 0, .no_divisors = 0, .alt_divisors = 0 \
+  }, \
+  [PL2303_TYPE_HXN] = { \
+    .max_baud_rate = 12000000, .quirks = 0, \
+    .no_autoxonxoff = 0, .no_divisors = 1, .alt_divisors = 0 \
+  }
+
+typedef struct TU_ATTR_PACKED {
+  pl2303_type_t type;
+  uint8_t quirks;
+  bool supports_hx_status;
+} pl2303_private_t;
+
+// buffer sizes for line coding data
+#define PL2303_LINE_CODING_BUFSIZE          7
+#define PL2303_LINE_CODING_BAUDRATE_BUFSIZE 4
+
+// bulk endpoints
+#define PL2303_OUT_EP                       0x02
+#define PL2303_IN_EP                        0x83
+
+#endif // TUSB_PL2303_H