Merge remote-tracking branch 'tinyusb/master' into hcd_ip3516

Signed-off-by: HiFiPhile <[email protected]>

1 files changed, 99 insertions, 92 deletions

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 3dc3fb4b6..0e5233bbe 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -117,6 +117,14 @@
 
   #define TUP_DCD_ENDPOINT_MAX 16
 
+#elif TU_CHECK_MCU(OPT_MCU_RW61X)
+  // USB0 is chipidea HS
+  #define TUP_USBIP_CHIPIDEA_HS
+  #define TUP_USBIP_EHCI
+
+  #define TUP_DCD_ENDPOINT_MAX 8
+  #define TUP_RHPORT_HIGHSPEED 1
+
 #elif TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX)
   #include "fsl_device_registers.h"
 
@@ -182,10 +190,15 @@
 //--------------------------------------------------------------------+
 // ST
 //--------------------------------------------------------------------+
+#elif TU_CHECK_MCU(OPT_MCU_STM32C0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define CFG_TUSB_FSDEV_PMA_SIZE 2048u
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32F0)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define CFG_TUSB_FSDEV_PMA_SIZE 1024u
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F1)
   // - F102, F103 use fsdev
@@ -201,7 +214,7 @@
     defined(STM32F103xE) || defined(STM32F103xG)
     #define TUP_USBIP_FSDEV
     #define TUP_USBIP_FSDEV_STM32
-    #define TUP_DCD_ENDPOINT_MAX 8
+    #define CFG_TUSB_FSDEV_PMA_SIZE 512u
   #else
     #error "Unsupported STM32F1 mcu"
   #endif
@@ -216,7 +229,16 @@
 #elif TU_CHECK_MCU(OPT_MCU_STM32F3)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+
+  #if defined(STM32F302xB) || defined(STM32F302xC) || defined(STM32F303xB) || defined(STM32F303xC) || \
+    defined(STM32F373xC)
+    #define CFG_TUSB_FSDEV_PMA_SIZE 512u
+  #elif defined(STM32F302x6) || defined(STM32F302x8) || defined(STM32F302xD) || defined(STM32F302xE) || \
+    defined(STM32F303xD) || defined(STM32F303xE)
+    #define CFG_TUSB_FSDEV_PMA_SIZE 1024u
+  #else
+    #error "Unsupported STM32F3 mcu"
+  #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F4)
   #define TUP_USBIP_DWC2
@@ -242,49 +264,63 @@
   #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUH_DWC2_DMA_ENABLE
   #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32G0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define CFG_TUSB_FSDEV_PMA_SIZE 2048u
+
+#elif TU_CHECK_MCU(OPT_MCU_STM32G4)
+  // Device controller
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define CFG_TUSB_FSDEV_PMA_SIZE 1024u
+
+  // TypeC controller
+  #define TUP_USBIP_TYPEC_STM32
+  #define TUP_TYPEC_RHPORTS_NUM 1
+
+#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define CFG_TUSB_FSDEV_PMA_SIZE 2048u
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
-  #include "stm32h7xx.h"
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_STM32
 
   #define TUP_DCD_ENDPOINT_MAX 9
 
-  #if __CORTEX_M == 7
+  #ifndef CORE_CM4
     // Enable dcache if DMA is enabled
     #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUD_DWC2_DMA_ENABLE
     #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUH_DWC2_DMA_ENABLE
     #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
   #endif
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+#elif TU_CHECK_MCU(OPT_MCU_STM32H7RS, OPT_MCU_STM32N6)
+  #define TUP_USBIP_DWC2
+  #define TUP_USBIP_DWC2_STM32
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32G4)
-  // Device controller
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_STM32
+  // FS has 6, HS has 9
+  #define TUP_DCD_ENDPOINT_MAX                  9
 
-  // TypeC controller
-  #define TUP_USBIP_TYPEC_STM32
-  #define TUP_DCD_ENDPOINT_MAX  8
-  #define TUP_TYPEC_RHPORTS_NUM 1
+  // MCU with on-chip HS Phy
+  #define TUP_RHPORT_HIGHSPEED                  1
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32G0)
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  // Enable dcache if DMA is enabled
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUD_DWC2_DMA_ENABLE
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUH_DWC2_DMA_ENABLE
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32C0)
+#elif TU_CHECK_MCU(OPT_MCU_STM32L0)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define CFG_TUSB_FSDEV_PMA_SIZE 1024u
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1)
+#elif TU_CHECK_MCU(OPT_MCU_STM32L1)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define CFG_TUSB_FSDEV_PMA_SIZE 512u
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32L4)
   // - L4x2, L4x3 use fsdev
@@ -301,28 +337,32 @@
     defined(STM32L442xx) || defined(STM32L443xx) || defined(STM32L452xx) || defined(STM32L462xx)
     #define TUP_USBIP_FSDEV
     #define TUP_USBIP_FSDEV_STM32
-    #define TUP_DCD_ENDPOINT_MAX 8
+    #define CFG_TUSB_FSDEV_PMA_SIZE 1024u
   #else
     #error "Unsupported STM32L4 mcu"
   #endif
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32WB)
+#elif TU_CHECK_MCU(OPT_MCU_STM32L5)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define CFG_TUSB_FSDEV_PMA_SIZE (1024u)
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32WBA)
-  #define TUP_USBIP_DWC2
-  #define TUP_USBIP_DWC2_STM32
-  #define TUP_DCD_ENDPOINT_MAX 9
-  #define TUP_RHPORT_HIGHSPEED 1
+#elif TU_CHECK_MCU(OPT_MCU_STM32U0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define CFG_TUSB_FSDEV_PMA_SIZE 1024u
+
+#elif TU_CHECK_MCU(OPT_MCU_STM32U3)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define CFG_TUSB_FSDEV_PMA_SIZE 2048u
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32U5)
+  // U535/545 use fsdev
   #if defined(STM32U535xx) || defined(STM32U545xx)
     #define TUP_USBIP_FSDEV
     #define TUP_USBIP_FSDEV_STM32
-    #define TUP_DCD_ENDPOINT_MAX 8
-
+    #define CFG_TUSB_FSDEV_PMA_SIZE 2048u
   #else
     #define TUP_USBIP_DWC2
     #define TUP_USBIP_DWC2_STM32
@@ -337,35 +377,16 @@
     #endif
   #endif
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32L5)
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_STM32U0)
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_STM32U3)
+#elif TU_CHECK_MCU(OPT_MCU_STM32WB)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define CFG_TUSB_FSDEV_PMA_SIZE 1024u
 
-#elif TU_CHECK_MCU(OPT_MCU_STM32H7RS, OPT_MCU_STM32N6)
+#elif TU_CHECK_MCU(OPT_MCU_STM32WBA)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_STM32
-
-  // FS has 6, HS has 9
-  #define TUP_DCD_ENDPOINT_MAX                  9
-
-  // MCU with on-chip HS Phy
-  #define TUP_RHPORT_HIGHSPEED                  1
-
-  // Enable dcache if DMA is enabled
-  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUD_DWC2_DMA_ENABLE
-  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUH_DWC2_DMA_ENABLE
-  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
+  #define TUP_DCD_ENDPOINT_MAX 9
+  #define TUP_RHPORT_HIGHSPEED 1
 
 //--------------------------------------------------------------------+
 // Sony
@@ -421,10 +442,6 @@
     #define TUP_MCU_MULTIPLE_CORE 1
   #endif
 
-  // Disable slave if DMA is enabled
-  #define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE
-  #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
-
 #elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_ESP32
@@ -437,10 +454,6 @@
 
   #define TUP_MCU_MULTIPLE_CORE                 1
 
-  // Disable slave if DMA is enabled
-  #define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT     !CFG_TUD_DWC2_DMA_ENABLE
-  #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT     !CFG_TUH_DWC2_DMA_ENABLE
-
   // Enable dcache if DMA is enabled
   #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUD_DWC2_DMA_ENABLE
   #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUH_DWC2_DMA_ENABLE
@@ -572,6 +585,7 @@
 
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_CH32
+  #define CFG_TUSB_FSDEV_PMA_SIZE 512u
 
   // default to FSDEV for device
   #if !defined(CFG_TUD_WCH_USBIP_USBFS)
@@ -617,32 +631,17 @@
 //--------------------------------------------------------------------+
 // ArteryTek
 //--------------------------------------------------------------------+
-#elif TU_CHECK_MCU(OPT_MCU_AT32F403A_407)
+#elif TU_CHECK_MCU(OPT_MCU_AT32F403A_407, OPT_MCU_AT32F413)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_AT32F413)
-  #define TUP_USBIP_FSDEV
-  #define TUP_USBIP_FSDEV_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
+  #define CFG_TUSB_FSDEV_PMA_SIZE 512u
 
 #elif TU_CHECK_MCU(OPT_MCU_AT32F415)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_AT32
   #define TUP_DCD_ENDPOINT_MAX 4
 
-#elif TU_CHECK_MCU(OPT_MCU_AT32F435_437)
-  #define TUP_USBIP_DWC2
-  #define TUP_USBIP_DWC2_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_AT32F423)
-  #define TUP_USBIP_DWC2
-  #define TUP_USBIP_DWC2_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405)
+#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405, OPT_MCU_AT32F423, OPT_MCU_AT32F425, OPT_MCU_AT32F435_437, OPT_MCU_AT32F45X)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_AT32
   #define TUP_DCD_ENDPOINT_MAX 8
@@ -654,17 +653,21 @@
     #define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
   #endif
 
-#elif TU_CHECK_MCU(OPT_MCU_AT32F425)
-  #define TUP_USBIP_DWC2
-  #define TUP_USBIP_DWC2_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
+//--------------------------------------------------------------------+
+// HPMicro
+//--------------------------------------------------------------------+
+#elif TU_CHECK_MCU(OPT_MCU_HPM)
+  #define TUP_USBIP_CHIPIDEA_HS
+  #define TUP_USBIP_EHCI
+
+  #define TUP_DCD_ENDPOINT_MAX    16
+  #define TUP_RHPORT_HIGHSPEED    1
+
+  #define TU_ATTR_FAST_FUNC __attribute__((section(".fast")))
 
 #endif
 
-//--------------------------------------------------------------------+
 // External USB controller
-//--------------------------------------------------------------------+
-
 #if defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
   #ifndef CFG_TUH_MAX3421_ENDPOINT_TOTAL
     #define CFG_TUH_MAX3421_ENDPOINT_TOTAL (8 + 4 * (CFG_TUH_DEVICE_MAX - 1))
@@ -676,6 +679,10 @@
 // Default Values
 //--------------------------------------------------------------------+
 
+#if defined(TUP_USBIP_FSDEV)
+  #define TUP_DCD_ENDPOINT_MAX 8
+#endif
+
 #ifndef TUP_MCU_MULTIPLE_CORE
   #define TUP_MCU_MULTIPLE_CORE 0
 #endif