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authorHiFiPhile <[email protected]>2024-05-13 22:26:19 +0200
committerHiFiPhile <[email protected]>2024-05-13 22:26:19 +0200
commite250b82377aa9c1433c6235501c72dd079544c75 (patch)
tree1c1dcffc81e0b95d06df286ac68877f24c2b285c /src/common
parent0fce7d1f54f5fc405bee3ac20ad6bbdb966abcd0 (diff)
Adjust logic.
Diffstat (limited to 'src/common')
-rw-r--r--src/common/tusb_mcu.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index e489e93e7..3a7d6ad33 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -195,6 +195,7 @@
#elif TU_CHECK_MCU(OPT_MCU_STM32F4)
#define TUP_USBIP_DWC2
#define TUP_USBIP_DWC2_STM32
+ #define TUP_USBIP_DWC2_TEST_MODE
// For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
#define TUP_DCD_ENDPOINT_MAX 6
@@ -209,7 +210,7 @@
// MCU with on-chip HS Phy
#if defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F733xx)
#define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
- #define TUP_USBIP_DWC2_TEST_MODE_SUPPORT
+ #define TUP_USBIP_DWC2_TEST_MODE
#endif
#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
@@ -278,7 +279,7 @@
defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
#define TUP_DCD_ENDPOINT_MAX 9
#define TUP_RHPORT_HIGHSPEED 1
- #define TUP_USBIP_DWC2_TEST_MODE_SUPPORT
+ #define TUP_USBIP_DWC2_TEST_MODE
#else
#define TUP_DCD_ENDPOINT_MAX 6
#endif