diff options
| author | hathach <[email protected]> | 2025-07-09 13:07:13 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2025-07-09 13:07:13 +0700 |
| commit | 386f5518992166dec0830659b21663aeddae4fc8 (patch) | |
| tree | c143f921067c6fbe0bbc9d68c8864b9b1fc71d11 /src/device/dcd.h | |
| parent | 965e26de1dcbd87c3b0e371857bc4ad0b9b3e840 (diff) | |
| parent | 04fb5873effebb3dff770e3257ed789ee36f3846 (diff) | |
Merge branch 'refs/heads/master' into fork/ChrisDeadman/hcd-samd-support
Diffstat (limited to 'src/device/dcd.h')
| -rw-r--r-- | src/device/dcd.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/device/dcd.h b/src/device/dcd.h index d01f82e01..789552d47 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) { // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool dcd_dcache_clean(const void* addr, uint32_t data_size); // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool dcd_dcache_invalidate(const void* addr, uint32_t data_size); // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size); //--------------------------------------------------------------------+ // Controller API |
