diff options
| author | hathach <[email protected]> | 2024-11-28 10:36:17 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2024-11-28 10:36:17 +0700 |
| commit | 3cacb01459670ed20b094ebafc97812437fc173f (patch) | |
| tree | 0a57dd4592f3646ec38596fa125b4b1143338d31 /src/device/dcd.h | |
| parent | 4212db1b83e472e669173b94f692e574c9f23720 (diff) | |
| parent | 5bb90efd5ff59d3b1d67f3c9269ce1aa57a925a6 (diff) | |
Merge branch 'refs/heads/master' into fork/GuavTek/recover_zero_length_desc
Diffstat (limited to 'src/device/dcd.h')
| -rw-r--r-- | src/device/dcd.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/device/dcd.h b/src/device/dcd.h index d01f82e01..789552d47 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) { // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool dcd_dcache_clean(const void* addr, uint32_t data_size); // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool dcd_dcache_invalidate(const void* addr, uint32_t data_size); // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size); //--------------------------------------------------------------------+ // Controller API |
