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authorhathach <[email protected]>2024-11-25 19:11:19 +0700
committerhathach <[email protected]>2024-11-25 19:11:19 +0700
commit833eb7d22d641b2c2b1dd701f86d823f67b12d6d (patch)
tree03a5e9f865b50ab1f6aa79816dbe7955b2343a7f /src/device/dcd.h
parent66741e35c2661ccaa6a8f8cd6d2f6d7aab049f2c (diff)
change dcd_dcache_*() API return type from void to bool
Diffstat (limited to 'src/device/dcd.h')
-rw-r--r--src/device/dcd.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 0ecdec4ed..789552d47 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) {
// clean/flush data cache: write cache -> memory.
// Required before an DMA TX transfer to make sure data is in memory
-void dcd_dcache_clean(const void* addr, uint32_t data_size);
+bool dcd_dcache_clean(const void* addr, uint32_t data_size);
// invalidate data cache: mark cache as invalid, next read will read from memory
// Required BOTH before and after an DMA RX transfer
-void dcd_dcache_invalidate(const void* addr, uint32_t data_size);
+bool dcd_dcache_invalidate(const void* addr, uint32_t data_size);
// clean and invalidate data cache
// Required before an DMA transfer where memory is both read/write by DMA
-void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);
+bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);
//--------------------------------------------------------------------+
// Controller API