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authorHiFiPhile <[email protected]>2024-11-30 18:05:04 +0100
committerHiFiPhile <[email protected]>2024-11-30 18:05:04 +0100
commitc41d9db3b1cf23b10b755b55a231fc9b1a7dd147 (patch)
treecfd006e9a2b6b3cb82a1c8c9f96a6671d5cf7cbb /src/device/dcd.h
parent486e14ea9b66432396089367e61a0480bbb960a9 (diff)
parent2179fb1bd93b71d755c4bf212aff7094f5e8337d (diff)
Merge branch 'master' into rt1170
Signed-off-by: HiFiPhile <[email protected]>
Diffstat (limited to 'src/device/dcd.h')
-rw-r--r--src/device/dcd.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/device/dcd.h b/src/device/dcd.h
index d01f82e01..789552d47 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) {
// clean/flush data cache: write cache -> memory.
// Required before an DMA TX transfer to make sure data is in memory
-void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool dcd_dcache_clean(const void* addr, uint32_t data_size);
// invalidate data cache: mark cache as invalid, next read will read from memory
// Required BOTH before and after an DMA RX transfer
-void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool dcd_dcache_invalidate(const void* addr, uint32_t data_size);
// clean and invalidate data cache
// Required before an DMA transfer where memory is both read/write by DMA
-void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);
//--------------------------------------------------------------------+
// Controller API