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| author | Martino Facchin <[email protected]> | 2023-06-05 09:12:50 +0200 |
|---|---|---|
| committer | Martino Facchin <[email protected]> | 2023-06-05 09:12:50 +0200 |
| commit | cdbd3a0b4ee6c97f2c3cd568b3ff453639ed81cd (patch) | |
| tree | d053d74ee2089a272a4fa1ac518a96231f83aaa0 /src/device/dcd.h | |
| parent | cdae66c8371e1c73d28279462fa8598a9daae5a7 (diff) | |
| parent | c7686f8d5e98660137ef176d35bc8a82f63675f3 (diff) | |
Merge remote-tracking branch 'mainline/master' into HEAD
Update fsp to 4.0.0
Diffstat (limited to 'src/device/dcd.h')
| -rw-r--r-- | src/device/dcd.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/device/dcd.h b/src/device/dcd.h index 00419ff05..f82b8633d 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -103,6 +103,22 @@ typedef struct TU_ATTR_ALIGNED(4) //TU_VERIFY_STATIC(sizeof(dcd_event_t) <= 12, "size is not correct"); //--------------------------------------------------------------------+ +// Memory API +//--------------------------------------------------------------------+ + +// clean/flush data cache: write cache -> memory. +// Required before an DMA TX transfer to make sure data is in memory +void dcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK; + +// invalidate data cache: mark cache as invalid, next read will read from memory +// Required BOTH before and after an DMA RX transfer +void dcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; + +// clean and invalidate data cache +// Required before an DMA transfer where memory is both read/write by DMA +void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; + +//--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ |
