diff options
| author | HiFiPhile <[email protected]> | 2024-12-01 00:00:55 +0100 |
|---|---|---|
| committer | HiFiPhile <[email protected]> | 2024-12-01 00:01:33 +0100 |
| commit | f10467e711017fb05a6e0ee496e451e2e8834549 (patch) | |
| tree | 92f8c27b2768564421cd05703e6833db3661df95 /src/device/dcd.h | |
| parent | 85ff529a310b7e6ec2e4234e3e292fef6432882b (diff) | |
| parent | 2179fb1bd93b71d755c4bf212aff7094f5e8337d (diff) | |
Merge branch 'master' into dcd_notif
Signed-off-by: HiFiPhile <[email protected]>
Diffstat (limited to 'src/device/dcd.h')
| -rw-r--r-- | src/device/dcd.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/device/dcd.h b/src/device/dcd.h index d01f82e01..789552d47 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) { // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool dcd_dcache_clean(const void* addr, uint32_t data_size); // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool dcd_dcache_invalidate(const void* addr, uint32_t data_size); // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size); //--------------------------------------------------------------------+ // Controller API |
