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authorhathach <[email protected]>2023-06-16 12:02:42 +0700
committerhathach <[email protected]>2023-06-16 12:02:42 +0700
commit65d6acdbfaea84c3274e359acd5e5474f04e8851 (patch)
treea6a89ff9a243e7a9e3b7f835e959a9cf3d4c798d /src/device
parent8af8869d3bcb1504835ead4ba472cd922d997e8d (diff)
fix build warnings
Diffstat (limited to 'src/device')
-rw-r--r--src/device/dcd.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 4e9cfd5d5..18a708347 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -108,15 +108,15 @@ typedef struct TU_ATTR_ALIGNED(4)
// clean/flush data cache: write cache -> memory.
// Required before an DMA TX transfer to make sure data is in memory
-void dcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
// invalidate data cache: mark cache as invalid, next read will read from memory
// Required BOTH before and after an DMA RX transfer
-void dcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
// clean and invalidate data cache
// Required before an DMA transfer where memory is both read/write by DMA
-void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
//--------------------------------------------------------------------+
// Controller API