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authorhathach <[email protected]>2024-11-28 16:11:30 +0700
committerhathach <[email protected]>2024-11-28 16:11:30 +0700
commit79373afaafffe64dd2bb33d725b88137c3d4ee6f (patch)
tree272da237079fd812ec088f16fa0cabb3494891c7 /src/host/hcd.h
parent047ba0a62db8a078aa2f7d68d00cbf41406c0fb2 (diff)
parent5bb90efd5ff59d3b1d67f3c9269ce1aa57a925a6 (diff)
Merge branch 'master' into fork/HiFiPhile/lwip_fix
Diffstat (limited to 'src/host/hcd.h')
-rw-r--r--src/host/hcd.h25
1 files changed, 9 insertions, 16 deletions
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 5547c7cc5..56b6fdb5d 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -53,26 +53,21 @@
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
-typedef enum
-{
+typedef enum {
HCD_EVENT_DEVICE_ATTACH,
HCD_EVENT_DEVICE_REMOVE,
HCD_EVENT_XFER_COMPLETE,
- // Not an HCD event, just a convenient way to defer ISR function
- USBH_EVENT_FUNC_CALL,
-
+ USBH_EVENT_FUNC_CALL, // Not an HCD event
HCD_EVENT_COUNT
} hcd_eventid_t;
-typedef struct
-{
+typedef struct {
uint8_t rhport;
uint8_t event_id;
uint8_t dev_addr;
- union
- {
+ union {
// Attach, Remove
struct {
uint8_t hub_addr;
@@ -93,11 +88,9 @@ typedef struct
void* param;
}func_call;
};
-
} hcd_event_t;
-typedef struct
-{
+typedef struct {
uint8_t rhport;
uint8_t hub_addr;
uint8_t hub_port;
@@ -110,15 +103,15 @@ typedef struct
// clean/flush data cache: write cache -> memory.
// Required before an DMA TX transfer to make sure data is in memory
-bool hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool hcd_dcache_clean(void const* addr, uint32_t data_size);
// invalidate data cache: mark cache as invalid, next read will read from memory
// Required BOTH before and after an DMA RX transfer
-bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool hcd_dcache_invalidate(void const* addr, uint32_t data_size);
// clean and invalidate data cache
// Required before an DMA transfer where memory is both read/write by DMA
-bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size);
//--------------------------------------------------------------------+
// Controller API
@@ -128,7 +121,7 @@ bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W
bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param);
// Initialize controller to host mode
-bool hcd_init(uint8_t rhport);
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
// De-initialize controller
bool hcd_deinit(uint8_t rhport);