rename bit_* helper to tu_bit_*, BIT_* to TU_BIT_* for consistency

4 files changed, 49 insertions, 49 deletions

diff --git a/src/host/ehci/ehci.c b/src/host/ehci/ehci.c
index b46c9bc64..b8f724122 100644
--- a/src/host/ehci/ehci.c
+++ b/src/host/ehci/ehci.c
@@ -260,9 +260,9 @@ static bool ehci_init(uint8_t rhport)
   regs->nxp_tt_control = 0;

 

   //------------- USB CMD Register -------------//

-  regs->command |= BIT_(EHCI_USBCMD_POS_RUN_STOP) | BIT_(EHCI_USBCMD_POS_ASYNC_ENABLE)

-                | BIT_(EHCI_USBCMD_POS_PERIOD_ENABLE) // TODO enable period list only there is int/iso endpoint

-                | ((EHCI_CFG_FRAMELIST_SIZE_BITS & BIN8(011)) << EHCI_USBCMD_POS_FRAMELIST_SZIE)

+  regs->command |= TU_BIT(EHCI_USBCMD_POS_RUN_STOP) | TU_BIT(EHCI_USBCMD_POS_ASYNC_ENABLE)

+                | TU_BIT(EHCI_USBCMD_POS_PERIOD_ENABLE) // TODO enable period list only there is int/iso endpoint

+                | ((EHCI_CFG_FRAMELIST_SIZE_BITS & TU_BIN8(011)) << EHCI_USBCMD_POS_FRAMELIST_SZIE)

                 | ((EHCI_CFG_FRAMELIST_SIZE_BITS >> 2) << EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB);

 

   //------------- ConfigFlag Register (skip) -------------//

@@ -791,19 +791,19 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
       if ( interval < 4) // sub milisecond interval

       {

         p_qhd->interval_ms = 0;

-        p_qhd->int_smask   = (interval == 1) ? BIN8(11111111) :

-                             (interval == 2) ? BIN8(10101010) : BIN8(01000100);

+        p_qhd->int_smask   = (interval == 1) ? TU_BIN8(11111111) :

+                             (interval == 2) ? TU_BIN8(10101010) : TU_BIN8(01000100);

       }else

       {

         p_qhd->interval_ms = (uint8_t) tu_min16( 1 << (interval-4), 255 );

-        p_qhd->int_smask = BIT_(interval % 8);

+        p_qhd->int_smask = TU_BIT(interval % 8);

       }

     }else

     {

       TU_ASSERT( 0 != interval, );

       // Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes

       p_qhd->int_smask    = 0x01;

-      p_qhd->fl_int_cmask = BIN8(11100);

+      p_qhd->fl_int_cmask = TU_BIN8(11100);

       p_qhd->interval_ms  = interval;

     }

   }else

diff --git a/src/host/ehci/ehci.h b/src/host/ehci/ehci.h
index c1c274793..23bbb310a 100644
--- a/src/host/ehci/ehci.h
+++ b/src/host/ehci/ehci.h
@@ -294,17 +294,17 @@ TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" );
 // EHCI Operational Register
 //--------------------------------------------------------------------+
 enum ehci_interrupt_mask_{
-  EHCI_INT_MASK_USB                   = BIT_(0),
-  EHCI_INT_MASK_ERROR                 = BIT_(1),
-  EHCI_INT_MASK_PORT_CHANGE           = BIT_(2),
+  EHCI_INT_MASK_USB                   = TU_BIT(0),
+  EHCI_INT_MASK_ERROR                 = TU_BIT(1),
+  EHCI_INT_MASK_PORT_CHANGE           = TU_BIT(2),
 
-  EHCI_INT_MASK_FRAMELIST_ROLLOVER    = BIT_(3),
-  EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR = BIT_(4),
-  EHCI_INT_MASK_ASYNC_ADVANCE         = BIT_(5),
-  EHCI_INT_MASK_NXP_SOF               = BIT_(7),
+  EHCI_INT_MASK_FRAMELIST_ROLLOVER    = TU_BIT(3),
+  EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR = TU_BIT(4),
+  EHCI_INT_MASK_ASYNC_ADVANCE         = TU_BIT(5),
+  EHCI_INT_MASK_NXP_SOF               = TU_BIT(7),
 
-  EHCI_INT_MASK_NXP_ASYNC             = BIT_(18),
-  EHCI_INT_MASK_NXP_PERIODIC          = BIT_(19),
+  EHCI_INT_MASK_NXP_ASYNC             = TU_BIT(18),
+  EHCI_INT_MASK_NXP_PERIODIC          = TU_BIT(19),
 
   EHCI_INT_MASK_ALL                   =
       EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
@@ -323,9 +323,9 @@ enum ehci_usbcmd_pos_ {
 };
 
 enum ehci_portsc_change_mask_{
-  EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE = BIT_(1),
-  EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE = BIT_(3),
-  EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE = BIT_(5),
+  EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE = TU_BIT(1),
+  EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE = TU_BIT(3),
+  EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE = TU_BIT(5),
 
   EHCI_PORTSC_MASK_ALL =
       EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
diff --git a/src/host/hub.c b/src/host/hub.c
index 6b87e935e..16560a812 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -97,7 +97,7 @@ bool hub_port_clear_feature_subtask(uint8_t hub_addr, uint8_t hub_port, uint8_t
   hub_port_status_response_t * p_port_status;

   p_port_status = (hub_port_status_response_t *) hub_enum_buffer;

 

-  TU_ASSERT( !BIT_TEST_(p_port_status->status_change.value, feature-16)  );

+  TU_ASSERT( !TU_BIT_TEST(p_port_status->status_change.value, feature-16)  );

 

   return true;

 }

@@ -225,7 +225,7 @@ void hub_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xf
     for (uint8_t port=1; port <= p_hub->port_number; port++)

     {

       // TODO HUB ignore bit0 hub_status_change

-      if ( BIT_TEST_(p_hub->status_change, port) )

+      if ( TU_BIT_TEST(p_hub->status_change, port) )

       {

         hcd_event_t event =

         {

diff --git a/src/host/ohci/ohci.c b/src/host/ohci/ohci.c
index bebb8a2ef..887b3e561 100644
--- a/src/host/ohci/ohci.c
+++ b/src/host/ohci/ohci.c
@@ -65,10 +65,10 @@ enum {
 

 enum {

   OHCI_CONTROL_CONTROL_BULK_RATIO           = 3, ///< This specifies the service ratio between Control and Bulk EDs. 0 = 1:1, 3 = 4:1

-  OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK    = BIT_(2),

-  OHCI_CONTROL_LIST_ISOCHRONOUS_ENABLE_MASK = BIT_(3),

-  OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK     = BIT_(4),

-  OHCI_CONTROL_LIST_BULK_ENABLE_MASK        = BIT_(5),

+  OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK    = TU_BIT(2),

+  OHCI_CONTROL_LIST_ISOCHRONOUS_ENABLE_MASK = TU_BIT(3),

+  OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK     = TU_BIT(4),

+  OHCI_CONTROL_LIST_BULK_ENABLE_MASK        = TU_BIT(5),

 };

 

 enum {

@@ -81,33 +81,33 @@ enum {
 };

 

 enum {

-  OHCI_INT_SCHEDULING_OVERUN_MASK    = BIT_(0),

-  OHCI_INT_WRITEBACK_DONEHEAD_MASK   = BIT_(1),

-  OHCI_INT_SOF_MASK                  = BIT_(2),

-  OHCI_INT_RESUME_DETECTED_MASK      = BIT_(3),

-  OHCI_INT_UNRECOVERABLE_ERROR_MASK  = BIT_(4),

-  OHCI_INT_FRAME_OVERFLOW_MASK       = BIT_(5),

-  OHCI_INT_RHPORT_STATUS_CHANGE_MASK = BIT_(6),

+  OHCI_INT_SCHEDULING_OVERUN_MASK    = TU_BIT(0),

+  OHCI_INT_WRITEBACK_DONEHEAD_MASK   = TU_BIT(1),

+  OHCI_INT_SOF_MASK                  = TU_BIT(2),

+  OHCI_INT_RESUME_DETECTED_MASK      = TU_BIT(3),

+  OHCI_INT_UNRECOVERABLE_ERROR_MASK  = TU_BIT(4),

+  OHCI_INT_FRAME_OVERFLOW_MASK       = TU_BIT(5),

+  OHCI_INT_RHPORT_STATUS_CHANGE_MASK = TU_BIT(6),

 

-  OHCI_INT_OWNERSHIP_CHANGE_MASK     = BIT_(30),

-  OHCI_INT_MASTER_ENABLE_MASK        = BIT_(31),

+  OHCI_INT_OWNERSHIP_CHANGE_MASK     = TU_BIT(30),

+  OHCI_INT_MASTER_ENABLE_MASK        = TU_BIT(31),

 };

 

 enum {

-  OHCI_RHPORT_CURRENT_CONNECT_STATUS_MASK      = BIT_(0),

-  OHCI_RHPORT_PORT_ENABLE_STATUS_MASK          = BIT_(1),

-  OHCI_RHPORT_PORT_SUSPEND_STATUS_MASK         = BIT_(2),

-  OHCI_RHPORT_PORT_OVER_CURRENT_INDICATOR_MASK = BIT_(3),

-  OHCI_RHPORT_PORT_RESET_STATUS_MASK           = BIT_(4), ///< write '1' to reset port

+  OHCI_RHPORT_CURRENT_CONNECT_STATUS_MASK      = TU_BIT(0),

+  OHCI_RHPORT_PORT_ENABLE_STATUS_MASK          = TU_BIT(1),

+  OHCI_RHPORT_PORT_SUSPEND_STATUS_MASK         = TU_BIT(2),

+  OHCI_RHPORT_PORT_OVER_CURRENT_INDICATOR_MASK = TU_BIT(3),

+  OHCI_RHPORT_PORT_RESET_STATUS_MASK           = TU_BIT(4), ///< write '1' to reset port

 

-  OHCI_RHPORT_PORT_POWER_STATUS_MASK           = BIT_(8),

-  OHCI_RHPORT_LOW_SPEED_DEVICE_ATTACHED_MASK   = BIT_(9),

+  OHCI_RHPORT_PORT_POWER_STATUS_MASK           = TU_BIT(8),

+  OHCI_RHPORT_LOW_SPEED_DEVICE_ATTACHED_MASK   = TU_BIT(9),

 

-  OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK       = BIT_(16),

-  OHCI_RHPORT_PORT_ENABLE_CHANGE_MASK          = BIT_(17),

-  OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK         = BIT_(18),

-  OHCI_RHPORT_OVER_CURRENT_CHANGE_MASK         = BIT_(19),

-  OHCI_RHPORT_PORT_RESET_CHANGE_MASK           = BIT_(20),

+  OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK       = TU_BIT(16),

+  OHCI_RHPORT_PORT_ENABLE_CHANGE_MASK          = TU_BIT(17),

+  OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK         = TU_BIT(18),

+  OHCI_RHPORT_OVER_CURRENT_CHANGE_MASK         = TU_BIT(19),

+  OHCI_RHPORT_PORT_RESET_CHANGE_MASK           = TU_BIT(20),

 

   OHCI_RHPORT_ALL_CHANGE_MASK = OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK | OHCI_RHPORT_PORT_ENABLE_CHANGE_MASK |

     OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK | OHCI_RHPORT_OVER_CURRENT_CHANGE_MASK | OHCI_RHPORT_PORT_RESET_CHANGE_MASK

@@ -131,7 +131,7 @@ enum {
 

 enum {

   OHCI_INT_ON_COMPLETE_YES = 0,

-  OHCI_INT_ON_COMPLETE_NO  = BIN8(111)

+  OHCI_INT_ON_COMPLETE_NO  = TU_BIN8(111)

 };

 //--------------------------------------------------------------------+

 // INTERNAL OBJECT & FUNCTION DECLARATION

@@ -300,7 +300,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   gtd_init(p_setup, (void*) setup_packet, 8);

   p_setup->index       = dev_addr;

   p_setup->pid         = OHCI_PID_SETUP;

-  p_setup->data_toggle = BIN8(10); // DATA0

+  p_setup->data_toggle = TU_BIN8(10); // DATA0

   p_setup->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;

 

   //------------- Attach TDs list to Control Endpoint -------------//

@@ -328,7 +328,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 

     p_data->index       = dev_addr;

     p_data->pid         = dir ? OHCI_PID_IN : OHCI_PID_OUT;

-    p_data->data_toggle = BIN8(11); // DATA1

+    p_data->data_toggle = TU_BIN8(11); // DATA1

     p_data->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;

 

     p_ed->td_head.address = (uint32_t) p_data;