Fix typos

2 files changed, 7 insertions, 7 deletions

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 76ba2a921..80f616478 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -199,7 +199,7 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
     #pragma GCC diagnostic pop
     if ( qhd->dev_addr == dev_addr )
     {
-      // TODO deactive all TD, wait for QHD to inactive before removal
+      // TODO deactivate all TD, wait for QHD to inactive before removal
       prev->address = qhd->next.address;
 
       // EHCI 4.8.2 link the removed qhd to async head (which always reachable by Host Controller)
@@ -839,7 +839,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
     if (TUSB_SPEED_HIGH == p_qhd->ep_speed)
     {
       TU_ASSERT( interval <= 16, );
-      if ( interval < 4) // sub milisecond interval
+      if ( interval < 4) // sub millisecond interval
       {
         p_qhd->interval_ms = 0;
         p_qhd->int_smask   = (interval == 1) ? TU_BIN8(11111111) :
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index ff9ae12e7..36f8649be 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -114,7 +114,7 @@ typedef struct
 	volatile uint32_t current_page         : 3  ; ///< Index into the qTD buffer pointer list
 	uint32_t int_on_complete               : 1  ; ///< Interrupt on complete
 	volatile uint32_t total_bytes          : 15 ; ///< Transfer bytes, decreased during transaction
-	volatile uint32_t data_toggle          : 1  ; ///< Data Toogle bit
+	volatile uint32_t data_toggle          : 1  ; ///< Data Toggle bit
 
 
 	/// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
@@ -160,7 +160,7 @@ typedef struct TU_ATTR_ALIGNED(32)
 	uint8_t used;
 	uint8_t removing; // removed from asyn list, waiting for async advance
 	uint8_t pid;
-	uint8_t interval_ms; // polling interval in frames (or milisecond)
+	uint8_t interval_ms; // polling interval in frames (or millisecond)
 
 	uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set
 	uint8_t reserved2[2];
@@ -225,7 +225,7 @@ typedef struct TU_ATTR_ALIGNED(32)
 	uint16_t reserved ; ///< reserved
 
 	// Word 3: siTD Transfer Status and Control
-	// Status [7:0] TODO indentical to qTD Token'status --> refractor later
+	// Status [7:0] TODO identical to qTD Token'status --> refactor later
 	volatile uint32_t                 : 1  ; // reserved
 	volatile uint32_t split_state     : 1  ;
 	volatile uint32_t missed_uframe   : 1  ;
@@ -350,8 +350,8 @@ typedef volatile struct
       uint32_t periodic_status       : 1  ; ///< Periodic schedule status
       uint32_t async_status          : 1  ; ///< Async schedule status
       uint32_t                       : 2  ;
-      uint32_t nxp_int_async         : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected andthe packet is on the asynchronous schedule.
-      uint32_t nxp_int_period        : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the periodic schedule.
+      uint32_t nxp_int_async         : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule.
+      uint32_t nxp_int_period        : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule.
       uint32_t                       : 12 ;
     }status_bm;
   };