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authorHiFiPhile <[email protected]>2024-05-09 15:51:53 +0200
committerHiFiPhile <[email protected]>2024-05-09 15:51:53 +0200
commit36ce6fad8ca997804a569fe575584b45a1b5fc79 (patch)
treef79aa084a42438667b5e26b588a6f794c9ad1608 /src/portable/synopsys
parentf607a99127cc9e8dfc3f716f977e6c1bfb6f7c2d (diff)
parent74e57499baac36c4cccf76549259905162031e41 (diff)
Merge branch 'master' into vendor_class_zero_length_transfer
Diffstat (limited to 'src/portable/synopsys')
-rw-r--r--src/portable/synopsys/dwc2/dcd_dwc2.c1198
-rw-r--r--src/portable/synopsys/dwc2/dwc2_bcm.h89
-rw-r--r--src/portable/synopsys/dwc2/dwc2_efm32.h89
-rw-r--r--src/portable/synopsys/dwc2/dwc2_esp32.h96
-rw-r--r--src/portable/synopsys/dwc2/dwc2_gd32.h101
-rw-r--r--src/portable/synopsys/dwc2/dwc2_info.md55
-rw-r--r--src/portable/synopsys/dwc2/dwc2_info.py169
-rw-r--r--src/portable/synopsys/dwc2/dwc2_stm32.h261
-rw-r--r--src/portable/synopsys/dwc2/dwc2_type.h1770
-rw-r--r--src/portable/synopsys/dwc2/dwc2_xmc.h88
10 files changed, 3916 insertions, 0 deletions
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
new file mode 100644
index 000000000..692096fc8
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -0,0 +1,1198 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 William D. Jones
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Jan Duempelmann
+ * Copyright (c) 2020 Reinhard Panhuber
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
+
+#include "device/dcd.h"
+#include "dwc2_type.h"
+
+// Following symbols must be defined by port header
+// - _dwc2_controller[]: array of controllers
+// - DWC2_EP_MAX: largest EP counts of all controllers
+// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
+// - dwc2_dcd_int_enable/dwc2_dcd_int_disable
+// - dwc2_remote_wakeup_delay
+
+#if defined(TUP_USBIP_DWC2_STM32)
+ #include "dwc2_stm32.h"
+#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+ #include "dwc2_esp32.h"
+#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
+ #include "dwc2_gd32.h"
+#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
+ #include "dwc2_bcm.h"
+#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
+ #include "dwc2_efm32.h"
+#elif TU_CHECK_MCU(OPT_MCU_XMC4000)
+ #include "dwc2_xmc.h"
+#else
+ #error "Unsupported MCUs"
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+// DWC2 registers
+#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
+
+// Debug level for DWC2
+#define DWC2_DEBUG 2
+
+#ifndef dcache_clean
+#define dcache_clean(_addr, _size)
+#endif
+
+#ifndef dcache_invalidate
+#define dcache_invalidate(_addr, _size)
+#endif
+
+#ifndef dcache_clean_invalidate
+#define dcache_clean_invalidate(_addr, _size)
+#endif
+
+static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
+
+typedef struct {
+ uint8_t* buffer;
+ tu_fifo_t* ff;
+ uint16_t total_len;
+ uint16_t max_size;
+ uint8_t interval;
+} xfer_ctl_t;
+
+static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
+#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
+
+// EP0 transfers are limited to 1 packet - larger sizes has to be split
+static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
+
+// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
+static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs)
+
+// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
+static bool _sof_en;
+
+// Calculate the RX FIFO size according to minimum recommendations from reference manual
+// RxFIFO = (5 * number of control endpoints + 8) +
+// ((largest USB packet used / 4) + 1 for status information) +
+// (2 * number of OUT endpoints) + 1 for Global NAK
+// with number of control endpoints = 1 we have
+// RxFIFO = 15 + (largest USB packet used / 4) + 2 * number of OUT endpoints
+// we double the largest USB packet size to be able to hold up to 2 packets
+static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) {
+ return 15 + 2 * (max_ep_size / 4) + 2 * ep_count;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) {
+ // flush TX fifo and wait for it cleared
+ dwc2->grstctl = GRSTCTL_TXFFLSH | (epnum << GRSTCTL_TXFNUM_Pos);
+ while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
+}
+TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_rx(dwc2_regs_t* dwc2) {
+ // flush RX fifo and wait for it cleared
+ dwc2->grstctl = GRSTCTL_RXFFLSH;
+ while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
+}
+
+static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ TU_ASSERT(epnum < ep_count);
+
+ uint16_t fifo_size = tu_div_ceil(packet_size, 4);
+
+ // "USB Data FIFOs" section in reference manual
+ // Peripheral FIFO architecture
+ //
+ // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+ // | IN FIFO 0 |
+ // --------------- (320 or 1024) - 16
+ // | IN FIFO 1 |
+ // --------------- (320 or 1024) - 16 - x
+ // | . . . . |
+ // --------------- (320 or 1024) - 16 - x - y - ... - z
+ // | IN FIFO MAX |
+ // ---------------
+ // | FREE |
+ // --------------- GRXFSIZ
+ // | OUT FIFO |
+ // | ( Shared ) |
+ // --------------- 0
+ //
+ // In FIFO is allocated by following rules:
+ // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
+ if (dir == TUSB_DIR_OUT) {
+ // Calculate required size of RX FIFO
+ uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count);
+
+ // If size_rx needs to be extended check if possible and if so enlarge it
+ if (dwc2->grxfsiz < sz) {
+ TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4);
+
+ // Enlarge RX FIFO
+ dwc2->grxfsiz = sz;
+ }
+ } else {
+ // Note if The TXFELVL is configured as half empty. In order
+ // to be able to write a packet at that point, the fifo must be twice the max_size.
+ if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) {
+ fifo_size *= 2;
+ }
+
+ // Check if free space is available
+ TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4);
+ _allocated_fifo_words_tx += fifo_size;
+ TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %" PRIu32, fifo_size * 4,
+ _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4);
+
+ // DIEPTXF starts at FIFO #1.
+ // Both TXFD and TXSA are in unit of 32-bit words.
+ dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) |
+ (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
+ }
+
+ return true;
+}
+
+static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+ uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+
+ xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
+ xfer->max_size = tu_edpt_packet_size(p_endpoint_desc);
+ xfer->interval = p_endpoint_desc->bInterval;
+
+ // USBAEP, EPTYP, SD0PID_SEVNFRM, MPSIZ are the same for IN and OUT endpoints.
+ uint32_t const dxepctl = (1 << DOEPCTL_USBAEP_Pos) |
+ (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
+ (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
+ (xfer->max_size << DOEPCTL_MPSIZ_Pos);
+
+ if (dir == TUSB_DIR_OUT) {
+ dwc2->epout[epnum].doepctl = dxepctl;
+ dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
+ } else {
+ dwc2->epin[epnum].diepctl = dxepctl | (epnum << DIEPCTL_TXFNUM_Pos);
+ dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
+ }
+}
+
+static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
+ (void) rhport;
+
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ if (dir == TUSB_DIR_IN) {
+ dwc2_epin_t* epin = dwc2->epin;
+
+ // Only disable currently enabled non-control endpoint
+ if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) {
+ epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
+ } else {
+ // Stop transmitting packets and NAK IN xfers.
+ epin[epnum].diepctl |= DIEPCTL_SNAK;
+ while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {}
+
+ // Disable the endpoint.
+ epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
+ while ((epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0) {}
+
+ epin[epnum].diepint = DIEPINT_EPDISD;
+ }
+
+ // Flush the FIFO, and wait until we have confirmed it cleared.
+ fifo_flush_tx(dwc2, epnum);
+ } else {
+ dwc2_epout_t* epout = dwc2->epout;
+
+ // Only disable currently enabled non-control endpoint
+ if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) {
+ epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
+ } else {
+ // Asserting GONAK is required to STALL an OUT endpoint.
+ // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
+ // anyway, and it can't be cleared by user code. If this while loop never
+ // finishes, we have bigger problems than just the stack.
+ dwc2->dctl |= DCTL_SGONAK;
+ while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {}
+
+ // Ditto here- disable the endpoint.
+ epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
+ while ((epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0) {}
+
+ epout[epnum].doepint = DOEPINT_EPDISD;
+
+ // Allow other OUT endpoints to keep receiving.
+ dwc2->dctl |= DCTL_CGONAK;
+ }
+ }
+}
+
+// Start of Bus Reset
+static void bus_reset(uint8_t rhport) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+
+ tu_memclr(xfer_status, sizeof(xfer_status));
+
+ _sof_en = false;
+
+ // clear device address
+ dwc2->dcfg &= ~DCFG_DAD_Msk;
+
+ // 1. NAK for all OUT endpoints
+ for (uint8_t n = 0; n < ep_count; n++) {
+ dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
+ }
+
+ // 2. Disable all IN endpoints
+ for (uint8_t n = 0; n < ep_count; n++) {
+ if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
+ dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
+ }
+ }
+
+ fifo_flush_tx(dwc2, 0x10); // all tx fifo
+ fifo_flush_rx(dwc2);
+
+ // 3. Set up interrupt mask
+ dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
+ dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM;
+ dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
+
+ // "USB Data FIFOs" section in reference manual
+ // Peripheral FIFO architecture
+ //
+ // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
+ // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
+ // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
+ // configuration done below.
+ //
+ // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
+ // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
+ // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
+ // opened when the host sends an additional command: setInterface. At this point in time
+ // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
+ // an additional memory
+ //
+ // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+ // | IN FIFO 0 |
+ // --------------- (320 or 1024) - 16
+ // | IN FIFO 1 |
+ // --------------- (320 or 1024) - 16 - x
+ // | . . . . |
+ // --------------- (320 or 1024) - 16 - x - y - ... - z
+ // | IN FIFO MAX |
+ // ---------------
+ // | FREE |
+ // --------------- GRXFSIZ
+ // | OUT FIFO |
+ // | ( Shared ) |
+ // --------------- 0
+ //
+ // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
+ // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
+ //
+ // - All EP OUT shared a unique OUT FIFO which uses
+ // - 13 for setup packets + control words (up to 3 setup packets).
+ // - 1 for global NAK (not required/used here).
+ // - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1"
+ // - 2 for each used OUT endpoint
+ //
+ // Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
+ // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x ep_count = 47 + 2 x ep_count
+ // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x ep_count = 271 + 2 x ep_count
+ //
+ // NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
+ // of the overall picture yet. We will use the worst scenario: largest possible + ep_count
+ //
+ // For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
+ // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to
+ // overwrite this.
+
+ // EP0 out max is 64
+ dwc2->grxfsiz = calc_grxfsiz(64, ep_count);
+
+ // Setup the control endpoint 0
+ _allocated_fifo_words_tx = 16;
+
+ // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
+ dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
+
+ // Fixed control EP0 size to 64 bytes
+ dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
+ xfer_status[0][TUSB_DIR_OUT].max_size = 64;
+ xfer_status[0][TUSB_DIR_IN].max_size = 64;
+
+ dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+
+ dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
+}
+
+static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets,
+ uint16_t total_bytes) {
+ (void) rhport;
+
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+ // EP0 is limited to one packet each xfer
+ // We use multiple transaction of xfer->max_size length to get a whole transfer done
+ if (epnum == 0) {
+ xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir);
+ total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
+ ep0_pending[dir] -= total_bytes;
+ }
+
+ // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
+ if (dir == TUSB_DIR_IN) {
+ dwc2_epin_t* epin = dwc2->epin;
+
+ // A full IN transfer (multiple packets, possibly) triggers XFRC.
+ epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
+ ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
+
+ epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+
+ // For ISO endpoint set correct odd/even bit for next frame.
+ if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
+ // Take odd/even bit from frame counter.
+ uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
+ epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
+ }
+ // Enable fifo empty interrupt only if there are something to put in the fifo.
+ if (total_bytes != 0) {
+ dwc2->diepempmsk |= (1 << epnum);
+ }
+ } else {
+ dwc2_epout_t* epout = dwc2->epout;
+
+ // A full OUT transfer (multiple packets, possibly) triggers XFRC.
+ epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
+ epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
+ ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
+
+ epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
+ if ((epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
+ XFER_CTL_BASE(epnum, dir)->interval == 1) {
+ // Take odd/even bit from frame counter.
+ uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
+ epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
+ }
+ }
+}
+
+/*------------------------------------------------------------------*/
+/* Controller API
+ *------------------------------------------------------------------*/
+#if CFG_TUSB_DEBUG >= DWC2_DEBUG
+void print_dwc2_info(dwc2_regs_t* dwc2) {
+ // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
+ // use dwc2_info.py/md for bit-field value and comparison with other ports
+ volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
+ TU_LOG(DWC2_DEBUG, "guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
+ for (size_t i = 0; i < 5; i++) {
+ TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 ", ", p[i]);
+ }
+ TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 "\r\n", p[5]);
+}
+#endif
+
+static void reset_core(dwc2_regs_t* dwc2) {
+ // reset core
+ dwc2->grstctl |= GRSTCTL_CSRST;
+
+ // wait for reset bit is cleared
+ // TODO version 4.20a should wait for RESET DONE mask
+ while (dwc2->grstctl & GRSTCTL_CSRST) {}
+
+ // wait for AHB master IDLE
+ while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {}
+
+ // wait for device mode ?
+}
+
+static bool phy_hs_supported(dwc2_regs_t* dwc2) {
+ (void) dwc2;
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+ // note: esp32 incorrect report its hs_phy_type as utmi
+ return false;
+#elif !TUD_OPT_HIGH_SPEED
+ return false;
+#else
+ return dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
+#endif
+}
+
+static void phy_fs_init(dwc2_regs_t* dwc2) {
+ TU_LOG(DWC2_DEBUG, "Fullspeed PHY init\r\n");
+
+ // Select FS PHY
+ dwc2->gusbcfg |= GUSBCFG_PHYSEL;
+
+ // MCU specific PHY init before reset
+ dwc2_phy_init(dwc2, HS_PHY_TYPE_NONE);
+
+ // Reset core after selecting PHY
+ reset_core(dwc2);
+
+ // USB turnaround time is critical for certification where long cables and 5-Hubs are used.
+ // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
+ // these bits can be programmed to a larger value. Default is 5
+ dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
+
+ // MCU specific PHY update post reset
+ dwc2_phy_update(dwc2, HS_PHY_TYPE_NONE);
+
+ // set max speed
+ dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
+}
+
+static void phy_hs_init(dwc2_regs_t* dwc2) {
+ uint32_t gusbcfg = dwc2->gusbcfg;
+
+ // De-select FS PHY
+ gusbcfg &= ~GUSBCFG_PHYSEL;
+
+ if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) {
+ TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
+
+ // Select ULPI
+ gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
+
+ // ULPI 8-bit interface, single data rate
+ gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
+
+ // default internal VBUS Indicator and Drive
+ gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
+
+ // Disable FS/LS ULPI
+ gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
+ } else {
+ TU_LOG(DWC2_DEBUG, "Highspeed UTMI+ PHY init\r\n");
+
+ // Select UTMI+ with 8-bit interface
+ gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
+
+ // Set 16-bit interface if supported
+ if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
+ }
+
+ // Apply config
+ dwc2->gusbcfg = gusbcfg;
+
+ // mcu specific phy init
+ dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
+
+ // Reset core after selecting PHY
+ reset_core(dwc2);
+
+ // Set turn-around, must after core reset otherwise it will be clear
+ // - 9 if using 8-bit PHY interface
+ // - 5 if using 16-bit PHY interface
+ gusbcfg &= ~GUSBCFG_TRDT_Msk;
+ gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
+ dwc2->gusbcfg = gusbcfg;
+
+ // MCU specific PHY update post reset
+ dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
+
+ // Set max speed
+ uint32_t dcfg = dwc2->dcfg;
+ dcfg &= ~DCFG_DSPD_Msk;
+ dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
+
+ // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
+ // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
+ if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY;
+
+ dwc2->dcfg = dcfg;
+}
+
+static bool check_dwc2(dwc2_regs_t* dwc2) {
+#if CFG_TUSB_DEBUG >= DWC2_DEBUG
+ print_dwc2_info(dwc2);
+#endif
+
+ // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
+ (void) dwc2;
+#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
+ uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
+ TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID);
+#endif
+
+ return true;
+}
+
+void dcd_init(uint8_t rhport) {
+ // Programming model begins in the last section of the chapter on the USB
+ // peripheral in each Reference Manual.
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+ // Check Synopsys ID register, failed if controller clock/power is not enabled
+ if (!check_dwc2(dwc2)) return;
+ dcd_disconnect(rhport);
+
+ // max number of endpoints & total_fifo_size are:
+ // hw_cfg2->num_dev_ep, hw_cfg2->total_fifo_size
+
+ if (phy_hs_supported(dwc2)) {
+ phy_hs_init(dwc2); // Highspeed
+ } else {
+ phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present
+ }
+
+ // Restart PHY clock
+ dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
+
+ /* Set HS/FS Timeout Calibration to 7 (max available value).
+ * The number of PHY clocks that the application programs in
+ * this field is added to the high/full speed interpacket timeout
+ * duration in the core to account for any additional delays
+ * introduced by the PHY. This can be required, because the delay
+ * introduced by the PHY in generating the linestate condition
+ * can vary from one PHY to another.
+ */
+ dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
+
+ // Force device mode
+ dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
+
+ // Clear A override, force B Valid
+ dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
+
+ // If USB host misbehaves during status portion of control xfer
+ // (non zero-length packet), send STALL back and discard.
+ dwc2->dcfg |= DCFG_NZLSOHSK;
+
+ fifo_flush_tx(dwc2, 0x10); // all tx fifo
+ fifo_flush_rx(dwc2);
+
+ // Clear all interrupts
+ uint32_t int_mask = dwc2->gintsts;
+ dwc2->gintsts |= int_mask;
+ int_mask = dwc2->gotgint;
+ dwc2->gotgint |= int_mask;
+
+ // Required as part of core initialization.
+ dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_RXFLVLM |
+ GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
+
+ // Configure TX FIFO empty level for interrupt. Default is complete empty
+ dwc2->gahbcfg |= GAHBCFG_TXFELVL;
+
+ // Enable global interrupt
+ dwc2->gahbcfg |= GAHBCFG_GINT;
+
+ // make sure we are in device mode
+// TU_ASSERT(!(dwc2->gintsts & GINTSTS_CMOD), );
+
+// TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl);
+// TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
+// TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg);
+// TU_LOG_HEX(DWC2_DEBUG, dwc2->gahbcfg);
+
+ dcd_connect(rhport);
+}
+
+void dcd_int_enable(uint8_t rhport) {
+ dwc2_dcd_int_enable(rhport);
+}
+
+void dcd_int_disable(uint8_t rhport) {
+ dwc2_dcd_int_disable(rhport);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ dwc2->dcfg = (dwc2->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
+
+ // Response with status after changing device address
+ dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+
+void dcd_remote_wakeup(uint8_t rhport) {
+ (void) rhport;
+
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+ // set remote wakeup
+ dwc2->dctl |= DCTL_RWUSIG;
+
+ // enable SOF to detect bus resume
+ dwc2->gintsts = GINTSTS_SOF;
+ dwc2->gintmsk |= GINTMSK_SOFM;
+
+ // Per specs: remote wakeup signal bit must be clear within 1-15ms
+ dwc2_remote_wakeup_delay();
+
+ dwc2->dctl &= ~DCTL_RWUSIG;
+}
+
+void dcd_connect(uint8_t rhport) {
+ (void) rhport;
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ dwc2->dctl &= ~DCTL_SDIS;
+}
+
+void dcd_disconnect(uint8_t rhport) {
+ (void) rhport;
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ dwc2->dctl |= DCTL_SDIS;
+}
+
+// Be advised: audio, video and possibly other iso-ep classes use dcd_sof_enable() to enable/disable its corresponding ISR on purpose!
+void dcd_sof_enable(uint8_t rhport, bool en) {
+ (void) rhport;
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+ _sof_en = en;
+
+ if (en) {
+ dwc2->gintsts = GINTSTS_SOF;
+ dwc2->gintmsk |= GINTMSK_SOFM;
+ } else {
+ dwc2->gintmsk &= ~GINTMSK_SOFM;
+ }
+}
+
+/*------------------------------------------------------------------*/
+/* DCD Endpoint port
+ *------------------------------------------------------------------*/
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
+ TU_ASSERT(fifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt)));
+ edpt_activate(rhport, desc_edpt);
+ return true;
+}
+
+// Close all non-control endpoints, cancel all pending transfers if any.
+void dcd_edpt_close_all(uint8_t rhport) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+
+ // Disable non-control interrupt
+ dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
+
+ for (uint8_t n = 1; n < ep_count; n++) {
+ // disable OUT endpoint
+ if (dwc2->epout[n].doepctl & DOEPCTL_EPENA) {
+ dwc2->epout[n].doepctl |= DOEPCTL_SNAK | DOEPCTL_EPDIS;
+ }
+ xfer_status[n][TUSB_DIR_OUT].max_size = 0;
+
+ // disable IN endpoint
+ if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
+ dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
+ }
+ xfer_status[n][TUSB_DIR_IN].max_size = 0;
+ }
+
+ // reset allocated fifo OUT
+ dwc2->grxfsiz = calc_grxfsiz(64, ep_count);
+ // reset allocated fifo IN
+ _allocated_fifo_words_tx = 16;
+
+ fifo_flush_tx(dwc2, 0x10); // all tx fifo
+ fifo_flush_rx(dwc2);
+}
+
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
+ TU_ASSERT(fifo_alloc(rhport, ep_addr, largest_packet_size));
+ return true;
+}
+
+bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) {
+ // Disable EP to clear potential incomplete transfers
+ edpt_disable(rhport, p_endpoint_desc->bEndpointAddress, false);
+
+ edpt_activate(rhport, p_endpoint_desc);
+
+ return true;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
+ xfer->buffer = buffer;
+ xfer->ff = NULL;
+ xfer->total_len = total_bytes;
+
+ // EP0 can only handle one packet
+ if (epnum == 0) {
+ ep0_pending[dir] = total_bytes;
+
+ // Schedule the first transaction for EP0 transfer
+ edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
+ } else {
+ uint16_t num_packets = (total_bytes / xfer->max_size);
+ uint16_t const short_packet_size = total_bytes % xfer->max_size;
+
+ // Zero-size packet is special case.
+ if ((short_packet_size > 0) || (total_bytes == 0)) num_packets++;
+
+ // Schedule packets to be sent within interrupt
+ edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
+ }
+
+ return true;
+}
+
+// The number of bytes has to be given explicitly to allow more flexible control of how many
+// bytes should be written and second to keep the return value free to give back a boolean
+// success message. If total_bytes is too big, the FIFO will copy only what is available
+// into the USB buffer!
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t total_bytes) {
+ // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
+ TU_ASSERT(ff->item_size == 1);
+
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
+ xfer->buffer = NULL;
+ xfer->ff = ff;
+ xfer->total_len = total_bytes;
+
+ uint16_t num_packets = (total_bytes / xfer->max_size);
+ uint16_t const short_packet_size = total_bytes % xfer->max_size;
+
+ // Zero-size packet is special case.
+ if (short_packet_size > 0 || (total_bytes == 0)) num_packets++;
+
+ // Schedule packets to be sent within interrupt
+ edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
+
+ return true;
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+ edpt_disable(rhport, ep_addr, false);
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+ edpt_disable(rhport, ep_addr, true);
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+ (void) rhport;
+
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ // Clear stall and reset data toggle
+ if (dir == TUSB_DIR_IN) {
+ dwc2->epin[epnum].diepctl &= ~DIEPCTL_STALL;
+ dwc2->epin[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM;
+ } else {
+ dwc2->epout[epnum].doepctl &= ~DOEPCTL_STALL;
+ dwc2->epout[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM;
+ }
+}
+
+/*------------------------------------------------------------------*/
+
+// Read a single data packet from receive FIFO
+static void read_fifo_packet(uint8_t rhport, uint8_t* dst, uint16_t len) {
+ (void) rhport;
+
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ volatile const uint32_t* rx_fifo = dwc2->fifo[0];
+
+ // Reading full available 32 bit words from fifo
+ uint16_t full_words = len >> 2;
+ while (full_words--) {
+ tu_unaligned_write32(dst, *rx_fifo);
+ dst += 4;
+ }
+
+ // Read the remaining 1-3 bytes from fifo
+ uint8_t const bytes_rem = len & 0x03;
+ if (bytes_rem != 0) {
+ uint32_t const tmp = *rx_fifo;
+ dst[0] = tu_u32_byte0(tmp);
+ if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp);
+ if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp);
+ }
+}
+
+// Write a single data packet to EPIN FIFO
+static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) {
+ (void) rhport;
+
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num];
+
+ // Pushing full available 32 bit words to fifo
+ uint16_t full_words = len >> 2;
+ while (full_words--) {
+ *tx_fifo = tu_unaligned_read32(src);
+ src += 4;
+ }
+
+ // Write the remaining 1-3 bytes into fifo
+ uint8_t const bytes_rem = len & 0x03;
+ if (bytes_rem) {
+ uint32_t tmp_word = src[0];
+ if (bytes_rem > 1) tmp_word |= (src[1] << 8);
+ if (bytes_rem > 2) tmp_word |= (src[2] << 16);
+
+ *tx_fifo = tmp_word;
+ }
+}
+
+static void handle_rxflvl_irq(uint8_t rhport) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ volatile uint32_t const* rx_fifo = dwc2->fifo[0];
+
+ // Pop control word off FIFO
+ uint32_t const ctl_word = dwc2->grxstsp;
+ uint8_t const pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
+ uint8_t const epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos;
+ uint16_t const bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
+
+ dwc2_epout_t* epout = &dwc2->epout[epnum];
+
+//#if CFG_TUSB_DEBUG >= DWC2_DEBUG
+// const char * pktsts_str[] =
+// {
+// "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)",
+// "Setup Complete (ISR)", "ASSERT", "Setup Data Received"
+// };
+// TU_LOG_LOCATION();
+// TU_LOG(DWC2_DEBUG, " EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]);
+// TU_LOG(DWC2_DEBUG, " daint = %08lX, doepint = %04X\r\n", (unsigned long) dwc2->daint, (unsigned int) epout->doepint);
+//#endif
+
+ switch (pktsts) {
+ // Global OUT NAK: do nothing
+ case GRXSTS_PKTSTS_GLOBALOUTNAK:
+ break;
+
+ case GRXSTS_PKTSTS_SETUPRX:
+ // Setup packet received
+
+ // We can receive up to three setup packets in succession, but
+ // only the last one is valid.
+ _setup_packet[0] = (*rx_fifo);
+ _setup_packet[1] = (*rx_fifo);
+ break;
+
+ case GRXSTS_PKTSTS_SETUPDONE:
+ // Setup packet done (Interrupt)
+ epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+ break;
+
+ case GRXSTS_PKTSTS_OUTRX: {
+ // Out packet received
+ xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+
+ // Read packet off RxFIFO
+ if (xfer->ff) {
+ // Ring buffer
+ tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt);
+ } else {
+ // Linear buffer
+ read_fifo_packet(rhport, xfer->buffer, bcnt);
+
+ // Increment pointer to xfer data
+ xfer->buffer += bcnt;
+ }
+
+ // Truncate transfer length in case of short packet
+ if (bcnt < xfer->max_size) {
+ xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
+ if (epnum == 0) {
+ xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
+ ep0_pending[TUSB_DIR_OUT] = 0;
+ }
+ }
+ }
+ break;
+
+ // Out packet done (Interrupt)
+ case GRXSTS_PKTSTS_OUTDONE:
+ // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a
+ // May (or not) be 3.10a specific feature/bug or depending on MCU configuration
+ // XFRC complete is additionally generated when
+ // - setup packet is received
+ // - complete the data stage of control write is complete
+ if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) {
+ uint32_t doepint = epout->doepint;
+
+ if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR)) {
+ // skip this "no-data" transfer complete event
+ // Note: STPKTRX will be clear later by setup received handler
+ uint32_t clear_flags = DOEPINT_XFRC;
+
+ if (doepint & DOEPINT_OTEPSPR) clear_flags |= DOEPINT_OTEPSPR;
+
+ epout->doepint = clear_flags;
+
+ // TU_LOG(DWC2_DEBUG, " FIX extra transfer complete on setup/data compete\r\n");
+ }
+ }
+ break;
+
+ default: // Invalid
+ TU_BREAKPOINT();
+ break;
+ }
+}
+
+static void handle_epout_irq(uint8_t rhport) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+
+ // DAINT for a given EP clears when DOEPINTx is cleared.
+ // OEPINT will be cleared when DAINT's out bits are cleared.
+ for (uint8_t n = 0; n < ep_count; n++) {
+ if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n)) {
+ dwc2_epout_t* epout = &dwc2->epout[n];
+
+ uint32_t const doepint = epout->doepint;
+
+ // SETUP packet Setup Phase done.
+ if (doepint & DOEPINT_STUP) {
+ uint32_t clear_flag = DOEPINT_STUP;
+
+ // STPKTRX is only available for version from 3_00a
+ if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) {
+ clear_flag |= DOEPINT_STPKTRX;
+ }
+
+ epout->doepint = clear_flag;
+ dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
+ }
+
+ // OUT XFER complete
+ if (epout->doepint & DOEPINT_XFRC) {
+ epout->doepint = DOEPINT_XFRC;
+
+ xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
+
+ // EP0 can only handle one packet
+ if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
+ // Schedule another packet to be received.
+ edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
+ } else {
+ dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ }
+ }
+ }
+ }
+}
+
+static void handle_epin_irq(uint8_t rhport) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+ dwc2_epin_t* epin = dwc2->epin;
+
+ // DAINT for a given EP clears when DIEPINTx is cleared.
+ // IEPINT will be cleared when DAINT's out bits are cleared.
+ for (uint8_t n = 0; n < ep_count; n++) {
+ if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n)) {
+ // IN XFER complete (entire xfer).
+ xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
+
+ if (epin[n].diepint & DIEPINT_XFRC) {
+ epin[n].diepint = DIEPINT_XFRC;
+
+ // EP0 can only handle one packet
+ if ((n == 0) && ep0_pending[TUSB_DIR_IN]) {
+ // Schedule another packet to be transmitted.
+ edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
+ } else {
+ dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ }
+ }
+
+ // XFER FIFO empty
+ if ((epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n))) {
+ // diepint's TXFE bit is read-only, software cannot clear it.
+ // It will only be cleared by hardware when written bytes is more than
+ // - 64 bytes or
+ // - Half of TX FIFO size (configured by DIEPTXF)
+
+ uint16_t remaining_packets = (epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
+
+ // Process every single packet (only whole packets can be written to fifo)
+ for (uint16_t i = 0; i < remaining_packets; i++) {
+ uint16_t const remaining_bytes = (epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
+
+ // Packet can not be larger than ep max size
+ uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
+
+ // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
+ // EP has to be checked if the buffer can take another WHOLE packet
+ if (packet_size > ((epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) break;
+
+ // Push packet to Tx-FIFO
+ if (xfer->ff) {
+ volatile uint32_t* tx_fifo = dwc2->fifo[n];
+ tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size);
+ } else {
+ write_fifo_packet(rhport, n, xfer->buffer, packet_size);
+
+ // Increment pointer to xfer data
+ xfer->buffer += packet_size;
+ }
+ }
+
+ // Turn off TXFE if all bytes are written.
+ if (((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) {
+ dwc2->diepempmsk &= ~(1 << n);
+ }
+ }
+ }
+ }
+}
+
+void dcd_int_handler(uint8_t rhport) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+ uint32_t const int_mask = dwc2->gintmsk;
+ uint32_t const int_status = dwc2->gintsts & int_mask;
+
+ if (int_status & GINTSTS_USBRST) {
+ // USBRST is start of reset.
+ dwc2->gintsts = GINTSTS_USBRST;
+ bus_reset(rhport);
+ }
+
+ if (int_status & GINTSTS_ENUMDNE) {
+ // ENUMDNE is the end of reset where speed of the link is detected
+ dwc2->gintsts = GINTSTS_ENUMDNE;
+
+ tusb_speed_t speed;
+ switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos) {
+ case DSTS_ENUMSPD_HS:
+ speed = TUSB_SPEED_HIGH;
+ break;
+
+ case DSTS_ENUMSPD_LS:
+ speed = TUSB_SPEED_LOW;
+ break;
+
+ case DSTS_ENUMSPD_FS_HSPHY:
+ case DSTS_ENUMSPD_FS:
+ default:
+ speed = TUSB_SPEED_FULL;
+ break;
+ }
+
+ // TODO must update GUSBCFG_TRDT according to link speed
+
+ dcd_event_bus_reset(rhport, speed, true);
+ }
+
+ if (int_status & GINTSTS_USBSUSP) {
+ dwc2->gintsts = GINTSTS_USBSUSP;
+ dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+ }
+
+ if (int_status & GINTSTS_WKUINT) {
+ dwc2->gintsts = GINTSTS_WKUINT;
+ dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+ }
+
+ // TODO check GINTSTS_DISCINT for disconnect detection
+ // if(int_status & GINTSTS_DISCINT)
+
+ if (int_status & GINTSTS_OTGINT) {
+ // OTG INT bit is read-only
+ uint32_t const otg_int = dwc2->gotgint;
+
+ if (otg_int & GOTGINT_SEDET) {
+ dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
+ }
+
+ dwc2->gotgint = otg_int;
+ }
+
+ if(int_status & GINTSTS_SOF) {
+ dwc2->gintsts = GINTSTS_SOF;
+ const uint32_t frame = (dwc2->dsts & DSTS_FNSOF) >> DSTS_FNSOF_Pos;
+
+ // Disable SOF interrupt if SOF was not explicitly enabled since SOF was used for remote wakeup detection
+ if (!_sof_en) {
+ dwc2->gintmsk &= ~GINTMSK_SOFM;
+ }
+
+ dcd_event_sof(rhport, frame, true);
+ }
+
+ // RxFIFO non-empty interrupt handling.
+ if (int_status & GINTSTS_RXFLVL) {
+ // RXFLVL bit is read-only
+
+ // Mask out RXFLVL while reading data from FIFO
+ dwc2->gintmsk &= ~GINTMSK_RXFLVLM;
+
+ // Loop until all available packets were handled
+ do {
+ handle_rxflvl_irq(rhport);
+ } while(dwc2->gintsts & GINTSTS_RXFLVL);
+
+ dwc2->gintmsk |= GINTMSK_RXFLVLM;
+ }
+
+ // OUT endpoint interrupt handling.
+ if (int_status & GINTSTS_OEPINT) {
+ // OEPINT is read-only, clear using DOEPINTn
+ handle_epout_irq(rhport);
+ }
+
+ // IN endpoint interrupt handling.
+ if (int_status & GINTSTS_IEPINT) {
+ // IEPINT bit read-only, clear using DIEPINTn
+ handle_epin_irq(rhport);
+ }
+
+ // // Check for Incomplete isochronous IN transfer
+ // if(int_status & GINTSTS_IISOIXFR) {
+ // printf(" IISOIXFR!\r\n");
+ //// TU_LOG(DWC2_DEBUG, " IISOIXFR!\r\n");
+ // }
+}
+
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
new file mode 100644
index 000000000..732d96ae0
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -0,0 +1,89 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_DWC2_BCM_H_
+#define _TUSB_DWC2_BCM_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "broadcom/defines.h"
+#include "broadcom/interrupts.h"
+#include "broadcom/caches.h"
+
+#define DWC2_EP_MAX 8
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+ { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 4096 }
+};
+
+#define dcache_clean(_addr, _size) data_clean(_addr, _size)
+#define dcache_invalidate(_addr, _size) data_invalidate(_addr, _size)
+#define dcache_clean_invalidate(_addr, _size) data_clean_and_invalidate(_addr, _size)
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_enable(uint8_t rhport)
+{
+ BP_EnableIRQ(_dwc2_controller[rhport].irqnum);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
+{
+ BP_DisableIRQ(_dwc2_controller[rhport].irqnum);
+}
+
+static inline void dwc2_remote_wakeup_delay(void)
+{
+ // try to delay for 1 ms
+ // TODO implement later
+}
+
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+ (void) dwc2;
+ (void) hs_phy_type;
+
+ // nothing to do
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+ (void) dwc2;
+ (void) hs_phy_type;
+
+ // nothing to do
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_efm32.h b/src/portable/synopsys/dwc2/dwc2_efm32.h
new file mode 100644
index 000000000..0e3570cbb
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_efm32.h
@@ -0,0 +1,89 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Rafael Silva (@perigoso)
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _DWC2_EFM32_H_
+#define _DWC2_EFM32_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "em_device.h"
+
+// EFM32 has custom control register before DWC registers
+#define DWC2_REG_BASE (USB_BASE + offsetof(USB_TypeDef, GOTGCTL))
+#define DWC2_EP_MAX 7
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+ { .reg_base = DWC2_REG_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 2048 }
+};
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_enable(uint8_t rhport)
+{
+ NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
+{
+ NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
+}
+
+static inline void dwc2_remote_wakeup_delay(void)
+{
+ // try to delay for 1 ms
+// uint32_t count = SystemCoreClock / 1000;
+// while ( count-- ) __NOP();
+}
+
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+ (void) dwc2;
+ (void) hs_phy_type;
+
+ // Enable PHY
+ USB->ROUTE = USB_ROUTE_PHYPEN;
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+ (void) dwc2;
+ (void) hs_phy_type;
+
+ // EFM32 Manual: turn around must be 5 (reset & default value)
+ // dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
new file mode 100644
index 000000000..c50dd66b8
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -0,0 +1,96 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef _DWC2_ESP32_H_
+#define _DWC2_ESP32_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "esp_intr_alloc.h"
+#include "soc/periph_defs.h"
+//#include "soc/usb_periph.h"
+
+#define DWC2_REG_BASE 0x60080000UL
+#define DWC2_EP_MAX 6 // USB_OUT_EP_NUM. TODO ESP32Sx only has 5 tx fifo (5 endpoint IN)
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+ { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1024 }
+};
+
+static intr_handle_t usb_ih;
+
+static void dcd_int_handler_wrap(void* arg)
+{
+ (void) arg;
+ dcd_int_handler(0);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_enable (uint8_t rhport)
+{
+ (void) rhport;
+ esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
+{
+ (void) rhport;
+ esp_intr_free(usb_ih);
+}
+
+static inline void dwc2_remote_wakeup_delay(void)
+{
+ vTaskDelay(pdMS_TO_TICKS(1));
+}
+
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+ (void) dwc2;
+ (void) hs_phy_type;
+
+ // nothing to do
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+ (void) dwc2;
+ (void) hs_phy_type;
+
+ // nothing to do
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DWC2_ESP32_H_ */
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
new file mode 100644
index 000000000..0375fffe4
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -0,0 +1,101 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef DWC2_GD32_H_
+#define DWC2_GD32_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define DWC2_REG_BASE 0x50000000UL
+#define DWC2_EP_MAX 4
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+ { .reg_base = DWC2_REG_BASE, .irqnum = 86, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1280 }
+};
+
+extern uint32_t SystemCoreClock;
+
+// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
+// Interrupt Controller by Nuclei. It is nearly API compatible to the
+// NVIC used by ARM MCUs.
+#define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL
+
+TU_ATTR_ALWAYS_INLINE
+static inline void __eclic_enable_interrupt (uint32_t irq) {
+ *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1;
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void __eclic_disable_interrupt (uint32_t irq){
+ *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0;
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_enable(uint8_t rhport)
+{
+ __eclic_enable_interrupt(_dwc2_controller[rhport].irqnum);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
+{
+ __eclic_disable_interrupt(_dwc2_controller[rhport].irqnum);
+}
+
+static inline void dwc2_remote_wakeup_delay(void)
+{
+ // try to delay for 1 ms
+ uint32_t count = SystemCoreClock / 1000;
+ while ( count-- ) __asm volatile ("nop");
+}
+
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+ (void) dwc2;
+ (void) hs_phy_type;
+
+ // nothing to do
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+ (void) dwc2;
+ (void) hs_phy_type;
+
+ // nothing to do
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DWC2_GD32_H_ */
diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md
new file mode 100644
index 000000000..8690a0755
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_info.md
@@ -0,0 +1,55 @@
+| | BCM2711 (Pi4) | EFM32GG FullSpeed | ESP32-S2 | STM32F407 Fullspeed | STM32F407 Highspeed | STM32F411 Fullspeed | STM32F412 Fullspeed | STM32F429 Fullspeed | STM32F429 Highspeed | STM32F723 Fullspeed | STM32F723 HighSpeed | STM32F767 Fullspeed | STM32H743 Highspeed | STM32L476 Fullspeed | STM32U5A5 Highspeed | GD32VF103 Fullspeed | XMC4500 |
+|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------|
+| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00001200 | 0x00001100 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 |
+| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54281A | 0x4F54281A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A |
+| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 2.81a | 3.20a | 2.81a | 2.81a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a |
+| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
+| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 |
+| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 |
+| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 |
+| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
+| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 |
+| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
+| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 3 | 5 | 3 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 |
+| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 |
+| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
+| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
+| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
+| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 |
+| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 |
+| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 |
+| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 |
+| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
+| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
+| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
+| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
+| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
+| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 512 | 1012 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 |
+| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 |
+| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 |
+| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
+| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
+| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
+| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
+| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 |
+| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
+| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
+| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
+| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
+| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 |
+| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
+| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py
new file mode 100644
index 000000000..55bec3d23
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_info.py
@@ -0,0 +1,169 @@
+import click
+import ctypes
+import pandas as pd
+
+# hex value for register: guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
+dwc2_reg_list = ['guid', 'gsnpsid', 'ghwcfg1', 'ghwcfg2', 'ghwcfg3', 'ghwcfg4']
+dwc2_reg_value = {
+ 'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020],
+ 'EFM32GG FullSpeed': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030],
+ 'ESP32-S2': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030],
+ 'STM32F407 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
+ 'STM32F407 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
+ 'STM32F411 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
+ 'STM32F412 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
+ 'STM32F429 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
+ 'STM32F429 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
+ 'STM32F723 Fullspeed': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
+ 'STM32F723 HighSpeed': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030],
+ 'STM32F767 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
+ 'STM32H743 Highspeed': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores
+ 'STM32L476 Fullspeed': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
+ 'STM32U5A5 Highspeed': [0x00005000, 0x4F54411A, 0x00000000, 0x228FE052, 0x03B882E8, 0xE2103E30],
+ 'GD32VF103 Fullspeed': [0x1000, 0, 0, 0, 0, 0],
+ 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x27A01E5, 0xDBF08030]
+}
+
+# Combine dwc2_info with dwc2_reg_list
+# dwc2_info = {
+# 'BCM2711 (Pi4)': {
+# 'guid': 0x2708A000,
+# 'gsnpsid': 0x4F54280A,
+# 'ghwcfg1': 0,
+# 'ghwcfg2': 0x228DDD50,
+# 'ghwcfg3': 0xFF000E8,
+# 'ghwcfg4': 0x1FF00020
+# },
+dwc2_info = {key: {field: value for field, value in zip(dwc2_reg_list, values)} for key, values in dwc2_reg_value.items()}
+
+
+class GHWCFG2(ctypes.LittleEndianStructure):
+ _fields_ = [
+ ("op_mode", ctypes.c_uint32, 3),
+ ("arch", ctypes.c_uint32, 2),
+ ("point2point", ctypes.c_uint32, 1),
+ ("hs_phy_type", ctypes.c_uint32, 2),
+ ("fs_phy_type", ctypes.c_uint32, 2),
+ ("num_dev_ep", ctypes.c_uint32, 4),
+ ("num_host_ch", ctypes.c_uint32, 4),
+ ("period_channel_support", ctypes.c_uint32, 1),
+ ("enable_dynamic_fifo", ctypes.c_uint32, 1),
+ ("mul_cpu_int", ctypes.c_uint32, 1),
+ ("reserved21", ctypes.c_uint32, 1),
+ ("nperiod_tx_q_depth", ctypes.c_uint32, 2),
+ ("host_period_tx_q_depth", ctypes.c_uint32, 2),
+ ("dev_token_q_depth", ctypes.c_uint32, 5),
+ ("otg_enable_ic_usb", ctypes.c_uint32, 1)
+ ]
+
+
+class GHWCFG3(ctypes.LittleEndianStructure):
+ _fields_ = [
+ ("xfer_size_width", ctypes.c_uint32, 4),
+ ("packet_size_width", ctypes.c_uint32, 3),
+ ("otg_enable", ctypes.c_uint32, 1),
+ ("i2c_enable", ctypes.c_uint32, 1),
+ ("vendor_ctrl_itf", ctypes.c_uint32, 1),
+ ("optional_feature_removed", ctypes.c_uint32, 1),
+ ("synch_reset", ctypes.c_uint32, 1),
+ ("otg_adp_support", ctypes.c_uint32, 1),
+ ("otg_enable_hsic", ctypes.c_uint32, 1),
+ ("battery_charger_support", ctypes.c_uint32, 1),
+ ("lpm_mode", ctypes.c_uint32, 1),
+ ("total_fifo_size", ctypes.c_uint32, 16)
+ ]
+
+
+class GHWCFG4(ctypes.LittleEndianStructure):
+ _fields_ = [
+ ("num_dev_period_in_ep", ctypes.c_uint32, 4),
+ ("power_optimized", ctypes.c_uint32, 1),
+ ("ahb_freq_min", ctypes.c_uint32, 1),
+ ("hibernation", ctypes.c_uint32, 1),
+ ("reserved7", ctypes.c_uint32, 3),
+ ("service_interval_mode", ctypes.c_uint32, 1),
+ ("ipg_isoc_en", ctypes.c_uint32, 1),
+ ("acg_enable", ctypes.c_uint32, 1),
+ ("reserved13", ctypes.c_uint32, 1),
+ ("utmi_phy_data_width", ctypes.c_uint32, 2),
+ ("dev_ctrl_ep_num", ctypes.c_uint32, 4),
+ ("iddg_filter_enabled", ctypes.c_uint32, 1),
+ ("vbus_valid_filter_enabled", ctypes.c_uint32, 1),
+ ("a_valid_filter_enabled", ctypes.c_uint32, 1),
+ ("b_valid_filter_enabled", ctypes.c_uint32, 1),
+ ("dedicated_fifos", ctypes.c_uint32, 1),
+ ("num_dev_in_eps", ctypes.c_uint32, 4),
+ ("dma_desc_enable", ctypes.c_uint32, 1),
+ ("dma_dynamic", ctypes.c_uint32, 1)
+ ]
+
+
[email protected]()
+def cli():
+ pass
+
+
[email protected]()
[email protected]('mcus', nargs=-1)
[email protected]('-a', '--all', is_flag=True, help='Print all bit-field values')
+def info(mcus, all):
+ """Print DWC2 register values for given MCU(s)"""
+ if len(mcus) == 0:
+ mcus = dwc2_info
+
+ for mcu in mcus:
+ for entry in dwc2_info:
+ if mcu.lower() in entry.lower():
+ print(f"## {entry}")
+ for r_name, r_value in dwc2_info[entry].items():
+ print(f"{r_name} = 0x{r_value:08X}")
+ # Print bit-field values
+ if all and r_name.upper() in globals():
+ class_name = globals()[r_name.upper()]
+ ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
+ for field_name, field_type, _ in class_name._fields_:
+ print(f" {field_name} = {getattr(ghwcfg, field_name)}")
+
+
[email protected]()
+def render_md():
+ """Render dwc2_info to Markdown table"""
+ # Create an empty list to hold the dictionaries
+ dwc2_info_list = []
+
+ # Iterate over the dwc2_info dictionary and extract fields
+ for device, reg_values in dwc2_info.items():
+ entry_dict = {"Device": device}
+ for r_name, r_value in reg_values.items():
+ entry_dict[r_name] = f"0x{r_value:08X}"
+
+ if r_name == 'gsnpsid':
+ # Get dwc2 specs version
+ major = ((r_value >> 8) >> 4) & 0x0F
+ minor = (r_value >> 4) & 0xFF
+ patch = chr((r_value & 0x0F) + ord('a') - 0xA)
+ entry_dict[f' - specs version'] = f"{major:X}.{minor:02X}{patch}"
+ elif r_name.upper() in globals():
+ # Get bit-field values which exist as ctypes structures
+ class_name = globals()[r_name.upper()]
+ ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
+ for field_name, field_type, _ in class_name._fields_:
+ entry_dict[f' - {field_name}'] = getattr(ghwcfg, field_name)
+
+ dwc2_info_list.append(entry_dict)
+
+ # Create a Pandas DataFrame from the list of dictionaries
+ df = pd.DataFrame(dwc2_info_list).set_index('Device')
+
+ # Transpose the DataFrame to switch rows and columns
+ df = df.T
+ #print(df)
+
+ # Write the Markdown table to a file
+ with open('dwc2_info.md', 'w') as md_file:
+ md_file.write(df.to_markdown())
+ md_file.write('\n')
+
+
+if __name__ == '__main__':
+ cli()
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
new file mode 100644
index 000000000..3237a50f6
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -0,0 +1,261 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef DWC2_STM32_H_
+#define DWC2_STM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// EP_MAX : Max number of bi-directional endpoints including EP0
+// EP_FIFO_SIZE : Size of dedicated USB SRAM
+#if CFG_TUSB_MCU == OPT_MCU_STM32F1
+ #include "stm32f1xx.h"
+ #define EP_MAX_FS 4
+ #define EP_FIFO_SIZE_FS 1280
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F2
+ #include "stm32f2xx.h"
+ #define EP_MAX_FS USB_OTG_FS_MAX_IN_ENDPOINTS
+ #define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
+
+ #define EP_MAX_HS USB_OTG_HS_MAX_IN_ENDPOINTS
+ #define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F4
+ #include "stm32f4xx.h"
+ #define EP_MAX_FS USB_OTG_FS_MAX_IN_ENDPOINTS
+ #define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
+
+ #define EP_MAX_HS USB_OTG_HS_MAX_IN_ENDPOINTS
+ #define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32H7
+ #include "stm32h7xx.h"
+ #define EP_MAX_FS 9
+ #define EP_FIFO_SIZE_FS 4096
+
+ #define EP_MAX_HS 9
+ #define EP_FIFO_SIZE_HS 4096
+
+ // NOTE: H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
+ // USB_OTG_FS_PERIPH_BASE and OTG_FS_IRQn not defined
+ #if (! defined USB2_OTG_FS)
+ #define USB_OTG_FS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+ #define OTG_FS_IRQn OTG_HS_IRQn
+ #endif
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
+ #include "stm32f7xx.h"
+ #define EP_MAX_FS 6
+ #define EP_FIFO_SIZE_FS 1280
+
+ #define EP_MAX_HS 9
+ #define EP_FIFO_SIZE_HS 4096
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
+ #include "stm32l4xx.h"
+ #define EP_MAX_FS 6
+ #define EP_FIFO_SIZE_FS 1280
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
+ #include "stm32u5xx.h"
+ // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
+ #ifdef USB_OTG_FS
+ #define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE
+ #define EP_MAX_FS 6
+ #define EP_FIFO_SIZE_FS 1280
+ #else
+ #define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE
+ #define EP_MAX_HS 9
+ #define EP_FIFO_SIZE_HS 4096
+ #endif
+#else
+ #error "Unsupported MCUs"
+#endif
+
+// OTG HS always has higher number of endpoints than FS
+#ifdef USB_OTG_HS_PERIPH_BASE
+ #define DWC2_EP_MAX EP_MAX_HS
+#else
+ #define DWC2_EP_MAX EP_MAX_FS
+#endif
+
+// On STM32 for consistency we associate
+// - Port0 to OTG_FS, and Port1 to OTG_HS
+static const dwc2_controller_t _dwc2_controller[] = {
+ #ifdef USB_OTG_FS_PERIPH_BASE
+ { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
+ #endif
+
+ #ifdef USB_OTG_HS_PERIPH_BASE
+ { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS },
+ #endif
+};
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// SystemCoreClock is already included by family header
+// extern uint32_t SystemCoreClock;
+
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) {
+ NVIC_EnableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
+ NVIC_DisableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
+ // try to delay for 1 ms
+ uint32_t count = SystemCoreClock / 1000;
+ while (count--) __NOP();
+}
+
+// MCU specific PHY init, called BEFORE core reset
+// - dwc2 3.30a (H5) use USB_HS_PHYC
+// - dwc2 4.11a (U5) use femtoPHY
+static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+ if (hs_phy_type == HS_PHY_TYPE_NONE) {
+ // Enable on-chip FS PHY
+ dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
+
+ // https://community.st.com/t5/stm32cubemx-mcus/why-stm32h743-usb-fs-doesn-t-work-if-freertos-tickless-idle/m-p/349480#M18867
+ // H7 running on full-speed phy need to disable ULPI clock in sleep mode.
+ // Otherwise, USB won't work when mcu executing WFI/WFE instruction i.e tick-less RTOS.
+ // Note: there may be other family that is affected by this, but only H7 and F7 is tested so far
+ #if defined(USB_OTG_FS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB2OTGFSULPILPEN)
+ if ( USB_OTG_FS_PERIPH_BASE == (uint32_t) dwc2 ) {
+ RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB2OTGFSULPILPEN;
+ }
+ #endif
+
+ #if defined(USB_OTG_HS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB1OTGHSULPILPEN)
+ if ( USB_OTG_HS_PERIPH_BASE == (uint32_t) dwc2 ) {
+ RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB1OTGHSULPILPEN;
+ }
+ #endif
+
+ #if defined(USB_OTG_HS_PERIPH_BASE) && defined(RCC_AHB1LPENR_OTGHSULPILPEN)
+ if ( USB_OTG_HS_PERIPH_BASE == (uint32_t) dwc2 ) {
+ RCC->AHB1LPENR &= ~RCC_AHB1LPENR_OTGHSULPILPEN;
+ }
+ #endif
+
+ } else {
+#if CFG_TUSB_MCU != OPT_MCU_STM32U5
+ // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
+ dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+#endif
+
+ // Enable on-chip HS PHY
+ if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) {
+ #ifdef USB_HS_PHYC
+ // Enable UTMI HS PHY
+ dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
+
+ // Enable LDO
+ USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
+
+ // Wait until LDO ready
+ while ( 0 == (USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
+
+ uint32_t phyc_pll = 0;
+
+ // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
+ switch ( HSE_VALUE )
+ {
+ case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break;
+ case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
+ case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break;
+ case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break;
+ case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break;
+ case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header
+ default:
+ TU_ASSERT(false, );
+ }
+ USB_HS_PHYC->USB_HS_PHYC_PLL = phyc_pll;
+
+ // Control the tuning interface of the High Speed PHY
+ // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver for F7
+ USB_HS_PHYC->USB_HS_PHYC_TUNE |= 0x00000F13U;
+
+ // Enable PLL internal PHY
+ USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
+ #else
+
+ #endif
+ }
+ }
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+ // used to set turnaround time for fullspeed, nothing to do in highspeed mode
+ if (hs_phy_type == HS_PHY_TYPE_NONE) {
+ // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
+ uint32_t turnaround;
+
+ if (SystemCoreClock >= 32000000u) {
+ turnaround = 0x6u;
+ } else if (SystemCoreClock >= 27500000u) {
+ turnaround = 0x7u;
+ } else if (SystemCoreClock >= 24000000u) {
+ turnaround = 0x8u;
+ } else if (SystemCoreClock >= 21800000u) {
+ turnaround = 0x9u;
+ }
+ else if (SystemCoreClock >= 20000000u) {
+ turnaround = 0xAu;
+ }
+ else if (SystemCoreClock >= 18500000u) {
+ turnaround = 0xBu;
+ }
+ else if (SystemCoreClock >= 17200000u) {
+ turnaround = 0xCu;
+ }
+ else if (SystemCoreClock >= 16000000u) {
+ turnaround = 0xDu;
+ }
+ else if (SystemCoreClock >= 15000000u) {
+ turnaround = 0xEu;
+ }
+ else {
+ turnaround = 0xFu;
+ }
+
+ dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos);
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
new file mode 100644
index 000000000..c15771237
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -0,0 +1,1770 @@
+/**
+ * @author MCD Application Team
+ * Ha Thach (tinyusb.org)
+ *
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ */
+
+#ifndef _TUSB_DWC2_TYPES_H_
+#define _TUSB_DWC2_TYPES_H_
+
+#include "stdint.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// Controller
+typedef struct
+{
+ uintptr_t reg_base;
+ uint32_t irqnum;
+ uint8_t ep_count;
+ uint32_t ep_fifo_size;
+}dwc2_controller_t;
+
+// DWC OTG HW Release versions
+#define DWC2_CORE_REV_2_71a 0x4f54271a
+#define DWC2_CORE_REV_2_72a 0x4f54272a
+#define DWC2_CORE_REV_2_80a 0x4f54280a
+#define DWC2_CORE_REV_2_90a 0x4f54290a
+#define DWC2_CORE_REV_2_91a 0x4f54291a
+#define DWC2_CORE_REV_2_92a 0x4f54292a
+#define DWC2_CORE_REV_2_94a 0x4f54294a
+#define DWC2_CORE_REV_3_00a 0x4f54300a
+#define DWC2_CORE_REV_3_10a 0x4f54310a
+#define DWC2_CORE_REV_4_00a 0x4f54400a
+#define DWC2_CORE_REV_4_11a 0x4f54411a
+#define DWC2_CORE_REV_4_20a 0x4f54420a
+#define DWC2_FS_IOT_REV_1_00a 0x5531100a
+#define DWC2_HS_IOT_REV_1_00a 0x5532100a
+#define DWC2_CORE_REV_MASK 0x0000ffff
+
+// DWC OTG HW Core ID
+#define DWC2_OTG_ID 0x4f540000
+#define DWC2_FS_IOT_ID 0x55310000
+#define DWC2_HS_IOT_ID 0x55320000
+
+#if 0
+// HS PHY
+typedef struct
+{
+ volatile uint32_t HS_PHYC_PLL; // 000h This register is used to control the PLL of the HS PHY.
+ volatile uint32_t Reserved04; // 004h Reserved
+ volatile uint32_t Reserved08; // 008h Reserved
+ volatile uint32_t HS_PHYC_TUNE; // 00Ch This register is used to control the tuning interface of the High Speed PHY.
+ volatile uint32_t Reserved10; // 010h Reserved
+ volatile uint32_t Reserved14; // 014h Reserved
+ volatile uint32_t HS_PHYC_LDO; // 018h This register is used to control the regulator (LDO).
+} HS_PHYC_GlobalTypeDef;
+#endif
+
+enum {
+ HS_PHY_TYPE_NONE = 0 , // not supported
+ HS_PHY_TYPE_UTMI , // internal PHY (mostly)
+ HS_PHY_TYPE_ULPI , // external PHY
+ HS_PHY_TYPE_UTMI_ULPI ,
+};
+
+enum {
+ FS_PHY_TYPE_NONE = 0, // not supported
+ FS_PHY_TYPE_DEDICATED,
+ FS_PHY_TYPE_UTMI,
+ FS_PHY_TYPE_ULPI,
+};
+
+typedef struct TU_ATTR_PACKED
+{
+ uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP
+ uint32_t arch : 2; // 0: slave-only | 1: External DMA | 2: Internal DMA | 3: others
+ uint32_t point2point : 1; // 0: support hub and split | 1: no hub, no split
+ uint32_t hs_phy_type : 2; // 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
+ uint32_t fs_phy_type : 2; // 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
+ uint32_t num_dev_ep : 4; // Number of device endpoints (not including EP0)
+ uint32_t num_host_ch : 4; // Number of host channel
+ uint32_t period_channel_support : 1; // Support Periodic OUT Host Channel
+ uint32_t enable_dynamic_fifo : 1; // Dynamic FIFO Sizing Enabled
+ uint32_t mul_cpu_int : 1; // Multi-Processor Interrupt Enabled
+ uint32_t reserved21 : 1;
+ uint32_t nperiod_tx_q_depth : 2; // Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
+ uint32_t host_period_tx_q_depth : 2; // Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
+ uint32_t dev_token_q_depth : 5; // Device IN token sequence learning queue depth: 0-30
+ uint32_t otg_enable_ic_usb : 1; // IC_USB mode specified for mode of operation
+} dwc2_ghwcfg2_t;
+
+TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED
+{
+ uint32_t xfer_size_width : 4; // Transfer size counter in bits = 11 + n (max 19 bits)
+ uint32_t packet_size_width : 3; // Packet size counter in bits = 4 + n (max 10 bits)
+ uint32_t otg_enable : 1; // 1 is OTG capable
+ uint32_t i2c_enable : 1; // I2C interface is available
+ uint32_t vendor_ctrl_itf : 1; // Vendor control interface is available
+ uint32_t optional_feature_removed : 1; // remove User ID, GPIO, SOF toggle & counter
+ uint32_t synch_reset : 1; // 0: async reset | 1: synch reset
+ uint32_t otg_adp_support : 1; // ADP logic is present along with HSOTG controller
+ uint32_t otg_enable_hsic : 1; // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
+ uint32_t battery_charger_support : 1; // support battery charger
+ uint32_t lpm_mode : 1; // LPC mode
+ uint32_t total_fifo_size : 16; // DFIFO depth value in terms of 32-bit words
+}dwc2_ghwcfg3_t;
+
+TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED
+{
+ uint32_t num_dev_period_in_ep : 4; // Number of Device Periodic IN Endpoints
+ uint32_t power_optimized : 1; // Partial Power Down Enabled
+ uint32_t ahb_freq_min : 1; // 1: minimum of AHB frequency is less than 60 MHz
+ uint32_t hibernation : 1; // Hibernation feature is enabled
+ uint32_t reserved7 : 3;
+ uint32_t service_interval_mode : 1; // Service Interval supported
+ uint32_t ipg_isoc_en : 1; // IPG ISOC supported
+ uint32_t acg_enable : 1; // ACG enabled
+ uint32_t reserved13 : 1;
+ uint32_t utmi_phy_data_width : 2; // 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
+ uint32_t dev_ctrl_ep_num : 4; // Number of Device control endpoints in addition to EP0
+ uint32_t iddg_filter_enabled : 1;
+ uint32_t vbus_valid_filter_enabled : 1;
+ uint32_t a_valid_filter_enabled : 1;
+ uint32_t b_valid_filter_enabled : 1;
+ uint32_t dedicated_fifos : 1; // Dedicated tx fifo for device IN Endpoint is enabled
+ uint32_t num_dev_in_eps : 4; // Number of Device IN Endpoints including EP0
+ uint32_t dma_desc_enable : 1; // scatter/gather DMA configuration
+ uint32_t dma_dynamic : 1; // Dynamic scatter/gather DMA
+}dwc2_ghwcfg4_t;
+
+TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size");
+
+// Host Channel
+typedef struct
+{
+ volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics
+ volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control
+ volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt
+ volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask
+ volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size
+ volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address
+ uint32_t reserved518; // 518 + 20*ch
+ volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address
+} dwc2_channel_t;
+
+// Endpoint IN
+typedef struct
+{
+ volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control
+ uint32_t reserved04; // 904
+ volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt
+ uint32_t reserved0c; // 90C
+ volatile uint32_t dieptsiz; // 910 + 20*ep Device IN Endpoint Transfer Size
+ volatile uint32_t diepdma; // 914 + 20*ep Device IN Endpoint DMA Address
+ volatile uint32_t dtxfsts; // 918 + 20*ep Device IN Endpoint Tx FIFO Status
+ uint32_t reserved1c; // 91C
+} dwc2_epin_t;
+
+// Endpoint OUT
+typedef struct
+{
+ volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control
+ uint32_t reserved04; // B04
+ volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt
+ uint32_t reserved0c; // B0C
+ volatile uint32_t doeptsiz; // B10 + 20*ep Device OUT Endpoint Transfer Size
+ volatile uint32_t doepdma; // B14 + 20*ep Device OUT Endpoint DMA Address
+ uint32_t reserved18[2]; // B18..B1C
+} dwc2_epout_t;
+
+typedef struct
+{
+ //------------- Core Global -------------//
+ volatile uint32_t gotgctl; // 000 OTG Control and Status
+ volatile uint32_t gotgint; // 004 OTG Interrupt
+ volatile uint32_t gahbcfg; // 008 AHB Configuration
+ volatile uint32_t gusbcfg; // 00c USB Configuration
+ volatile uint32_t grstctl; // 010 Reset
+ volatile uint32_t gintsts; // 014 Interrupt
+ volatile uint32_t gintmsk; // 018 Interrupt Mask
+ volatile uint32_t grxstsr; // 01c Receive Status Debug Read
+ volatile uint32_t grxstsp; // 020 Receive Status Read/Pop
+ volatile uint32_t grxfsiz; // 024 Receive FIFO Size
+union {
+ volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size
+ volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size
+};
+ volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status
+ volatile uint32_t gi2cctl; // 030 I2C Address
+ volatile uint32_t gpvndctl; // 034 PHY Vendor Control
+union {
+ volatile uint32_t ggpio; // 038 General Purpose IO
+ volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration
+};
+ volatile uint32_t guid; // 03C User (Application programmable) ID
+ volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version
+ volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
+union {
+ volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2
+ dwc2_ghwcfg2_t ghwcfg2_bm;
+};
+union {
+ volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3
+ dwc2_ghwcfg3_t ghwcfg3_bm;
+};
+union {
+ volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4
+ dwc2_ghwcfg4_t ghwcfg4_bm;
+};
+ volatile uint32_t glpmcfg; // 054 Core LPM Configuration
+ volatile uint32_t gpwrdn; // 058 Power Down
+ volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration
+ volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status
+ uint32_t reserved64[39]; // 064..0FF
+ volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size
+ volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size
+ uint32_t reserved140[176]; // 140..3FF
+
+ //------------- Host -------------//
+ volatile uint32_t hcfg; // 400 Host Configuration
+ volatile uint32_t hfir; // 404 Host Frame Interval
+ volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining
+ uint32_t reserved40c; // 40C
+ volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status
+ volatile uint32_t haint; // 414 Host All Channels Interrupt
+ volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask
+ volatile uint32_t hflbaddr; // 41C Host Frame List Base Address
+ uint32_t reserved420[8]; // 420..43F
+ volatile uint32_t hprt; // 440 Host Port Control and Status
+ uint32_t reserved444[47]; // 444..4FF
+
+ //------------- Host Channel -------------//
+ dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15
+ uint32_t reserved700[64]; // 700..7FF
+
+ //------------- Device -------------//
+ volatile uint32_t dcfg; // 800 Device Configuration
+ volatile uint32_t dctl; // 804 Device Control
+ volatile uint32_t dsts; // 808 Device Status (RO)
+ uint32_t reserved80c; // 80C
+ volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask
+ volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask
+ volatile uint32_t daint; // 818 Device All Endpoints Interrupt
+ volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask
+ volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1
+ volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2
+ volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time
+ volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time
+ volatile uint32_t dthrctl; // 830 Device threshold Control
+ volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask
+ volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt
+ volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk
+ volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask
+ volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask
+ uint32_t reserved8c0[16]; // 8C0..8FF
+
+ //------------- Device Endpoint -------------//
+ dwc2_epin_t epin[16]; // 900..AFF IN Endpoints
+ dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints
+ uint32_t reservedd00[64]; // D00..DFF
+
+ //------------- Power Clock -------------//
+ volatile uint32_t pcgctl; // E00 Power and Clock Gating Control
+ volatile uint32_t pcgctl1; // E04
+ uint32_t reservede08[126]; // E08..FFF
+
+ //------------- FIFOs -------------//
+ // Word-accessed only using first pointer since it auto shift
+ volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO
+} dwc2_regs_t;
+
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x0800, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin ) == 0x0900, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0x0B00, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctl ) == 0x0E00, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
+
+//--------------------------------------------------------------------+
+// Register Bit Definitions
+//--------------------------------------------------------------------+
+
+/******************** Bit definition for GOTGCTL register ********************/
+#define GOTGCTL_SRQSCS_Pos (0U)
+#define GOTGCTL_SRQSCS_Msk (0x1UL << GOTGCTL_SRQSCS_Pos) // 0x00000001
+#define GOTGCTL_SRQSCS GOTGCTL_SRQSCS_Msk // Session request success
+#define GOTGCTL_SRQ_Pos (1U)
+#define GOTGCTL_SRQ_Msk (0x1UL << GOTGCTL_SRQ_Pos) // 0x00000002
+#define GOTGCTL_SRQ GOTGCTL_SRQ_Msk // Session request
+#define GOTGCTL_VBVALOEN_Pos (2U)
+#define GOTGCTL_VBVALOEN_Msk (0x1UL << GOTGCTL_VBVALOEN_Pos) // 0x00000004
+#define GOTGCTL_VBVALOEN GOTGCTL_VBVALOEN_Msk // VBUS valid override enable
+#define GOTGCTL_VBVALOVAL_Pos (3U)
+#define GOTGCTL_VBVALOVAL_Msk (0x1UL << GOTGCTL_VBVALOVAL_Pos) // 0x00000008
+#define GOTGCTL_VBVALOVAL GOTGCTL_VBVALOVAL_Msk // VBUS valid override value
+#define GOTGCTL_AVALOEN_Pos (4U)
+#define GOTGCTL_AVALOEN_Msk (0x1UL << GOTGCTL_AVALOEN_Pos) // 0x00000010
+#define GOTGCTL_AVALOEN GOTGCTL_AVALOEN_Msk // A-peripheral session valid override enable
+#define GOTGCTL_AVALOVAL_Pos (5U)
+#define GOTGCTL_AVALOVAL_Msk (0x1UL << GOTGCTL_AVALOVAL_Pos) // 0x00000020
+#define GOTGCTL_AVALOVAL GOTGCTL_AVALOVAL_Msk // A-peripheral session valid override value
+#define GOTGCTL_BVALOEN_Pos (6U)
+#define GOTGCTL_BVALOEN_Msk (0x1UL << GOTGCTL_BVALOEN_Pos) // 0x00000040
+#define GOTGCTL_BVALOEN GOTGCTL_BVALOEN_Msk // B-peripheral session valid override enable
+#define GOTGCTL_BVALOVAL_Pos (7U)
+#define GOTGCTL_BVALOVAL_Msk (0x1UL << GOTGCTL_BVALOVAL_Pos) // 0x00000080
+#define GOTGCTL_BVALOVAL GOTGCTL_BVALOVAL_Msk // B-peripheral session valid override value
+#define GOTGCTL_HNGSCS_Pos (8U)
+#define GOTGCTL_HNGSCS_Msk (0x1UL << GOTGCTL_HNGSCS_Pos) // 0x00000100
+#define GOTGCTL_HNGSCS GOTGCTL_HNGSCS_Msk // Host set HNP enable
+#define GOTGCTL_HNPRQ_Pos (9U)
+#define GOTGCTL_HNPRQ_Msk (0x1UL << GOTGCTL_HNPRQ_Pos) // 0x00000200
+#define GOTGCTL_HNPRQ GOTGCTL_HNPRQ_Msk // HNP request
+#define GOTGCTL_HSHNPEN_Pos (10U)
+#define GOTGCTL_HSHNPEN_Msk (0x1UL << GOTGCTL_HSHNPEN_Pos) // 0x00000400
+#define GOTGCTL_HSHNPEN GOTGCTL_HSHNPEN_Msk // Host set HNP enable
+#define GOTGCTL_DHNPEN_Pos (11U)
+#define GOTGCTL_DHNPEN_Msk (0x1UL << GOTGCTL_DHNPEN_Pos) // 0x00000800
+#define GOTGCTL_DHNPEN GOTGCTL_DHNPEN_Msk // Device HNP enabled
+#define GOTGCTL_EHEN_Pos (12U)
+#define GOTGCTL_EHEN_Msk (0x1UL << GOTGCTL_EHEN_Pos) // 0x00001000
+#define GOTGCTL_EHEN GOTGCTL_EHEN_Msk // Embedded host enable
+#define GOTGCTL_CIDSTS_Pos (16U)
+#define GOTGCTL_CIDSTS_Msk (0x1UL << GOTGCTL_CIDSTS_Pos) // 0x00010000
+#define GOTGCTL_CIDSTS GOTGCTL_CIDSTS_Msk // Connector ID status
+#define GOTGCTL_DBCT_Pos (17U)
+#define GOTGCTL_DBCT_Msk (0x1UL << GOTGCTL_DBCT_Pos) // 0x00020000
+#define GOTGCTL_DBCT GOTGCTL_DBCT_Msk // Long/short debounce time
+#define GOTGCTL_ASVLD_Pos (18U)
+#define GOTGCTL_ASVLD_Msk (0x1UL << GOTGCTL_ASVLD_Pos) // 0x00040000
+#define GOTGCTL_ASVLD GOTGCTL_ASVLD_Msk // A-session valid
+#define GOTGCTL_BSESVLD_Pos (19U)
+#define GOTGCTL_BSESVLD_Msk (0x1UL << GOTGCTL_BSESVLD_Pos) // 0x00080000
+#define GOTGCTL_BSESVLD GOTGCTL_BSESVLD_Msk // B-session valid
+#define GOTGCTL_OTGVER_Pos (20U)
+#define GOTGCTL_OTGVER_Msk (0x1UL << GOTGCTL_OTGVER_Pos) // 0x00100000
+#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk // OTG version
+
+/******************** Bit definition for HCFG register ********************/
+#define HCFG_FSLSPCS_Pos (0U)
+#define HCFG_FSLSPCS_Msk (0x3UL << HCFG_FSLSPCS_Pos) // 0x00000003
+#define HCFG_FSLSPCS HCFG_FSLSPCS_Msk // FS/LS PHY clock select
+#define HCFG_FSLSPCS_0 (0x1UL << HCFG_FSLSPCS_Pos) // 0x00000001
+#define HCFG_FSLSPCS_1 (0x2UL << HCFG_FSLSPCS_Pos) // 0x00000002
+#define HCFG_FSLSS_Pos (2U)
+#define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) // 0x00000004
+#define HCFG_FSLSS HCFG_FSLSS_Msk // FS- and LS-only support
+
+/******************** Bit definition for PCGCR register ********************/
+#define PCGCR_STPPCLK_Pos (0U)
+#define PCGCR_STPPCLK_Msk (0x1UL << PCGCR_STPPCLK_Pos) // 0x00000001
+#define PCGCR_STPPCLK PCGCR_STPPCLK_Msk // Stop PHY clock
+#define PCGCR_GATEHCLK_Pos (1U)
+#define PCGCR_GATEHCLK_Msk (0x1UL << PCGCR_GATEHCLK_Pos) // 0x00000002
+#define PCGCR_GATEHCLK PCGCR_GATEHCLK_Msk // Gate HCLK
+#define PCGCR_PHYSUSP_Pos (4U)
+#define PCGCR_PHYSUSP_Msk (0x1UL << PCGCR_PHYSUSP_Pos) // 0x00000010
+#define PCGCR_PHYSUSP PCGCR_PHYSUSP_Msk // PHY suspended
+
+/******************** Bit definition for GOTGINT register ********************/
+#define GOTGINT_SEDET_Pos (2U)
+#define GOTGINT_SEDET_Msk (0x1UL << GOTGINT_SEDET_Pos) // 0x00000004
+#define GOTGINT_SEDET GOTGINT_SEDET_Msk // Session end detected
+#define GOTGINT_SRSSCHG_Pos (8U)
+#define GOTGINT_SRSSCHG_Msk (0x1UL << GOTGINT_SRSSCHG_Pos) // 0x00000100
+#define GOTGINT_SRSSCHG GOTGINT_SRSSCHG_Msk // Session request success status change
+#define GOTGINT_HNSSCHG_Pos (9U)
+#define GOTGINT_HNSSCHG_Msk (0x1UL << GOTGINT_HNSSCHG_Pos) // 0x00000200
+#define GOTGINT_HNSSCHG GOTGINT_HNSSCHG_Msk // Host negotiation success status change
+#define GOTGINT_HNGDET_Pos (17U)
+#define GOTGINT_HNGDET_Msk (0x1UL << GOTGINT_HNGDET_Pos) // 0x00020000
+#define GOTGINT_HNGDET GOTGINT_HNGDET_Msk // Host negotiation detected
+#define GOTGINT_ADTOCHG_Pos (18U)
+#define GOTGINT_ADTOCHG_Msk (0x1UL << GOTGINT_ADTOCHG_Pos) // 0x00040000
+#define GOTGINT_ADTOCHG GOTGINT_ADTOCHG_Msk // A-device timeout change
+#define GOTGINT_DBCDNE_Pos (19U)
+#define GOTGINT_DBCDNE_Msk (0x1UL << GOTGINT_DBCDNE_Pos) // 0x00080000
+#define GOTGINT_DBCDNE GOTGINT_DBCDNE_Msk // Debounce done
+#define GOTGINT_IDCHNG_Pos (20U)
+#define GOTGINT_IDCHNG_Msk (0x1UL << GOTGINT_IDCHNG_Pos) // 0x00100000
+#define GOTGINT_IDCHNG GOTGINT_IDCHNG_Msk // Change in ID pin input value
+
+/******************** Bit definition for DCFG register ********************/
+#define DCFG_DSPD_Pos (0U)
+#define DCFG_DSPD_Msk (0x3UL << DCFG_DSPD_Pos) // 0x00000003
+#define DCFG_DSPD_HS 0 // Highspeed
+#define DCFG_DSPD_FS_HSPHY 1 // Fullspeed on HS PHY
+#define DCFG_DSPD_LS 2 // Lowspeed
+#define DCFG_DSPD_FS 3 // Fullspeed on FS PHY
+
+#define DCFG_NZLSOHSK_Pos (2U)
+#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) // 0x00000004
+#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk // Nonzero-length status OUT handshake
+
+#define DCFG_DAD_Pos (4U)
+#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) // 0x000007F0
+#define DCFG_DAD DCFG_DAD_Msk // Device address
+#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) // 0x00000010
+#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) // 0x00000020
+#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) // 0x00000040
+#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) // 0x00000080
+#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) // 0x00000100
+#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) // 0x00000200
+#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) // 0x00000400
+
+#define DCFG_PFIVL_Pos (11U)
+#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) // 0x00001800
+#define DCFG_PFIVL DCFG_PFIVL_Msk // Periodic (micro)frame interval
+#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800
+#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000
+
+#define DCFG_XCVRDLY_Pos (14U)
+#define DCFG_XCVRDLY_Msk (0x1UL << DCFG_XCVRDLY_Pos) // 0x00004000
+#define DCFG_XCVRDLY DCFG_XCVRDLY_Msk // Enables delay between xcvr_sel and txvalid during device chirp
+
+#define DCFG_PERSCHIVL_Pos (24U)
+#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000
+#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval
+#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) // 0x01000000
+#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) // 0x02000000
+
+/******************** Bit definition for DCTL register ********************/
+#define DCTL_RWUSIG_Pos (0U)
+#define DCTL_RWUSIG_Msk (0x1UL << DCTL_RWUSIG_Pos) // 0x00000001
+#define DCTL_RWUSIG DCTL_RWUSIG_Msk // Remote wakeup signaling
+#define DCTL_SDIS_Pos (1U)
+#define DCTL_SDIS_Msk (0x1UL << DCTL_SDIS_Pos) // 0x00000002
+#define DCTL_SDIS DCTL_SDIS_Msk // Soft disconnect
+#define DCTL_GINSTS_Pos (2U)
+#define DCTL_GINSTS_Msk (0x1UL << DCTL_GINSTS_Pos) // 0x00000004
+#define DCTL_GINSTS DCTL_GINSTS_Msk // Global IN NAK status
+#define DCTL_GONSTS_Pos (3U)
+#define DCTL_GONSTS_Msk (0x1UL << DCTL_GONSTS_Pos) // 0x00000008
+#define DCTL_GONSTS DCTL_GONSTS_Msk // Global OUT NAK status
+
+#define DCTL_TCTL_Pos (4U)
+#define DCTL_TCTL_Msk (0x7UL << DCTL_TCTL_Pos) // 0x00000070
+#define DCTL_TCTL DCTL_TCTL_Msk // Test control
+#define DCTL_TCTL_0 (0x1UL << DCTL_TCTL_Pos) // 0x00000010
+#define DCTL_TCTL_1 (0x2UL << DCTL_TCTL_Pos) // 0x00000020
+#define DCTL_TCTL_2 (0x4UL << DCTL_TCTL_Pos) // 0x00000040
+#define DCTL_SGINAK_Pos (7U)
+#define DCTL_SGINAK_Msk (0x1UL << DCTL_SGINAK_Pos) // 0x00000080
+#define DCTL_SGINAK DCTL_SGINAK_Msk // Set global IN NAK
+#define DCTL_CGINAK_Pos (8U)
+#define DCTL_CGINAK_Msk (0x1UL << DCTL_CGINAK_Pos) // 0x00000100
+#define DCTL_CGINAK DCTL_CGINAK_Msk // Clear global IN NAK
+#define DCTL_SGONAK_Pos (9U)
+#define DCTL_SGONAK_Msk (0x1UL << DCTL_SGONAK_Pos) // 0x00000200
+#define DCTL_SGONAK DCTL_SGONAK_Msk // Set global OUT NAK
+#define DCTL_CGONAK_Pos (10U)
+#define DCTL_CGONAK_Msk (0x1UL << DCTL_CGONAK_Pos) // 0x00000400
+#define DCTL_CGONAK DCTL_CGONAK_Msk // Clear global OUT NAK
+#define DCTL_POPRGDNE_Pos (11U)
+#define DCTL_POPRGDNE_Msk (0x1UL << DCTL_POPRGDNE_Pos) // 0x00000800
+#define DCTL_POPRGDNE DCTL_POPRGDNE_Msk // Power-on programming done
+
+/******************** Bit definition for HFIR register ********************/
+#define HFIR_FRIVL_Pos (0U)
+#define HFIR_FRIVL_Msk (0xFFFFUL << HFIR_FRIVL_Pos) // 0x0000FFFF
+#define HFIR_FRIVL HFIR_FRIVL_Msk // Frame interval
+
+/******************** Bit definition for HFNUM register ********************/
+#define HFNUM_FRNUM_Pos (0U)
+#define HFNUM_FRNUM_Msk (0xFFFFUL << HFNUM_FRNUM_Pos) // 0x0000FFFF
+#define HFNUM_FRNUM HFNUM_FRNUM_Msk // Frame number
+#define HFNUM_FTREM_Pos (16U)
+#define HFNUM_FTREM_Msk (0xFFFFUL << HFNUM_FTREM_Pos) // 0xFFFF0000
+#define HFNUM_FTREM HFNUM_FTREM_Msk // Frame time remaining
+
+/******************** Bit definition for DSTS register ********************/
+#define DSTS_SUSPSTS_Pos (0U)
+#define DSTS_SUSPSTS_Msk (0x1UL << DSTS_SUSPSTS_Pos) // 0x00000001
+#define DSTS_SUSPSTS DSTS_SUSPSTS_Msk // Suspend status
+#define DSTS_ENUMSPD_Pos (1U)
+#define DSTS_ENUMSPD_Msk (0x3UL << DSTS_ENUMSPD_Pos) // 0x00000006
+#define DSTS_ENUMSPD DSTS_ENUMSPD_Msk // Enumerated speed
+#define DSTS_ENUMSPD_HS 0 // Highspeed
+#define DSTS_ENUMSPD_FS_HSPHY 1 // Fullspeed on HS PHY
+#define DSTS_ENUMSPD_LS 2 // Lowspeed
+#define DSTS_ENUMSPD_FS 3 // Fullspeed on FS PHY
+
+
+#define DSTS_EERR_Pos (3U)
+#define DSTS_EERR_Msk (0x1UL << DSTS_EERR_Pos) // 0x00000008
+#define DSTS_EERR DSTS_EERR_Msk // Erratic error
+#define DSTS_FNSOF_Pos (8U)
+#define DSTS_FNSOF_Msk (0x3FFFUL << DSTS_FNSOF_Pos) // 0x003FFF00
+#define DSTS_FNSOF DSTS_FNSOF_Msk // Frame number of the received SOF
+
+/******************** Bit definition for GAHBCFG register ********************/
+#define GAHBCFG_GINT_Pos (0U)
+#define GAHBCFG_GINT_Msk (0x1UL << GAHBCFG_GINT_Pos) // 0x00000001
+#define GAHBCFG_GINT GAHBCFG_GINT_Msk // Global interrupt mask
+#define GAHBCFG_HBSTLEN_Pos (1U)
+#define GAHBCFG_HBSTLEN_Msk (0xFUL << GAHBCFG_HBSTLEN_Pos) // 0x0000001E
+#define GAHBCFG_HBSTLEN GAHBCFG_HBSTLEN_Msk // Burst length/type
+#define GAHBCFG_HBSTLEN_0 (0x0UL << GAHBCFG_HBSTLEN_Pos) // Single
+#define GAHBCFG_HBSTLEN_1 (0x1UL << GAHBCFG_HBSTLEN_Pos) // INCR
+#define GAHBCFG_HBSTLEN_2 (0x3UL << GAHBCFG_HBSTLEN_Pos) // INCR4
+#define GAHBCFG_HBSTLEN_3 (0x5UL << GAHBCFG_HBSTLEN_Pos) // INCR8
+#define GAHBCFG_HBSTLEN_4 (0x7UL << GAHBCFG_HBSTLEN_Pos) // INCR16
+#define GAHBCFG_DMAEN_Pos (5U)
+#define GAHBCFG_DMAEN_Msk (0x1UL << GAHBCFG_DMAEN_Pos) // 0x00000020
+#define GAHBCFG_DMAEN GAHBCFG_DMAEN_Msk // DMA enable
+#define GAHBCFG_TXFELVL_Pos (7U)
+#define GAHBCFG_TXFELVL_Msk (0x1UL << GAHBCFG_TXFELVL_Pos) // 0x00000080
+#define GAHBCFG_TXFELVL GAHBCFG_TXFELVL_Msk // TxFIFO empty level
+#define GAHBCFG_PTXFELVL_Pos (8U)
+#define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) // 0x00000100
+#define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk // Periodic TxFIFO empty level
+
+#define GSNPSID_ID_MASK TU_GENMASK(31, 16)
+
+/******************** Bit definition for GUSBCFG register ********************/
+#define GUSBCFG_TOCAL_Pos (0U)
+#define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) // 0x00000007
+#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // FS timeout calibration
+#define GUSBCFG_PHYIF16_Pos (3U)
+#define GUSBCFG_PHYIF16_Msk (0x1UL << GUSBCFG_PHYIF16_Pos) // 0x00000008
+#define GUSBCFG_PHYIF16 GUSBCFG_PHYIF16_Msk // PHY Interface (PHYIf)
+#define GUSBCFG_ULPI_UTMI_SEL_Pos (4U)
+#define GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) // 0x00000010
+#define GUSBCFG_ULPI_UTMI_SEL GUSBCFG_ULPI_UTMI_SEL_Msk // ULPI or UTMI+ Select (ULPI_UTMI_Sel)
+#define GUSBCFG_PHYSEL_Pos (6U)
+#define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) // 0x00000040
+#define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
+#define GUSBCFG_DDRSEL TU_BIT(7) // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
+#define GUSBCFG_SRPCAP_Pos (8U)
+#define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) // 0x00000100
+#define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk // SRP-capable
+#define GUSBCFG_HNPCAP_Pos (9U)
+#define GUSBCFG_HNPCAP_Msk (0x1UL << GUSBCFG_HNPCAP_Pos) // 0x00000200
+#define GUSBCFG_HNPCAP GUSBCFG_HNPCAP_Msk // HNP-capable
+#define GUSBCFG_TRDT_Pos (10U)
+#define GUSBCFG_TRDT_Msk (0xFUL << GUSBCFG_TRDT_Pos) // 0x00003C00
+#define GUSBCFG_TRDT GUSBCFG_TRDT_Msk // USB turnaround time
+#define GUSBCFG_PHYLPCS_Pos (15U)
+#define GUSBCFG_PHYLPCS_Msk (0x1UL << GUSBCFG_PHYLPCS_Pos) // 0x00008000
+#define GUSBCFG_PHYLPCS GUSBCFG_PHYLPCS_Msk // PHY Low-power clock select
+#define GUSBCFG_ULPIFSLS_Pos (17U)
+#define GUSBCFG_ULPIFSLS_Msk (0x1UL << GUSBCFG_ULPIFSLS_Pos) // 0x00020000
+#define GUSBCFG_ULPIFSLS GUSBCFG_ULPIFSLS_Msk // ULPI FS/LS select
+#define GUSBCFG_ULPIAR_Pos (18U)
+#define GUSBCFG_ULPIAR_Msk (0x1UL << GUSBCFG_ULPIAR_Pos) // 0x00040000
+#define GUSBCFG_ULPIAR GUSBCFG_ULPIAR_Msk // ULPI Auto-resume
+#define GUSBCFG_ULPICSM_Pos (19U)
+#define GUSBCFG_ULPICSM_Msk (0x1UL << GUSBCFG_ULPICSM_Pos) // 0x00080000
+#define GUSBCFG_ULPICSM GUSBCFG_ULPICSM_Msk // ULPI Clock SuspendM
+#define GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define GUSBCFG_ULPIEVBUSD_Msk (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) // 0x00100000
+#define GUSBCFG_ULPIEVBUSD GUSBCFG_ULPIEVBUSD_Msk // ULPI External VBUS Drive
+#define GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define GUSBCFG_ULPIEVBUSI_Msk (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) // 0x00200000
+#define GUSBCFG_ULPIEVBUSI GUSBCFG_ULPIEVBUSI_Msk // ULPI external VBUS indicator
+#define GUSBCFG_TSDPS_Pos (22U)
+#define GUSBCFG_TSDPS_Msk (0x1UL << GUSBCFG_TSDPS_Pos) // 0x00400000
+#define GUSBCFG_TSDPS GUSBCFG_TSDPS_Msk // TermSel DLine pulsing selection
+#define GUSBCFG_PCCI_Pos (23U)
+#define GUSBCFG_PCCI_Msk (0x1UL << GUSBCFG_PCCI_Pos) // 0x00800000
+#define GUSBCFG_PCCI GUSBCFG_PCCI_Msk // Indicator complement
+#define GUSBCFG_PTCI_Pos (24U)
+#define GUSBCFG_PTCI_Msk (0x1UL << GUSBCFG_PTCI_Pos) // 0x01000000
+#define GUSBCFG_PTCI GUSBCFG_PTCI_Msk // Indicator pass through
+#define GUSBCFG_ULPIIPD_Pos (25U)
+#define GUSBCFG_ULPIIPD_Msk (0x1UL << GUSBCFG_ULPIIPD_Pos) // 0x02000000
+#define GUSBCFG_ULPIIPD GUSBCFG_ULPIIPD_Msk // ULPI interface protect disable
+#define GUSBCFG_FHMOD_Pos (29U)
+#define GUSBCFG_FHMOD_Msk (0x1UL << GUSBCFG_FHMOD_Pos) // 0x20000000
+#define GUSBCFG_FHMOD GUSBCFG_FHMOD_Msk // Forced host mode
+#define GUSBCFG_FDMOD_Pos (30U)
+#define GUSBCFG_FDMOD_Msk (0x1UL << GUSBCFG_FDMOD_Pos) // 0x40000000
+#define GUSBCFG_FDMOD GUSBCFG_FDMOD_Msk // Forced peripheral mode
+#define GUSBCFG_CTXPKT_Pos (31U)
+#define GUSBCFG_CTXPKT_Msk (0x1UL << GUSBCFG_CTXPKT_Pos) // 0x80000000
+#define GUSBCFG_CTXPKT GUSBCFG_CTXPKT_Msk // Corrupt Tx packet
+
+/******************** Bit definition for GRSTCTL register ********************/
+#define GRSTCTL_CSRST_Pos (0U)
+#define GRSTCTL_CSRST_Msk (0x1UL << GRSTCTL_CSRST_Pos) // 0x00000001
+#define GRSTCTL_CSRST GRSTCTL_CSRST_Msk // Core soft reset
+#define GRSTCTL_HSRST_Pos (1U)
+#define GRSTCTL_HSRST_Msk (0x1UL << GRSTCTL_HSRST_Pos) // 0x00000002
+#define GRSTCTL_HSRST GRSTCTL_HSRST_Msk // HCLK soft reset
+#define GRSTCTL_FCRST_Pos (2U)
+#define GRSTCTL_FCRST_Msk (0x1UL << GRSTCTL_FCRST_Pos) // 0x00000004
+#define GRSTCTL_FCRST GRSTCTL_FCRST_Msk // Host frame counter reset
+#define GRSTCTL_RXFFLSH_Pos (4U)
+#define GRSTCTL_RXFFLSH_Msk (0x1UL << GRSTCTL_RXFFLSH_Pos) // 0x00000010
+#define GRSTCTL_RXFFLSH GRSTCTL_RXFFLSH_Msk // RxFIFO flush
+#define GRSTCTL_TXFFLSH_Pos (5U)
+#define GRSTCTL_TXFFLSH_Msk (0x1UL << GRSTCTL_TXFFLSH_Pos) // 0x00000020
+#define GRSTCTL_TXFFLSH GRSTCTL_TXFFLSH_Msk // TxFIFO flush
+#define GRSTCTL_TXFNUM_Pos (6U)
+#define GRSTCTL_TXFNUM_Msk (0x1FUL << GRSTCTL_TXFNUM_Pos) // 0x000007C0
+#define GRSTCTL_TXFNUM GRSTCTL_TXFNUM_Msk // TxFIFO number
+#define GRSTCTL_TXFNUM_0 (0x01UL << GRSTCTL_TXFNUM_Pos) // 0x00000040
+#define GRSTCTL_TXFNUM_1 (0x02UL << GRSTCTL_TXFNUM_Pos) // 0x00000080
+#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) // 0x00000100
+#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) // 0x00000200
+#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) // 0x00000400
+#define GRSTCTL_CSFTRST_DONE_Pos (29)
+#define GRSTCTL_CSFTRST_DONE (1u << GRSTCTL_CSFTRST_DONE_Pos) // Reset Done, only available from v4.20a
+#define GRSTCTL_DMAREQ_Pos (30U)
+#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) // 0x40000000
+#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk // DMA request signal
+#define GRSTCTL_AHBIDL_Pos (31U)
+#define GRSTCTL_AHBIDL_Msk (0x1UL << GRSTCTL_AHBIDL_Pos) // 0x80000000
+#define GRSTCTL_AHBIDL GRSTCTL_AHBIDL_Msk // AHB master idle
+
+/******************** Bit definition for DIEPMSK register ********************/
+#define DIEPMSK_XFRCM_Pos (0U)
+#define DIEPMSK_XFRCM_Msk (0x1UL << DIEPMSK_XFRCM_Pos) // 0x00000001
+#define DIEPMSK_XFRCM DIEPMSK_XFRCM_Msk // Transfer completed interrupt mask
+#define DIEPMSK_EPDM_Pos (1U)
+#define DIEPMSK_EPDM_Msk (0x1UL << DIEPMSK_EPDM_Pos) // 0x00000002
+#define DIEPMSK_EPDM DIEPMSK_EPDM_Msk // Endpoint disabled interrupt mask
+#define DIEPMSK_TOM_Pos (3U)
+#define DIEPMSK_TOM_Msk (0x1UL << DIEPMSK_TOM_Pos) // 0x00000008
+#define DIEPMSK_TOM DIEPMSK_TOM_Msk // Timeout condition mask (nonisochronous endpoints)
+#define DIEPMSK_ITTXFEMSK_Pos (4U)
+#define DIEPMSK_ITTXFEMSK_Msk (0x1UL << DIEPMSK_ITTXFEMSK_Pos) // 0x00000010
+#define DIEPMSK_ITTXFEMSK DIEPMSK_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask
+#define DIEPMSK_INEPNMM_Pos (5U)
+#define DIEPMSK_INEPNMM_Msk (0x1UL << DIEPMSK_INEPNMM_Pos) // 0x00000020
+#define DIEPMSK_INEPNMM DIEPMSK_INEPNMM_Msk // IN token received with EP mismatch mask
+#define DIEPMSK_INEPNEM_Pos (6U)
+#define DIEPMSK_INEPNEM_Msk (0x1UL << DIEPMSK_INEPNEM_Pos) // 0x00000040
+#define DIEPMSK_INEPNEM DIEPMSK_INEPNEM_Msk // IN endpoint NAK effective mask
+#define DIEPMSK_TXFURM_Pos (8U)
+#define DIEPMSK_TXFURM_Msk (0x1UL << DIEPMSK_TXFURM_Pos) // 0x00000100
+#define DIEPMSK_TXFURM DIEPMSK_TXFURM_Msk // FIFO underrun mask
+#define DIEPMSK_BIM_Pos (9U)
+#define DIEPMSK_BIM_Msk (0x1UL << DIEPMSK_BIM_Pos) // 0x00000200
+#define DIEPMSK_BIM DIEPMSK_BIM_Msk // BNA interrupt mask
+
+/******************** Bit definition for HPTXSTS register ********************/
+#define HPTXSTS_PTXFSAVL_Pos (0U)
+#define HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) // 0x0000FFFF
+#define HPTXSTS_PTXFSAVL HPTXSTS_PTXFSAVL_Msk // Periodic transmit data FIFO space available
+#define HPTXSTS_PTXQSAV_Pos (16U)
+#define HPTXSTS_PTXQSAV_Msk (0xFFUL << HPTXSTS_PTXQSAV_Pos) // 0x00FF0000
+#define HPTXSTS_PTXQSAV HPTXSTS_PTXQSAV_Msk // Periodic transmit request queue space available
+#define HPTXSTS_PTXQSAV_0 (0x01UL << HPTXSTS_PTXQSAV_Pos) // 0x00010000
+#define HPTXSTS_PTXQSAV_1 (0x02UL << HPTXSTS_PTXQSAV_Pos) // 0x00020000
+#define HPTXSTS_PTXQSAV_2 (0x04UL << HPTXSTS_PTXQSAV_Pos) // 0x00040000
+#define HPTXSTS_PTXQSAV_3 (0x08UL << HPTXSTS_PTXQSAV_Pos) // 0x00080000
+#define HPTXSTS_PTXQSAV_4 (0x10UL << HPTXSTS_PTXQSAV_Pos) // 0x00100000
+#define HPTXSTS_PTXQSAV_5 (0x20UL << HPTXSTS_PTXQSAV_Pos) // 0x00200000
+#define HPTXSTS_PTXQSAV_6 (0x40UL << HPTXSTS_PTXQSAV_Pos) // 0x00400000
+#define HPTXSTS_PTXQSAV_7 (0x80UL << HPTXSTS_PTXQSAV_Pos) // 0x00800000
+
+#define HPTXSTS_PTXQTOP_Pos (24U)
+#define HPTXSTS_PTXQTOP_Msk (0xFFUL << HPTXSTS_PTXQTOP_Pos) // 0xFF000000
+#define HPTXSTS_PTXQTOP HPTXSTS_PTXQTOP_Msk // Top of the periodic transmit request queue
+#define HPTXSTS_PTXQTOP_0 (0x01UL << HPTXSTS_PTXQTOP_Pos) // 0x01000000
+#define HPTXSTS_PTXQTOP_1 (0x02UL << HPTXSTS_PTXQTOP_Pos) // 0x02000000
+#define HPTXSTS_PTXQTOP_2 (0x04UL << HPTXSTS_PTXQTOP_Pos) // 0x04000000
+#define HPTXSTS_PTXQTOP_3 (0x08UL << HPTXSTS_PTXQTOP_Pos) // 0x08000000
+#define HPTXSTS_PTXQTOP_4 (0x10UL << HPTXSTS_PTXQTOP_Pos) // 0x10000000
+#define HPTXSTS_PTXQTOP_5 (0x20UL << HPTXSTS_PTXQTOP_Pos) // 0x20000000
+#define HPTXSTS_PTXQTOP_6 (0x40UL << HPTXSTS_PTXQTOP_Pos) // 0x40000000
+#define HPTXSTS_PTXQTOP_7 (0x80UL << HPTXSTS_PTXQTOP_Pos) // 0x80000000
+
+/******************** Bit definition for HAINT register ********************/
+#define HAINT_HAINT_Pos (0U)
+#define HAINT_HAINT_Msk (0xFFFFUL << HAINT_HAINT_Pos) // 0x0000FFFF
+#define HAINT_HAINT HAINT_HAINT_Msk // Channel interrupts
+
+/******************** Bit definition for DOEPMSK register ********************/
+#define DOEPMSK_XFRCM_Pos (0U)
+#define DOEPMSK_XFRCM_Msk (0x1UL << DOEPMSK_XFRCM_Pos) // 0x00000001
+#define DOEPMSK_XFRCM DOEPMSK_XFRCM_Msk // Transfer completed interrupt mask
+#define DOEPMSK_EPDM_Pos (1U)
+#define DOEPMSK_EPDM_Msk (0x1UL << DOEPMSK_EPDM_Pos) // 0x00000002
+#define DOEPMSK_EPDM DOEPMSK_EPDM_Msk // Endpoint disabled interrupt mask
+#define DOEPMSK_AHBERRM_Pos (2U)
+#define DOEPMSK_AHBERRM_Msk (0x1UL << DOEPMSK_AHBERRM_Pos) // 0x00000004
+#define DOEPMSK_AHBERRM DOEPMSK_AHBERRM_Msk // OUT transaction AHB Error interrupt mask
+#define DOEPMSK_STUPM_Pos (3U)
+#define DOEPMSK_STUPM_Msk (0x1UL << DOEPMSK_STUPM_Pos) // 0x00000008
+#define DOEPMSK_STUPM DOEPMSK_STUPM_Msk // SETUP phase done mask
+#define DOEPMSK_OTEPDM_Pos (4U)
+#define DOEPMSK_OTEPDM_Msk (0x1UL << DOEPMSK_OTEPDM_Pos) // 0x00000010
+#define DOEPMSK_OTEPDM DOEPMSK_OTEPDM_Msk // OUT token received when endpoint disabled mask
+#define DOEPMSK_OTEPSPRM_Pos (5U)
+#define DOEPMSK_OTEPSPRM_Msk (0x1UL << DOEPMSK_OTEPSPRM_Pos) // 0x00000020
+#define DOEPMSK_OTEPSPRM DOEPMSK_OTEPSPRM_Msk // Status Phase Received mask
+#define DOEPMSK_B2BSTUP_Pos (6U)
+#define DOEPMSK_B2BSTUP_Msk (0x1UL << DOEPMSK_B2BSTUP_Pos) // 0x00000040
+#define DOEPMSK_B2BSTUP DOEPMSK_B2BSTUP_Msk // Back-to-back SETUP packets received mask
+#define DOEPMSK_OPEM_Pos (8U)
+#define DOEPMSK_OPEM_Msk (0x1UL << DOEPMSK_OPEM_Pos) // 0x00000100
+#define DOEPMSK_OPEM DOEPMSK_OPEM_Msk // OUT packet error mask
+#define DOEPMSK_BOIM_Pos (9U)
+#define DOEPMSK_BOIM_Msk (0x1UL << DOEPMSK_BOIM_Pos) // 0x00000200
+#define DOEPMSK_BOIM DOEPMSK_BOIM_Msk // BNA interrupt mask
+#define DOEPMSK_BERRM_Pos (12U)
+#define DOEPMSK_BERRM_Msk (0x1UL << DOEPMSK_BERRM_Pos) // 0x00001000
+#define DOEPMSK_BERRM DOEPMSK_BERRM_Msk // Babble error interrupt mask
+#define DOEPMSK_NAKM_Pos (13U)
+#define DOEPMSK_NAKM_Msk (0x1UL << DOEPMSK_NAKM_Pos) // 0x00002000
+#define DOEPMSK_NAKM DOEPMSK_NAKM_Msk // OUT Packet NAK interrupt mask
+#define DOEPMSK_NYETM_Pos (14U)
+#define DOEPMSK_NYETM_Msk (0x1UL << DOEPMSK_NYETM_Pos) // 0x00004000
+#define DOEPMSK_NYETM DOEPMSK_NYETM_Msk // NYET interrupt mask
+
+/******************** Bit definition for GINTSTS register ********************/
+#define GINTSTS_CMOD_Pos (0U)
+#define GINTSTS_CMOD_Msk (0x1UL << GINTSTS_CMOD_Pos) // 0x00000001
+#define GINTSTS_CMOD GINTSTS_CMOD_Msk // Current mode of operation
+#define GINTSTS_MMIS_Pos (1U)
+#define GINTSTS_MMIS_Msk (0x1UL << GINTSTS_MMIS_Pos) // 0x00000002
+#define GINTSTS_MMIS GINTSTS_MMIS_Msk // Mode mismatch interrupt
+#define GINTSTS_OTGINT_Pos (2U)
+#define GINTSTS_OTGINT_Msk (0x1UL << GINTSTS_OTGINT_Pos) // 0x00000004
+#define GINTSTS_OTGINT GINTSTS_OTGINT_Msk // OTG interrupt
+#define GINTSTS_SOF_Pos (3U)
+#define GINTSTS_SOF_Msk (0x1UL << GINTSTS_SOF_Pos) // 0x00000008
+#define GINTSTS_SOF GINTSTS_SOF_Msk // Start of frame
+#define GINTSTS_RXFLVL_Pos (4U)
+#define GINTSTS_RXFLVL_Msk (0x1UL << GINTSTS_RXFLVL_Pos) // 0x00000010
+#define GINTSTS_RXFLVL GINTSTS_RXFLVL_Msk // RxFIFO nonempty
+#define GINTSTS_NPTXFE_Pos (5U)
+#define GINTSTS_NPTXFE_Msk (0x1UL << GINTSTS_NPTXFE_Pos) // 0x00000020
+#define GINTSTS_NPTXFE GINTSTS_NPTXFE_Msk // Nonperiodic TxFIFO empty
+#define GINTSTS_GINAKEFF_Pos (6U)
+#define GINTSTS_GINAKEFF_Msk (0x1UL << GINTSTS_GINAKEFF_Pos) // 0x00000040
+#define GINTSTS_GINAKEFF GINTSTS_GINAKEFF_Msk // Global IN nonperiodic NAK effective
+#define GINTSTS_BOUTNAKEFF_Pos (7U)
+#define GINTSTS_BOUTNAKEFF_Msk (0x1UL << GINTSTS_BOUTNAKEFF_Pos) // 0x00000080
+#define GINTSTS_BOUTNAKEFF GINTSTS_BOUTNAKEFF_Msk // Global OUT NAK effective
+#define GINTSTS_ESUSP_Pos (10U)
+#define GINTSTS_ESUSP_Msk (0x1UL << GINTSTS_ESUSP_Pos) // 0x00000400
+#define GINTSTS_ESUSP GINTSTS_ESUSP_Msk // Early suspend
+#define GINTSTS_USBSUSP_Pos (11U)
+#define GINTSTS_USBSUSP_Msk (0x1UL << GINTSTS_USBSUSP_Pos) // 0x00000800
+#define GINTSTS_USBSUSP GINTSTS_USBSUSP_Msk // USB suspend
+#define GINTSTS_USBRST_Pos (12U)
+#define GINTSTS_USBRST_Msk (0x1UL << GINTSTS_USBRST_Pos) // 0x00001000
+#define GINTSTS_USBRST GINTSTS_USBRST_Msk // USB reset
+#define GINTSTS_ENUMDNE_Pos (13U)
+#define GINTSTS_ENUMDNE_Msk (0x1UL << GINTSTS_ENUMDNE_Pos) // 0x00002000
+#define GINTSTS_ENUMDNE GINTSTS_ENUMDNE_Msk // Enumeration done
+#define GINTSTS_ISOODRP_Pos (14U)
+#define GINTSTS_ISOODRP_Msk (0x1UL << GINTSTS_ISOODRP_Pos) // 0x00004000
+#define GINTSTS_ISOODRP GINTSTS_ISOODRP_Msk // Isochronous OUT packet dropped interrupt
+#define GINTSTS_EOPF_Pos (15U)
+#define GINTSTS_EOPF_Msk (0x1UL << GINTSTS_EOPF_Pos) // 0x00008000
+#define GINTSTS_EOPF GINTSTS_EOPF_Msk // End of periodic frame interrupt
+#define GINTSTS_IEPINT_Pos (18U)
+#define GINTSTS_IEPINT_Msk (0x1UL << GINTSTS_IEPINT_Pos) // 0x00040000
+#define GINTSTS_IEPINT GINTSTS_IEPINT_Msk // IN endpoint interrupt
+#define GINTSTS_OEPINT_Pos (19U)
+#define GINTSTS_OEPINT_Msk (0x1UL << GINTSTS_OEPINT_Pos) // 0x00080000
+#define GINTSTS_OEPINT GINTSTS_OEPINT_Msk // OUT endpoint interrupt
+#define GINTSTS_IISOIXFR_Pos (20U)
+#define GINTSTS_IISOIXFR_Msk (0x1UL << GINTSTS_IISOIXFR_Pos) // 0x00100000
+#define GINTSTS_IISOIXFR GINTSTS_IISOIXFR_Msk // Incomplete isochronous IN transfer
+#define GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) // 0x00200000
+#define GINTSTS_PXFR_INCOMPISOOUT GINTSTS_PXFR_INCOMPISOOUT_Msk // Incomplete periodic transfer
+#define GINTSTS_DATAFSUSP_Pos (22U)
+#define GINTSTS_DATAFSUSP_Msk (0x1UL << GINTSTS_DATAFSUSP_Pos) // 0x00400000
+#define GINTSTS_DATAFSUSP GINTSTS_DATAFSUSP_Msk // Data fetch suspended
+#define GINTSTS_RSTDET_Pos (23U)
+#define GINTSTS_RSTDET_Msk (0x1UL << GINTSTS_RSTDET_Pos) // 0x00800000
+#define GINTSTS_RSTDET GINTSTS_RSTDET_Msk // Reset detected interrupt
+#define GINTSTS_HPRTINT_Pos (24U)
+#define GINTSTS_HPRTINT_Msk (0x1UL << GINTSTS_HPRTINT_Pos) // 0x01000000
+#define GINTSTS_HPRTINT GINTSTS_HPRTINT_Msk // Host port interrupt
+#define GINTSTS_HCINT_Pos (25U)
+#define GINTSTS_HCINT_Msk (0x1UL << GINTSTS_HCINT_Pos) // 0x02000000
+#define GINTSTS_HCINT GINTSTS_HCINT_Msk // Host channels interrupt
+#define GINTSTS_PTXFE_Pos (26U)
+#define GINTSTS_PTXFE_Msk (0x1UL << GINTSTS_PTXFE_Pos) // 0x04000000
+#define GINTSTS_PTXFE GINTSTS_PTXFE_Msk // Periodic TxFIFO empty
+#define GINTSTS_LPMINT_Pos (27U)
+#define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) // 0x08000000
+#define GINTSTS_LPMINT GINTSTS_LPMINT_Msk // LPM interrupt
+#define GINTSTS_CIDSCHG_Pos (28U)
+#define GINTSTS_CIDSCHG_Msk (0x1UL << GINTSTS_CIDSCHG_Pos) // 0x10000000
+#define GINTSTS_CIDSCHG GINTSTS_CIDSCHG_Msk // Connector ID status change
+#define GINTSTS_DISCINT_Pos (29U)
+#define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) // 0x20000000
+#define GINTSTS_DISCINT GINTSTS_DISCINT_Msk // Disconnect detected interrupt
+#define GINTSTS_SRQINT_Pos (30U)
+#define GINTSTS_SRQINT_Msk (0x1UL << GINTSTS_SRQINT_Pos) // 0x40000000
+#define GINTSTS_SRQINT GINTSTS_SRQINT_Msk // Session request/new session detected interrupt
+#define GINTSTS_WKUINT_Pos (31U)
+#define GINTSTS_WKUINT_Msk (0x1UL << GINTSTS_WKUINT_Pos) // 0x80000000
+#define GINTSTS_WKUINT GINTSTS_WKUINT_Msk // Resume/remote wakeup detected interrupt
+
+/******************** Bit definition for GINTMSK register ********************/
+#define GINTMSK_MMISM_Pos (1U)
+#define GINTMSK_MMISM_Msk (0x1UL << GINTMSK_MMISM_Pos) // 0x00000002
+#define GINTMSK_MMISM GINTMSK_MMISM_Msk // Mode mismatch interrupt mask
+#define GINTMSK_OTGINT_Pos (2U)
+#define GINTMSK_OTGINT_Msk (0x1UL << GINTMSK_OTGINT_Pos) // 0x00000004
+#define GINTMSK_OTGINT GINTMSK_OTGINT_Msk // OTG interrupt mask
+#define GINTMSK_SOFM_Pos (3U)
+#define GINTMSK_SOFM_Msk (0x1UL << GINTMSK_SOFM_Pos) // 0x00000008
+#define GINTMSK_SOFM GINTMSK_SOFM_Msk // Start of frame mask
+#define GINTMSK_RXFLVLM_Pos (4U)
+#define GINTMSK_RXFLVLM_Msk (0x1UL << GINTMSK_RXFLVLM_Pos) // 0x00000010
+#define GINTMSK_RXFLVLM GINTMSK_RXFLVLM_Msk // Receive FIFO nonempty mask
+#define GINTMSK_NPTXFEM_Pos (5U)
+#define GINTMSK_NPTXFEM_Msk (0x1UL << GINTMSK_NPTXFEM_Pos) // 0x00000020
+#define GINTMSK_NPTXFEM GINTMSK_NPTXFEM_Msk // Nonperiodic TxFIFO empty mask
+#define GINTMSK_GINAKEFFM_Pos (6U)
+#define GINTMSK_GINAKEFFM_Msk (0x1UL << GINTMSK_GINAKEFFM_Pos) // 0x00000040
+#define GINTMSK_GINAKEFFM GINTMSK_GINAKEFFM_Msk // Global nonperiodic IN NAK effective mask
+#define GINTMSK_GONAKEFFM_Pos (7U)
+#define GINTMSK_GONAKEFFM_Msk (0x1UL << GINTMSK_GONAKEFFM_Pos) // 0x00000080
+#define GINTMSK_GONAKEFFM GINTMSK_GONAKEFFM_Msk // Global OUT NAK effective mask
+#define GINTMSK_ESUSPM_Pos (10U)
+#define GINTMSK_ESUSPM_Msk (0x1UL << GINTMSK_ESUSPM_Pos) // 0x00000400
+#define GINTMSK_ESUSPM GINTMSK_ESUSPM_Msk // Early suspend mask
+#define GINTMSK_USBSUSPM_Pos (11U)
+#define GINTMSK_USBSUSPM_Msk (0x1UL << GINTMSK_USBSUSPM_Pos) // 0x00000800
+#define GINTMSK_USBSUSPM GINTMSK_USBSUSPM_Msk // USB suspend mask
+#define GINTMSK_USBRST_Pos (12U)
+#define GINTMSK_USBRST_Msk (0x1UL << GINTMSK_USBRST_Pos) // 0x00001000
+#define GINTMSK_USBRST GINTMSK_USBRST_Msk // USB reset mask
+#define GINTMSK_ENUMDNEM_Pos (13U)
+#define GINTMSK_ENUMDNEM_Msk (0x1UL << GINTMSK_ENUMDNEM_Pos) // 0x00002000
+#define GINTMSK_ENUMDNEM GINTMSK_ENUMDNEM_Msk // Enumeration done mask
+#define GINTMSK_ISOODRPM_Pos (14U)
+#define GINTMSK_ISOODRPM_Msk (0x1UL << GINTMSK_ISOODRPM_Pos) // 0x00004000
+#define GINTMSK_ISOODRPM GINTMSK_ISOODRPM_Msk // Isochronous OUT packet dropped interrupt mask
+#define GINTMSK_EOPFM_Pos (15U)
+#define GINTMSK_EOPFM_Msk (0x1UL << GINTMSK_EOPFM_Pos) // 0x00008000
+#define GINTMSK_EOPFM GINTMSK_EOPFM_Msk // End of periodic frame interrupt mask
+#define GINTMSK_EPMISM_Pos (17U)
+#define GINTMSK_EPMISM_Msk (0x1UL << GINTMSK_EPMISM_Pos) // 0x00020000
+#define GINTMSK_EPMISM GINTMSK_EPMISM_Msk // Endpoint mismatch interrupt mask
+#define GINTMSK_IEPINT_Pos (18U)
+#define GINTMSK_IEPINT_Msk (0x1UL << GINTMSK_IEPINT_Pos) // 0x00040000
+#define GINTMSK_IEPINT GINTMSK_IEPINT_Msk // IN endpoints interrupt mask
+#define GINTMSK_OEPINT_Pos (19U)
+#define GINTMSK_OEPINT_Msk (0x1UL << GINTMSK_OEPINT_Pos) // 0x00080000
+#define GINTMSK_OEPINT GINTMSK_OEPINT_Msk // OUT endpoints interrupt mask
+#define GINTMSK_IISOIXFRM_Pos (20U)
+#define GINTMSK_IISOIXFRM_Msk (0x1UL << GINTMSK_IISOIXFRM_Pos) // 0x00100000
+#define GINTMSK_IISOIXFRM GINTMSK_IISOIXFRM_Msk // Incomplete isochronous IN transfer mask
+#define GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) // 0x00200000
+#define GINTMSK_PXFRM_IISOOXFRM GINTMSK_PXFRM_IISOOXFRM_Msk // Incomplete periodic transfer mask
+#define GINTMSK_FSUSPM_Pos (22U)
+#define GINTMSK_FSUSPM_Msk (0x1UL << GINTMSK_FSUSPM_Pos) // 0x00400000
+#define GINTMSK_FSUSPM GINTMSK_FSUSPM_Msk // Data fetch suspended mask
+#define GINTMSK_RSTDEM_Pos (23U)
+#define GINTMSK_RSTDEM_Msk (0x1UL << GINTMSK_RSTDEM_Pos) // 0x00800000
+#define GINTMSK_RSTDEM GINTMSK_RSTDEM_Msk // Reset detected interrupt mask
+#define GINTMSK_PRTIM_Pos (24U)
+#define GINTMSK_PRTIM_Msk (0x1UL << GINTMSK_PRTIM_Pos) // 0x01000000
+#define GINTMSK_PRTIM GINTMSK_PRTIM_Msk // Host port interrupt mask
+#define GINTMSK_HCIM_Pos (25U)
+#define GINTMSK_HCIM_Msk (0x1UL << GINTMSK_HCIM_Pos) // 0x02000000
+#define GINTMSK_HCIM GINTMSK_HCIM_Msk // Host channels interrupt mask
+#define GINTMSK_PTXFEM_Pos (26U)
+#define GINTMSK_PTXFEM_Msk (0x1UL << GINTMSK_PTXFEM_Pos) // 0x04000000
+#define GINTMSK_PTXFEM GINTMSK_PTXFEM_Msk // Periodic TxFIFO empty mask
+#define GINTMSK_LPMINTM_Pos (27U)
+#define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) // 0x08000000
+#define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk // LPM interrupt Mask
+#define GINTMSK_CIDSCHGM_Pos (28U)
+#define GINTMSK_CIDSCHGM_Msk (0x1UL << GINTMSK_CIDSCHGM_Pos) // 0x10000000
+#define GINTMSK_CIDSCHGM GINTMSK_CIDSCHGM_Msk // Connector ID status change mask
+#define GINTMSK_DISCINT_Pos (29U)
+#define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) // 0x20000000
+#define GINTMSK_DISCINT GINTMSK_DISCINT_Msk // Disconnect detected interrupt mask
+#define GINTMSK_SRQIM_Pos (30U)
+#define GINTMSK_SRQIM_Msk (0x1UL << GINTMSK_SRQIM_Pos) // 0x40000000
+#define GINTMSK_SRQIM GINTMSK_SRQIM_Msk // Session request/new session detected interrupt mask
+#define GINTMSK_WUIM_Pos (31U)
+#define GINTMSK_WUIM_Msk (0x1UL << GINTMSK_WUIM_Pos) // 0x80000000
+#define GINTMSK_WUIM GINTMSK_WUIM_Msk // Resume/remote wakeup detected interrupt mask
+
+/******************** Bit definition for DAINT register ********************/
+#define DAINT_IEPINT_Pos (0U)
+#define DAINT_IEPINT_Msk (0xFFFFUL << DAINT_IEPINT_Pos) // 0x0000FFFF
+#define DAINT_IEPINT DAINT_IEPINT_Msk // IN endpoint interrupt bits
+#define DAINT_OEPINT_Pos (16U)
+#define DAINT_OEPINT_Msk (0xFFFFUL << DAINT_OEPINT_Pos) // 0xFFFF0000
+#define DAINT_OEPINT DAINT_OEPINT_Msk // OUT endpoint interrupt bits
+
+/******************** Bit definition for HAINTMSK register ********************/
+#define HAINTMSK_HAINTM_Pos (0U)
+#define HAINTMSK_HAINTM_Msk (0xFFFFUL << HAINTMSK_HAINTM_Pos) // 0x0000FFFF
+#define HAINTMSK_HAINTM HAINTMSK_HAINTM_Msk // Channel interrupt mask
+
+/******************** Bit definition for GRXSTSP register ********************/
+#define GRXSTSP_EPNUM_Pos (0U)
+#define GRXSTSP_EPNUM_Msk (0xFUL << GRXSTSP_EPNUM_Pos) // 0x0000000F
+#define GRXSTSP_EPNUM GRXSTSP_EPNUM_Msk // IN EP interrupt mask bits
+#define GRXSTSP_BCNT_Pos (4U)
+#define GRXSTSP_BCNT_Msk (0x7FFUL << GRXSTSP_BCNT_Pos) // 0x00007FF0
+#define GRXSTSP_BCNT GRXSTSP_BCNT_Msk // OUT EP interrupt mask bits
+#define GRXSTSP_DPID_Pos (15U)
+#define GRXSTSP_DPID_Msk (0x3UL << GRXSTSP_DPID_Pos) // 0x00018000
+#define GRXSTSP_DPID GRXSTSP_DPID_Msk // OUT EP interrupt mask bits
+#define GRXSTSP_PKTSTS_Pos (17U)
+#define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) // 0x001E0000
+#define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk // OUT EP interrupt mask bits
+
+#define GRXSTS_PKTSTS_GLOBALOUTNAK 1
+#define GRXSTS_PKTSTS_OUTRX 2
+#define GRXSTS_PKTSTS_HCHIN 2
+#define GRXSTS_PKTSTS_OUTDONE 3
+#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
+#define GRXSTS_PKTSTS_SETUPDONE 4
+#define GRXSTS_PKTSTS_DATATOGGLEERR 5
+#define GRXSTS_PKTSTS_SETUPRX 6
+#define GRXSTS_PKTSTS_HCHHALTED 7
+
+
+/******************** Bit definition for DAINTMSK register ********************/
+#define DAINTMSK_IEPM_Pos (0U)
+#define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) // 0x0000FFFF
+#define DAINTMSK_IEPM DAINTMSK_IEPM_Msk // IN EP interrupt mask bits
+#define DAINTMSK_OEPM_Pos (16U)
+#define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) // 0xFFFF0000
+#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk // OUT EP interrupt mask bits
+
+#if 0
+/******************** Bit definition for OTG register ********************/
+#define CHNUM_Pos (0U)
+#define CHNUM_Msk (0xFUL << CHNUM_Pos) // 0x0000000F
+#define CHNUM CHNUM_Msk // Channel number
+#define CHNUM_0 (0x1UL << CHNUM_Pos) // 0x00000001
+#define CHNUM_1 (0x2UL << CHNUM_Pos) // 0x00000002
+#define CHNUM_2 (0x4UL << CHNUM_Pos) // 0x00000004
+#define CHNUM_3 (0x8UL << CHNUM_Pos) // 0x00000008
+#define BCNT_Pos (4U)
+#define BCNT_Msk (0x7FFUL << BCNT_Pos) // 0x00007FF0
+#define BCNT BCNT_Msk // Byte count
+
+#define DPID_Pos (15U)
+#define DPID_Msk (0x3UL << DPID_Pos) // 0x00018000
+#define DPID DPID_Msk // Data PID
+#define DPID_0 (0x1UL << DPID_Pos) // 0x00008000
+#define DPID_1 (0x2UL << DPID_Pos) // 0x00010000
+
+#define PKTSTS_Pos (17U)
+#define PKTSTS_Msk (0xFUL << PKTSTS_Pos) // 0x001E0000
+#define PKTSTS PKTSTS_Msk // Packet status
+#define PKTSTS_0 (0x1UL << PKTSTS_Pos) // 0x00020000
+#define PKTSTS_1 (0x2UL << PKTSTS_Pos) // 0x00040000
+#define PKTSTS_2 (0x4UL << PKTSTS_Pos) // 0x00080000
+#define PKTSTS_3 (0x8UL << PKTSTS_Pos) // 0x00100000
+
+#define EPNUM_Pos (0U)
+#define EPNUM_Msk (0xFUL << EPNUM_Pos) // 0x0000000F
+#define EPNUM EPNUM_Msk // Endpoint number
+#define EPNUM_0 (0x1UL << EPNUM_Pos) // 0x00000001
+#define EPNUM_1 (0x2UL << EPNUM_Pos) // 0x00000002
+#define EPNUM_2 (0x4UL << EPNUM_Pos) // 0x00000004
+#define EPNUM_3 (0x8UL << EPNUM_Pos) // 0x00000008
+
+#define FRMNUM_Pos (21U)
+#define FRMNUM_Msk (0xFUL << FRMNUM_Pos) // 0x01E00000
+#define FRMNUM FRMNUM_Msk // Frame number
+#define FRMNUM_0 (0x1UL << FRMNUM_Pos) // 0x00200000
+#define FRMNUM_1 (0x2UL << FRMNUM_Pos) // 0x00400000
+#define FRMNUM_2 (0x4UL << FRMNUM_Pos) // 0x00800000
+#define FRMNUM_3 (0x8UL << FRMNUM_Pos) // 0x01000000
+#endif
+
+/******************** Bit definition for GRXFSIZ register ********************/
+#define GRXFSIZ_RXFD_Pos (0U)
+#define GRXFSIZ_RXFD_Msk (0xFFFFUL << GRXFSIZ_RXFD_Pos) // 0x0000FFFF
+#define GRXFSIZ_RXFD GRXFSIZ_RXFD_Msk // RxFIFO depth
+
+/******************** Bit definition for DVBUSDIS register ********************/
+#define DVBUSDIS_VBUSDT_Pos (0U)
+#define DVBUSDIS_VBUSDT_Msk (0xFFFFUL << DVBUSDIS_VBUSDT_Pos) // 0x0000FFFF
+#define DVBUSDIS_VBUSDT DVBUSDIS_VBUSDT_Msk // Device VBUS discharge time
+
+/******************** Bit definition for OTG register ********************/
+#define GNPTXFSIZ_NPTXFSA_Pos (0U)
+#define GNPTXFSIZ_NPTXFSA_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFSA_Pos) // 0x0000FFFF
+#define GNPTXFSIZ_NPTXFSA GNPTXFSIZ_NPTXFSA_Msk // Nonperiodic transmit RAM start address
+#define GNPTXFSIZ_NPTXFD_Pos (16U)
+#define GNPTXFSIZ_NPTXFD_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFD_Pos) // 0xFFFF0000
+#define GNPTXFSIZ_NPTXFD GNPTXFSIZ_NPTXFD_Msk // Nonperiodic TxFIFO depth
+#define DIEPTXF0_TX0FSA_Pos (0U)
+#define DIEPTXF0_TX0FSA_Msk (0xFFFFUL << DIEPTXF0_TX0FSA_Pos) // 0x0000FFFF
+#define DIEPTXF0_TX0FSA DIEPTXF0_TX0FSA_Msk // Endpoint 0 transmit RAM start address
+#define DIEPTXF0_TX0FD_Pos (16U)
+#define DIEPTXF0_TX0FD_Msk (0xFFFFUL << DIEPTXF0_TX0FD_Pos) // 0xFFFF0000
+#define DIEPTXF0_TX0FD DIEPTXF0_TX0FD_Msk // Endpoint 0 TxFIFO depth
+
+/******************** Bit definition for DVBUSPULSE register ********************/
+#define DVBUSPULSE_DVBUSP_Pos (0U)
+#define DVBUSPULSE_DVBUSP_Msk (0xFFFUL << DVBUSPULSE_DVBUSP_Pos) // 0x00000FFF
+#define DVBUSPULSE_DVBUSP DVBUSPULSE_DVBUSP_Msk // Device VBUS pulsing time
+
+/******************** Bit definition for GNPTXSTS register ********************/
+#define GNPTXSTS_NPTXFSAV_Pos (0U)
+#define GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos) // 0x0000FFFF
+#define GNPTXSTS_NPTXFSAV GNPTXSTS_NPTXFSAV_Msk // Nonperiodic TxFIFO space available
+
+#define GNPTXSTS_NPTQXSAV_Pos (16U)
+#define GNPTXSTS_NPTQXSAV_Msk (0xFFUL << GNPTXSTS_NPTQXSAV_Pos) // 0x00FF0000
+#define GNPTXSTS_NPTQXSAV GNPTXSTS_NPTQXSAV_Msk // Nonperiodic transmit request queue space available
+#define GNPTXSTS_NPTQXSAV_0 (0x01UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00010000
+#define GNPTXSTS_NPTQXSAV_1 (0x02UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00020000
+#define GNPTXSTS_NPTQXSAV_2 (0x04UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00040000
+#define GNPTXSTS_NPTQXSAV_3 (0x08UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00080000
+#define GNPTXSTS_NPTQXSAV_4 (0x10UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00100000
+#define GNPTXSTS_NPTQXSAV_5 (0x20UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00200000
+#define GNPTXSTS_NPTQXSAV_6 (0x40UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00400000
+#define GNPTXSTS_NPTQXSAV_7 (0x80UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00800000
+
+#define GNPTXSTS_NPTXQTOP_Pos (24U)
+#define GNPTXSTS_NPTXQTOP_Msk (0x7FUL << GNPTXSTS_NPTXQTOP_Pos) // 0x7F000000
+#define GNPTXSTS_NPTXQTOP GNPTXSTS_NPTXQTOP_Msk // Top of the nonperiodic transmit request queue
+#define GNPTXSTS_NPTXQTOP_0 (0x01UL << GNPTXSTS_NPTXQTOP_Pos) // 0x01000000
+#define GNPTXSTS_NPTXQTOP_1 (0x02UL << GNPTXSTS_NPTXQTOP_Pos) // 0x02000000
+#define GNPTXSTS_NPTXQTOP_2 (0x04UL << GNPTXSTS_NPTXQTOP_Pos) // 0x04000000
+#define GNPTXSTS_NPTXQTOP_3 (0x08UL << GNPTXSTS_NPTXQTOP_Pos) // 0x08000000
+#define GNPTXSTS_NPTXQTOP_4 (0x10UL << GNPTXSTS_NPTXQTOP_Pos) // 0x10000000
+#define GNPTXSTS_NPTXQTOP_5 (0x20UL << GNPTXSTS_NPTXQTOP_Pos) // 0x20000000
+#define GNPTXSTS_NPTXQTOP_6 (0x40UL << GNPTXSTS_NPTXQTOP_Pos) // 0x40000000
+
+/******************** Bit definition for DTHRCTL register ********************/
+#define DTHRCTL_NONISOTHREN_Pos (0U)
+#define DTHRCTL_NONISOTHREN_Msk (0x1UL << DTHRCTL_NONISOTHREN_Pos) // 0x00000001
+#define DTHRCTL_NONISOTHREN DTHRCTL_NONISOTHREN_Msk // Nonisochronous IN endpoints threshold enable
+#define DTHRCTL_ISOTHREN_Pos (1U)
+#define DTHRCTL_ISOTHREN_Msk (0x1UL << DTHRCTL_ISOTHREN_Pos) // 0x00000002
+#define DTHRCTL_ISOTHREN DTHRCTL_ISOTHREN_Msk // ISO IN endpoint threshold enable
+
+#define DTHRCTL_TXTHRLEN_Pos (2U)
+#define DTHRCTL_TXTHRLEN_Msk (0x1FFUL << DTHRCTL_TXTHRLEN_Pos) // 0x000007FC
+#define DTHRCTL_TXTHRLEN DTHRCTL_TXTHRLEN_Msk // Transmit threshold length
+#define DTHRCTL_TXTHRLEN_0 (0x001UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000004
+#define DTHRCTL_TXTHRLEN_1 (0x002UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000008
+#define DTHRCTL_TXTHRLEN_2 (0x004UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000010
+#define DTHRCTL_TXTHRLEN_3 (0x008UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000020
+#define DTHRCTL_TXTHRLEN_4 (0x010UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000040
+#define DTHRCTL_TXTHRLEN_5 (0x020UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000080
+#define DTHRCTL_TXTHRLEN_6 (0x040UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000100
+#define DTHRCTL_TXTHRLEN_7 (0x080UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000200
+#define DTHRCTL_TXTHRLEN_8 (0x100UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000400
+#define DTHRCTL_RXTHREN_Pos (16U)
+#define DTHRCTL_RXTHREN_Msk (0x1UL << DTHRCTL_RXTHREN_Pos) // 0x00010000
+#define DTHRCTL_RXTHREN DTHRCTL_RXTHREN_Msk // Receive threshold enable
+
+#define DTHRCTL_RXTHRLEN_Pos (17U)
+#define DTHRCTL_RXTHRLEN_Msk (0x1FFUL << DTHRCTL_RXTHRLEN_Pos) // 0x03FE0000
+#define DTHRCTL_RXTHRLEN DTHRCTL_RXTHRLEN_Msk // Receive threshold length
+#define DTHRCTL_RXTHRLEN_0 (0x001UL << DTHRCTL_RXTHRLEN_Pos) // 0x00020000
+#define DTHRCTL_RXTHRLEN_1 (0x002UL << DTHRCTL_RXTHRLEN_Pos) // 0x00040000
+#define DTHRCTL_RXTHRLEN_2 (0x004UL << DTHRCTL_RXTHRLEN_Pos) // 0x00080000
+#define DTHRCTL_RXTHRLEN_3 (0x008UL << DTHRCTL_RXTHRLEN_Pos) // 0x00100000
+#define DTHRCTL_RXTHRLEN_4 (0x010UL << DTHRCTL_RXTHRLEN_Pos) // 0x00200000
+#define DTHRCTL_RXTHRLEN_5 (0x020UL << DTHRCTL_RXTHRLEN_Pos) // 0x00400000
+#define DTHRCTL_RXTHRLEN_6 (0x040UL << DTHRCTL_RXTHRLEN_Pos) // 0x00800000
+#define DTHRCTL_RXTHRLEN_7 (0x080UL << DTHRCTL_RXTHRLEN_Pos) // 0x01000000
+#define DTHRCTL_RXTHRLEN_8 (0x100UL << DTHRCTL_RXTHRLEN_Pos) // 0x02000000
+#define DTHRCTL_ARPEN_Pos (27U)
+#define DTHRCTL_ARPEN_Msk (0x1UL << DTHRCTL_ARPEN_Pos) // 0x08000000
+#define DTHRCTL_ARPEN DTHRCTL_ARPEN_Msk // Arbiter parking enable
+
+/******************** Bit definition for DIEPEMPMSK register ********************/
+#define DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos) // 0x0000FFFF
+#define DIEPEMPMSK_INEPTXFEM DIEPEMPMSK_INEPTXFEM_Msk // IN EP Tx FIFO empty interrupt mask bits
+
+/******************** Bit definition for DEACHINT register ********************/
+#define DEACHINT_IEP1INT_Pos (1U)
+#define DEACHINT_IEP1INT_Msk (0x1UL << DEACHINT_IEP1INT_Pos) // 0x00000002
+#define DEACHINT_IEP1INT DEACHINT_IEP1INT_Msk // IN endpoint 1interrupt bit
+#define DEACHINT_OEP1INT_Pos (17U)
+#define DEACHINT_OEP1INT_Msk (0x1UL << DEACHINT_OEP1INT_Pos) // 0x00020000
+#define DEACHINT_OEP1INT DEACHINT_OEP1INT_Msk // OUT endpoint 1 interrupt bit
+
+/******************** Bit definition for GCCFG register ********************/
+#define STM32_GCCFG_DCDET_Pos (0U)
+#define STM32_GCCFG_DCDET_Msk (0x1UL << STM32_GCCFG_DCDET_Pos) // 0x00000001
+#define STM32_GCCFG_DCDET STM32_GCCFG_DCDET_Msk // Data contact detection (DCD) status
+
+#define STM32_GCCFG_PDET_Pos (1U)
+#define STM32_GCCFG_PDET_Msk (0x1UL << STM32_GCCFG_PDET_Pos) // 0x00000002
+#define STM32_GCCFG_PDET STM32_GCCFG_PDET_Msk // Primary detection (PD) status
+
+#define STM32_GCCFG_SDET_Pos (2U)
+#define STM32_GCCFG_SDET_Msk (0x1UL << STM32_GCCFG_SDET_Pos) // 0x00000004
+#define STM32_GCCFG_SDET STM32_GCCFG_SDET_Msk // Secondary detection (SD) status
+
+#define STM32_GCCFG_PS2DET_Pos (3U)
+#define STM32_GCCFG_PS2DET_Msk (0x1UL << STM32_GCCFG_PS2DET_Pos) // 0x00000008
+#define STM32_GCCFG_PS2DET STM32_GCCFG_PS2DET_Msk // DM pull-up detection status
+
+#define STM32_GCCFG_PWRDWN_Pos (16U)
+#define STM32_GCCFG_PWRDWN_Msk (0x1UL << STM32_GCCFG_PWRDWN_Pos) // 0x00010000
+#define STM32_GCCFG_PWRDWN STM32_GCCFG_PWRDWN_Msk // Power down
+
+#define STM32_GCCFG_BCDEN_Pos (17U)
+#define STM32_GCCFG_BCDEN_Msk (0x1UL << STM32_GCCFG_BCDEN_Pos) // 0x00020000
+#define STM32_GCCFG_BCDEN STM32_GCCFG_BCDEN_Msk // Battery charging detector (BCD) enable
+
+#define STM32_GCCFG_DCDEN_Pos (18U)
+#define STM32_GCCFG_DCDEN_Msk (0x1UL << STM32_GCCFG_DCDEN_Pos) // 0x00040000
+#define STM32_GCCFG_DCDEN STM32_GCCFG_DCDEN_Msk // Data contact detection (DCD) mode enable*/
+
+#define STM32_GCCFG_PDEN_Pos (19U)
+#define STM32_GCCFG_PDEN_Msk (0x1UL << STM32_GCCFG_PDEN_Pos) // 0x00080000
+#define STM32_GCCFG_PDEN STM32_GCCFG_PDEN_Msk // Primary detection (PD) mode enable*/
+
+#define STM32_GCCFG_SDEN_Pos (20U)
+#define STM32_GCCFG_SDEN_Msk (0x1UL << STM32_GCCFG_SDEN_Pos) // 0x00100000
+#define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (SD) mode enable
+
+#define STM32_GCCFG_VBDEN_Pos (21U)
+#define STM32_GCCFG_VBDEN_Msk (0x1UL << STM32_GCCFG_VBDEN_Pos) // 0x00200000
+#define STM32_GCCFG_VBDEN STM32_GCCFG_VBDEN_Msk // VBUS mode enable
+
+#define STM32_GCCFG_OTGIDEN_Pos (22U)
+#define STM32_GCCFG_OTGIDEN_Msk (0x1UL << STM32_GCCFG_OTGIDEN_Pos) // 0x00400000
+#define STM32_GCCFG_OTGIDEN STM32_GCCFG_OTGIDEN_Msk // OTG Id enable
+
+#define STM32_GCCFG_PHYHSEN_Pos (23U)
+#define STM32_GCCFG_PHYHSEN_Msk (0x1UL << STM32_GCCFG_PHYHSEN_Pos) // 0x00800000
+#define STM32_GCCFG_PHYHSEN STM32_GCCFG_PHYHSEN_Msk // HS PHY enable
+
+// TODO stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
+//#define STM32_GCCFG_SDEN_Pos (22U)
+//#define STM32_GCCFG_SDEN_Msk (0x1U << STM32_GCCFG_SDEN_Pos) // 0x00400000
+//#define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (PD) mode enable
+
+// TODO stm32u5a5 VBVALOVA is 23rd bit, conflict with PHYHSEN bit above
+#define STM32_GCCFG_VBVALOVAL_Pos (23U)
+#define STM32_GCCFG_VBVALOVAL_Msk (0x1U << STM32_GCCFG_VBVALOVAL_Pos) // 0x00800000
+#define STM32_GCCFG_VBVALOVAL STM32_GCCFG_VBVALOVAL_Msk // Value of VBUSVLDEXT0 femtoPHY input
+
+#define STM32_GCCFG_VBVALEXTOEN_Pos (24U)
+#define STM32_GCCFG_VBVALEXTOEN_Msk (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos) // 0x01000000
+#define STM32_GCCFG_VBVALEXTOEN STM32_GCCFG_VBVALEXTOEN_Msk // Enables of VBUSVLDEXT0 femtoPHY input override
+
+#define STM32_GCCFG_PULLDOWNEN_Pos (25U)
+#define STM32_GCCFG_PULLDOWNEN_Msk (0x1U << STM32_GCCFG_PULLDOWNEN_Pos) // 0x02000000
+#define STM32_GCCFG_PULLDOWNEN STM32_GCCFG_PULLDOWNEN_Msk // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
+
+
+/******************** Bit definition for DEACHINTMSK register ********************/
+#define DEACHINTMSK_IEP1INTM_Pos (1U)
+#define DEACHINTMSK_IEP1INTM_Msk (0x1UL << DEACHINTMSK_IEP1INTM_Pos) // 0x00000002
+#define DEACHINTMSK_IEP1INTM DEACHINTMSK_IEP1INTM_Msk // IN Endpoint 1 interrupt mask bit
+#define DEACHINTMSK_OEP1INTM_Pos (17U)
+#define DEACHINTMSK_OEP1INTM_Msk (0x1UL << DEACHINTMSK_OEP1INTM_Pos) // 0x00020000
+#define DEACHINTMSK_OEP1INTM DEACHINTMSK_OEP1INTM_Msk // OUT Endpoint 1 interrupt mask bit
+
+/******************** Bit definition for CID register ********************/
+#define CID_PRODUCT_ID_Pos (0U)
+#define CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos) // 0xFFFFFFFF
+#define CID_PRODUCT_ID CID_PRODUCT_ID_Msk // Product ID field
+
+/******************** Bit definition for GLPMCFG register ********************/
+#define GLPMCFG_LPMEN_Pos (0U)
+#define GLPMCFG_LPMEN_Msk (0x1UL << GLPMCFG_LPMEN_Pos) // 0x00000001
+#define GLPMCFG_LPMEN GLPMCFG_LPMEN_Msk // LPM support enable
+#define GLPMCFG_LPMACK_Pos (1U)
+#define GLPMCFG_LPMACK_Msk (0x1UL << GLPMCFG_LPMACK_Pos) // 0x00000002
+#define GLPMCFG_LPMACK GLPMCFG_LPMACK_Msk // LPM Token acknowledge enable
+#define GLPMCFG_BESL_Pos (2U)
+#define GLPMCFG_BESL_Msk (0xFUL << GLPMCFG_BESL_Pos) // 0x0000003C
+#define GLPMCFG_BESL GLPMCFG_BESL_Msk // BESL value received with last ACKed LPM Token
+#define GLPMCFG_REMWAKE_Pos (6U)
+#define GLPMCFG_REMWAKE_Msk (0x1UL << GLPMCFG_REMWAKE_Pos) // 0x00000040
+#define GLPMCFG_REMWAKE GLPMCFG_REMWAKE_Msk // bRemoteWake value received with last ACKed LPM Token
+#define GLPMCFG_L1SSEN_Pos (7U)
+#define GLPMCFG_L1SSEN_Msk (0x1UL << GLPMCFG_L1SSEN_Pos) // 0x00000080
+#define GLPMCFG_L1SSEN GLPMCFG_L1SSEN_Msk // L1 shallow sleep enable
+#define GLPMCFG_BESLTHRS_Pos (8U)
+#define GLPMCFG_BESLTHRS_Msk (0xFUL << GLPMCFG_BESLTHRS_Pos) // 0x00000F00
+#define GLPMCFG_BESLTHRS GLPMCFG_BESLTHRS_Msk // BESL threshold
+#define GLPMCFG_L1DSEN_Pos (12U)
+#define GLPMCFG_L1DSEN_Msk (0x1UL << GLPMCFG_L1DSEN_Pos) // 0x00001000
+#define GLPMCFG_L1DSEN GLPMCFG_L1DSEN_Msk // L1 deep sleep enable
+#define GLPMCFG_LPMRSP_Pos (13U)
+#define GLPMCFG_LPMRSP_Msk (0x3UL << GLPMCFG_LPMRSP_Pos) // 0x00006000
+#define GLPMCFG_LPMRSP GLPMCFG_LPMRSP_Msk // LPM response
+#define GLPMCFG_SLPSTS_Pos (15U)
+#define GLPMCFG_SLPSTS_Msk (0x1UL << GLPMCFG_SLPSTS_Pos) // 0x00008000
+#define GLPMCFG_SLPSTS GLPMCFG_SLPSTS_Msk // Port sleep status
+#define GLPMCFG_L1RSMOK_Pos (16U)
+#define GLPMCFG_L1RSMOK_Msk (0x1UL << GLPMCFG_L1RSMOK_Pos) // 0x00010000
+#define GLPMCFG_L1RSMOK GLPMCFG_L1RSMOK_Msk // Sleep State Resume OK
+#define GLPMCFG_LPMCHIDX_Pos (17U)
+#define GLPMCFG_LPMCHIDX_Msk (0xFUL << GLPMCFG_LPMCHIDX_Pos) // 0x001E0000
+#define GLPMCFG_LPMCHIDX GLPMCFG_LPMCHIDX_Msk // LPM Channel Index
+#define GLPMCFG_LPMRCNT_Pos (21U)
+#define GLPMCFG_LPMRCNT_Msk (0x7UL << GLPMCFG_LPMRCNT_Pos) // 0x00E00000
+#define GLPMCFG_LPMRCNT GLPMCFG_LPMRCNT_Msk // LPM retry count
+#define GLPMCFG_SNDLPM_Pos (24U)
+#define GLPMCFG_SNDLPM_Msk (0x1UL << GLPMCFG_SNDLPM_Pos) // 0x01000000
+#define GLPMCFG_SNDLPM GLPMCFG_SNDLPM_Msk // Send LPM transaction
+#define GLPMCFG_LPMRCNTSTS_Pos (25U)
+#define GLPMCFG_LPMRCNTSTS_Msk (0x7UL << GLPMCFG_LPMRCNTSTS_Pos) // 0x0E000000
+#define GLPMCFG_LPMRCNTSTS GLPMCFG_LPMRCNTSTS_Msk // LPM retry count status
+#define GLPMCFG_ENBESL_Pos (28U)
+#define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) // 0x10000000
+#define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk // Enable best effort service latency
+
+/******************** Bit definition for DIEPEACHMSK1 register ********************/
+#define DIEPEACHMSK1_XFRCM_Pos (0U)
+#define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) // 0x00000001
+#define DIEPEACHMSK1_XFRCM DIEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask
+#define DIEPEACHMSK1_EPDM_Pos (1U)
+#define DIEPEACHMSK1_EPDM_Msk (0x1UL << DIEPEACHMSK1_EPDM_Pos) // 0x00000002
+#define DIEPEACHMSK1_EPDM DIEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask
+#define DIEPEACHMSK1_TOM_Pos (3U)
+#define DIEPEACHMSK1_TOM_Msk (0x1UL << DIEPEACHMSK1_TOM_Pos) // 0x00000008
+#define DIEPEACHMSK1_TOM DIEPEACHMSK1_TOM_Msk // Timeout condition mask (nonisochronous endpoints)
+#define DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010
+#define DIEPEACHMSK1_ITTXFEMSK DIEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask
+#define DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define DIEPEACHMSK1_INEPNMM_Msk (0x1UL << DIEPEACHMSK1_INEPNMM_Pos) // 0x00000020
+#define DIEPEACHMSK1_INEPNMM DIEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask
+#define DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define DIEPEACHMSK1_INEPNEM_Msk (0x1UL << DIEPEACHMSK1_INEPNEM_Pos) // 0x00000040
+#define DIEPEACHMSK1_INEPNEM DIEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask
+#define DIEPEACHMSK1_TXFURM_Pos (8U)
+#define DIEPEACHMSK1_TXFURM_Msk (0x1UL << DIEPEACHMSK1_TXFURM_Pos) // 0x00000100
+#define DIEPEACHMSK1_TXFURM DIEPEACHMSK1_TXFURM_Msk // FIFO underrun mask
+#define DIEPEACHMSK1_BIM_Pos (9U)
+#define DIEPEACHMSK1_BIM_Msk (0x1UL << DIEPEACHMSK1_BIM_Pos) // 0x00000200
+#define DIEPEACHMSK1_BIM DIEPEACHMSK1_BIM_Msk // BNA interrupt mask
+#define DIEPEACHMSK1_NAKM_Pos (13U)
+#define DIEPEACHMSK1_NAKM_Msk (0x1UL << DIEPEACHMSK1_NAKM_Pos) // 0x00002000
+#define DIEPEACHMSK1_NAKM DIEPEACHMSK1_NAKM_Msk // NAK interrupt mask
+
+/******************** Bit definition for HPRT register ********************/
+#define HPRT_PCSTS_Pos (0U)
+#define HPRT_PCSTS_Msk (0x1UL << HPRT_PCSTS_Pos) // 0x00000001
+#define HPRT_PCSTS HPRT_PCSTS_Msk // Port connect status
+#define HPRT_PCDET_Pos (1U)
+#define HPRT_PCDET_Msk (0x1UL << HPRT_PCDET_Pos) // 0x00000002
+#define HPRT_PCDET HPRT_PCDET_Msk // Port connect detected
+#define HPRT_PENA_Pos (2U)
+#define HPRT_PENA_Msk (0x1UL << HPRT_PENA_Pos) // 0x00000004
+#define HPRT_PENA HPRT_PENA_Msk // Port enable
+#define HPRT_PENCHNG_Pos (3U)
+#define HPRT_PENCHNG_Msk (0x1UL << HPRT_PENCHNG_Pos) // 0x00000008
+#define HPRT_PENCHNG HPRT_PENCHNG_Msk // Port enable/disable change
+#define HPRT_POCA_Pos (4U)
+#define HPRT_POCA_Msk (0x1UL << HPRT_POCA_Pos) // 0x00000010
+#define HPRT_POCA HPRT_POCA_Msk // Port overcurrent active
+#define HPRT_POCCHNG_Pos (5U)
+#define HPRT_POCCHNG_Msk (0x1UL << HPRT_POCCHNG_Pos) // 0x00000020
+#define HPRT_POCCHNG HPRT_POCCHNG_Msk // Port overcurrent change
+#define HPRT_PRES_Pos (6U)
+#define HPRT_PRES_Msk (0x1UL << HPRT_PRES_Pos) // 0x00000040
+#define HPRT_PRES HPRT_PRES_Msk // Port resume
+#define HPRT_PSUSP_Pos (7U)
+#define HPRT_PSUSP_Msk (0x1UL << HPRT_PSUSP_Pos) // 0x00000080
+#define HPRT_PSUSP HPRT_PSUSP_Msk // Port suspend
+#define HPRT_PRST_Pos (8U)
+#define HPRT_PRST_Msk (0x1UL << HPRT_PRST_Pos) // 0x00000100
+#define HPRT_PRST HPRT_PRST_Msk // Port reset
+
+#define HPRT_PLSTS_Pos (10U)
+#define HPRT_PLSTS_Msk (0x3UL << HPRT_PLSTS_Pos) // 0x00000C00
+#define HPRT_PLSTS HPRT_PLSTS_Msk // Port line status
+#define HPRT_PLSTS_0 (0x1UL << HPRT_PLSTS_Pos) // 0x00000400
+#define HPRT_PLSTS_1 (0x2UL << HPRT_PLSTS_Pos) // 0x00000800
+#define HPRT_PPWR_Pos (12U)
+#define HPRT_PPWR_Msk (0x1UL << HPRT_PPWR_Pos) // 0x00001000
+#define HPRT_PPWR HPRT_PPWR_Msk // Port power
+
+#define HPRT_PTCTL_Pos (13U)
+#define HPRT_PTCTL_Msk (0xFUL << HPRT_PTCTL_Pos) // 0x0001E000
+#define HPRT_PTCTL HPRT_PTCTL_Msk // Port test control
+#define HPRT_PTCTL_0 (0x1UL << HPRT_PTCTL_Pos) // 0x00002000
+#define HPRT_PTCTL_1 (0x2UL << HPRT_PTCTL_Pos) // 0x00004000
+#define HPRT_PTCTL_2 (0x4UL << HPRT_PTCTL_Pos) // 0x00008000
+#define HPRT_PTCTL_3 (0x8UL << HPRT_PTCTL_Pos) // 0x00010000
+
+#define HPRT_PSPD_Pos (17U)
+#define HPRT_PSPD_Msk (0x3UL << HPRT_PSPD_Pos) // 0x00060000
+#define HPRT_PSPD HPRT_PSPD_Msk // Port speed
+#define HPRT_PSPD_0 (0x1UL << HPRT_PSPD_Pos) // 0x00020000
+#define HPRT_PSPD_1 (0x2UL << HPRT_PSPD_Pos) // 0x00040000
+
+/******************** Bit definition for DOEPEACHMSK1 register ********************/
+#define DOEPEACHMSK1_XFRCM_Pos (0U)
+#define DOEPEACHMSK1_XFRCM_Msk (0x1UL << DOEPEACHMSK1_XFRCM_Pos) // 0x00000001
+#define DOEPEACHMSK1_XFRCM DOEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask
+#define DOEPEACHMSK1_EPDM_Pos (1U)
+#define DOEPEACHMSK1_EPDM_Msk (0x1UL << DOEPEACHMSK1_EPDM_Pos) // 0x00000002
+#define DOEPEACHMSK1_EPDM DOEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask
+#define DOEPEACHMSK1_TOM_Pos (3U)
+#define DOEPEACHMSK1_TOM_Msk (0x1UL << DOEPEACHMSK1_TOM_Pos) // 0x00000008
+#define DOEPEACHMSK1_TOM DOEPEACHMSK1_TOM_Msk // Timeout condition mask
+#define DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010
+#define DOEPEACHMSK1_ITTXFEMSK DOEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask
+#define DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define DOEPEACHMSK1_INEPNMM_Msk (0x1UL << DOEPEACHMSK1_INEPNMM_Pos) // 0x00000020
+#define DOEPEACHMSK1_INEPNMM DOEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask
+#define DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define DOEPEACHMSK1_INEPNEM_Msk (0x1UL << DOEPEACHMSK1_INEPNEM_Pos) // 0x00000040
+#define DOEPEACHMSK1_INEPNEM DOEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask
+#define DOEPEACHMSK1_TXFURM_Pos (8U)
+#define DOEPEACHMSK1_TXFURM_Msk (0x1UL << DOEPEACHMSK1_TXFURM_Pos) // 0x00000100
+#define DOEPEACHMSK1_TXFURM DOEPEACHMSK1_TXFURM_Msk // OUT packet error mask
+#define DOEPEACHMSK1_BIM_Pos (9U)
+#define DOEPEACHMSK1_BIM_Msk (0x1UL << DOEPEACHMSK1_BIM_Pos) // 0x00000200
+#define DOEPEACHMSK1_BIM DOEPEACHMSK1_BIM_Msk // BNA interrupt mask
+#define DOEPEACHMSK1_BERRM_Pos (12U)
+#define DOEPEACHMSK1_BERRM_Msk (0x1UL << DOEPEACHMSK1_BERRM_Pos) // 0x00001000
+#define DOEPEACHMSK1_BERRM DOEPEACHMSK1_BERRM_Msk // Bubble error interrupt mask
+#define DOEPEACHMSK1_NAKM_Pos (13U)
+#define DOEPEACHMSK1_NAKM_Msk (0x1UL << DOEPEACHMSK1_NAKM_Pos) // 0x00002000
+#define DOEPEACHMSK1_NAKM DOEPEACHMSK1_NAKM_Msk // NAK interrupt mask
+#define DOEPEACHMSK1_NYETM_Pos (14U)
+#define DOEPEACHMSK1_NYETM_Msk (0x1UL << DOEPEACHMSK1_NYETM_Pos) // 0x00004000
+#define DOEPEACHMSK1_NYETM DOEPEACHMSK1_NYETM_Msk // NYET interrupt mask
+
+/******************** Bit definition for HPTXFSIZ register ********************/
+#define HPTXFSIZ_PTXSA_Pos (0U)
+#define HPTXFSIZ_PTXSA_Msk (0xFFFFUL << HPTXFSIZ_PTXSA_Pos) // 0x0000FFFF
+#define HPTXFSIZ_PTXSA HPTXFSIZ_PTXSA_Msk // Host periodic TxFIFO start address
+#define HPTXFSIZ_PTXFD_Pos (16U)
+#define HPTXFSIZ_PTXFD_Msk (0xFFFFUL << HPTXFSIZ_PTXFD_Pos) // 0xFFFF0000
+#define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk // Host periodic TxFIFO depth
+
+/******************** Bit definition for DIEPCTL register ********************/
+#define DIEPCTL_MPSIZ_Pos (0U)
+#define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) // 0x000007FF
+#define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk // Maximum packet size
+#define DIEPCTL_USBAEP_Pos (15U)
+#define DIEPCTL_USBAEP_Msk (0x1UL << DIEPCTL_USBAEP_Pos) // 0x00008000
+#define DIEPCTL_USBAEP DIEPCTL_USBAEP_Msk // USB active endpoint
+#define DIEPCTL_EONUM_DPID_Pos (16U)
+#define DIEPCTL_EONUM_DPID_Msk (0x1UL << DIEPCTL_EONUM_DPID_Pos) // 0x00010000
+#define DIEPCTL_EONUM_DPID DIEPCTL_EONUM_DPID_Msk // Even/odd frame
+#define DIEPCTL_NAKSTS_Pos (17U)
+#define DIEPCTL_NAKSTS_Msk (0x1UL << DIEPCTL_NAKSTS_Pos) // 0x00020000
+#define DIEPCTL_NAKSTS DIEPCTL_NAKSTS_Msk // NAK status
+
+#define DIEPCTL_EPTYP_Pos (18U)
+#define DIEPCTL_EPTYP_Msk (0x3UL << DIEPCTL_EPTYP_Pos) // 0x000C0000
+#define DIEPCTL_EPTYP DIEPCTL_EPTYP_Msk // Endpoint type
+#define DIEPCTL_EPTYP_0 (0x1UL << DIEPCTL_EPTYP_Pos) // 0x00040000
+#define DIEPCTL_EPTYP_1 (0x2UL << DIEPCTL_EPTYP_Pos) // 0x00080000
+#define DIEPCTL_STALL_Pos (21U)
+#define DIEPCTL_STALL_Msk (0x1UL << DIEPCTL_STALL_Pos) // 0x00200000
+#define DIEPCTL_STALL DIEPCTL_STALL_Msk // STALL handshake
+
+#define DIEPCTL_TXFNUM_Pos (22U)
+#define DIEPCTL_TXFNUM_Msk (0xFUL << DIEPCTL_TXFNUM_Pos) // 0x03C00000
+#define DIEPCTL_TXFNUM DIEPCTL_TXFNUM_Msk // TxFIFO number
+#define DIEPCTL_TXFNUM_0 (0x1UL << DIEPCTL_TXFNUM_Pos) // 0x00400000
+#define DIEPCTL_TXFNUM_1 (0x2UL << DIEPCTL_TXFNUM_Pos) // 0x00800000
+#define DIEPCTL_TXFNUM_2 (0x4UL << DIEPCTL_TXFNUM_Pos) // 0x01000000
+#define DIEPCTL_TXFNUM_3 (0x8UL << DIEPCTL_TXFNUM_Pos) // 0x02000000
+#define DIEPCTL_CNAK_Pos (26U)
+#define DIEPCTL_CNAK_Msk (0x1UL << DIEPCTL_CNAK_Pos) // 0x04000000
+#define DIEPCTL_CNAK DIEPCTL_CNAK_Msk // Clear NAK
+#define DIEPCTL_SNAK_Pos (27U)
+#define DIEPCTL_SNAK_Msk (0x1UL << DIEPCTL_SNAK_Pos) // 0x08000000
+#define DIEPCTL_SNAK DIEPCTL_SNAK_Msk // Set NAK
+#define DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000
+#define DIEPCTL_SD0PID_SEVNFRM DIEPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID
+#define DIEPCTL_SODDFRM_Pos (29U)
+#define DIEPCTL_SODDFRM_Msk (0x1UL << DIEPCTL_SODDFRM_Pos) // 0x20000000
+#define DIEPCTL_SODDFRM DIEPCTL_SODDFRM_Msk // Set odd frame
+#define DIEPCTL_EPDIS_Pos (30U)
+#define DIEPCTL_EPDIS_Msk (0x1UL << DIEPCTL_EPDIS_Pos) // 0x40000000
+#define DIEPCTL_EPDIS DIEPCTL_EPDIS_Msk // Endpoint disable
+#define DIEPCTL_EPENA_Pos (31U)
+#define DIEPCTL_EPENA_Msk (0x1UL << DIEPCTL_EPENA_Pos) // 0x80000000
+#define DIEPCTL_EPENA DIEPCTL_EPENA_Msk // Endpoint enable
+
+/******************** Bit definition for HCCHAR register ********************/
+#define HCCHAR_MPSIZ_Pos (0U)
+#define HCCHAR_MPSIZ_Msk (0x7FFUL << HCCHAR_MPSIZ_Pos) // 0x000007FF
+#define HCCHAR_MPSIZ HCCHAR_MPSIZ_Msk // Maximum packet size
+
+#define HCCHAR_EPNUM_Pos (11U)
+#define HCCHAR_EPNUM_Msk (0xFUL << HCCHAR_EPNUM_Pos) // 0x00007800
+#define HCCHAR_EPNUM HCCHAR_EPNUM_Msk // Endpoint number
+#define HCCHAR_EPNUM_0 (0x1UL << HCCHAR_EPNUM_Pos) // 0x00000800
+#define HCCHAR_EPNUM_1 (0x2UL << HCCHAR_EPNUM_Pos) // 0x00001000
+#define HCCHAR_EPNUM_2 (0x4UL << HCCHAR_EPNUM_Pos) // 0x00002000
+#define HCCHAR_EPNUM_3 (0x8UL << HCCHAR_EPNUM_Pos) // 0x00004000
+#define HCCHAR_EPDIR_Pos (15U)
+#define HCCHAR_EPDIR_Msk (0x1UL << HCCHAR_EPDIR_Pos) // 0x00008000
+#define HCCHAR_EPDIR HCCHAR_EPDIR_Msk // Endpoint direction
+#define HCCHAR_LSDEV_Pos (17U)
+#define HCCHAR_LSDEV_Msk (0x1UL << HCCHAR_LSDEV_Pos) // 0x00020000
+#define HCCHAR_LSDEV HCCHAR_LSDEV_Msk // Low-speed device
+
+#define HCCHAR_EPTYP_Pos (18U)
+#define HCCHAR_EPTYP_Msk (0x3UL << HCCHAR_EPTYP_Pos) // 0x000C0000
+#define HCCHAR_EPTYP HCCHAR_EPTYP_Msk // Endpoint type
+#define HCCHAR_EPTYP_0 (0x1UL << HCCHAR_EPTYP_Pos) // 0x00040000
+#define HCCHAR_EPTYP_1 (0x2UL << HCCHAR_EPTYP_Pos) // 0x00080000
+
+#define HCCHAR_MC_Pos (20U)
+#define HCCHAR_MC_Msk (0x3UL << HCCHAR_MC_Pos) // 0x00300000
+#define HCCHAR_MC HCCHAR_MC_Msk // Multi Count (MC) / Error Count (EC)
+#define HCCHAR_MC_0 (0x1UL << HCCHAR_MC_Pos) // 0x00100000
+#define HCCHAR_MC_1 (0x2UL << HCCHAR_MC_Pos) // 0x00200000
+
+#define HCCHAR_DAD_Pos (22U)
+#define HCCHAR_DAD_Msk (0x7FUL << HCCHAR_DAD_Pos) // 0x1FC00000
+#define HCCHAR_DAD HCCHAR_DAD_Msk // Device address
+#define HCCHAR_DAD_0 (0x01UL << HCCHAR_DAD_Pos) // 0x00400000
+#define HCCHAR_DAD_1 (0x02UL << HCCHAR_DAD_Pos) // 0x00800000
+#define HCCHAR_DAD_2 (0x04UL << HCCHAR_DAD_Pos) // 0x01000000
+#define HCCHAR_DAD_3 (0x08UL << HCCHAR_DAD_Pos) // 0x02000000
+#define HCCHAR_DAD_4 (0x10UL << HCCHAR_DAD_Pos) // 0x04000000
+#define HCCHAR_DAD_5 (0x20UL << HCCHAR_DAD_Pos) // 0x08000000
+#define HCCHAR_DAD_6 (0x40UL << HCCHAR_DAD_Pos) // 0x10000000
+#define HCCHAR_ODDFRM_Pos (29U)
+#define HCCHAR_ODDFRM_Msk (0x1UL << HCCHAR_ODDFRM_Pos) // 0x20000000
+#define HCCHAR_ODDFRM HCCHAR_ODDFRM_Msk // Odd frame
+#define HCCHAR_CHDIS_Pos (30U)
+#define HCCHAR_CHDIS_Msk (0x1UL << HCCHAR_CHDIS_Pos) // 0x40000000
+#define HCCHAR_CHDIS HCCHAR_CHDIS_Msk // Channel disable
+#define HCCHAR_CHENA_Pos (31U)
+#define HCCHAR_CHENA_Msk (0x1UL << HCCHAR_CHENA_Pos) // 0x80000000
+#define HCCHAR_CHENA HCCHAR_CHENA_Msk // Channel enable
+
+/******************** Bit definition for HCSPLT register ********************/
+
+#define HCSPLT_PRTADDR_Pos (0U)
+#define HCSPLT_PRTADDR_Msk (0x7FUL << HCSPLT_PRTADDR_Pos) // 0x0000007F
+#define HCSPLT_PRTADDR HCSPLT_PRTADDR_Msk // Port address
+#define HCSPLT_PRTADDR_0 (0x01UL << HCSPLT_PRTADDR_Pos) // 0x00000001
+#define HCSPLT_PRTADDR_1 (0x02UL << HCSPLT_PRTADDR_Pos) // 0x00000002
+#define HCSPLT_PRTADDR_2 (0x04UL << HCSPLT_PRTADDR_Pos) // 0x00000004
+#define HCSPLT_PRTADDR_3 (0x08UL << HCSPLT_PRTADDR_Pos) // 0x00000008
+#define HCSPLT_PRTADDR_4 (0x10UL << HCSPLT_PRTADDR_Pos) // 0x00000010
+#define HCSPLT_PRTADDR_5 (0x20UL << HCSPLT_PRTADDR_Pos) // 0x00000020
+#define HCSPLT_PRTADDR_6 (0x40UL << HCSPLT_PRTADDR_Pos) // 0x00000040
+
+#define HCSPLT_HUBADDR_Pos (7U)
+#define HCSPLT_HUBADDR_Msk (0x7FUL << HCSPLT_HUBADDR_Pos) // 0x00003F80
+#define HCSPLT_HUBADDR HCSPLT_HUBADDR_Msk // Hub address
+#define HCSPLT_HUBADDR_0 (0x01UL << HCSPLT_HUBADDR_Pos) // 0x00000080
+#define HCSPLT_HUBADDR_1 (0x02UL << HCSPLT_HUBADDR_Pos) // 0x00000100
+#define HCSPLT_HUBADDR_2 (0x04UL << HCSPLT_HUBADDR_Pos) // 0x00000200
+#define HCSPLT_HUBADDR_3 (0x08UL << HCSPLT_HUBADDR_Pos) // 0x00000400
+#define HCSPLT_HUBADDR_4 (0x10UL << HCSPLT_HUBADDR_Pos) // 0x00000800
+#define HCSPLT_HUBADDR_5 (0x20UL << HCSPLT_HUBADDR_Pos) // 0x00001000
+#define HCSPLT_HUBADDR_6 (0x40UL << HCSPLT_HUBADDR_Pos) // 0x00002000
+
+#define HCSPLT_XACTPOS_Pos (14U)
+#define HCSPLT_XACTPOS_Msk (0x3UL << HCSPLT_XACTPOS_Pos) // 0x0000C000
+#define HCSPLT_XACTPOS HCSPLT_XACTPOS_Msk // XACTPOS
+#define HCSPLT_XACTPOS_0 (0x1UL << HCSPLT_XACTPOS_Pos) // 0x00004000
+#define HCSPLT_XACTPOS_1 (0x2UL << HCSPLT_XACTPOS_Pos) // 0x00008000
+#define HCSPLT_COMPLSPLT_Pos (16U)
+#define HCSPLT_COMPLSPLT_Msk (0x1UL << HCSPLT_COMPLSPLT_Pos) // 0x00010000
+#define HCSPLT_COMPLSPLT HCSPLT_COMPLSPLT_Msk // Do complete split
+#define HCSPLT_SPLITEN_Pos (31U)
+#define HCSPLT_SPLITEN_Msk (0x1UL << HCSPLT_SPLITEN_Pos) // 0x80000000
+#define HCSPLT_SPLITEN HCSPLT_SPLITEN_Msk // Split enable
+
+/******************** Bit definition for HCINT register ********************/
+#define HCINT_XFRC_Pos (0U)
+#define HCINT_XFRC_Msk (0x1UL << HCINT_XFRC_Pos) // 0x00000001
+#define HCINT_XFRC HCINT_XFRC_Msk // Transfer completed
+#define HCINT_CHH_Pos (1U)
+#define HCINT_CHH_Msk (0x1UL << HCINT_CHH_Pos) // 0x00000002
+#define HCINT_CHH HCINT_CHH_Msk // Channel halted
+#define HCINT_AHBERR_Pos (2U)
+#define HCINT_AHBERR_Msk (0x1UL << HCINT_AHBERR_Pos) // 0x00000004
+#define HCINT_AHBERR HCINT_AHBERR_Msk // AHB error
+#define HCINT_STALL_Pos (3U)
+#define HCINT_STALL_Msk (0x1UL << HCINT_STALL_Pos) // 0x00000008
+#define HCINT_STALL HCINT_STALL_Msk // STALL response received interrupt
+#define HCINT_NAK_Pos (4U)
+#define HCINT_NAK_Msk (0x1UL << HCINT_NAK_Pos) // 0x00000010
+#define HCINT_NAK HCINT_NAK_Msk // NAK response received interrupt
+#define HCINT_ACK_Pos (5U)
+#define HCINT_ACK_Msk (0x1UL << HCINT_ACK_Pos) // 0x00000020
+#define HCINT_ACK HCINT_ACK_Msk // ACK response received/transmitted interrupt
+#define HCINT_NYET_Pos (6U)
+#define HCINT_NYET_Msk (0x1UL << HCINT_NYET_Pos) // 0x00000040
+#define HCINT_NYET HCINT_NYET_Msk // Response received interrupt
+#define HCINT_TXERR_Pos (7U)
+#define HCINT_TXERR_Msk (0x1UL << HCINT_TXERR_Pos) // 0x00000080
+#define HCINT_TXERR HCINT_TXERR_Msk // Transaction error
+#define HCINT_BBERR_Pos (8U)
+#define HCINT_BBERR_Msk (0x1UL << HCINT_BBERR_Pos) // 0x00000100
+#define HCINT_BBERR HCINT_BBERR_Msk // Babble error
+#define HCINT_FRMOR_Pos (9U)
+#define HCINT_FRMOR_Msk (0x1UL << HCINT_FRMOR_Pos) // 0x00000200
+#define HCINT_FRMOR HCINT_FRMOR_Msk // Frame overrun
+#define HCINT_DTERR_Pos (10U)
+#define HCINT_DTERR_Msk (0x1UL << HCINT_DTERR_Pos) // 0x00000400
+#define HCINT_DTERR HCINT_DTERR_Msk // Data toggle error
+
+/******************** Bit definition for DIEPINT register ********************/
+#define DIEPINT_XFRC_Pos (0U)
+#define DIEPINT_XFRC_Msk (0x1UL << DIEPINT_XFRC_Pos) // 0x00000001
+#define DIEPINT_XFRC DIEPINT_XFRC_Msk // Transfer completed interrupt
+#define DIEPINT_EPDISD_Pos (1U)
+#define DIEPINT_EPDISD_Msk (0x1UL << DIEPINT_EPDISD_Pos) // 0x00000002
+#define DIEPINT_EPDISD DIEPINT_EPDISD_Msk // Endpoint disabled interrupt
+#define DIEPINT_AHBERR_Pos (2U)
+#define DIEPINT_AHBERR_Msk (0x1UL << DIEPINT_AHBERR_Pos) // 0x00000004
+#define DIEPINT_AHBERR DIEPINT_AHBERR_Msk // AHB Error (AHBErr) during an IN transaction
+#define DIEPINT_TOC_Pos (3U)
+#define DIEPINT_TOC_Msk (0x1UL << DIEPINT_TOC_Pos) // 0x00000008
+#define DIEPINT_TOC DIEPINT_TOC_Msk // Timeout condition
+#define DIEPINT_ITTXFE_Pos (4U)
+#define DIEPINT_ITTXFE_Msk (0x1UL << DIEPINT_ITTXFE_Pos) // 0x00000010
+#define DIEPINT_ITTXFE DIEPINT_ITTXFE_Msk // IN token received when TxFIFO is empty
+#define DIEPINT_INEPNM_Pos (5U)
+#define DIEPINT_INEPNM_Msk (0x1UL << DIEPINT_INEPNM_Pos) // 0x00000020
+#define DIEPINT_INEPNM DIEPINT_INEPNM_Msk // IN token received with EP mismatch
+#define DIEPINT_INEPNE_Pos (6U)
+#define DIEPINT_INEPNE_Msk (0x1UL << DIEPINT_INEPNE_Pos) // 0x00000040
+#define DIEPINT_INEPNE DIEPINT_INEPNE_Msk // IN endpoint NAK effective
+#define DIEPINT_TXFE_Pos (7U)
+#define DIEPINT_TXFE_Msk (0x1UL << DIEPINT_TXFE_Pos) // 0x00000080
+#define DIEPINT_TXFE DIEPINT_TXFE_Msk // Transmit FIFO empty
+#define DIEPINT_TXFIFOUDRN_Pos (8U)
+#define DIEPINT_TXFIFOUDRN_Msk (0x1UL << DIEPINT_TXFIFOUDRN_Pos) // 0x00000100
+#define DIEPINT_TXFIFOUDRN DIEPINT_TXFIFOUDRN_Msk // Transmit Fifo Underrun
+#define DIEPINT_BNA_Pos (9U)
+#define DIEPINT_BNA_Msk (0x1UL << DIEPINT_BNA_Pos) // 0x00000200
+#define DIEPINT_BNA DIEPINT_BNA_Msk // Buffer not available interrupt
+#define DIEPINT_PKTDRPSTS_Pos (11U)
+#define DIEPINT_PKTDRPSTS_Msk (0x1UL << DIEPINT_PKTDRPSTS_Pos) // 0x00000800
+#define DIEPINT_PKTDRPSTS DIEPINT_PKTDRPSTS_Msk // Packet dropped status
+#define DIEPINT_BERR_Pos (12U)
+#define DIEPINT_BERR_Msk (0x1UL << DIEPINT_BERR_Pos) // 0x00001000
+#define DIEPINT_BERR DIEPINT_BERR_Msk // Babble error interrupt
+#define DIEPINT_NAK_Pos (13U)
+#define DIEPINT_NAK_Msk (0x1UL << DIEPINT_NAK_Pos) // 0x00002000
+#define DIEPINT_NAK DIEPINT_NAK_Msk // NAK interrupt
+
+/******************** Bit definition for HCINTMSK register ********************/
+#define HCINTMSK_XFRCM_Pos (0U)
+#define HCINTMSK_XFRCM_Msk (0x1UL << HCINTMSK_XFRCM_Pos) // 0x00000001
+#define HCINTMSK_XFRCM HCINTMSK_XFRCM_Msk // Transfer completed mask
+#define HCINTMSK_CHHM_Pos (1U)
+#define HCINTMSK_CHHM_Msk (0x1UL << HCINTMSK_CHHM_Pos) // 0x00000002
+#define HCINTMSK_CHHM HCINTMSK_CHHM_Msk // Channel halted mask
+#define HCINTMSK_AHBERR_Pos (2U)
+#define HCINTMSK_AHBERR_Msk (0x1UL << HCINTMSK_AHBERR_Pos) // 0x00000004
+#define HCINTMSK_AHBERR HCINTMSK_AHBERR_Msk // AHB error
+#define HCINTMSK_STALLM_Pos (3U)
+#define HCINTMSK_STALLM_Msk (0x1UL << HCINTMSK_STALLM_Pos) // 0x00000008
+#define HCINTMSK_STALLM HCINTMSK_STALLM_Msk // STALL response received interrupt mask
+#define HCINTMSK_NAKM_Pos (4U)
+#define HCINTMSK_NAKM_Msk (0x1UL << HCINTMSK_NAKM_Pos) // 0x00000010
+#define HCINTMSK_NAKM HCINTMSK_NAKM_Msk // NAK response received interrupt mask
+#define HCINTMSK_ACKM_Pos (5U)
+#define HCINTMSK_ACKM_Msk (0x1UL << HCINTMSK_ACKM_Pos) // 0x00000020
+#define HCINTMSK_ACKM HCINTMSK_ACKM_Msk // ACK response received/transmitted interrupt mask
+#define HCINTMSK_NYET_Pos (6U)
+#define HCINTMSK_NYET_Msk (0x1UL << HCINTMSK_NYET_Pos) // 0x00000040
+#define HCINTMSK_NYET HCINTMSK_NYET_Msk // response received interrupt mask
+#define HCINTMSK_TXERRM_Pos (7U)
+#define HCINTMSK_TXERRM_Msk (0x1UL << HCINTMSK_TXERRM_Pos) // 0x00000080
+#define HCINTMSK_TXERRM HCINTMSK_TXERRM_Msk // Transaction error mask
+#define HCINTMSK_BBERRM_Pos (8U)
+#define HCINTMSK_BBERRM_Msk (0x1UL << HCINTMSK_BBERRM_Pos) // 0x00000100
+#define HCINTMSK_BBERRM HCINTMSK_BBERRM_Msk // Babble error mask
+#define HCINTMSK_FRMORM_Pos (9U)
+#define HCINTMSK_FRMORM_Msk (0x1UL << HCINTMSK_FRMORM_Pos) // 0x00000200
+#define HCINTMSK_FRMORM HCINTMSK_FRMORM_Msk // Frame overrun mask
+#define HCINTMSK_DTERRM_Pos (10U)
+#define HCINTMSK_DTERRM_Msk (0x1UL << HCINTMSK_DTERRM_Pos) // 0x00000400
+#define HCINTMSK_DTERRM HCINTMSK_DTERRM_Msk // Data toggle error mask
+
+/******************** Bit definition for DIEPTSIZ register ********************/
+
+#define DIEPTSIZ_XFRSIZ_Pos (0U)
+#define DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos) // 0x0007FFFF
+#define DIEPTSIZ_XFRSIZ DIEPTSIZ_XFRSIZ_Msk // Transfer size
+#define DIEPTSIZ_PKTCNT_Pos (19U)
+#define DIEPTSIZ_PKTCNT_Msk (0x3FFUL << DIEPTSIZ_PKTCNT_Pos) // 0x1FF80000
+#define DIEPTSIZ_PKTCNT DIEPTSIZ_PKTCNT_Msk // Packet count
+#define DIEPTSIZ_MULCNT_Pos (29U)
+#define DIEPTSIZ_MULCNT_Msk (0x3UL << DIEPTSIZ_MULCNT_Pos) // 0x60000000
+#define DIEPTSIZ_MULCNT DIEPTSIZ_MULCNT_Msk // Packet count
+ /******************** Bit definition for HCTSIZ register ********************/
+#define HCTSIZ_XFRSIZ_Pos (0U)
+#define HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) // 0x0007FFFF
+#define HCTSIZ_XFRSIZ HCTSIZ_XFRSIZ_Msk // Transfer size
+#define HCTSIZ_PKTCNT_Pos (19U)
+#define HCTSIZ_PKTCNT_Msk (0x3FFUL << HCTSIZ_PKTCNT_Pos) // 0x1FF80000
+#define HCTSIZ_PKTCNT HCTSIZ_PKTCNT_Msk // Packet count
+#define HCTSIZ_DOPING_Pos (31U)
+#define HCTSIZ_DOPING_Msk (0x1UL << HCTSIZ_DOPING_Pos) // 0x80000000
+#define HCTSIZ_DOPING HCTSIZ_DOPING_Msk // Do PING
+#define HCTSIZ_DPID_Pos (29U)
+#define HCTSIZ_DPID_Msk (0x3UL << HCTSIZ_DPID_Pos) // 0x60000000
+#define HCTSIZ_DPID HCTSIZ_DPID_Msk // Data PID
+#define HCTSIZ_DPID_0 (0x1UL << HCTSIZ_DPID_Pos) // 0x20000000
+#define HCTSIZ_DPID_1 (0x2UL << HCTSIZ_DPID_Pos) // 0x40000000
+
+/******************** Bit definition for DIEPDMA register ********************/
+#define DIEPDMA_DMAADDR_Pos (0U)
+#define DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos) // 0xFFFFFFFF
+#define DIEPDMA_DMAADDR DIEPDMA_DMAADDR_Msk // DMA address
+
+/******************** Bit definition for HCDMA register ********************/
+#define HCDMA_DMAADDR_Pos (0U)
+#define HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) // 0xFFFFFFFF
+#define HCDMA_DMAADDR HCDMA_DMAADDR_Msk // DMA address
+
+ /******************** Bit definition for DTXFSTS register ********************/
+#define DTXFSTS_INEPTFSAV_Pos (0U)
+#define DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) // 0x0000FFFF
+#define DTXFSTS_INEPTFSAV DTXFSTS_INEPTFSAV_Msk // IN endpoint TxFIFO space available
+
+ /******************** Bit definition for DIEPTXF register ********************/
+#define DIEPTXF_INEPTXSA_Pos (0U)
+#define DIEPTXF_INEPTXSA_Msk (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) // 0x0000FFFF
+#define DIEPTXF_INEPTXSA DIEPTXF_INEPTXSA_Msk // IN endpoint FIFOx transmit RAM start address
+#define DIEPTXF_INEPTXFD_Pos (16U)
+#define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) // 0xFFFF0000
+#define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk // IN endpoint TxFIFO depth
+
+/******************** Bit definition for DOEPCTL register ********************/
+#define DOEPCTL_MPSIZ_Pos (0U)
+#define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) // 0x000007FF
+#define DOEPCTL_MPSIZ DOEPCTL_MPSIZ_Msk // Maximum packet size //Bit 1
+#define DOEPCTL_USBAEP_Pos (15U)
+#define DOEPCTL_USBAEP_Msk (0x1UL << DOEPCTL_USBAEP_Pos) // 0x00008000
+#define DOEPCTL_USBAEP DOEPCTL_USBAEP_Msk // USB active endpoint
+#define DOEPCTL_NAKSTS_Pos (17U)
+#define DOEPCTL_NAKSTS_Msk (0x1UL << DOEPCTL_NAKSTS_Pos) // 0x00020000
+#define DOEPCTL_NAKSTS DOEPCTL_NAKSTS_Msk // NAK status
+#define DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000
+#define DOEPCTL_SD0PID_SEVNFRM DOEPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID
+#define DOEPCTL_SODDFRM_Pos (29U)
+#define DOEPCTL_SODDFRM_Msk (0x1UL << DOEPCTL_SODDFRM_Pos) // 0x20000000
+#define DOEPCTL_SODDFRM DOEPCTL_SODDFRM_Msk // Set odd frame
+#define DOEPCTL_EPTYP_Pos (18U)
+#define DOEPCTL_EPTYP_Msk (0x3UL << DOEPCTL_EPTYP_Pos) // 0x000C0000
+#define DOEPCTL_EPTYP DOEPCTL_EPTYP_Msk // Endpoint type
+#define DOEPCTL_EPTYP_0 (0x1UL << DOEPCTL_EPTYP_Pos) // 0x00040000
+#define DOEPCTL_EPTYP_1 (0x2UL << DOEPCTL_EPTYP_Pos) // 0x00080000
+#define DOEPCTL_SNPM_Pos (20U)
+#define DOEPCTL_SNPM_Msk (0x1UL << DOEPCTL_SNPM_Pos) // 0x00100000
+#define DOEPCTL_SNPM DOEPCTL_SNPM_Msk // Snoop mode
+#define DOEPCTL_STALL_Pos (21U)
+#define DOEPCTL_STALL_Msk (0x1UL << DOEPCTL_STALL_Pos) // 0x00200000
+#define DOEPCTL_STALL DOEPCTL_STALL_Msk // STALL handshake
+#define DOEPCTL_CNAK_Pos (26U)
+#define DOEPCTL_CNAK_Msk (0x1UL << DOEPCTL_CNAK_Pos) // 0x04000000
+#define DOEPCTL_CNAK DOEPCTL_CNAK_Msk // Clear NAK
+#define DOEPCTL_SNAK_Pos (27U)
+#define DOEPCTL_SNAK_Msk (0x1UL << DOEPCTL_SNAK_Pos) // 0x08000000
+#define DOEPCTL_SNAK DOEPCTL_SNAK_Msk // Set NAK
+#define DOEPCTL_EPDIS_Pos (30U)
+#define DOEPCTL_EPDIS_Msk (0x1UL << DOEPCTL_EPDIS_Pos) // 0x40000000
+#define DOEPCTL_EPDIS DOEPCTL_EPDIS_Msk // Endpoint disable
+#define DOEPCTL_EPENA_Pos (31U)
+#define DOEPCTL_EPENA_Msk (0x1UL << DOEPCTL_EPENA_Pos) // 0x80000000
+#define DOEPCTL_EPENA DOEPCTL_EPENA_Msk // Endpoint enable
+
+/******************** Bit definition for DOEPINT register ********************/
+#define DOEPINT_XFRC_Pos (0U)
+#define DOEPINT_XFRC_Msk (0x1UL << DOEPINT_XFRC_Pos) // 0x00000001
+#define DOEPINT_XFRC DOEPINT_XFRC_Msk // Transfer completed interrupt
+#define DOEPINT_EPDISD_Pos (1U)
+#define DOEPINT_EPDISD_Msk (0x1UL << DOEPINT_EPDISD_Pos) // 0x00000002
+#define DOEPINT_EPDISD DOEPINT_EPDISD_Msk // Endpoint disabled interrupt
+#define DOEPINT_AHBERR_Pos (2U)
+#define DOEPINT_AHBERR_Msk (0x1UL << DOEPINT_AHBERR_Pos) // 0x00000004
+#define DOEPINT_AHBERR DOEPINT_AHBERR_Msk // AHB Error (AHBErr) during an OUT transaction
+#define DOEPINT_STUP_Pos (3U)
+#define DOEPINT_STUP_Msk (0x1UL << DOEPINT_STUP_Pos) // 0x00000008
+#define DOEPINT_STUP DOEPINT_STUP_Msk // SETUP phase done
+#define DOEPINT_OTEPDIS_Pos (4U)
+#define DOEPINT_OTEPDIS_Msk (0x1UL << DOEPINT_OTEPDIS_Pos) // 0x00000010
+#define DOEPINT_OTEPDIS DOEPINT_OTEPDIS_Msk // OUT token received when endpoint disabled
+#define DOEPINT_OTEPSPR_Pos (5U)
+#define DOEPINT_OTEPSPR_Msk (0x1UL << DOEPINT_OTEPSPR_Pos) // 0x00000020
+#define DOEPINT_OTEPSPR DOEPINT_OTEPSPR_Msk // Status Phase Received For Control Write
+#define DOEPINT_B2BSTUP_Pos (6U)
+#define DOEPINT_B2BSTUP_Msk (0x1UL << DOEPINT_B2BSTUP_Pos) // 0x00000040
+#define DOEPINT_B2BSTUP DOEPINT_B2BSTUP_Msk // Back-to-back SETUP packets received
+#define DOEPINT_OUTPKTERR_Pos (8U)
+#define DOEPINT_OUTPKTERR_Msk (0x1UL << DOEPINT_OUTPKTERR_Pos) // 0x00000100
+#define DOEPINT_OUTPKTERR DOEPINT_OUTPKTERR_Msk // OUT packet error
+#define DOEPINT_NAK_Pos (13U)
+#define DOEPINT_NAK_Msk (0x1UL << DOEPINT_NAK_Pos) // 0x00002000
+#define DOEPINT_NAK DOEPINT_NAK_Msk // NAK Packet is transmitted by the device
+#define DOEPINT_NYET_Pos (14U)
+#define DOEPINT_NYET_Msk (0x1UL << DOEPINT_NYET_Pos) // 0x00004000
+#define DOEPINT_NYET DOEPINT_NYET_Msk // NYET interrupt
+#define DOEPINT_STPKTRX_Pos (15U)
+#define DOEPINT_STPKTRX_Msk (0x1UL << DOEPINT_STPKTRX_Pos) // 0x00008000
+#define DOEPINT_STPKTRX DOEPINT_STPKTRX_Msk // Setup Packet Received
+
+/******************** Bit definition for DOEPTSIZ register ********************/
+#define DOEPTSIZ_XFRSIZ_Pos (0U)
+#define DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos) // 0x0007FFFF
+#define DOEPTSIZ_XFRSIZ DOEPTSIZ_XFRSIZ_Msk // Transfer size
+#define DOEPTSIZ_PKTCNT_Pos (19U)
+#define DOEPTSIZ_PKTCNT_Msk (0x3FFUL << DOEPTSIZ_PKTCNT_Pos) // 0x1FF80000
+#define DOEPTSIZ_PKTCNT DOEPTSIZ_PKTCNT_Msk // Packet count
+
+#define DOEPTSIZ_STUPCNT_Pos (29U)
+#define DOEPTSIZ_STUPCNT_Msk (0x3UL << DOEPTSIZ_STUPCNT_Pos) // 0x60000000
+#define DOEPTSIZ_STUPCNT DOEPTSIZ_STUPCNT_Msk // SETUP packet count
+#define DOEPTSIZ_STUPCNT_0 (0x1UL << DOEPTSIZ_STUPCNT_Pos) // 0x20000000
+#define DOEPTSIZ_STUPCNT_1 (0x2UL << DOEPTSIZ_STUPCNT_Pos) // 0x40000000
+
+/******************** Bit definition for PCGCTL register ********************/
+#define PCGCTL_IF_DEV_MODE TU_BIT(31)
+#define PCGCTL_P2HD_PRT_SPD_MASK (0x3ul << 29)
+#define PCGCTL_P2HD_PRT_SPD_SHIFT 29
+#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3ul << 27)
+#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
+#define PCGCTL_MAC_DEV_ADDR_MASK (0x7ful << 20)
+#define PCGCTL_MAC_DEV_ADDR_SHIFT 20
+#define PCGCTL_MAX_TERMSEL TU_BIT(19)
+#define PCGCTL_MAX_XCVRSELECT_MASK (0x3ul << 17)
+#define PCGCTL_MAX_XCVRSELECT_SHIFT 17
+#define PCGCTL_PORT_POWER TU_BIT(16)
+#define PCGCTL_PRT_CLK_SEL_MASK (0x3ul << 14)
+#define PCGCTL_PRT_CLK_SEL_SHIFT 14
+#define PCGCTL_ESS_REG_RESTORED TU_BIT(13)
+#define PCGCTL_EXTND_HIBER_SWITCH TU_BIT(12)
+#define PCGCTL_EXTND_HIBER_PWRCLMP TU_BIT(11)
+#define PCGCTL_ENBL_EXTND_HIBER TU_BIT(10)
+#define PCGCTL_RESTOREMODE TU_BIT(9)
+#define PCGCTL_RESETAFTSUSP TU_BIT(8)
+#define PCGCTL_DEEP_SLEEP TU_BIT(7)
+#define PCGCTL_PHY_IN_SLEEP TU_BIT(6)
+#define PCGCTL_ENBL_SLEEP_GATING TU_BIT(5)
+#define PCGCTL_RSTPDWNMODULE TU_BIT(3)
+#define PCGCTL_PWRCLMP TU_BIT(2)
+#define PCGCTL_GATEHCLK TU_BIT(1)
+#define PCGCTL_STOPPCLK TU_BIT(0)
+
+#define PCGCTL1_TIMER (0x3ul << 1)
+#define PCGCTL1_GATEEN TU_BIT(0)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_xmc.h b/src/portable/synopsys/dwc2/dwc2_xmc.h
new file mode 100644
index 000000000..63419abf7
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_xmc.h
@@ -0,0 +1,88 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Rafael Silva (@perigoso)
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _DWC2_XMC_H_
+#define _DWC2_XMC_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "xmc_device.h"
+
+#define DWC2_EP_MAX 7
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+ // Note: XMC has some custom control registers before DWC registers
+ { .reg_base = USB0_BASE, .irqnum = USB0_0_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 2048 }
+};
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_enable(uint8_t rhport)
+{
+ NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
+{
+ NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
+}
+
+static inline void dwc2_remote_wakeup_delay(void)
+{
+ // try to delay for 1 ms
+// uint32_t count = SystemCoreClock / 1000;
+// while ( count-- ) __NOP();
+}
+
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+ (void) dwc2;
+ (void) hs_phy_type;
+
+ // Enable PHY
+ //USB->ROUTE = USB_ROUTE_PHYPEN;
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+ (void) dwc2;
+ (void) hs_phy_type;
+
+ // XMC Manual: turn around must be 5 (reset & default value)
+ // dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-28 03:11:59 +0000