Merge remote-tracking branch 'tinyusb/master' into pr-osal-spin-deinit

Signed-off-by: HiFiPhile <[email protected]>

15 files changed, 1226 insertions, 575 deletions

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index f10f0bdc3..e1a2f6cf2 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -39,6 +39,7 @@
 #define DWC2_DEBUG    2
 
 #include "device/dcd.h"
+#include "device/usbd.h"
 #include "device/usbd_pvt.h"
 #include "dwc2_common.h"
 
@@ -51,6 +52,7 @@ typedef struct {
   uint16_t total_len;
   uint16_t max_size;
   uint8_t interval;
+  uint8_t iso_retry; // ISO retry counter
 } xfer_ctl_t;
 
 // This variable is modified from ISR context, so it must be protected by critical section
@@ -71,12 +73,22 @@ typedef struct {
 
 static dcd_data_t _dcd_data;
 
+// DMA receives up to 3 back-to-back SETUP packets (3 x 8 bytes), Slave mode only needs 1 packet (8 bytes)
+#if CFG_TUD_DWC2_DMA_ENABLE
+  #define DWC2_SETUP_BUFFER_SIZE 24
+#else
+  #define DWC2_SETUP_BUFFER_SIZE 8
+#endif
+
 CFG_TUD_MEM_SECTION static struct {
-  TUD_EPBUF_DEF(setup_packet, 8);
+  TUD_EPBUF_DEF(setup_buffer, DWC2_SETUP_BUFFER_SIZE);
 } _dcd_usbbuf;
 
+static tud_configure_dwc2_t _tud_cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+
 TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc2) {
   #if TU_CHECK_MCU(OPT_MCU_GD32VF103)
+  (void) dwc2;
   return DWC2_EP_MAX;
   #else
   const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
@@ -84,11 +96,21 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc
   #endif
 }
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+TU_ATTR_ALWAYS_INLINE static inline bool edpt_is_enabled(dwc2_dep_t* dep) {
+  return (dep->ctl & EPCTL_EPENA) != 0;
+}
 
-//--------------------------------------------------------------------
-// DMA
-//--------------------------------------------------------------------
-#if CFG_TUD_MEM_DCACHE_ENABLE
+  #if CFG_TUD_DWC2_SLAVE_ENABLE
+static uint16_t epin_write_tx_fifo(dwc2_regs_t *dwc2, uint8_t epnum);
+  #endif
+
+  //--------------------------------------------------------------------
+  // DMA
+  //--------------------------------------------------------------------
+  #if CFG_TUD_MEM_DCACHE_ENABLE
 bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
   TU_VERIFY(addr && data_size);
   return dwc2_dcache_clean(addr, data_size);
@@ -116,14 +138,14 @@ static void dma_setup_prepare(uint8_t rhport) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) {
-    if(dwc2->epout[0].doepctl & DOEPCTL_EPENA) {
+    if(edpt_is_enabled(&dwc2->epout[0])) {
       return;
     }
   }
 
-  // Receive only 1 packet
-  dwc2->epout[0].doeptsiz = (1 << DOEPTSIZ_STUPCNT_Pos) | (1 << DOEPTSIZ_PKTCNT_Pos) | (8 << DOEPTSIZ_XFRSIZ_Pos);
-  dwc2->epout[0].doepdma = (uintptr_t) _dcd_usbbuf.setup_packet;
+  // Receive back-to-back setup packets
+  dwc2->epout[0].doeptsiz = (3 << DOEPTSIZ_STUPCNT_Pos);
+  dwc2->epout[0].doepdma = (uintptr_t) _dcd_usbbuf.setup_buffer;
   dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP;
 }
 
@@ -133,22 +155,23 @@ static void dma_setup_prepare(uint8_t rhport) {
 
 
 /* Device Data FIFO scheme
+  The controller has a single SPRAM of otg_dfifo_depth 32-bit words shared between all FIFOs and optional DMA metadata.
+  otg_dfifo_depth = ghwcfg3.dfifo_depth + EP_LOC_CNT. It is split up into:
 
-  The FIFO is split up into
-  - EPInfo: for storing DMA metadata, only required when use DMA. Maximum size is called
-    EP_LOC_CNT = ep_fifo_size - ghwcfg3.dfifo_depth. For value less than EP_LOC_CNT, gdfifocfg must be configured before
-    gahbcfg.dmaen is set
-      - Buffer mode: 1 word per endpoint direction
-      - Scatter/Gather DMA: 4 words per endpoint direction
+  - EPInfo: for storing DMA address registers (DxEPDMAn), only required when DMA is used.
+    gdfifocfg.EPINFOBASE and gdfifocfg.GDFIFOCfg must be configured before gahbcfg.dmaen is set.
+    The number of words needed per endpoint direction depends on the DMA mode used at runtime:
+      - Buffer DMA mode: 1 word per endpoint direction
+      - Scatter/Gather DMA mode: 4 words per endpoint direction
   - TX FIFO: one fifo for each IN endpoint. Size is dynamic depending on packet size, starting from top with EP0 IN.
   - Shared RX FIFO: a shared fifo for all OUT endpoints. Typically, can hold up to 2 packets of the largest EP size.
 
-  We allocated TX FIFO from top to bottom (using top pointer), this to allow the RX FIFO to grow dynamically which is
+  We allocate TX FIFOs from top to bottom (using a top pointer), this to allow the RX FIFO to grow dynamically, which is
   possible since the free space is located between the RX and TX FIFOs.
 
-   ---------------- ep_fifo_size
-  |  DxEPIDMAn  |
-  |-------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth)
+   --------------- otg_dfifo_depth
+  |  EPInfo      |   DxEPDMAn (DMA only, sized per runtime DMA mode)
+  |-------------|-- gdfifocfg.EPINFOBASE (start of EPInfo; FIFO space sized by GDFIFOCFG)
   | IN FIFO 0   |       control EP
   |-------------|
   | IN FIFO 1   |
@@ -168,17 +191,17 @@ static void dma_setup_prepare(uint8_t rhport) {
   - All EP OUT shared a unique OUT FIFO which uses (for Slave or Buffer DMA, Scatt/Gather DMA use different formula):
     - 13 for setup packets + control words (up to 3 setup packets).
     - 1 for global NAK (not required/used here).
-    - Largest-EPsize/4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is  "2 x (Largest-EPsize/4 + 1)"
-    - 2 for each used OUT endpoint
+    - Largest-EPsize/4 + 1. (FS: 64 bytes, HS: 512 bytes). Recommended is  "2 x (Largest-EPsize/4 + 1)"
+    - 2 for each used OUT endpoint.
 
-    Therefore GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum
+    Therefore, GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum
 */
 
 TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_device_grxfsiz(uint16_t largest_ep_size, uint8_t ep_count) {
-  return 13 + 1 + 2 * ((largest_ep_size / 4) + 1) + 2 * ep_count;
+  return (uint16_t)(13 + 1 + 2 * ((largest_ep_size / 4) + 1) + 2 * ep_count);
 }
 
-static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
+static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size, bool is_bulk) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
   const uint8_t ep_count = dwc2_controller->ep_count;
@@ -187,7 +210,7 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
 
   TU_ASSERT(epnum < ep_count);
 
-  uint16_t fifo_size = tu_div_ceil(packet_size, 4);
+  uint16_t fifo_size = (uint16_t)tu_div_ceil(packet_size, 4);
   if (dir == TUSB_DIR_OUT) {
     // Calculate required size of RX FIFO
     const uint16_t new_sz = calc_device_grxfsiz(4 * fifo_size, ep_count);
@@ -199,13 +222,14 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
     }
   } else {
     // Check IN endpoints concurrently active limit
-    if(dwc2_controller->ep_in_count) {
+    if(0 != dwc2_controller->ep_in_count) {
       TU_ASSERT(_dcd_data.allocated_epin_count < dwc2_controller->ep_in_count);
       _dcd_data.allocated_epin_count++;
     }
 
-    // If The TXFELVL is configured as half empty, the fifo must be twice the max_size.
-    if ((dwc2->gahbcfg & GAHBCFG_TX_FIFO_EPMTY_LVL) == 0) {
+    // Enable double buffering if configured, only effective for non-periodic endpoints
+    // Since we queue only 1 control transfer at a time, it's only applicable for bulk IN endpoints
+    if (((_tud_cfg.bm_double_buffered & (1 << epnum)) != 0) && epnum > 0 && is_bulk) {
       fifo_size *= 2;
     }
 
@@ -216,10 +240,10 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
 
     // Both TXFD and TXSA are in unit of 32-bit words.
     if (epnum == 0) {
-      dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dcd_data.dfifo_top;
+      dwc2->dieptxf0 = ((uint32_t) fifo_size << DIEPTXF0_TX0FD_Pos) | _dcd_data.dfifo_top;
     } else {
       // DIEPTXF starts at FIFO #1.
-      dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dcd_data.dfifo_top;
+      dwc2->dieptxf[epnum - 1] = ((uint32_t) fifo_size << DIEPTXF_INEPTXFD_Pos) | _dcd_data.dfifo_top;
     }
   }
 
@@ -233,14 +257,14 @@ static void dfifo_device_init(uint8_t rhport) {
 
   // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction
   const bool is_dma = dma_device_enabled(dwc2);
-  _dcd_data.dfifo_top = dwc2_controller->ep_fifo_size/4;
+  _dcd_data.dfifo_top = dwc2_controller->otg_dfifo_depth;
   if (is_dma) {
     _dcd_data.dfifo_top -= 2 * dwc2_controller->ep_count;
   }
-  dwc2->gdfifocfg = (_dcd_data.dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dcd_data.dfifo_top;
+  dwc2->gdfifocfg = ((uint32_t) _dcd_data.dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dcd_data.dfifo_top;
 
   // Allocate FIFO for EP0 IN
-  dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE);
+  (void) dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE, false);
 }
 
 
@@ -254,7 +278,13 @@ static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint
 
   xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
   xfer->max_size = tu_edpt_packet_size(p_endpoint_desc);
-  xfer->interval = p_endpoint_desc->bInterval;
+
+  const dwc2_dsts_t dsts = {.value = dwc2->dsts};
+  if (dsts.enum_speed == DCFG_SPEED_HIGH) {
+    xfer->interval = 1 << (p_endpoint_desc->bInterval - 1);
+  } else {
+    xfer->interval =  p_endpoint_desc->bInterval;
+  }
 
   // Endpoint control
   dwc2_depctl_t depctl = {.value = 0};
@@ -281,17 +311,18 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
   const uint8_t dir = tu_edpt_dir(ep_addr);
   dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
 
+  const uint32_t stall_mask = (stall ? EPCTL_STALL : 0);
+
   if (dir == TUSB_DIR_IN) {
-    // Only disable currently enabled non-control endpoint
-    if ((epnum == 0) || !(dep->diepctl & DIEPCTL_EPENA)) {
-      dep->diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
+    if (!edpt_is_enabled(dep)) {
+      dep->diepctl |= DIEPCTL_SNAK | stall_mask;
     } else {
       // Stop transmitting packets and NAK IN xfers.
       dep->diepctl |= DIEPCTL_SNAK;
       while ((dep->diepint & DIEPINT_INEPNE) == 0) {}
 
       // Disable the endpoint.
-      dep->diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
+      dep->diepctl |= DIEPCTL_EPDIS | stall_mask;
       while ((dep->diepint & DIEPINT_EPDISD_Msk) == 0) {}
 
       dep->diepint = DIEPINT_EPDISD;
@@ -300,9 +331,10 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
     // Flush the FIFO, and wait until we have confirmed it cleared.
     dfifo_flush_tx(dwc2, epnum);
   } else {
-    // Only disable currently enabled non-control endpoint
-    if ((epnum == 0) || !(dep->doepctl & DOEPCTL_EPENA)) {
-      dep->doepctl |= stall ? DOEPCTL_STALL : 0;
+    if (!edpt_is_enabled(dep) || epnum == 0) {
+      // non-control not-enabled: stall if set
+      // For EP0 Out, keep it enabled to receive SETUP packets
+      dep->doepctl |= stall_mask;
     } else {
       // Asserting GONAK is required to STALL an OUT endpoint.
       // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
@@ -312,7 +344,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
       while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {}
 
       // Ditto here disable the endpoint.
-      dep->doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
+      dep->doepctl |= DOEPCTL_EPDIS | stall_mask;
       while ((dep->doepint & DOEPINT_EPDISD_Msk) == 0) {}
 
       dep->doepint = DOEPINT_EPDISD;
@@ -321,6 +353,11 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
       dwc2->dctl |= DCTL_CGONAK;
     }
   }
+
+  // Clear ActEP
+  if (!stall && epnum != 0) {
+    dep->ctl &= ~EPCTL_USBAEP;
+  }
 }
 
 // Since this function returns void, it is not possible to return a boolean success message
@@ -336,12 +373,12 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
 
   // EP0 is limited to one packet per xfer
   if (epnum == 0) {
-    total_bytes = tu_min16(_dcd_data.ep0_pending[dir], xfer->max_size);
+    total_bytes = tu_min16(_dcd_data.ep0_pending[dir], CFG_TUD_ENDPOINT0_SIZE);
     _dcd_data.ep0_pending[dir] -= total_bytes;
     num_packets = 1;
   } else {
     total_bytes = xfer->total_len;
-    num_packets = tu_div_ceil(total_bytes, xfer->max_size);
+    num_packets = (uint16_t)tu_div_ceil(total_bytes, xfer->max_size);
     if (num_packets == 0) {
       num_packets = 1; // zero length packet still count as 1
     }
@@ -357,16 +394,17 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
   dwc2_depctl_t depctl = {.value = dep->ctl};
   depctl.clear_nak = 1;
   depctl.enable = 1;
-  if (depctl.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) {
+  if (depctl.type == DEPCTL_EPTYPE_ISOCHRONOUS) {
     const dwc2_dsts_t dsts = {.value = dwc2->dsts};
     const uint32_t odd_now = dsts.frame_number & 1u;
-    if (odd_now) {
+    if (odd_now != 0) {
       depctl.set_data0_iso_even = 1;
     } else {
       depctl.set_data1_iso_odd = 1;
     }
   }
 
+  #if CFG_TUD_DWC2_DMA_ENABLE
   const bool is_dma = dma_device_enabled(dwc2);
   if(is_dma) {
     if (dir == TUSB_DIR_IN && total_bytes != 0) {
@@ -374,35 +412,58 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
     }
     dep->diepdma = (uintptr_t) xfer->buffer;
     dep->diepctl = depctl.value; // enable endpoint
-  } else {
+    // Advance buffer pointer for EP0
+    if (epnum == 0) {
+      xfer->buffer += total_bytes;
+    }
+  } else
+  #endif
+  {
+  #if CFG_TUD_DWC2_SLAVE_ENABLE
     dep->diepctl = depctl.value; // enable endpoint
 
-    // Enable tx fifo empty interrupt only if there is data. Note must after depctl enable
     if (dir == TUSB_DIR_IN && total_bytes != 0) {
-      dwc2->diepempmsk |= (1 << epnum);
+      const uint16_t xferred_bytes = epin_write_tx_fifo(dwc2, epnum);
+
+      // Enable TXFE interrupt if there are still data to be sent
+      // EP0 only sends one packet at a time, so no need to check for EP0
+      if ((epnum != 0) && (xfer->total_len - xferred_bytes > 0)) {
+         dwc2->diepempmsk |= (1u << epnum);
+      }
     }
+  #endif
   }
 }
 
 //--------------------------------------------------------------------
 // Controller API
 //--------------------------------------------------------------------
+// optional dcd configuration, called by tud_configure()
+bool dcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
+  (void) rhport;
+  TU_VERIFY(cfg_id == TUD_CFGID_DWC2 && cfg_param != NULL);
+
+  const tud_configure_param_t* const cfg = (const tud_configure_param_t*) cfg_param;
+  _tud_cfg = cfg->dwc2;
+  return true;
+}
+
 bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
-  (void) rh_init;
-  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  dwc2_clock_init(rhport, rh_init->role);
 
   tu_memclr(&_dcd_data, sizeof(_dcd_data));
 
   // Core Initialization
-  const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const bool is_hs_phy = dwc2_core_is_highspeed_phy(dwc2, TUD_OPT_HIGH_SPEED);
   const bool is_dma = dma_device_enabled(dwc2);
-  TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma));
+  TU_ASSERT(dwc2_core_init(rhport, is_hs_phy, is_dma));
 
   //------------- 7.1 Device Initialization -------------//
   // Set device max speed
   uint32_t dcfg = dwc2->dcfg & ~DCFG_DSPD_Msk;
-  if (is_highspeed) {
-    dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
+  if (is_hs_phy) {
+    // dcfg Highspeed's mask is 0
 
     // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
     // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
@@ -422,20 +483,21 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   // Force device mode
   dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
 
-  // Clear A override, force B Valid
-  dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
+  // OTG Ctrl
+  uint32_t gotgctl = dwc2->gotgctl & ~GOTGCTL_AVALOEN; // Clear A-override
+  if (!_tud_cfg.vbus_sensing) {
+    gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;     // force B Valid if not sensing VBus
+  }
+  dwc2->gotgctl = gotgctl;
 
-#if CFG_TUSB_MCU == OPT_MCU_STM32N6
-  // No hardware detection of Vbus B-session is available on the STM32N6
-  dwc2->stm32_gccfg |= STM32_GCCFG_VBVALOVAL;
-#endif
+  #ifdef TUP_USBIP_DWC2_STM32
+  dwc2_stm32_gccfg_cfg(dwc2, _tud_cfg.vbus_sensing, false);
+  #endif
 
   // Enable required interrupts
   dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
 
-  // TX FIFO empty level for interrupt is complete empty
   uint32_t gahbcfg = dwc2->gahbcfg;
-  gahbcfg |= GAHBCFG_TX_FIFO_EPMTY_LVL;
   gahbcfg |= GAHBCFG_GINT; // Enable global interrupt
   dwc2->gahbcfg = gahbcfg;
 
@@ -443,6 +505,12 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   return true;
 }
 
+bool dcd_deinit(uint8_t rhport) {
+  dcd_disconnect(rhport);
+  dwc2_core_deinit(rhport);
+  return true;
+}
+
 void dcd_int_enable(uint8_t rhport) {
   dwc2_dcd_int_enable(rhport);
 }
@@ -456,7 +524,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
   dwc2->dcfg = (dwc2->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
 
   // Response with status after changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0, false);
 }
 
 void dcd_remote_wakeup(uint8_t rhport) {
@@ -478,34 +546,40 @@ void dcd_remote_wakeup(uint8_t rhport) {
 }
 
 void dcd_connect(uint8_t rhport) {
-  (void) rhport;
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
-#ifdef TUP_USBIP_DWC2_ESP32
-  usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
-  conf.pad_pull_override = 0;
-  conf.dp_pullup = 0;
-  conf.dp_pulldown = 0;
-  conf.dm_pullup = 0;
-  conf.dm_pulldown = 0;
-  USB_WRAP.otg_conf = conf;
+#if defined(TUP_USBIP_DWC2_ESP32) && !TU_CHECK_MCU(OPT_MCU_ESP32S31)
+  // S31 is excluded at compile time (no USB_WRAP peripheral).
+  // On P4, the HS PHY (port 1) must not touch USB_WRAP which belongs to the FS PHY.
+  if (rhport == 0) {
+    usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
+    conf.pad_pull_override = 0;
+    conf.dp_pullup = 0;
+    conf.dp_pulldown = 0;
+    conf.dm_pullup = 0;
+    conf.dm_pulldown = 0;
+    USB_WRAP.otg_conf = conf;
+  }
 #endif
 
   dwc2->dctl &= ~DCTL_SDIS;
 }
 
 void dcd_disconnect(uint8_t rhport) {
-  (void) rhport;
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
-#ifdef TUP_USBIP_DWC2_ESP32
-  usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
-  conf.pad_pull_override = 1;
-  conf.dp_pullup = 0;
-  conf.dp_pulldown = 1;
-  conf.dm_pullup = 0;
-  conf.dm_pulldown = 1;
-  USB_WRAP.otg_conf = conf;
+#if defined(TUP_USBIP_DWC2_ESP32) && !TU_CHECK_MCU(OPT_MCU_ESP32S31)
+  // S31 is excluded at compile time (no USB_WRAP peripheral).
+  // On P4, the HS PHY (port 1) must not touch USB_WRAP which belongs to the FS PHY.
+  if (rhport == 0) {
+    usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
+    conf.pad_pull_override = 1;
+    conf.dp_pullup = 0;
+    conf.dp_pulldown = 1;
+    conf.dm_pullup = 0;
+    conf.dm_pulldown = 1;
+    USB_WRAP.otg_conf = conf;
+  }
 #endif
 
   dwc2->dctl |= DCTL_SDIS;
@@ -531,7 +605,8 @@ void dcd_sof_enable(uint8_t rhport, bool en) {
  *------------------------------------------------------------------*/
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
-  TU_ASSERT(dfifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt)));
+  TU_ASSERT(dfifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt),
+                       desc_edpt->bmAttributes.xfer == TUSB_XFER_BULK));
   edpt_activate(rhport, desc_edpt);
   return true;
 }
@@ -551,7 +626,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
   for (uint8_t n = 1; n < ep_count; n++) {
     for (uint8_t d = 0; d < 2; d++) {
       dwc2_dep_t* dep = &dwc2->ep[d][n];
-      if (dep->ctl & EPCTL_EPENA) {
+      if (edpt_is_enabled(dep)) {
         dep->ctl |= EPCTL_SNAK | EPCTL_EPDIS;
       }
       xfer_status[n][1-d].max_size = 0;
@@ -566,7 +641,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
 }
 
 bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
-  TU_ASSERT(dfifo_alloc(rhport, ep_addr, largest_packet_size));
+  TU_ASSERT(dfifo_alloc(rhport, ep_addr, largest_packet_size, false));
   return true;
 }
 
@@ -577,13 +652,14 @@ bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpo
   return true;
 }
 
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes, bool is_isr) {
+  (void) is_isr;
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir = tu_edpt_dir(ep_addr);
   xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
   bool ret;
 
-  usbd_spin_lock(false);
+  usbd_spin_lock(is_isr);
 
   if (xfer->max_size == 0) {
     ret = false;  // Endpoint is closed
@@ -591,6 +667,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
     xfer->buffer = buffer;
     xfer->ff = NULL;
     xfer->total_len = total_bytes;
+    xfer->iso_retry = xfer->interval; // Reset ISO retry counter to interval value
 
     // EP0 can only handle one packet
     if (epnum == 0) {
@@ -602,7 +679,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
     ret = true;
   }
 
-  usbd_spin_unlock(false);
+  usbd_spin_unlock(is_isr);
 
   return ret;
 }
@@ -611,16 +688,14 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
 // bytes should be written and second to keep the return value free to give back a boolean
 // success message. If total_bytes is too big, the FIFO will copy only what is available
 // into the USB buffer!
-bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t total_bytes) {
-  // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
-  TU_ASSERT(ff->item_size == 1);
-
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t total_bytes, bool is_isr) {
+  (void) is_isr;
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir = tu_edpt_dir(ep_addr);
   xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
   bool ret;
 
-  usbd_spin_lock(false);
+  usbd_spin_lock(is_isr);
 
   if (xfer->max_size == 0) {
     ret = false;  // Endpoint is closed
@@ -628,6 +703,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
     xfer->buffer = NULL;
     xfer->ff = ff;
     xfer->total_len = total_bytes;
+    xfer->iso_retry = xfer->interval; // Reset ISO retry counter to interval value
 
     // Schedule packets to be sent within interrupt
     // TODO xfer fifo may only available for slave mode
@@ -635,7 +711,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
     ret = true;
   }
 
-  usbd_spin_unlock(false);
+  usbd_spin_unlock(is_isr);
 
   return ret;
 }
@@ -643,8 +719,12 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   edpt_disable(rhport, ep_addr, true);
-  if((tu_edpt_number(ep_addr) == 0) && dma_device_enabled(dwc2)) {
-    dma_setup_prepare(rhport);
+
+  // For control endpoint, prepare to receive SETUP packet
+  if (tu_edpt_number(ep_addr) == 0) {
+    if (dma_device_enabled(dwc2)) {
+      dma_setup_prepare(rhport);
+    }
   }
 }
 
@@ -681,8 +761,9 @@ static void handle_bus_reset(uint8_t rhport) {
 
   // Disable all IN endpoints
   for (uint8_t n = 0; n < ep_count; n++) {
-    if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
-      dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
+    dwc2_dep_t* dep = &dwc2->epin[n];
+    if (edpt_is_enabled(dep)) {
+      dep->diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
     }
   }
 
@@ -701,20 +782,33 @@ static void handle_bus_reset(uint8_t rhport) {
   dcfg.address = 0;
   dwc2->dcfg = dcfg.value;
 
-  // Fixed both control EP0 size to 64 bytes
-  dwc2->epin[0].ctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
-  dwc2->epout[0].ctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos);
+  // 6. Configure maximum packet size for EP0
+  uint8_t mps = 0;
+  switch (CFG_TUD_ENDPOINT0_SIZE) {
+    case 8: mps = 3; break;
+    case 16: mps = 2; break;
+    case 32: mps = 1; break;
+    case 64: mps = 0; break;
+    default: mps = 0; break;
+  }
+
+  dwc2->epin[0].ctl &= ~DIEPCTL0_MPSIZ_Msk;
+  dwc2->epout[0].ctl &= ~DOEPCTL0_MPSIZ_Msk;
+  dwc2->epin[0].ctl |= mps << DIEPCTL0_MPSIZ_Pos;
+  dwc2->epout[0].ctl |= mps << DOEPCTL0_MPSIZ_Pos;
 
-  xfer_status[0][TUSB_DIR_OUT].max_size = 64;
-  xfer_status[0][TUSB_DIR_IN].max_size = 64;
+  xfer_status[0][TUSB_DIR_OUT].max_size = CFG_TUD_ENDPOINT0_SIZE;
+  xfer_status[0][TUSB_DIR_IN].max_size = CFG_TUD_ENDPOINT0_SIZE;
 
+  uint32_t gintmsk = GINTMSK_OTGINT | GINTMSK_IEPINT | GINTMSK_IISOIXFRM;
   if(dma_device_enabled(dwc2)) {
+    gintmsk |= GINTMSK_OEPINT;
     dma_setup_prepare(rhport);
   } else {
     dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
   }
 
-  dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
+  dwc2->gintmsk |= gintmsk;
 }
 
 static void handle_enum_done(uint8_t rhport) {
@@ -760,95 +854,137 @@ TU_ATTR_ALWAYS_INLINE static inline void print_doepint(uint32_t doepint) {
 #endif
 
 #if CFG_TUD_DWC2_SLAVE_ENABLE
+static uint16_t epin_write_tx_fifo(dwc2_regs_t *dwc2, uint8_t epnum) {
+  dwc2_dep_t *const epin = &dwc2->ep[0][epnum];
+  xfer_ctl_t *const xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
+
+  dwc2_ep_tsize_t tsiz           = {.value = epin->tsiz};
+  const uint16_t  remain_packets = tsiz.packet_count;
+
+  uint16_t total_bytes_written = 0;
+  // Process every single packet (only whole packets can be written to fifo)
+  for (uint16_t i = 0; i < remain_packets; i++) {
+    tsiz.value                  = epin->tsiz;
+    const uint16_t remain_bytes = (uint16_t)tsiz.xfer_size;
+    const uint16_t xact_bytes   = tu_min16(remain_bytes, xfer->max_size);
+
+    // Check if dtxfsts has enough space available
+    if (xact_bytes > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) {
+      break;
+    }
+
+    // Push packet to Tx-FIFO
+    volatile uint32_t *tx_fifo = dwc2->fifo[epnum];
+    if (xfer->ff) {
+      tu_hwfifo_write_from_fifo(tx_fifo, xfer->ff, xact_bytes, NULL);
+      total_bytes_written += xact_bytes;
+    } else {
+      tu_hwfifo_write(tx_fifo, xfer->buffer, xact_bytes, NULL);
+      xfer->buffer += xact_bytes;
+      total_bytes_written += xact_bytes;
+    }
+  }
+  return total_bytes_written;
+}
+
 // Process shared receive FIFO, this interrupt is only used in Slave mode
 static void handle_rxflvl_irq(uint8_t rhport) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   const volatile uint32_t* rx_fifo = dwc2->fifo[0];
 
+  // DWC2 v3.10a (e.g. STM32L476) emits an extra EP0 RX_COMPLETE that is NOT a real OUT data transfer completion, in two
+  // situations - each flagged by a DOEPINT bit set on that word:
+  // - DOEPINT.STPKTRX (Setup Packet Received): pushed between SETUP_RX and SETUP_DONE of every control transfer.
+  // - DOEPINT.STSPHSRX (Status Phase Received for control write): pushed after the OUT data stage when the host
+  //   starts the IN status phase.
+  // Both are dropped in the RX_COMPLETE case below, clearing the flag (W1C) so a latched STSPHSRX
+  // does not block the core from emitting the next SETUP_DONE. usbd still processes the real OUT data
+  // and queues the IN status ZLP itself - the core does not auto-complete the control-write status.
+  const bool quirk_v310a = (dwc2->gsnpsid == DWC2_CORE_REV_3_10a);
+
   // Pop control word off FIFO
   const dwc2_grxstsp_t grxstsp = {.value = dwc2->grxstsp};
+  const uint8_t packet_status = grxstsp.packet_status;
   const uint8_t epnum = grxstsp.ep_ch_num;
 
   dwc2_dep_t* epout = &dwc2->epout[epnum];
 
-  switch (grxstsp.packet_status) {
+  switch (packet_status) {
     case GRXSTS_PKTSTS_GLOBAL_OUT_NAK:
       // Global OUT NAK: do nothing
       break;
 
     case GRXSTS_PKTSTS_SETUP_RX: {
       // Setup packet received
-      uint32_t* setup = (uint32_t*)(uintptr_t) _dcd_usbbuf.setup_packet;
+      uint32_t * setup = (uint32_t*)(uintptr_t) _dcd_usbbuf.setup_buffer;
       // We can receive up to three setup packets in succession, but only the last one is valid.
       setup[0] = (*rx_fifo);
       setup[1] = (*rx_fifo);
       break;
     }
 
-    case GRXSTS_PKTSTS_SETUP_DONE:
-      // Setup packet done:
-      // After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq()
+    case GRXSTS_PKTSTS_SETUP_DONE: {
+      // Pop this word causes the Setup interrupt
       epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+      epout->doepint = DOEPINT_SETUP | DOEPINT_STPKTRX; // Clear SETUP interrupt, required for core to re-write this control word
+      if (edpt_is_enabled(&dwc2->epin[0])) {
+        edpt_disable(rhport, 0x80, false);
+      }
+      dcd_event_setup_received(rhport, _dcd_usbbuf.setup_buffer, true);
       break;
+    }
 
     case GRXSTS_PKTSTS_RX_DATA: {
       // Out packet received
       const uint16_t byte_count = grxstsp.byte_count;
       xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
 
-      if (byte_count) {
+      if (byte_count != 0) {
         // Read packet off RxFIFO
-        if (xfer->ff) {
-          tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, byte_count);
+        if (xfer->ff != NULL) {
+          tu_hwfifo_read_to_fifo(rx_fifo, xfer->ff, byte_count, NULL);
         } else {
-          dfifo_read_packet(dwc2, xfer->buffer, byte_count);
+          tu_hwfifo_read(rx_fifo, xfer->buffer, byte_count, NULL);
           xfer->buffer += byte_count;
         }
+      }
 
-        // short packet, minus remaining bytes (xfer_size)
-        if (byte_count < xfer->max_size) {
-          const dwc2_ep_tsize_t tsiz = {.value = epout->tsiz};
-          xfer->total_len -= tsiz.xfer_size;
-          if (epnum == 0) {
-            xfer->total_len -= _dcd_data.ep0_pending[TUSB_DIR_OUT];
-            _dcd_data.ep0_pending[TUSB_DIR_OUT] = 0;
-          }
+      // short packet (including ZLP when byte_count == 0), minus remaining bytes (xfer_size)
+      if (byte_count < xfer->max_size) {
+        const dwc2_ep_tsize_t tsiz = {.value = epout->tsiz};
+        xfer->total_len -= tsiz.xfer_size;
+        if (epnum == 0) {
+          _dcd_data.ep0_pending[TUSB_DIR_OUT] = 0;
         }
       }
       break;
     }
 
-    case GRXSTS_PKTSTS_RX_COMPLETE:
-      // Out packet done
-      // After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on
-      // the specified OUT endpoint which will be handled by handle_epout_irq()
-      break;
-
-    default: break;
-  }
-}
+    case GRXSTS_PKTSTS_RX_COMPLETE: {
+      // Pop this word causes the xfer complete interrupt
+      const uint32_t doepint = epout->doepint;
+      epout->doepint = DOEPINT_XFRC;
 
-static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) {
-  if (doepint_bm.setup_phase_done) {
-    dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true);
-    return;
-  }
+      // v3.10a quirk (see top of function): the extra RX_COMPLETE flagged with Setup Packet Received (STPKTRX) or
+      // Status Phase Received for control write (STSPHSRX) is not a real OUT completion. Drop it
+      if (quirk_v310a) {
+        if (doepint & (DOEPINT_STPKTRX | DOEPINT_STSPHSRX)) {
+          epout->doepint = DOEPINT_STPKTRX | DOEPINT_STSPHSRX;
+          break;
+        }
+      }
 
-  // Normal OUT transfer complete
-  if (doepint_bm.xfer_complete) {
-    // only handle data skip if it is setup or status related
-    // Note: even though (xfer_complete + status_phase_rx) is for buffered DMA only, for STM32L47x (dwc2 v3.00a) they
-    // can is set when GRXSTS_PKTSTS_SETUP_RX is popped therefore they can bet set before/together with setup_phase_done
-    if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) {
       xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
-
-      if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_OUT]) {
-        // EP0 can only handle one packet, Schedule another packet to be received.
-        edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT);
+      if (epnum == 0 && _dcd_data.ep0_pending[TUSB_DIR_OUT] > 0) {
+        // EP0 can only handle one packet, schedule another packet to be received.
+        edpt_schedule_packets(rhport, 0, TUSB_DIR_OUT);
       } else {
         dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
       }
+      break;
     }
+
+    default: break; // nothing to do
   }
 }
 
@@ -858,7 +994,7 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep
   xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
 
   if (diepint_bm.xfer_complete) {
-    if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_IN]) {
+    if ((epnum == 0) && (0 != _dcd_data.ep0_pending[TUSB_DIR_IN])) {
       // EP0 can only handle one packet. Schedule another packet to be transmitted.
       edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN);
     } else {
@@ -869,35 +1005,13 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep
   // TX FIFO empty bit is read-only. It will only be cleared by hardware when written bytes is more than
   // - 64 bytes or
   // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL)
-  if (diepint_bm.txfifo_empty && (dwc2->diepempmsk & (1 << epnum))) {
-    dwc2_ep_tsize_t tsiz = {.value = epin->tsiz};
-    const uint16_t remain_packets = tsiz.packet_count;
-
-    // Process every single packet (only whole packets can be written to fifo)
-    for (uint16_t i = 0; i < remain_packets; i++) {
-      tsiz.value = epin->tsiz;
-      const uint16_t remain_bytes = (uint16_t) tsiz.xfer_size;
-      const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size);
-
-      // Check if dtxfsts has enough space available
-      if (xact_bytes > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) {
-        break;
-      }
-
-      // Push packet to Tx-FIFO
-      if (xfer->ff) {
-        volatile uint32_t* tx_fifo = dwc2->fifo[epnum];
-        tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*)(uintptr_t)tx_fifo, xact_bytes);
-      } else {
-        dfifo_write_packet(dwc2, epnum, xfer->buffer, xact_bytes);
-        xfer->buffer += xact_bytes;
-      }
-    }
+  if (diepint_bm.txfifo_empty && tu_bit_test(dwc2->diepempmsk, epnum)) {
+    epin_write_tx_fifo(dwc2, epnum);
 
     // Turn off TXFE if all bytes are written.
-    tsiz.value = epin->tsiz;
+    dwc2_ep_tsize_t tsiz = {.value = epin->tsiz};
     if (tsiz.xfer_size == 0) {
-      dwc2->diepempmsk &= ~(1 << epnum);
+      dwc2->diepempmsk &= ~(1u << epnum);
     }
   }
 }
@@ -908,9 +1022,24 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   if (doepint_bm.setup_phase_done) {
-    dma_setup_prepare(rhport);
-    dcd_dcache_invalidate(_dcd_usbbuf.setup_packet, 8);
-    dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true);
+    // Cleanup previous pending EP0 IN transfer if any
+    dwc2_dep_t* epin0 = &dwc2->epin[0];
+    dwc2_dep_t* epout0 = &dwc2->epout[0];
+    if (edpt_is_enabled(epin0)) {
+      edpt_disable(rhport, 0x80, false);
+    }
+
+    dcd_dcache_invalidate(_dcd_usbbuf.setup_buffer, sizeof(_dcd_usbbuf.setup_buffer));
+
+    // DOEPDMA0 has advanced past the last received SETUP packet; back up one packet to the latest valid one
+    // (Programming Guide v4.20a section 9.1.2.1: "DOEPDMAn-8 provides the pointer to the last valid SETUP data")
+    tusb_control_request_t *setup_packet = (tusb_control_request_t *) (uintptr_t) (epout0->doepdma - sizeof(tusb_control_request_t));
+    dcd_event_setup_received(rhport, (uint8_t*)setup_packet, true);
+
+    // Prepare EP0 for next setup if this setup has no data stage
+    if (setup_packet->wLength == 0) {
+      dma_setup_prepare(rhport);
+    }
     return;
   }
 
@@ -931,9 +1060,8 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
         const uint16_t remain = tsiz.xfer_size;
         xfer->total_len -= remain;
 
-        // this is ZLP, so prepare EP0 for next setup
-        // TODO use status phase rx
-        if(epnum == 0 && xfer->total_len == 0) {
+        // prepare EP0 for next setup
+        if(epnum == 0) {
           dma_setup_prepare(rhport);
         }
 
@@ -952,9 +1080,6 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin
       // EP0 can only handle one packet. Schedule another packet to be transmitted.
       edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN);
     } else {
-      if(epnum == 0) {
-        dma_setup_prepare(rhport);
-      }
       dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
     }
   }
@@ -971,7 +1096,7 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
   // DAINT for a given EP clears when DEPINTx is cleared.
   // EPINT will be cleared when DAINT bits are cleared.
   for (uint8_t epnum = 0; epnum < ep_count; epnum++) {
-    if (dwc2->daint & TU_BIT(daint_offset + epnum)) {
+    if (tu_bit_test(dwc2->daint,daint_offset + epnum)) {
       dwc2_dep_t* epout = &ep_base[epnum];
       union {
         uint32_t value;
@@ -980,7 +1105,7 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
       } intr;
       intr.value = epout->intr;
 
-      epout->intr = intr.value; // Clear interrupt
+      epout->intr = intr.value; // Clear interrupt //-V::2584::{otg_int}
 
       if (is_dma) {
         #if CFG_TUD_DWC2_DMA_ENABLE
@@ -995,7 +1120,7 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
         if (dir == TUSB_DIR_IN) {
           handle_epin_slave(rhport, epnum, intr.diepint_bm);
         } else {
-          handle_epout_slave(rhport, epnum, intr.doepint_bm);
+          // epout is handled in handle_rxflvl_irq
         }
         #endif
       }
@@ -1003,6 +1128,44 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
   }
 }
 
+static void handle_incomplete_iso_in(uint8_t rhport) {
+  dwc2_regs_t      *dwc2    = DWC2_REG(rhport);
+  const dwc2_dsts_t dsts    = {.value = dwc2->dsts};
+  const uint32_t    odd_now = dsts.frame_number & 1u;
+
+  // Loop over all IN endpoints
+  const uint8_t ep_count = dwc2_ep_count(dwc2);
+  for (uint8_t epnum = 0; epnum < ep_count; epnum++) {
+    dwc2_dep_t   *epin   = &dwc2->epin[epnum];
+    dwc2_depctl_t depctl = {.value = epin->diepctl};
+    // Read DSTS and DIEPCTLn for all isochronous endpoints. If the current EP is enabled and the read value of
+    // DSTS.SOFFN is the targeted uframe number for this EP, then this EP has an incomplete transfer.
+    if (depctl.enable && depctl.type == DEPCTL_EPTYPE_ISOCHRONOUS && depctl.dpid_iso_odd == odd_now) {
+      xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
+      if (xfer->iso_retry > 0) {
+        xfer->iso_retry--;
+        // Restart ISO transfe: re-write TSIZ and CTL
+        dwc2_ep_tsize_t deptsiz = {.value = 0};
+        deptsiz.xfer_size       = xfer->total_len;
+        deptsiz.packet_count    = tu_div_ceil(xfer->total_len, xfer->max_size);
+        epin->tsiz              = deptsiz.value;
+
+        if (odd_now) {
+          depctl.set_data0_iso_even = 1;
+        } else {
+          depctl.set_data1_iso_odd = 1;
+        }
+        epin->diepctl = depctl.value;
+      } else {
+        // too many retries, give up, but keep endpoint activated
+        edpt_disable(rhport, epnum | TUSB_DIR_IN_MASK, false);
+        epin->diepctl |= DIEPCTL_USBAEP;
+        dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, 0, XFER_RESULT_FAILED, true);
+      }
+    }
+  }
+}
+
 /* Interrupt Hierarchy
                  DIEPINT  DIEPINT
                     \       /
@@ -1032,6 +1195,8 @@ void dcd_int_handler(uint8_t rhport) {
   if (gintsts & GINTSTS_ENUMDNE) {
     // ENUMDNE is the end of reset where speed of the link is detected
     dwc2->gintsts = GINTSTS_ENUMDNE;
+    // There may be a pending suspend event, so we clear it first
+    dwc2->gintsts = GINTSTS_USBSUSP;
     dwc2->gintmsk |= GINTMSK_USBSUSPM;
     handle_enum_done(rhport);
   }
@@ -1056,13 +1221,14 @@ void dcd_int_handler(uint8_t rhport) {
     const uint32_t otg_int = dwc2->gotgint;
 
     if (otg_int & GOTGINT_SEDET) {
+      dwc2->gintmsk &= ~GINTMSK_OTGINT;
       dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
     }
 
     dwc2->gotgint = otg_int;
   }
 
-  if(gintsts & GINTSTS_SOF) {
+  if(gintsts & GINTSTS_SOF && dwc2->gintmsk & GINTMSK_SOFM) {
     dwc2->gintsts = GINTSTS_SOF;
     dwc2->gintmsk |= GINTMSK_USBSUSPM;
     const uint32_t frame = (dwc2->dsts & DSTS_FNSOF) >> DSTS_FNSOF_Pos;
@@ -1075,6 +1241,12 @@ void dcd_int_handler(uint8_t rhport) {
     dcd_event_sof(rhport, frame, true);
   }
 
+  // IN endpoint interrupt handling.
+  if (gintsts & GINTSTS_IEPINT) {
+    // IEPINT bit read-only, clear using DIEPINTn
+    handle_ep_irq(rhport, TUSB_DIR_IN);
+  }
+
 #if CFG_TUD_DWC2_SLAVE_ENABLE
   // RxFIFO non-empty interrupt handling.
   if (gintsts & GINTSTS_RXFLVL) {
@@ -1089,16 +1261,18 @@ void dcd_int_handler(uint8_t rhport) {
   }
 #endif
 
+#if CFG_TUD_DWC2_DMA_ENABLE
   // OUT endpoint interrupt handling.
   if (gintsts & GINTSTS_OEPINT) {
     // OEPINT is read-only, clear using DOEPINTn
     handle_ep_irq(rhport, TUSB_DIR_OUT);
   }
+#endif
 
-  // IN endpoint interrupt handling.
-  if (gintsts & GINTSTS_IEPINT) {
-    // IEPINT bit read-only, clear using DIEPINTn
-    handle_ep_irq(rhport, TUSB_DIR_IN);
+  // Incomplete isochronous IN transfer interrupt handling.
+  if (gintsts & GINTSTS_IISOIXFR) {
+    dwc2->gintsts = GINTSTS_IISOIXFR;
+    handle_incomplete_iso_in(rhport);
   }
 }
 
diff --git a/src/portable/synopsys/dwc2/dwc2_at32.h b/src/portable/synopsys/dwc2/dwc2_at32.h
index 37b6592c4..85fa9b20b 100644
--- a/src/portable/synopsys/dwc2/dwc2_at32.h
+++ b/src/portable/synopsys/dwc2/dwc2_at32.h
@@ -32,90 +32,108 @@
 
 #if CFG_TUSB_MCU == OPT_MCU_AT32F415
   #include <at32f415.h>
-  #define OTG1_FIFO_SIZE           1280
+  #define OTG1_DFIFO_DEPTH           320
   #define OTG1_IRQn                OTGFS1_IRQn
   #define DWC2_OTG1_REG_BASE       0x50000000UL
 #elif CFG_TUSB_MCU == OPT_MCU_AT32F435_437
   #include <at32f435_437.h>
-  #define OTG1_FIFO_SIZE           1280
-  #define OTG2_FIFO_SIZE           1280
+  #define OTG1_DFIFO_DEPTH           320
+  #define OTG2_DFIFO_DEPTH           320
   #define OTG1_IRQn                OTGFS1_IRQn
   #define OTG2_IRQn                OTGFS2_IRQn
   #define DWC2_OTG1_REG_BASE       0x50000000UL
   #define DWC2_OTG2_REG_BASE       0x40040000UL
 #elif CFG_TUSB_MCU == OPT_MCU_AT32F423
   #include <at32f423.h>
-  #define OTG1_FIFO_SIZE           1280
+  #define OTG1_DFIFO_DEPTH           320
   #define OTG1_IRQn                OTGFS1_IRQn
   #define DWC2_OTG1_REG_BASE       0x50000000UL
 #elif CFG_TUSB_MCU == OPT_MCU_AT32F402_405
   #include <at32f402_405.h>
-  #define OTG1_FIFO_SIZE           1280
-  #define OTG2_FIFO_SIZE           4096
+  #define OTG1_DFIFO_DEPTH           320
+  #define OTG2_DFIFO_DEPTH           1024
   #define OTG1_IRQn                OTGFS1_IRQn
   #define OTG2_IRQn                OTGHS_IRQn
   #define DWC2_OTG1_REG_BASE       0x50000000UL
   #define DWC2_OTG2_REG_BASE       0x40040000UL //OTGHS
 #elif CFG_TUSB_MCU == OPT_MCU_AT32F425
   #include <at32f425.h>
-  #define OTG1_FIFO_SIZE           1280
+  #define OTG1_DFIFO_DEPTH           320
+  #define OTG1_IRQn                OTGFS1_IRQn
+  #define DWC2_OTG1_REG_BASE       0x50000000UL
+#elif CFG_TUSB_MCU == OPT_MCU_AT32F45X
+  #include <at32f45x.h>
+  #define OTG1_DFIFO_DEPTH           320
   #define OTG1_IRQn                OTGFS1_IRQn
   #define DWC2_OTG1_REG_BASE       0x50000000UL
 #endif
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
- static const dwc2_controller_t _dwc2_controller[] = {
-{.reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE},
+static const dwc2_controller_t _dwc2_controller[] = {
+    {.reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .otg_dfifo_depth = OTG1_DFIFO_DEPTH},
 #if defined DWC2_OTG2_REG_BASE
-  {.reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE}
+    {.reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .otg_dfifo_depth = OTG2_DFIFO_DEPTH}
 #endif
- };
+};
+
+// MCU specific to enable dwc2 clock/power before any access to register
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_clock_init(uint8_t rhport, tusb_role_t role) {
+  (void) rhport;
+  (void) role;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
+  (void) role;
+  const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
+  if (enabled) {
+    NVIC_EnableIRQ(irqn);
+  } else {
+    NVIC_DisableIRQ(irqn);
+  }
+}
 
- TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
-   (void) role;
-   const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
-   if (enabled) {
-     NVIC_EnableIRQ(irqn);
-   } else {
-     NVIC_DisableIRQ(irqn);
-   }
- }
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) {
+  NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
+}
 
- TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
- }
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
+  NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
+}
 
- TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
-   NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
- }
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
+  // try to delay for 1 ms
+  uint32_t count = system_core_clock / 1000;
+  while (count--) __asm volatile("nop");
+}
 
- TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
-   // try to delay for 1 ms
-   uint32_t count = system_core_clock / 1000;
-   while (count--) __asm volatile("nop");
- }
+// MCU specific PHY init, called BEFORE core reset
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
+  (void) dwc2;
+  // Enable on-chip HS PHY
+  if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) {
+  } else if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
+  }
+}
 
- // MCU specific PHY init, called BEFORE core reset
- TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
-   (void) dwc2;
-   // Enable on-chip HS PHY
-   if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) {
-   } else if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
-   }
- }
+// MCU specific PHY deinit, disable PHY power
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
+  (void) hs_phy_type;
+  dwc2->stm32_gccfg &= ~(STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN);
+}
 
- // MCU specific PHY update, it is called AFTER init() and core reset
- TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
-   (void) dwc2;
-   (void) hs_phy_type;
+// MCU specific PHY update, it is called AFTER init() and core reset
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
+  (void) dwc2;
+  (void) hs_phy_type;
 
-   dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN;
- }
+  dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN;
+}
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* DWC2_GD32_H_ */
+#endif /* DWC2_AT32_H_ */
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index e5824606a..91cae821e 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_DWC2_BCM_H_
-#define _TUSB_DWC2_BCM_H_
+#ifndef TUSB_DWC2_BCM_H_
+#define TUSB_DWC2_BCM_H_
 
 #ifdef __cplusplus
  extern "C" {
@@ -39,13 +39,19 @@
 
 static const dwc2_controller_t _dwc2_controller[] =
 {
-  { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 16384 }
+  { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .otg_dfifo_depth = 4096 }
 };
 
 #define dcache_clean(_addr, _size)              data_clean(_addr, _size)
 #define dcache_invalidate(_addr, _size)         data_invalidate(_addr, _size)
 #define dcache_clean_invalidate(_addr, _size)   data_clean_and_invalidate(_addr, _size)
 
+// MCU specific to enable dwc2 clock/power before any access to register
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_clock_init(uint8_t rhport, tusb_role_t role) {
+  (void) rhport;
+  (void) role;
+}
+
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
@@ -73,6 +79,13 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
   // nothing to do
 }
 
+// MCU specific PHY deinit, disable PHY power
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
+  (void) dwc2;
+  (void) hs_phy_type;
+  // nothing to do
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c
index 5ff18ab94..33eabaeab 100644
--- a/src/portable/synopsys/dwc2/dwc2_common.c
+++ b/src/portable/synopsys/dwc2/dwc2_common.c
@@ -29,16 +29,6 @@
 #define DWC2_COMMON_DEBUG   2
 
 #if defined(TUP_USBIP_DWC2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED)
-
-#if CFG_TUD_ENABLED
-#include "device/dcd.h"
-#endif
-
-#if CFG_TUH_ENABLED
-#include "host/hcd.h"
-#include "host/usbh.h"
-#endif
-
 #include "dwc2_common.h"
 
 //--------------------------------------------------------------------
@@ -49,14 +39,11 @@ static void reset_core(dwc2_regs_t* dwc2) {
   while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {
   }
 
-  // load gsnpsid (it is not readable after reset is asserted)
-  const uint32_t gsnpsid = dwc2->gsnpsid;
-
-  // reset core
-  dwc2->grstctl |= GRSTCTL_CSRST;
+  const uint32_t gsnpsid = dwc2->gsnpsid; // preload gsnpsid which is not readable while resetting
+  dwc2->grstctl |= GRSTCTL_CSRST; // reset core
 
   if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
-    // prior v4.20a: CSRST is self-clearing and the core clears this bit after all the necessary logic is reset in
+    // prior v4.20a: CSRST is self-clearing, and the core clears this bit after all the necessary logic is reset in
     // the core, which can take several clocks, depending on the current state of the core. Once this bit has been
     // cleared, the software must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay).
     while (dwc2->grstctl & GRSTCTL_CSRST) {}
@@ -70,6 +57,7 @@ static void reset_core(dwc2_regs_t* dwc2) {
   while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} // wait for AHB master IDLE
 }
 
+// Dedicated FS PHY is internal with a clock 48Mhz.
 static void phy_fs_init(dwc2_regs_t* dwc2) {
   TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n");
 
@@ -96,6 +84,12 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
   dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
 }
 
+/* dwc2 has 2 highspeed PHYs options
+ * - UTMI+ is internal highspeed PHY, can be clocked at 30 Mhz (8-bit) or 60 Mhz (16-bit).
+ * - ULPI is external highspeed PHY, clocked at 60Mhz with 8-bit interface.
+ *
+ * In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz
+ */
 static void phy_hs_init(dwc2_regs_t* dwc2) {
   uint32_t gusbcfg = dwc2->gusbcfg;
   const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
@@ -189,32 +183,20 @@ static bool check_dwc2(dwc2_regs_t* dwc2) {
 //--------------------------------------------------------------------
 //
 //--------------------------------------------------------------------
-bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) {
-  (void)dwc2;
-#if CFG_TUD_ENABLED
-  if (role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) {
-    return false;
-  }
-#endif
-#if CFG_TUH_ENABLED
-  if (role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) {
-    return false;
-  }
-#endif
+bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, bool prefer_hs_phy) {
+  const dwc2_ghwcfg2_t ghwcfg2    = {.value = dwc2->ghwcfg2};
+  const bool           has_hs_phy = (ghwcfg2.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED);
 
-  const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
-  return ghwcfg2.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
+  if (prefer_hs_phy) {
+    return has_hs_phy;
+  } else {
+    const bool has_fs_phy = (ghwcfg2.fs_phy_type != GHWCFG2_FSPHY_NOT_SUPPORTED);
+    // false if has fs phy, otherwise true since hs phy is the only available phy
+    return !has_fs_phy && has_hs_phy;
+  }
 }
 
-/* dwc2 has several PHYs option
- * - UTMI+ is internal highspeed PHY, clock can be 30 Mhz (8-bit) or 60 Mhz (16-bit)
- * - ULPI is external highspeed PHY, clock is 60Mhz with only 8-bit interface
- * - Dedicated FS PHY is internal with clock 48Mhz.
- *
- * In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz
- *
-*/
-bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
+bool dwc2_core_init(uint8_t rhport, bool is_hs_phy, bool is_dma) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   // Check Synopsys ID register, failed if controller clock/power is not enabled
@@ -223,7 +205,7 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
   // disable global interrupt
   dwc2->gahbcfg &= ~GAHBCFG_GINT;
 
-  if (is_highspeed) {
+  if (is_hs_phy) {
     phy_hs_init(dwc2);
   } else {
     phy_fs_init(dwc2);
@@ -261,6 +243,24 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
   return true;
 }
 
+void dwc2_core_deinit(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  // Disable global interrupt
+  dwc2->gahbcfg &= ~GAHBCFG_GINT;
+
+  // Reset core: this also flushes FIFOs and clears all interrupt registers
+  reset_core(dwc2);
+
+  // Stop PHY clock and gate HCLK for power saving (per databook chapter 14)
+  dwc2->pcgcctl |= PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK;
+
+  // MCU-specific PHY deinit (disable PHY power)
+  const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
+  const uint8_t hs_phy_type = (dwc2->gusbcfg & GUSBCFG_PHYSEL) ? GHWCFG2_HSPHY_NOT_SUPPORTED : ghwcfg2.hs_phy_type;
+  dwc2_phy_deinit(dwc2, hs_phy_type);
+}
+
 // void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr) {
 //   (void) in_isr;
 //   dwc2_regs_t * const dwc2 = DWC2_REG(rhport);
@@ -274,58 +274,4 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
 //
 // }
 
-//--------------------------------------------------------------------
-// DFIFO
-//--------------------------------------------------------------------
-// Read a single data packet from receive DFIFO
-void dfifo_read_packet(dwc2_regs_t* dwc2, uint8_t* dst, uint16_t len) {
-  const volatile uint32_t* rx_fifo = dwc2->fifo[0];
-
-  // Reading full available 32 bit words from fifo
-  uint16_t word_count = len >> 2;
-  while (word_count--) {
-    tu_unaligned_write32(dst, *rx_fifo);
-    dst += 4;
-  }
-
-  // Read the remaining 1-3 bytes from fifo
-  const uint8_t bytes_rem = len & 0x03;
-  if (bytes_rem != 0) {
-    const uint32_t tmp = *rx_fifo;
-    dst[0] = tu_u32_byte0(tmp);
-    if (bytes_rem > 1) {
-      dst[1] = tu_u32_byte1(tmp);
-    }
-    if (bytes_rem > 2) {
-      dst[2] = tu_u32_byte2(tmp);
-    }
-  }
-}
-
-// Write a single data packet to DFIFO
-void dfifo_write_packet(dwc2_regs_t* dwc2, uint8_t fifo_num, const uint8_t* src, uint16_t len) {
-  volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num];
-
-  // Pushing full available 32 bit words to fifo
-  uint16_t word_count = len >> 2;
-  while (word_count--) {
-    *tx_fifo = tu_unaligned_read32(src);
-    src += 4;
-  }
-
-  // Write the remaining 1-3 bytes into fifo
-  const uint8_t bytes_rem = len & 0x03;
-  if (bytes_rem) {
-    uint32_t tmp_word = src[0];
-    if (bytes_rem > 1) {
-      tmp_word |= (src[1] << 8);
-    }
-    if (bytes_rem > 2) {
-      tmp_word |= (src[2] << 16);
-    }
-
-    *tx_fifo = tmp_word;
-  }
-}
-
 #endif
diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h
index 33219f786..5c4798d21 100644
--- a/src/portable/synopsys/dwc2/dwc2_common.h
+++ b/src/portable/synopsys/dwc2/dwc2_common.h
@@ -30,12 +30,23 @@
 #include "common/tusb_common.h"
 #include "dwc2_type.h"
 
-// Following symbols must be defined by port header
-// - _dwc2_controller[]: array of controllers
-// - DWC2_EP_MAX: largest EP counts of all controllers
-// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
-// - dwc2_dcd_int_enable/dwc2_dcd_int_disable
-// - dwc2_remote_wakeup_delay
+#if CFG_TUD_ENABLED
+#include "device/dcd.h"
+#endif
+
+#if CFG_TUH_ENABLED
+#include "host/hcd.h"
+#endif
+
+/* Following symbols must be defined by port header
+  - _dwc2_controller[]: array of controllers
+  - DWC2_EP_MAX: largest EP counts of all controllers
+  - dwc2_clock_init(): clock init call before
+  - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
+  - dwc2_phy_deinit(dwc2, hs_phy_type): phy deinit to disable PHY power, only deinit the phy used by core
+  - dwc2_dcd_int_enable/dwc2_dcd_int_disable
+  - dwc2_remote_wakeup_delay
+*/
 
 #if defined(TUP_USBIP_DWC2_STM32)
   #include "dwc2_stm32.h"
@@ -51,6 +62,8 @@
   #include "dwc2_xmc.h"
 #elif defined(TUP_USBIP_DWC2_AT32)
   #include "dwc2_at32.h"
+#elif defined(TUP_USBIP_DWC2_NRF)
+  #include "dwc2_nrf.h"
 #else
   #error "Unsupported MCUs"
 #endif
@@ -74,8 +87,10 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
   return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base;
 }
 
-bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role);
-bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma);
+// check if highspeed phy should be used
+bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, bool prefer_hs_phy);
+bool dwc2_core_init(uint8_t rhport, bool is_hs_phy, bool is_dma);
+void dwc2_core_deinit(uint8_t rhport);
 void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr);
 
 //--------------------------------------------------------------------+
@@ -84,13 +99,13 @@ void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr);
 TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t fnum) {
   // flush TX fifo and wait for it cleared
   dwc2->grstctl = GRSTCTL_TXFFLSH | (fnum << GRSTCTL_TXFNUM_Pos);
-  while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
+  while (0 != (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk)) {}
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) {
   // flush RX fifo and wait for it cleared
   dwc2->grstctl = GRSTCTL_RXFFLSH;
-  while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
+  while (0 != (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk)) {}
 }
 
 void dfifo_read_packet(dwc2_regs_t* dwc2, uint8_t* dst, uint16_t len);
diff --git a/src/portable/synopsys/dwc2/dwc2_efm32.h b/src/portable/synopsys/dwc2/dwc2_efm32.h
index 0e3570cbb..063360873 100644
--- a/src/portable/synopsys/dwc2/dwc2_efm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_efm32.h
@@ -40,9 +40,15 @@
 
 static const dwc2_controller_t _dwc2_controller[] =
 {
-  { .reg_base = DWC2_REG_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 2048 }
+  { .reg_base = DWC2_REG_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .otg_dfifo_depth = 512 }
 };
 
+// MCU specific to enable dwc2 clock/power before any access to register
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_clock_init(uint8_t rhport, tusb_role_t role) {
+  (void) rhport;
+  (void) role;
+}
+
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
@@ -72,6 +78,14 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
   USB->ROUTE = USB_ROUTE_PHYPEN;
 }
 
+// MCU specific PHY deinit, disable PHY power
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
+  (void) dwc2;
+  (void) hs_phy_type;
+  // Disable PHY pin
+  USB->ROUTE = 0;
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index a4e0d1770..436f8dc30 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -37,14 +37,18 @@
 
 #include "esp_intr_alloc.h"
 #include "soc/periph_defs.h"
+
+// ESP32-S31 does not have USB_WRAP peripheral (HS-only with UTMI PHY)
+#if !TU_CHECK_MCU(OPT_MCU_ESP32S31)
 #include "soc/usb_wrap_struct.h"
+#endif
 
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
 #define DWC2_FS_REG_BASE   0x60080000UL
 #define DWC2_EP_MAX        7
 
 static const dwc2_controller_t _dwc2_controller[] = {
-  { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 }
+  { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .otg_dfifo_depth = 256 }
 };
 
 #elif TU_CHECK_MCU(OPT_MCU_ESP32H4)
@@ -61,7 +65,7 @@ static const dwc2_controller_t _dwc2_controller[] = {
 #define DWC2_EP_MAX        7
 
 static const dwc2_controller_t _dwc2_controller[] = {
-  { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 }
+  { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .otg_dfifo_depth = 256 }
 };
 
 #elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
@@ -72,8 +76,16 @@ static const dwc2_controller_t _dwc2_controller[] = {
 // On ESP32 for consistency we associate
 // - Port0 to OTG_FS, and Port1 to OTG_HS
 static const dwc2_controller_t _dwc2_controller[] = {
-  { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
-  { .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
+  { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .otg_dfifo_depth = 256 },
+  { .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .otg_dfifo_depth = 1024 }
+};
+
+#elif TU_CHECK_MCU(OPT_MCU_ESP32S31)
+#define DWC2_HS_REG_BASE   0x20300000UL
+#define DWC2_EP_MAX        16
+
+static const dwc2_controller_t _dwc2_controller[] = {
+  { .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTGHS_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .otg_dfifo_depth = 1024 }
 };
 #endif
 
@@ -97,6 +109,12 @@ static void dwc2_int_handler_wrap(void* arg) {
 #endif
 }
 
+// MCU specific to enable dwc2 clock/power before any access to register
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_clock_init(uint8_t rhport, tusb_role_t role) {
+  (void) rhport;
+  (void) role;
+}
+
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
   if (enabled) {
     esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED,
@@ -121,6 +139,13 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_
 
 }
 
+// MCU specific PHY deinit, disable PHY power
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+  (void)dwc2;
+  (void)hs_phy_type;
+  // PHY managed by ESP-IDF
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   (void)dwc2;
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index 0375fffe4..28c3fde5e 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -37,7 +37,7 @@
 
 static const dwc2_controller_t _dwc2_controller[] =
 {
-  { .reg_base = DWC2_REG_BASE, .irqnum = 86, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1280 }
+  { .reg_base = DWC2_REG_BASE, .irqnum = 86, .ep_count = DWC2_EP_MAX, .otg_dfifo_depth = 320 }
 };
 
 extern uint32_t SystemCoreClock;
@@ -57,6 +57,12 @@ static inline void __eclic_disable_interrupt (uint32_t irq){
   *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0;
 }
 
+// MCU specific to enable dwc2 clock/power before any access to register
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_clock_init(uint8_t rhport, tusb_role_t role) {
+  (void) rhport;
+  (void) role;
+}
+
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
@@ -85,6 +91,13 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
   // nothing to do
 }
 
+// MCU specific PHY deinit, disable PHY power
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
+  (void) dwc2;
+  (void) hs_phy_type;
+  // nothing to do
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md
index f655e4dba..205684e4b 100644
--- a/src/portable/synopsys/dwc2/dwc2_info.md
+++ b/src/portable/synopsys/dwc2/dwc2_info.md
@@ -1,58 +1,58 @@
-|                            | AT32 F405 FS   | AT32 F405 HS   | AT32 F415   | BCM2711 (Pi4)   | EFM32GG      | ESP32-S2/S3   | ESP32-P4     | nRF54        | ST F207/F407/411/429 FS   | ST F407/429 HS   | ST F412/76x FS   | ST F723/L4P5 FS   | ST F723 HS   | ST F76x HS   | ST H743/H750   | ST L476 FS   | ST U5A5/H7RS/N6 HS   | XMC4500      | GD32VF103   |
-|:---------------------------|:---------------|:---------------|:------------|:----------------|:-------------|:--------------|:-------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:---------------------|:-------------|:------------|
-| GUID                       | 0x00002000     | 0x00000000     | 0x00001000  | 0x2708A000      | 0x00000000   | 0x00000000    | 0x00000000   | 0x00000000   | 0x00001200                | 0x00001100       | 0x00002000       | 0x00003000        | 0x00003100   | 0x00002100   | 0x00002300     | 0x00002000   | 0x00005000           | 0x00AEC000   | 0x00001000  |
-| GSNPSID                    | 0x4F54400A     | 0x4F54400A     | 0x4F54400A  | 0x4F54280A      | 0x4F54330A   | 0x4F54400A    | 0x4F54400A   | 0x4F54430A   | 0x4F54281A                | 0x4F54281A       | 0x4F54320A       | 0x4F54330A        | 0x4F54330A   | 0x4F54320A   | 0x4F54330A     | 0x4F54310A   | 0x4F54411A           | 0x4F54292A   | 0x00000000  |
-| - specs version            | 4.00a          | 4.00a          | 4.00a       | 2.80a           | 3.30a        | 4.00a         | 4.00a        | 4.30a        | 2.81a                     | 2.81a            | 3.20a            | 3.30a             | 3.30a        | 3.20a        | 3.30a          | 3.10a        | 4.11a                | 2.92a        | 0.00W       |
-| GHWCFG1                    | 0x00000000     | 0x00000000     | 0x00000000  | 0x00000000      | 0x00000000   | 0x00000000    | 0x00000000   | 0xAA555000   | 0x00000000                | 0x00000000       | 0x00000000       | 0x00000000        | 0x00000000   | 0x00000000   | 0x00000000     | 0x00000000   | 0x00000000           | 0x00000000   | 0x00000000  |
-| GHWCFG2                    | 0x228FDD00     | 0x229FDDD0     | 0x228DCD00  | 0x228DDD50      | 0x228F5910   | 0x224DD930    | 0x215FFFD0   | 0x228BFC72   | 0x229DCD20                | 0x229ED590       | 0x229ED520       | 0x229ED520        | 0x229FE1D0   | 0x229FE190   | 0x229FE190     | 0x229ED520   | 0x228FE052           | 0x228F5930   | 0x00000000  |
-| - op_mode                  | HNP SRP        | HNP SRP        | HNP SRP     | HNP SRP         | HNP SRP      | HNP SRP       | HNP SRP      | noHNP noSRP  | HNP SRP                   | HNP SRP          | HNP SRP          | HNP SRP           | HNP SRP      | HNP SRP      | HNP SRP        | HNP SRP      | noHNP noSRP          | HNP SRP      | HNP SRP     |
-| - arch                     | Slave only     | DMA internal   | Slave only  | DMA internal    | DMA internal | DMA internal  | DMA internal | DMA internal | Slave only                | DMA internal     | Slave only       | Slave only        | DMA internal | DMA internal | DMA internal   | Slave only   | DMA internal         | DMA internal | Slave only  |
-| - single_point             | hub            | hub            | hub         | hub             | hub          | n/a           | hub          | n/a          | n/a                       | hub              | n/a              | n/a               | hub          | hub          | hub            | n/a          | hub                  | n/a          | hub         |
-| - hs_phy_type              | n/a            | UTMI+/ULPI     | n/a         | UTMI+           | n/a          | n/a           | UTMI+/ULPI   | UTMI+        | n/a                       | ULPI             | n/a              | n/a               | UTMI+/ULPI   | ULPI         | ULPI           | n/a          | UTMI+                | n/a          | n/a         |
-| - fs_phy_type              | Dedicated      | Dedicated      | Dedicated   | Dedicated       | Dedicated    | Dedicated     | Shared ULPI  | n/a          | Dedicated                 | Dedicated        | Dedicated        | Dedicated         | Dedicated    | Dedicated    | Dedicated      | Dedicated    | n/a                  | Dedicated    | n/a         |
-| - num_dev_ep               | 7              | 7              | 3           | 7               | 6            | 6             | 15           | 15           | 3                         | 5                | 5                | 5                 | 8            | 8            | 8              | 5            | 8                    | 6            | 0           |
-| - num_host_ch              | 15             | 15             | 7           | 7               | 13           | 7             | 15           | 15           | 7                         | 11               | 11               | 11                | 15           | 15           | 15             | 11           | 15                   | 13           | 0           |
-| - period_channel_support   | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - enable_dynamic_fifo      | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - mul_proc_intrpt          | 0              | 1              | 0           | 0               | 0            | 0             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 0            | 0           |
-| - reserved21               | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - nptx_q_depth             | 8              | 8              | 8           | 8               | 8            | 4             | 4            | 8            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8                    | 8            | 2           |
-| - ptx_q_depth              | 8              | 8              | 8           | 8               | 8            | 8             | 4            | 8            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8                    | 8            | 2           |
-| - token_q_depth            | 8              | 8              | 8           | 8               | 8            | 8             | 8            | 8            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8                    | 8            | 0           |
-| - otg_enable_ic_usb        | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| GHWCFG3                    | 0x020004E8     | 0x03F006E8     | 0x020004E8  | 0x0FF000E8      | 0x01F204E8   | 0x00C804B5    | 0x03805EB5   | 0x0BEAC0E8   | 0x020001E8                | 0x03F403E8       | 0x0200D1E8       | 0x0200D1E8        | 0x03EED2E8   | 0x03EED2E8   | 0x03B8D2E8     | 0x0200D1E8   | 0x03B882E8           | 0x027A01E5   | 0x00000000  |
-| - xfer_size_width          | 8              | 8              | 8           | 8               | 8            | 5             | 5            | 8            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8                    | 5            | 0           |
-| - packet_size_width        | 6              | 6              | 6           | 6               | 6            | 3             | 3            | 6            | 6                         | 6                | 6                | 6                 | 6            | 6            | 6              | 6            | 6                    | 6            | 0           |
-| - otg_enable               | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - i2c_enable               | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 1                         | 1                | 1                | 1                 | 0            | 0            | 0              | 1            | 0                    | 1            | 0           |
-| - vendor_ctrl_itf          | 0              | 1              | 0           | 0               | 0            | 0             | 1            | 0            | 0                         | 1                | 0                | 0                 | 1            | 1            | 1              | 0            | 1                    | 0            | 0           |
-| - optional_feature_removed | 1              | 1              | 1           | 0               | 1            | 1             | 1            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - synch_reset              | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - otg_adp_support          | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0                         | 0                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 0            | 0           |
-| - otg_enable_hsic          | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - battery_charger_support  | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 1            | 0                         | 0                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 0            | 0           |
-| - lpm_mode                 | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                         | 0                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 0            | 0           |
-| - dfifo_depth              | 512            | 1008           | 512         | 4080            | 498          | 200           | 896          | 3050         | 512                       | 1012             | 512              | 512               | 1006         | 1006         | 952            | 512          | 952                  | 634          | 0           |
-| GHWCFG4                    | 0x1FF0A020     | 0x1FF0A020     | 0x0000000F  | 0x1FF00020      | 0x1BF08030   | 0xD3F0A030    | 0xDFF1A030   | 0x1E10AA60   | 0x0FF08030                | 0x17F00030       | 0x17F08030       | 0x17F08030        | 0x23F00030   | 0x23F00030   | 0xE3F00030     | 0x17F08030   | 0xE2103E30           | 0xDBF08030   | 0x00000000  |
-| - num_dev_period_in_ep     | 0              | 0              | 15          | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - partial_powerdown        | 0              | 0              | 0           | 0               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - ahb_freq_min             | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - hibernation              | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - extended_hibernation     | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - reserved8                | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - enhanced_lpm_support1    | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1                    | 0            | 0           |
-| - service_interval_flow    | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1                    | 0            | 0           |
-| - ipg_isoc_support         | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1                    | 0            | 0           |
-| - acg_support              | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1                    | 0            | 0           |
-| - enhanced_lpm_support     | 1              | 1              | 0           | 0               | 0            | 1             | 1            | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1                    | 0            | 0           |
-| - phy_data_width           | 8/16 bit       | 8/16 bit       | 8 bit       | 8 bit           | 8/16 bit     | 8/16 bit      | 8/16 bit     | 8/16 bit     | 8/16 bit                  | 8 bit            | 8/16 bit         | 8/16 bit          | 8 bit        | 8 bit        | 8 bit          | 8/16 bit     | 8 bit                | 8/16 bit     | 8 bit       |
-| - ctrl_ep_num              | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - iddg_filter              | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - vbus_valid_filter        | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 1            | 0           |
-| - a_valid_filter           | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 1            | 0           |
-| - b_valid_filter           | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 1            | 0           |
-| - session_end_filter       | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 1            | 0           |
-| - dedicated_fifos          | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - num_dev_in_eps           | 7              | 7              | 0           | 7               | 6            | 4             | 7            | 7            | 3                         | 5                | 5                | 5                 | 8            | 8            | 8              | 5            | 8                    | 6            | 0           |
-| - dma_desc_enable          | 0              | 0              | 0           | 0               | 0            | 1             | 1            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 1              | 0            | 1                    | 1            | 0           |
-| - dma_desc_dynamic         | 0              | 0              | 0           | 0               | 0            | 1             | 1            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 1              | 0            | 1                    | 1            | 0           |
+|                            | AT32 F405 FS   | AT32 F405 HS   | AT32 F415   | BCM2711 (Pi4)   | EFM32GG      | ESP32-S2/S3   | ESP32-P4     | nRF54H20     | nRF54LM20    | ST F407/429 HS   | ST F207/F407/411/429 FS   | ST L476 FS   | ST F412/76x FS   | ST F76x HS   | ST H743/H750   | ST F723/L4P5 FS   | ST F723 HS   | ST H7RS FS   | ST U5A5/H7RS/N6 HS   | XMC4500      | GD32VF103   |
+|:---------------------------|:---------------|:---------------|:------------|:----------------|:-------------|:--------------|:-------------|:-------------|:-------------|:-----------------|:--------------------------|:-------------|:-----------------|:-------------|:---------------|:------------------|:-------------|:-------------|:---------------------|:-------------|:------------|
+| GUID                       | 0x00002000     | 0x00000000     | 0x00001000  | 0x2708A000      | 0x00000000   | 0x00000000    | 0x00000000   | 0x00000000   | 0x00000000   | 0x00001100       | 0x00001200                | 0x00002000   | 0x00002000       | 0x00002100   | 0x00002300     | 0x00003000        | 0x00003100   | 0x00004000   | 0x00005000           | 0x00AEC000   | 0x00001000  |
+| GSNPSID                    | 0x4F54400A     | 0x4F54400A     | 0x4F54400A  | 0x4F54280A      | 0x4F54330A   | 0x4F54400A    | 0x4F54400A   | 0x4F54430A   | 0x4F54500B   | 0x4F54281A       | 0x4F54281A                | 0x4F54310A   | 0x4F54320A       | 0x4F54320A   | 0x4F54330A     | 0x4F54330A        | 0x4F54330A   | 0x4F54411A   | 0x4F54411A           | 0x4F54292A   | 0x00000000  |
+| - specs version            | 4.00a          | 4.00a          | 4.00a       | 2.80a           | 3.30a        | 4.00a         | 4.00a        | 4.30a        | 5.00b        | 2.81a            | 2.81a                     | 3.10a        | 3.20a            | 3.20a        | 3.30a          | 3.30a             | 3.30a        | 4.11a        | 4.11a                | 2.92a        | 0.00W       |
+| GHWCFG1                    | 0x00000000     | 0x00000000     | 0x00000000  | 0x00000000      | 0x00000000   | 0x00000000    | 0x00000000   | 0xAA555000   | 0x00000000   | 0x00000000       | 0x00000000                | 0x00000000   | 0x00000000       | 0x00000000   | 0x00000000     | 0x00000000        | 0x00000000   | 0x00000000   | 0x00000000           | 0x00000000   | 0x00000000  |
+| GHWCFG2                    | 0x228FDD00     | 0x229FDDD0     | 0x228DCD00  | 0x228DDD50      | 0x228F5910   | 0x224DD930    | 0x215FFFD0   | 0x228BFC72   | 0x22AFFC52   | 0x229ED590       | 0x229DCD20                | 0x229ED520   | 0x229ED520       | 0x229FE190   | 0x229FE190     | 0x229ED520        | 0x229FE1D0   | 0x229ED522   | 0x228FE052           | 0x228F5930   | 0x00000000  |
+| - op_mode                  | HNP SRP        | HNP SRP        | HNP SRP     | HNP SRP         | HNP SRP      | HNP SRP       | HNP SRP      | noHNP noSRP  | noHNP noSRP  | HNP SRP          | HNP SRP                   | HNP SRP      | HNP SRP          | HNP SRP      | HNP SRP        | HNP SRP           | HNP SRP      | noHNP noSRP  | noHNP noSRP          | HNP SRP      | HNP SRP     |
+| - arch                     | Slave only     | DMA internal   | Slave only  | DMA internal    | DMA internal | DMA internal  | DMA internal | DMA internal | DMA internal | DMA internal     | Slave only                | Slave only   | Slave only       | DMA internal | DMA internal   | Slave only        | DMA internal | Slave only   | DMA internal         | DMA internal | Slave only  |
+| - single_point             | hub            | hub            | hub         | hub             | hub          | n/a           | hub          | n/a          | hub          | hub              | n/a                       | n/a          | n/a              | hub          | hub            | n/a               | hub          | n/a          | hub                  | n/a          | hub         |
+| - hs_phy_type              | n/a            | UTMI+/ULPI     | n/a         | UTMI+           | n/a          | n/a           | UTMI+/ULPI   | UTMI+        | UTMI+        | ULPI             | n/a                       | n/a          | n/a              | ULPI         | ULPI           | n/a               | UTMI+/ULPI   | n/a          | UTMI+                | n/a          | n/a         |
+| - fs_phy_type              | Dedicated      | Dedicated      | Dedicated   | Dedicated       | Dedicated    | Dedicated     | Shared ULPI  | n/a          | n/a          | Dedicated        | Dedicated                 | Dedicated    | Dedicated        | Dedicated    | Dedicated      | Dedicated         | Dedicated    | Dedicated    | n/a                  | Dedicated    | n/a         |
+| - num_dev_ep               | 7              | 7              | 3           | 7               | 6            | 6             | 15           | 15           | 15           | 5                | 3                         | 5            | 5                | 8            | 8              | 5                 | 8            | 5            | 8                    | 6            | 0           |
+| - num_host_ch              | 15             | 15             | 7           | 7               | 13           | 7             | 15           | 15           | 15           | 11               | 7                         | 11           | 11               | 15           | 15             | 11                | 15           | 11           | 15                   | 13           | 0           |
+| - period_channel_support   | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 0            | 1            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - enable_dynamic_fifo      | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 1            | 1            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - mul_proc_intrpt          | 0              | 1              | 0           | 0               | 0            | 0             | 1            | 0            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 0                    | 0            | 0           |
+| - reserved21               | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 1            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - nptx_q_depth             | 8              | 8              | 8           | 8               | 8            | 4             | 4            | 8            | 8            | 8                | 8                         | 8            | 8                | 8            | 8              | 8                 | 8            | 8            | 8                    | 8            | 2           |
+| - ptx_q_depth              | 8              | 8              | 8           | 8               | 8            | 8             | 4            | 8            | 8            | 8                | 8                         | 8            | 8                | 8            | 8              | 8                 | 8            | 8            | 8                    | 8            | 2           |
+| - token_q_depth            | 8              | 8              | 8           | 8               | 8            | 8             | 8            | 8            | 8            | 8                | 8                         | 8            | 8                | 8            | 8              | 8                 | 8            | 8            | 8                    | 8            | 0           |
+| - otg_enable_ic_usb        | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| GHWCFG3                    | 0x020004E8     | 0x03F006E8     | 0x020004E8  | 0x0FF000E8      | 0x01F204E8   | 0x00C804B5    | 0x03805EB5   | 0x0BEAC0E8   | 0x0BE0C0E8   | 0x03F403E8       | 0x020001E8                | 0x0200D1E8   | 0x0200D1E8       | 0x03EED2E8   | 0x03B8D2E8     | 0x0200D1E8        | 0x03EED2E8   | 0x020081E8   | 0x03B882E8           | 0x027A01E5   | 0x00000000  |
+| - xfer_size_width          | 8              | 8              | 8           | 8               | 8            | 5             | 5            | 8            | 8            | 8                | 8                         | 8            | 8                | 8            | 8              | 8                 | 8            | 8            | 8                    | 5            | 0           |
+| - packet_size_width        | 6              | 6              | 6           | 6               | 6            | 3             | 3            | 6            | 6            | 6                | 6                         | 6            | 6                | 6            | 6              | 6                 | 6            | 6            | 6                    | 6            | 0           |
+| - otg_enable               | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 1            | 1            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - i2c_enable               | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0            | 1                | 1                         | 1            | 1                | 0            | 0              | 1                 | 0            | 1            | 0                    | 1            | 0           |
+| - vendor_ctrl_itf          | 0              | 1              | 0           | 0               | 0            | 0             | 1            | 0            | 0            | 1                | 0                         | 0            | 0                | 1            | 1              | 0                 | 1            | 0            | 1                    | 0            | 0           |
+| - optional_feature_removed | 1              | 1              | 1           | 0               | 1            | 1             | 1            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - synch_reset              | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - otg_adp_support          | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0            | 0                | 0                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 0            | 0           |
+| - otg_enable_hsic          | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - battery_charger_support  | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 1            | 1            | 0                | 0                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 0            | 0           |
+| - lpm_mode                 | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 1            | 0                | 0                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 0            | 0           |
+| - dfifo_depth              | 512            | 1008           | 512         | 4080            | 498          | 200           | 896          | 3050         | 3040         | 1012             | 512                       | 512          | 512              | 1006         | 952            | 512               | 1006         | 512          | 952                  | 634          | 0           |
+| GHWCFG4                    | 0x1FF0A020     | 0x1FF0A020     | 0x0000000F  | 0x1FF00020      | 0x1BF08030   | 0xD3F0A030    | 0xDFF1A030   | 0x1E10AA60   | 0x3E10AA60   | 0x17F00030       | 0x0FF08030                | 0x17F08030   | 0x17F08030       | 0x23F00030   | 0xE3F00030     | 0x17F08030        | 0x23F00030   | 0x1610B230   | 0xE2103E30           | 0xDBF08030   | 0x00000000  |
+| - num_dev_period_in_ep     | 0              | 0              | 15          | 0               | 0            | 0             | 0            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - partial_powerdown        | 0              | 0              | 0           | 0               | 1            | 1             | 1            | 0            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - ahb_freq_min             | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - hibernation              | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 1            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - extended_hibernation     | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - reserved8                | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - enhanced_lpm_support1    | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 1            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 1            | 1                    | 0            | 0           |
+| - service_interval_flow    | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 1                    | 0            | 0           |
+| - ipg_isoc_support         | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 1            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 1                    | 0            | 0           |
+| - acg_support              | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 1            | 1                    | 0            | 0           |
+| - enhanced_lpm_support     | 1              | 1              | 0           | 0               | 0            | 1             | 1            | 1            | 1            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 1            | 1                    | 0            | 0           |
+| - phy_data_width           | 8/16 bit       | 8/16 bit       | 8 bit       | 8 bit           | 8/16 bit     | 8/16 bit      | 8/16 bit     | 8/16 bit     | 8/16 bit     | 8 bit            | 8/16 bit                  | 8/16 bit     | 8/16 bit         | 8 bit        | 8 bit          | 8/16 bit          | 8 bit        | 8/16 bit     | 8 bit                | 8/16 bit     | 8 bit       |
+| - ctrl_ep_num              | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - iddg_filter              | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - vbus_valid_filter        | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 1            | 0           |
+| - a_valid_filter           | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 1            | 0           |
+| - b_valid_filter           | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 1            | 0           |
+| - session_end_filter       | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 1            | 0           |
+| - dedicated_fifos          | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - num_dev_in_eps           | 7              | 7              | 0           | 7               | 6            | 4             | 7            | 7            | 15           | 5                | 3                         | 5            | 5                | 8            | 8              | 5                 | 8            | 5            | 8                    | 6            | 0           |
+| - dma_desc_enable          | 0              | 0              | 0           | 0               | 0            | 1             | 1            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 1              | 0                 | 0            | 0            | 1                    | 1            | 0           |
+| - dma_desc_dynamic         | 0              | 0              | 0           | 0               | 0            | 1             | 1            | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 1              | 0                 | 0            | 0            | 1                    | 1            | 0           |
diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py
index f6bd2785a..8ee04e179 100755
--- a/src/portable/synopsys/dwc2/dwc2_info.py
+++ b/src/portable/synopsys/dwc2/dwc2_info.py
@@ -2,7 +2,6 @@
 
 import ctypes
 import argparse
-import click
 import pandas as pd
 
 # hex value for register: guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
@@ -10,21 +9,24 @@ import pandas as pd
 dwc2_reg_list = ['GUID', 'GSNPSID', 'GHWCFG1', 'GHWCFG2', 'GHWCFG3', 'GHWCFG4']
 dwc2_reg_value = {
     'AT32 F405 FS': [0x00002000, 0x4F54400A, 0x00000000, 0x228FDD00, 0x020004E8, 0x1FF0A020],
-    'AT32 F405 HS': [0x00000000, 0x4F54400A, 0x00000000, 0x229FDDD0, 0x03F006E8, 0x1FF0A020],
+    'AT32 F405 HS': [0, 0x4F54400A, 0x00000000, 0x229FDDD0, 0x03F006E8, 0x1FF0A020],
     'AT32 F415': [0x00001000, 0x4F54400A, 0x00000000, 0x228DCD00, 0x020004E8, 0x0F],
     'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020],
     'EFM32GG': [0, 0x4F54330A, 0, 0x228F5910, 0x01F204E8, 0x1BF08030],
     'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0x0C804B5, 0xD3F0A030],
     'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030],
-    'nRF54': [0, 0x4F54430A, 0xAA555000, 0x228BFC72, 0x0BEAC0E8, 0x1E10AA60],
-    'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030],
+    'nRF54H20': [0, 0x4F54430A, 0xAA555000, 0x228BFC72, 0x0BEAC0E8, 0x1E10AA60], # base on Preliminary Datasheet v0.7
+    'nRF54LM20': [0, 0x4F54500B, 0x00000000, 0x22AFFC52, 0x0BE0C0E8, 0x3E10AA60],
+    # ST sort by GUID
     'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x03F403E8, 0x17F00030],
+    'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030],
+    'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
     'ST F412/76x FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
-    'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
-    'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030],
     'ST F76x HS': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030],
     'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030],
-    'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
+    'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
+    'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030],
+    'ST H7RS FS': [0x4000, 0x4F54411A, 0, 0x229ED522, 0x20081E8, 0x1610B230],
     'ST U5A5/H7RS/N6 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30],
     'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030],
     'GD32VF103': [0x1000, 0, 0, 0, 0, 0],
diff --git a/src/portable/synopsys/dwc2/dwc2_nrf.h b/src/portable/synopsys/dwc2/dwc2_nrf.h
new file mode 100644
index 000000000..a1bf692f8
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_nrf.h
@@ -0,0 +1,150 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ *
+ * Modification
+ * - Gabriel Koppenstein add nRF54LM20 support
+ */
+#ifndef TUSB_DWC2_NRF_H
+#define TUSB_DWC2_NRF_H
+
+// NRF is device only without OTG support
+#include "nrf.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-align"
+#endif
+
+#include <soc/nrfx_coredep.h>
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#define DWC2_EP_MAX 16
+
+// Use the auto-resolving peripheral pointer (respects TrustZone secure/non-secure mapping)
+#if defined(NRF54LM20A_ENGA_XXAA)
+  #define DWC2_REG_BASE ((uintptr_t)NRF_USBHSCORE)
+#else
+  #define DWC2_REG_BASE ((uintptr_t)NRF_USBHSCORE0)
+#endif
+
+static const dwc2_controller_t _dwc2_controller[] = {
+  {.reg_base = DWC2_REG_BASE, .irqnum = USBHS_IRQn, .ep_count = 16, .otg_dfifo_depth = 3072},
+};
+
+// MCU specific to enable dwc2 clock/power before any access to register
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_clock_init(uint8_t rhport, tusb_role_t role) {
+  (void) rhport;
+  (void) role;
+
+  #if defined(NRF54LM20A_ENGA_XXAA)
+  // Start the USB voltage regulator
+  NRF_VREGUSB->TASKS_START = VREGUSB_TASKS_START_TASKS_START_Trigger;
+
+  // Based on Zephyr usbhs_enable_core() in drivers/usb/udc/udc_dwc2_vendor_quirks.h
+  // Step 1: Power up core only (PHY not yet)
+  NRF_USBHS->ENABLE = USBHS_ENABLE_CORE_Msk;
+
+  // Step 2: Override ID=Device (bit 31), and temporarily override VBUSVALID
+  NRF_USBHS->PHY.OVERRIDEVALUES = (USBHS_PHY_OVERRIDEVALUES_ID_Device << USBHS_PHY_OVERRIDEVALUES_ID_Pos);
+  NRF_USBHS->PHY.INPUTOVERRIDE = USBHS_PHY_INPUTOVERRIDE_ID_Msk | USBHS_PHY_INPUTOVERRIDE_VBUSVALID_Msk;
+
+  // Step 3: Release PHY power-on reset by enabling PHY
+  NRF_USBHS->ENABLE = USBHS_ENABLE_PHY_Msk | USBHS_ENABLE_CORE_Msk;
+
+  // Step 4: Wait 45us for PHY clock to start
+  nrfx_coredep_delay_us(45);
+
+  // Step 5: Release DWC2 reset
+  NRF_USBHS->TASKS_START = USBHS_TASKS_START_TASKS_START_Trigger;
+
+  // Step 6: Wait for clock to start to avoid hang on too early register read
+  nrfx_coredep_delay_us(2);
+
+  // Step 7: Clear VBUSVALID override (keep ID=Device override)
+  // DWC2 is now in Non-Driving opmode; D+ pull-up will activate when DWC2 clears DCTL SftDiscon
+  NRF_USBHS->PHY.INPUTOVERRIDE = USBHS_PHY_INPUTOVERRIDE_ID_Msk;
+
+  // Barrier: USBHS wrapper (0x5005A000) and USBHSCORE (0x50020000) are separate
+  // peripheral blocks. Ensure the ENABLE/TASKS_START writes have propagated from
+  // the Cortex-M33 write buffer to hardware before anyone reads DWC2 core regs.
+  __DSB();
+  #endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
+  (void)rhport;
+  (void)role;
+  if (enabled) {
+    NVIC_EnableIRQ(USBHS_IRQn);
+  } else {
+    NVIC_DisableIRQ(USBHS_IRQn);
+  }
+}
+
+#define dwc2_dcd_int_enable(_rhport)  dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, true)
+#define dwc2_dcd_int_disable(_rhport) dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, false)
+
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
+}
+
+// MCU specific PHY init, called BEFORE core reset
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
+  (void)dwc2;
+  (void)hs_phy_type;
+}
+
+// MCU specific PHY deinit, disable PHY power
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
+  (void)dwc2;
+  (void)hs_phy_type;
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
+  (void)dwc2;
+  (void)hs_phy_type;
+}
+
+// nRF54 Cortex-M33 has no D-cache, provide no-op stubs for DMA mode
+TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean(const void *addr, uint32_t data_size) {
+  (void)addr;
+  (void)data_size;
+  return true;
+}
+TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_invalidate(const void *addr, uint32_t data_size) {
+  (void)addr;
+  (void)data_size;
+  return true;
+}
+TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean_invalidate(const void *addr, uint32_t data_size) {
+  (void)addr;
+  (void)data_size;
+  return true;
+}
+
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 08950ccc0..126632fec 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -31,36 +31,36 @@
 extern "C" {
 #endif
 
-// EP_MAX       : Max number of bi-directional endpoints including EP0
-// EP_FIFO_SIZE : Size of dedicated USB SRAM
+// EP_MAX          : Max number of bi-directional endpoints including EP0
+// DFIFO_DEPTH_FS/HS : DFIFO depth in 32-bit words (OTG_DFIFO_DEPTH)
 #if CFG_TUSB_MCU == OPT_MCU_STM32F1
   #include "stm32f1xx.h"
   #define EP_MAX_FS       4
-  #define EP_FIFO_SIZE_FS 1280
+  #define DFIFO_DEPTH_FS 320
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F2
   #include "stm32f2xx.h"
   #define EP_MAX_FS       USB_OTG_FS_MAX_IN_ENDPOINTS
-  #define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
+  #define DFIFO_DEPTH_FS  320
 
   #define EP_MAX_HS       USB_OTG_HS_MAX_IN_ENDPOINTS
-  #define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE
+  #define DFIFO_DEPTH_HS  1024
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F4
   #include "stm32f4xx.h"
   #define EP_MAX_FS       USB_OTG_FS_MAX_IN_ENDPOINTS
-  #define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
+  #define DFIFO_DEPTH_FS  320
 
   #define EP_MAX_HS       USB_OTG_HS_MAX_IN_ENDPOINTS
-  #define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE
+  #define DFIFO_DEPTH_HS  1024
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32H7
   #include "stm32h7xx.h"
   #define EP_MAX_FS       9
-  #define EP_FIFO_SIZE_FS 4096
+  #define DFIFO_DEPTH_FS 1024
 
   #define EP_MAX_HS       9
-  #define EP_FIFO_SIZE_HS 4096
+  #define DFIFO_DEPTH_HS 1024
 
   // NOTE: H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
   // USB_OTG_FS_PERIPH_BASE and OTG_FS_IRQn not defined
@@ -72,34 +72,37 @@ extern "C" {
 #elif CFG_TUSB_MCU == OPT_MCU_STM32H7RS
   #include "stm32h7rsxx.h"
   #define EP_MAX_FS       6
-  #define EP_FIFO_SIZE_FS 1280
+  #define DFIFO_DEPTH_FS 320
 
   #define EP_MAX_HS       9
-  #define EP_FIFO_SIZE_HS 4096
+  #define DFIFO_DEPTH_HS 1024
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32N6
   #include "stm32n6xx.h"
   #define EP_MAX_FS       9
-  #define EP_FIFO_SIZE_FS 4096
+  #define DFIFO_DEPTH_FS 1024
 
   #define EP_MAX_HS       9
-  #define EP_FIFO_SIZE_HS 4096
+  #define DFIFO_DEPTH_HS 1024
 
-  #define USB_OTG_HS_PERIPH_BASE    USB1_OTG_HS_BASE
-  #define OTG_HS_IRQn               USB1_OTG_HS_IRQn
+  #define USB_OTG_FS_PERIPH_BASE    USB1_OTG_HS_BASE
+  #define OTG_FS_IRQn               USB1_OTG_HS_IRQn
+
+  #define USB_OTG_HS_PERIPH_BASE    USB2_OTG_HS_BASE
+  #define OTG_HS_IRQn               USB2_OTG_HS_IRQn
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F7
   #include "stm32f7xx.h"
   #define EP_MAX_FS       6
-  #define EP_FIFO_SIZE_FS 1280
+  #define DFIFO_DEPTH_FS 320
 
   #define EP_MAX_HS       9
-  #define EP_FIFO_SIZE_HS 4096
+  #define DFIFO_DEPTH_HS 1024
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L4
   #include "stm32l4xx.h"
   #define EP_MAX_FS       6
-  #define EP_FIFO_SIZE_FS 1280
+  #define DFIFO_DEPTH_FS 320
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
   #include "stm32u5xx.h"
@@ -107,11 +110,11 @@ extern "C" {
   #ifdef USB_OTG_FS
     #define USB_OTG_FS_PERIPH_BASE    USB_OTG_FS_BASE
     #define EP_MAX_FS                 6
-    #define EP_FIFO_SIZE_FS           1280
+    #define DFIFO_DEPTH_FS           320
   #else
     #define USB_OTG_HS_PERIPH_BASE    USB_OTG_HS_BASE
     #define EP_MAX_HS                 9
-    #define EP_FIFO_SIZE_HS           4096
+    #define DFIFO_DEPTH_HS           1024
   #endif
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WBA
@@ -128,7 +131,7 @@ extern "C" {
   #define USB_OTG_HS_PERIPH_BASE    USB_OTG_HS_BASE_NS
   #define OTG_HS_IRQn               USB_OTG_HS_IRQn
   #define EP_MAX_HS                 9
-  #define EP_FIFO_SIZE_HS           4096
+  #define DFIFO_DEPTH_HS           1024
 #else
   #error "Unsupported MCUs"
 #endif
@@ -144,11 +147,11 @@ extern "C" {
 // - Port0 to OTG_FS, and Port1 to OTG_HS
 static const dwc2_controller_t _dwc2_controller[] = {
     #ifdef USB_OTG_FS_PERIPH_BASE
-    { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
+    { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .otg_dfifo_depth = DFIFO_DEPTH_FS },
     #endif
 
     #ifdef USB_OTG_HS_PERIPH_BASE
-    { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS },
+    { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .otg_dfifo_depth = DFIFO_DEPTH_HS },
     #endif
 };
 
@@ -159,6 +162,12 @@ static const dwc2_controller_t _dwc2_controller[] = {
 // SystemCoreClock is already included by family header
 // extern uint32_t SystemCoreClock;
 
+// MCU specific to enable dwc2 clock/power before any access to register
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_clock_init(uint8_t rhport, tusb_role_t role) {
+  (void) rhport;
+  (void) role;
+}
+
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
   (void) role;
   const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
@@ -176,7 +185,9 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
   // try to delay for 1 ms
   uint32_t count = SystemCoreClock / 1000;
-  while (count--) __NOP();
+  while (count--) {
+    __NOP();
+  }
 }
 
 // MCU specific PHY init, called BEFORE core reset
@@ -259,6 +270,22 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   }
 }
 
+// MCU specific PHY deinit, disable PHY power
+static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+  if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
+    // Disable on-chip FS PHY
+    dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+  } else {
+    // Disable HS PHY
+    #ifdef USB_HS_PHYC
+    dwc2->stm32_gccfg &= ~STM32_GCCFG_PHYHSEN;
+    // Disable PLL and LDO
+    USB_HS_PHYC->USB_HS_PHYC_PLL &= ~USB_HS_PHYC_PLL_PLLEN;
+    USB_HS_PHYC->USB_HS_PHYC_LDO &= ~USB_HS_PHYC_LDO_ENABLE;
+    #endif
+  }
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   // used to set turnaround time for fullspeed, nothing to do in highspeed mode
@@ -298,6 +325,66 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   }
 }
 
+//------------- GCCFG configuration -------------//
+static inline void dwc2_stm32_gccfg_cfg(dwc2_regs_t* dwc2, bool vbus_sensing, bool is_host) {
+  if (is_host) {
+    vbus_sensing = false;
+  }
+
+  uint32_t gccfg = dwc2->stm32_gccfg;
+  if (dwc2->guid < 0x2000) {
+    // use VBUSASEN/VBUSBSEN/NOVBUSSENS bits
+    if (is_host) {
+      gccfg &= ~(STM32_GCCFG_NOVBUSSENS | STM32_GCCFG_VBUSBSEN | STM32_GCCFG_VBUSASEN);
+    } else {
+      if (vbus_sensing) {
+        gccfg &= ~STM32_GCCFG_NOVBUSSENS;
+        gccfg |= STM32_GCCFG_VBUSBSEN;
+      } else {
+        gccfg |= STM32_GCCFG_NOVBUSSENS;
+        gccfg &= ~(STM32_GCCFG_VBUSBSEN | STM32_GCCFG_VBUSASEN);
+      }
+    }
+  } else if (dwc2->guid < 0x5000) {
+    // the later version uses VBDEN with battery charging detection
+    if (vbus_sensing) {
+      gccfg |= STM32_GCCFG_VBDEN;
+    } else {
+      gccfg &= ~STM32_GCCFG_VBDEN;
+    }
+  } else {
+    // from 0x5000 ST seems to use femtoPHY for UTMI+ HS PHY. Which use VBVALEXTOEN and VBVALOVAL for software override
+    // external VBUS sensing
+    // Note: N6 does not support hardware VBUS sensing, so the software override is always active. Therefore, VBDEN and
+    //       VBVALEXTOEN are not available
+#if CFG_TUSB_MCU == OPT_MCU_STM32N6
+    if (is_host) {
+      gccfg |= STM32_GCCFG_PULLDOWNEN;
+      gccfg &= ~(STM32_GCCFG_VBVALOVAL);
+    } else {
+      gccfg &= ~STM32_GCCFG_PULLDOWNEN;
+      gccfg |= STM32_GCCFG_VBVALOVAL;
+    }
+#else
+    if (is_host) {
+      gccfg |= STM32_GCCFG_PULLDOWNEN;
+      gccfg &= ~(STM32_GCCFG_VBDEN | STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL);
+    } else {
+      gccfg &= ~STM32_GCCFG_PULLDOWNEN;
+      if (vbus_sensing) {
+        gccfg |= STM32_GCCFG_VBDEN;
+        gccfg &= ~(STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL);
+      } else {
+        gccfg &= ~STM32_GCCFG_VBDEN;
+        gccfg |= STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL;
+      }
+    }
+#endif
+  }
+
+  dwc2->stm32_gccfg = gccfg;
+}
+
 //------------- DCache -------------//
 #if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
 
@@ -319,8 +406,13 @@ static mem_region_t uncached_regions[] = {
   // DTCM (although USB DMA can't transfer to/from DTCM)
   {.start = 0x20000000, .end = 0x2002FFFF},
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F7
-    // DTCM
+  // DTCM
   {.start = 0x20000000, .end = 0x2000FFFF},
+#elif CFG_TUSB_MCU == OPT_MCU_STM32N6
+  // DTCM NS
+  {.start = 0x20000000, .end = 0x2003FFFF},
+  // DTCM S
+  {.start = 0x30000000, .end = 0x3003FFFF},
 #else
 #error "Cache maintenance is not supported yet"
 #endif
@@ -335,6 +427,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uintptr_t addr) {
+  if (0 == (SCB->CCR & SCB_CCR_DC_Msk)) {
+    return false; // D-Cache is disabled
+  }
   for (unsigned int i = 0; i < TU_ARRAY_SIZE(uncached_regions); i++) {
     if (uncached_regions[i].start <= addr && addr <= uncached_regions[i].end) { return false; }
   }
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 0a8dacf5f..7c03a4a91 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -47,7 +47,7 @@ typedef struct
   uint32_t  irqnum;
   uint8_t   ep_count;
   uint8_t   ep_in_count;
-  uint32_t  ep_fifo_size;
+  uint16_t  otg_dfifo_depth; // total SPRAM in 32-bit words = ghwcfg3.dfifo_depth + EP_LOC_CNT
 }dwc2_controller_t;
 
 // DWC OTG HW Release versions
@@ -63,6 +63,7 @@ typedef struct
 #define DWC2_CORE_REV_4_00a   0x4f54400a
 #define DWC2_CORE_REV_4_11a   0x4f54411a
 #define DWC2_CORE_REV_4_20a   0x4f54420a
+#define DWC2_CORE_REV_5_00b   0x4F54500b
 #define DWC2_FS_IOT_REV_1_00a 0x5531100a
 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
 #define DWC2_CORE_REV_MASK    0x0000ffff
@@ -92,6 +93,16 @@ enum {
 };
 
 enum {
+  GUSBCFG_PHYSEL_HIGHSPEED = 0,
+  GUSBCFG_PHYSEL_FULLSPEED = 1,
+};
+
+enum {
+  GUSBCFG_PHYHS_UTMI = 0,
+  GUSBCFG_PHYHS_ULPI = 1,
+};
+
+enum {
   GHWCFG2_OPMODE_HNP_SRP         = 0,
   GHWCFG2_OPMODE_SRP             = 1,
   GHWCFG2_OPMODE_NON_HNP_NON_SRP = 2,
@@ -1435,7 +1446,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos)          // 0xFFFF0000
 #define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk                        // OUT EP interrupt mask bits
 
-#define DAINT_SHIFT(_dir)            ((_dir == TUSB_DIR_IN) ? 0 : 16)
+#define DAINT_SHIFT(_dir)                (((_dir) == TUSB_DIR_IN) ? 0 : 16)
 
 #if 0
 /********************  Bit definition for OTG register  ********************/
@@ -1640,24 +1651,38 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define STM32_GCCFG_PHYHSEN_Msk          (0x1UL << STM32_GCCFG_PHYHSEN_Pos)       // 0x00800000
 #define STM32_GCCFG_PHYHSEN              STM32_GCCFG_PHYHSEN_Msk                  // HS PHY enable
 
-// TODO stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
-//#define STM32_GCCFG_SDEN_Pos                   (22U)
-//#define STM32_GCCFG_SDEN_Msk                   (0x1U << STM32_GCCFG_SDEN_Pos)             // 0x00400000
-//#define STM32_GCCFG_SDEN                       STM32_GCCFG_SDEN_Msk                       // Secondary detection (PD) mode enable
+// GUID < 0x2000: VBUSASEN, VBUSBSEN, NOVBUSSENS bits
+#define STM32_GCCFG_VBUSASEN_Pos         (18U)
+#define STM32_GCCFG_VBUSASEN_Msk         (0x1UL << STM32_GCCFG_VBUSASEN_Pos)      // 0x00040000
+#define STM32_GCCFG_VBUSASEN             STM32_GCCFG_VBUSASEN_Msk                 // Enable A-device (host) VBUS sensing
+
+#define STM32_GCCFG_VBUSBSEN_Pos         (19U)
+#define STM32_GCCFG_VBUSBSEN_Msk         (0x1UL << STM32_GCCFG_VBUSBSEN_Pos)      // 0x00080000
+#define STM32_GCCFG_VBUSBSEN             STM32_GCCFG_VBUSBSEN_Msk                 // Enable B-device (peripheral) VBUS sensing
+
+#define STM32_GCCFG_NOVBUSSENS_Pos       (21U)
+#define STM32_GCCFG_NOVBUSSENS_Msk       (0x1UL << STM32_GCCFG_NOVBUSSENS_Pos)     // 0x00200000
+#define STM32_GCCFG_NOVBUSSENS           STM32_GCCFG_NOVBUSSENS_Msk                // VBUS sensing disable option
+// GUID < 0x2000: end
 
-// TODO stm32u5a5 VBVALOVA is 23rd bit, conflict with PHYHSEN bit above
-#define STM32_GCCFG_VBVALOVAL_Pos              (23U)
-#define STM32_GCCFG_VBVALOVAL_Msk              (0x1U << STM32_GCCFG_VBVALOVAL_Pos)        // 0x00800000
-#define STM32_GCCFG_VBVALOVAL                  STM32_GCCFG_VBVALOVAL_Msk                  // Value of VBUSVLDEXT0 femtoPHY input
+// TODO: stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
+// #define STM32_GCCFG_SDEN_Pos             (22U)
+// #define STM32_GCCFG_SDEN_Msk             (0x1U << STM32_GCCFG_SDEN_Pos)             // 0x00400000
+// #define STM32_GCCFG_SDEN                 STM32_GCCFG_SDEN_Msk                       // Secondary detection (PD) mode enable
 
-#define STM32_GCCFG_VBVALEXTOEN_Pos            (24U)
-#define STM32_GCCFG_VBVALEXTOEN_Msk            (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos)      // 0x01000000
-#define STM32_GCCFG_VBVALEXTOEN                STM32_GCCFG_VBVALEXTOEN_Msk                // Enables of VBUSVLDEXT0 femtoPHY input override
+// GUID >= 0x5000 use femtoPHY: VBVALOVA, VBVALEXTOEN, PULLDOWNEN
+#define STM32_GCCFG_VBVALOVAL_Pos        (23U)
+#define STM32_GCCFG_VBVALOVAL_Msk        (0x1U << STM32_GCCFG_VBVALOVAL_Pos)        // 0x00800000
+#define STM32_GCCFG_VBVALOVAL            STM32_GCCFG_VBVALOVAL_Msk                  // Value of VBUSVLDEXT0 femtoPHY input
 
-#define STM32_GCCFG_PULLDOWNEN_Pos             (25U)
-#define STM32_GCCFG_PULLDOWNEN_Msk             (0x1U << STM32_GCCFG_PULLDOWNEN_Pos)       // 0x02000000
-#define STM32_GCCFG_PULLDOWNEN                 STM32_GCCFG_PULLDOWNEN_Msk                 // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
+#define STM32_GCCFG_VBVALEXTOEN_Pos      (24U)
+#define STM32_GCCFG_VBVALEXTOEN_Msk      (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos)      // 0x01000000
+#define STM32_GCCFG_VBVALEXTOEN          STM32_GCCFG_VBVALEXTOEN_Msk                // Enables of VBUSVLDEXT0 femtoPHY input override
 
+#define STM32_GCCFG_PULLDOWNEN_Pos       (25U)
+#define STM32_GCCFG_PULLDOWNEN_Msk       (0x1U << STM32_GCCFG_PULLDOWNEN_Pos)       // 0x02000000
+#define STM32_GCCFG_PULLDOWNEN           STM32_GCCFG_PULLDOWNEN_Msk                 // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
+// GUID >= 0x5000: end
 
 /********************  Bit definition for DEACHINTMSK register  ********************/
 #define DEACHINTMSK_IEP1INTM_Pos         (1U)
@@ -1847,6 +1872,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define HPTXFSIZ_PTXFD                   HPTXFSIZ_PTXFD_Msk                       // Host periodic TxFIFO depth
 
 /********************  Bit definition for DIEPCTL register  ********************/
+#define DIEPCTL0_MPSIZ_Pos               (0U)
+#define DIEPCTL0_MPSIZ_Msk               (0x3UL << DIEPCTL0_MPSIZ_Pos)            // 0x00000003
+#define DIEPCTL0_MPSIZ                   DIEPCTL0_MPSIZ_Msk                       // Maximum packet size(endpoint 0)
 #define DIEPCTL_MPSIZ_Pos                (0U)
 #define DIEPCTL_MPSIZ_Msk                (0x7FFUL << DIEPCTL_MPSIZ_Pos)           // 0x000007FF
 #define DIEPCTL_MPSIZ                    DIEPCTL_MPSIZ_Msk                        // Maximum packet size
@@ -2155,6 +2183,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define EPCTL_EPENA                    EPCTL_EPENA_Msk                        // Endpoint enable
 
 /********************  Bit definition for DOEPCTL register  ********************/
+#define DOEPCTL0_MPSIZ_Pos               (0U)
+#define DOEPCTL0_MPSIZ_Msk               (0x3UL << DOEPCTL0_MPSIZ_Pos)            // 0x00000003
+#define DOEPCTL0_MPSIZ                   DOEPCTL0_MPSIZ_Msk                       // Maximum packet size(endpoint 0)
 #define DOEPCTL_MPSIZ_Pos                (0U)
 #define DOEPCTL_MPSIZ_Msk                (0x7FFUL << DOEPCTL_MPSIZ_Pos)           // 0x000007FF
 #define DOEPCTL_MPSIZ                    DOEPCTL_MPSIZ_Msk                        // Maximum packet size          //Bit 1
diff --git a/src/portable/synopsys/dwc2/dwc2_xmc.h b/src/portable/synopsys/dwc2/dwc2_xmc.h
index 63419abf7..85b2a2633 100644
--- a/src/portable/synopsys/dwc2/dwc2_xmc.h
+++ b/src/portable/synopsys/dwc2/dwc2_xmc.h
@@ -39,9 +39,15 @@
 static const dwc2_controller_t _dwc2_controller[] =
 {
   // Note: XMC has some custom control registers before DWC registers
-  { .reg_base = USB0_BASE, .irqnum = USB0_0_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 2048 }
+  { .reg_base = USB0_BASE, .irqnum = USB0_0_IRQn, .ep_count = DWC2_EP_MAX, .otg_dfifo_depth = 512 }
 };
 
+// MCU specific to enable dwc2 clock/power before any access to register
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_clock_init(uint8_t rhport, tusb_role_t role) {
+  (void) rhport;
+  (void) role;
+}
+
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
@@ -71,6 +77,13 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
   //USB->ROUTE = USB_ROUTE_PHYPEN;
 }
 
+// MCU specific PHY deinit, disable PHY power
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
+  (void) dwc2;
+  (void) hs_phy_type;
+  // nothing to do
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c
index 257fa2833..84a0c6afd 100644
--- a/src/portable/synopsys/dwc2/hcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/hcd_dwc2.c
@@ -32,19 +32,19 @@
 #error DWC2 require either CFG_TUH_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled
 #endif
 
-// Debug level for DWC2
-#define DWC2_DEBUG    2
-
 #include "host/hcd.h"
 #include "host/usbh.h"
 #include "dwc2_common.h"
 
-// Max number of endpoints application can open, can be larger than DWC2_CHANNEL_COUNT_MAX
-#ifndef CFG_TUH_DWC2_ENDPOINT_MAX
-#define CFG_TUH_DWC2_ENDPOINT_MAX 16
-#endif
+  // Debug level for DWC2
+  #define DWC2_DEBUG 2
+
+  // Max number of endpoints application can open, can be larger than DWC2_CHANNEL_COUNT_MAX
+  #ifndef CFG_TUH_DWC2_ENDPOINT_MAX
+    #define CFG_TUH_DWC2_ENDPOINT_MAX 16u
+  #endif
 
-#define DWC2_CHANNEL_COUNT_MAX    16 // absolute max channel count
+  #define DWC2_CHANNEL_COUNT_MAX 16u // absolute max channel count
 TU_VERIFY_STATIC(CFG_TUH_DWC2_ENDPOINT_MAX <= 255, "currently only use 8-bit for index");
 
 enum {
@@ -79,7 +79,8 @@ typedef struct {
     uint32_t speed           : 2;
     uint32_t next_pid        : 2; // PID for next transfer
     uint32_t next_do_ping    : 1; // Do PING for next transfer if possible (highspeed OUT)
-    // uint32_t : 9;
+    uint32_t closing         : 1; // endpoint is closing
+    // uint32_t : 8;
   };
 
   uint32_t uframe_countdown; // micro-frame count down to transfer for periodic, only need 18-bit
@@ -96,12 +97,14 @@ typedef struct {
     uint8_t err_count : 3;
     uint8_t period_split_nyet_count : 3;
     uint8_t halted_nyet : 1;
+    uint8_t closing : 1; // closing channel
   };
   uint8_t result;
 
   uint16_t xferred_bytes;  // bytes that accumulate transferred though USB bus for the whole hcd_edpt_xfer(), which can
                            // be composed of multiple channel_xfer_start() (retry with NAK/NYET)
   uint16_t fifo_bytes;     // bytes written/read from/to FIFO (may not be transferred on USB bus).
+  uint8_t  retry_disabled; // 1: channel was disabled to throttle a split retry (NAK in / XactErr out); re-arm on its halt
 } hcd_xfer_t;
 
 typedef struct {
@@ -109,7 +112,8 @@ typedef struct {
   hcd_endpoint_t edpt[CFG_TUH_DWC2_ENDPOINT_MAX];
 } hcd_data_t;
 
-hcd_data_t _hcd_data;
+static hcd_data_t _hcd_data;
+static tuh_configure_dwc2_t _tuh_cfg = {.use_hs_phy = TUH_OPT_HIGH_SPEED};
 
 //--------------------------------------------------------------------
 //
@@ -195,8 +199,21 @@ TU_ATTR_ALWAYS_INLINE static inline void channel_dealloc(dwc2_regs_t* dwc2, uint
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool channel_disable(const dwc2_regs_t* dwc2, dwc2_channel_t* channel) {
-  // disable also require request queue
-  TU_ASSERT(req_queue_avail(dwc2, channel_is_periodic(channel->hcchar)));
+  const bool is_period = channel_is_periodic(channel->hcchar);
+  if (dma_host_enabled(dwc2)) {
+    // In buffer DMA or external DMA mode:
+    // - Channel disable must not be programmed for non-split periodic channels. At the end of the next uframe/frame (in
+    //   the worst case), the controller generates a channel halted and disables the channel automatically.
+    // - For split enabled channels (both non-periodic and periodic), channel disable must not be programmed randomly.
+    //   However, channel disable can be programmed for specific scenarios such as NAK and FrmOvrn.
+    if (is_period && (channel->hcsplt & HCSPLT_SPLITEN)) {
+      return true;
+    }
+  } else {
+    while (0 == req_queue_avail(dwc2, is_period)) {
+      // blocking wait for request queue available
+    }
+  }
   channel->hcintmsk |= HCINT_HALTED;
   channel->hcchar |= HCCHAR_CHDIS | HCCHAR_CHENA; // must set both CHDIS and CHENA
   return true;
@@ -204,7 +221,9 @@ TU_ATTR_ALWAYS_INLINE static inline bool channel_disable(const dwc2_regs_t* dwc2
 
 // attempt to send IN token to receive data
 TU_ATTR_ALWAYS_INLINE static inline bool channel_send_in_token(const dwc2_regs_t* dwc2, dwc2_channel_t* channel) {
-  TU_ASSERT(req_queue_avail(dwc2, channel_is_periodic(channel->hcchar)));
+  while (0 == req_queue_avail(dwc2, channel_is_periodic(channel->hcchar))) {
+    // blocking wait for request queue available
+  }
   channel->hcchar |= HCCHAR_CHENA;
   return true;
 }
@@ -237,13 +256,37 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_alloc(void) {
   return TUSB_INDEX_INVALID_8;
 }
 
-// Find a endpoint that is opened previously with hcd_edpt_open()
+TU_ATTR_ALWAYS_INLINE static inline void edpt_dealloc(hcd_endpoint_t *edpt) {
+  edpt->hcchar_bm.enable = 0;
+}
+
+// close an opened endpoint
+static void edpt_close(dwc2_regs_t *dwc2, uint8_t ep_id) {
+  hcd_endpoint_t *edpt = &_hcd_data.edpt[ep_id];
+  edpt->closing        = 1; // mark endpoint as closing
+
+  // disable active channel belong to this endpoint
+  for (uint8_t ch_id = 0; ch_id < DWC2_CHANNEL_COUNT_MAX; ch_id++) {
+    hcd_xfer_t *xfer = &_hcd_data.xfer[ch_id];
+    if (xfer->allocated && xfer->ep_id == ep_id) {
+      dwc2_channel_t *channel = &dwc2->channel[ch_id];
+      xfer->closing           = 1;
+      channel_disable(dwc2, channel);
+      return; // only 1 active channel per endpoint
+    }
+  }
+
+  edpt_dealloc(edpt); // no active channel, safe to de-alloc now
+}
+
+// Find an endpoint that is opened previously with hcd_edpt_open()
 // Note: EP0 is bidirectional
 TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_find_opened(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) {
   for (uint8_t i = 0; i < (uint8_t)CFG_TUH_DWC2_ENDPOINT_MAX; i++) {
-    const dwc2_channel_char_t* hcchar_bm = &_hcd_data.edpt[i].hcchar_bm;
-    if (hcchar_bm->enable && hcchar_bm->dev_addr == dev_addr &&
-        hcchar_bm->ep_num == ep_num && (ep_num == 0 || hcchar_bm->ep_dir == ep_dir)) {
+    const hcd_endpoint_t     *edpt      = &_hcd_data.edpt[i];
+    const dwc2_channel_char_t hcchar_bm = edpt->hcchar_bm;
+    if (hcchar_bm.enable && hcchar_bm.dev_addr == dev_addr && hcchar_bm.ep_num == ep_num &&
+        (ep_num == 0 || hcchar_bm.ep_dir == ep_dir)) {
       return i;
     }
   }
@@ -259,8 +302,8 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t cal_packet_count(uint16_t len, uint
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint8_t cal_next_pid(uint8_t pid, uint8_t packet_count) {
-  if (packet_count & 0x01) {
-    return pid ^ 0x02; // toggle DATA0 and DATA1
+  if (packet_count & 0x01u) {
+    return pid ^ 0x02u; // toggle DATA0 and DATA1
   } else {
     return pid;
   }
@@ -281,9 +324,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t cal_next_pid(uint8_t pid, uint8_t pa
   We allocated TX FIFO from top to bottom (using top pointer), this to allow the RX FIFO to grow dynamically which is
   possible since the free space is located between the RX and TX FIFOs.
 
-   ----------------- ep_fifo_size
-  |    HCDMAn    |
-  |--------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth)
+   ----------------- otg_dfifo_depth
+  |    HCDMAn    |   (DMA only, sized per runtime DMA mode)
+  |--------------|-- gdfifocfg.EPINFOBASE (= gdfifocfg.GDFIFOCfg)
   | Non-Periodic |
   |   TX FIFO    |
   |--------------|--- GNPTXFSIZ.addr (fixed size)
@@ -309,23 +352,29 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t cal_next_pid(uint8_t pid, uint8_t pa
  * TX periodic (PTX)
  * - At least largest-EPsize*MulCount/4 (MulCount up to 3 for high-bandwidth ISO/interrupt)
 */
-static void dfifo_host_init(uint8_t rhport) {
+static void dfifo_host_init(uint8_t rhport, bool is_hs_phy) {
   const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
 
   // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per channel
   const bool is_dma = dma_host_enabled(dwc2);
-  uint16_t dfifo_top = dwc2_controller->ep_fifo_size/4;
+  uint16_t dfifo_top = dwc2_controller->otg_dfifo_depth;
   if (is_dma) {
     dfifo_top -= ghwcfg2.num_host_ch;
   }
 
   // fixed allocation for now, improve later:
-    // - ptx_largest is limited to 256 for FS since most FS core only has 1024 bytes total
-  bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST);
-  uint32_t nptx_largest = is_highspeed ? TUSB_EPSIZE_BULK_HS/4 : TUSB_EPSIZE_BULK_FS/4;
-  uint32_t ptx_largest = is_highspeed ? TUSB_EPSIZE_ISO_HS_MAX/4 : 256/4;
+  // - ptx_largest is limited to 64 words for FS since most FS core only has 256-320 words total
+  uint32_t nptx_largest;
+  uint32_t ptx_largest;
+  if (is_hs_phy) {
+    nptx_largest = TUSB_EPSIZE_BULK_HS / 4;
+    ptx_largest = TUSB_EPSIZE_ISO_HS_MAX / 4;
+  } else {
+    nptx_largest = TUSB_EPSIZE_BULK_FS / 4;
+    ptx_largest = 256 / 4;
+  }
 
   uint16_t nptxfsiz = 2 * nptx_largest;
   uint16_t rxfsiz = 2 * (ptx_largest + 2) + ghwcfg2.num_host_ch;
@@ -351,29 +400,25 @@ static void dfifo_host_init(uint8_t rhport) {
 // optional hcd configuration, called by tuh_configure()
 bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   (void) rhport;
-  (void) cfg_id;
-  (void) cfg_param;
-
+  TU_VERIFY(cfg_id == TUH_CFGID_DWC2 && cfg_param != NULL);
+  tuh_configure_param_t const* cfg = (tuh_configure_param_t const*) cfg_param;
+  _tuh_cfg = cfg->dwc2;
   return true;
 }
 
 // Initialize controller to host mode
 bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
-  (void) rh_init;
-  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  dwc2_clock_init(rhport, rh_init->role);
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
   // Core Initialization
-  const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  const bool is_hs_phy = dwc2_core_is_highspeed_phy(dwc2, _tuh_cfg.use_hs_phy);
   const bool is_dma = dma_host_enabled(dwc2);
-  TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma));
+  TU_ASSERT(dwc2_core_init(rhport, is_hs_phy, is_dma));
 
   //------------- 3.1 Host Initialization -------------//
-
-  // work at max supported speed
-  dwc2->hcfg &= ~HCFG_FSLS_ONLY;
-
   // Enable HFIR reload
   if (dwc2->gsnpsid >= DWC2_CORE_REV_2_92a) {
     dwc2->hfir |= HFIR_RELOAD_CTRL;
@@ -381,20 +426,26 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
 
   // force host mode and wait for mode switch
   dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD;
-#if CFG_TUSB_MCU == OPT_MCU_STM32N6
-  // No hardware detection of Vbus B-session is available on the STM32N6
-  dwc2->stm32_gccfg &= ~STM32_GCCFG_VBVALOVAL;
-#endif
   while ((dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {}
 
-  // configure fixed-allocated fifo scheme
-  dfifo_host_init(rhport);
+  #ifdef TUP_USBIP_DWC2_STM32
+  dwc2_stm32_gccfg_cfg(dwc2, false, true);
+  #endif
+
+  if (is_hs_phy && (rh_init->speed == TUSB_SPEED_HIGH || rh_init->speed == TUSB_SPEED_AUTO)) {
+    dwc2->hcfg &= ~HCFG_FSLS_ONLY; // max speed
+  } else {
+    dwc2->hcfg |= HCFG_FSLS_ONLY;  // disable high speed mode
+  }
+
+  // configure a fixed-allocated fifo scheme
+  dfifo_host_init(rhport, is_hs_phy);
 
   dwc2->hprt = HPRT_W1_MASK; // clear all write-1-clear bits
   dwc2->hprt = HPRT_POWER; // turn on VBUS
 
   // Enable required interrupts
-  dwc2->gintmsk |= GINTSTS_OTGINT | GINTSTS_CONIDSTSCHNG | GINTSTS_HPRTINT | GINTSTS_HCINT | GINTSTS_DISCINT;
+  dwc2->gintmsk |= GINTSTS_OTGINT | GINTSTS_HPRTINT | GINTSTS_HCINT | GINTSTS_DISCINT;
 
   // NPTX can hold at least 2 packet, change interrupt level to half-empty
   uint32_t gahbcfg = dwc2->gahbcfg & ~GAHBCFG_TX_FIFO_EPMTY_LVL;
@@ -404,6 +455,17 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   return true;
 }
 
+bool hcd_deinit(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  // Turn off VBUS
+  dwc2->hprt = HPRT_W1_MASK; // clear w1c bits without side effects
+  // HPRT_POWER is not set -> VBUS off
+
+  dwc2_core_deinit(rhport);
+  return true;
+}
+
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport) {
   dwc2_int_set(rhport, TUSB_ROLE_HOST, true);
@@ -456,11 +518,11 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
 
 // HCD closes all opened endpoints belong to this device
 void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
-  (void) rhport;
-  for (uint8_t i = 0; i < (uint8_t) CFG_TUH_DWC2_ENDPOINT_MAX; i++) {
-    hcd_endpoint_t* edpt = &_hcd_data.edpt[i];
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  for (uint8_t ep_id = 0; ep_id < CFG_TUH_DWC2_ENDPOINT_MAX; ep_id++) {
+    const hcd_endpoint_t *edpt = &_hcd_data.edpt[ep_id];
     if (edpt->hcchar_bm.enable && edpt->hcchar_bm.dev_addr == dev_addr) {
-      tu_memclr(edpt, sizeof(hcd_endpoint_t));
+      edpt_close(dwc2, ep_id);
     }
   }
 }
@@ -503,25 +565,39 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t*
 
   edpt->speed = bus_info.speed;
   edpt->next_pid = HCTSIZ_PID_DATA0;
-  if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
-    edpt->uframe_interval = 1 << (desc_ep->bInterval - 1);
-    if (bus_info.speed == TUSB_SPEED_FULL) {
-      edpt->uframe_interval <<= 3;
-    }
-  } else if (desc_ep->bmAttributes.xfer == TUSB_XFER_INTERRUPT) {
-    if (bus_info.speed == TUSB_SPEED_HIGH) {
+  switch (desc_ep->bmAttributes.xfer) {
+    case TUSB_XFER_ISOCHRONOUS:
       edpt->uframe_interval = 1 << (desc_ep->bInterval - 1);
-    } else {
-      edpt->uframe_interval = desc_ep->bInterval << 3;
-    }
+      if (bus_info.speed == TUSB_SPEED_FULL) {
+        edpt->uframe_interval <<= 3;
+      }
+      break;
+
+    case TUSB_XFER_INTERRUPT:
+      if (bus_info.speed == TUSB_SPEED_HIGH) {
+        edpt->uframe_interval = 1 << (desc_ep->bInterval - 1);
+      } else {
+        edpt->uframe_interval = desc_ep->bInterval << 3;
+      }
+      break;
+
+    default:
+      break;
   }
 
   return true;
 }
 
 bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
-  (void) rhport; (void) daddr; (void) ep_addr;
-  return false; // TODO not implemented yet
+  dwc2_regs_t  *dwc2   = DWC2_REG(rhport);
+  const uint8_t ep_num = tu_edpt_number(ep_addr);
+  const uint8_t ep_dir = tu_edpt_dir(ep_addr);
+  const uint8_t ep_id  = edpt_find_opened(daddr, ep_num, ep_dir);
+  TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX);
+
+  edpt_close(dwc2, ep_id);
+
+  return true;
 }
 
 // clean up channel after part of transfer is done but the whole urb is not complete
@@ -590,8 +666,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) {
   channel->hcint = 0xFFFFFFFFU; // clear all channel interrupts
 
   if (dma_host_enabled(dwc2)) {
-    uint32_t hcintmsk = HCINT_HALTED;
-    channel->hcintmsk = hcintmsk;
+    channel->hcintmsk = HCINT_HALTED;
     dwc2->haintmsk |= TU_BIT(ch_id);
 
     channel->hcdma = (uint32_t) edpt->buffer;
@@ -646,7 +721,6 @@ static bool edpt_xfer_kickoff(dwc2_regs_t* dwc2, uint8_t ep_id) {
   return channel_xfer_start(dwc2, ch_id);
 }
 
-// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   const uint8_t ep_num = tu_edpt_number(ep_addr);
@@ -654,7 +728,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 
   uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir);
   TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX);
-  hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id];
+  hcd_endpoint_t *edpt = &_hcd_data.edpt[ep_id];
+  TU_VERIFY(edpt->closing == 0); // skip if endpoint is closing
 
   edpt->buffer = buffer;
   edpt->buflen = buflen;
@@ -754,7 +829,7 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci
       edpt->next_pid = hctsiz.pid; // save PID
       edpt->uframe_countdown = edpt->uframe_interval - ucount;
       // enable SOF interrupt if not already enabled
-      if (!(dwc2->gintmsk & GINTMSK_SOFM)) {
+      if (0 == (dwc2->gintmsk & GINTMSK_SOFM)) {
         dwc2->gintsts = GINTSTS_SOF;
         dwc2->gintmsk |= GINTMSK_SOFM;
       }
@@ -767,7 +842,7 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci
   }
 }
 
-#if CFG_TUSB_DEBUG
+#if CFG_TUSB_DEBUG && 0
 TU_ATTR_ALWAYS_INLINE static inline void print_hcint(uint32_t hcint) {
   const char* str[] = {
     "XFRC", "HALTED", "AHBERR", "STALL",
@@ -801,8 +876,8 @@ static void handle_rxflvl_irq(uint8_t rhport) {
       TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,);
       hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
 
-      if (byte_count) {
-        dfifo_read_packet(dwc2, edpt->buffer + xfer->xferred_bytes, byte_count);
+      if (byte_count > 0) {
+        tu_hwfifo_read(dwc2->fifo[0], edpt->buffer + xfer->xferred_bytes, byte_count, NULL);
         xfer->xferred_bytes += byte_count;
         xfer->fifo_bytes = byte_count;
       }
@@ -815,7 +890,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
       break;
 
     case GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR:
-      TU_ASSERT(0, ); // maybe try to change DToggle
+      // handle in channel interrupt
       break;
 
     case GRXSTS_PKTSTS_HOST_CHANNEL_HALTED:
@@ -829,16 +904,13 @@ static void handle_rxflvl_irq(uint8_t rhport) {
 
 // return true if there is still pending data and need more ISR
 static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) {
-  // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough)
-  const dwc2_hptxsts_t txsts = {.value = (is_periodic ? dwc2->hptxsts : dwc2->hnptxsts)};
-
   const uint8_t max_channel = dwc2_channel_count(dwc2);
   for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) {
     dwc2_channel_t* channel = &dwc2->channel[ch_id];
     const dwc2_channel_char_t hcchar = {.value = channel->hcchar};
     // skip writing to FIFO if channel is expecting halted.
-    if (!(channel->hcintmsk & HCINT_HALTED) && (hcchar.ep_dir == TUSB_DIR_OUT)) {
-      hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
+    if (0 == (channel->hcintmsk & HCINT_HALTED) && (hcchar.ep_dir == TUSB_DIR_OUT)) {
+      hcd_xfer_t *xfer = &_hcd_data.xfer[ch_id];
       TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX);
       hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
       const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz};
@@ -849,11 +921,13 @@ static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) {
 
         // skip if there is not enough space in FIFO and RequestQueue.
         // Packet's last word written to FIFO will trigger a request queue
+        // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough)
+        const dwc2_hptxsts_t txsts = {.value = (is_periodic ? dwc2->hptxsts : dwc2->hnptxsts)};
         if ((xact_bytes > (txsts.fifo_available << 2)) || (txsts.req_queue_available == 0)) {
           return true;
         }
 
-        dfifo_write_packet(dwc2, ch_id, edpt->buffer + xfer->fifo_bytes, xact_bytes);
+        tu_hwfifo_write(dwc2->fifo[ch_id], edpt->buffer + xfer->fifo_bytes, xact_bytes, NULL);
         xfer->fifo_bytes += xact_bytes;
       }
     }
@@ -899,6 +973,8 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h
     } else if (hcint & HCINT_XACT_ERR) {
       xfer->err_count++;
       channel->hcintmsk |= HCINT_ACK;
+    } else {
+      // nothing to do
     }
 
     channel_disable(dwc2, channel);
@@ -910,7 +986,7 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h
     channel_disable(dwc2, channel);
   } else if (hcint & HCINT_NAK) {
     // NAK received, disable channel to flush all posted request and try again
-    if (hcsplt.split_en) {
+    if (hcsplt.split_en == 1u) {
       hcsplt.split_compl = 0; // restart with start-split
       channel->hcsplt = hcsplt.value;
     }
@@ -919,8 +995,8 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h
   } else if (hcint & HCINT_ACK) {
     xfer->err_count = 0;
 
-    if (hcsplt.split_en) {
-      if (!hcsplt.split_compl) {
+    if (hcsplt.split_en == 1u) {
+      if (hcsplt.split_compl == 0) {
         // start split is ACK --> do complete split
         channel->hcintmsk |= HCINT_NYET;
         hcsplt.split_compl = 1;
@@ -932,7 +1008,7 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h
     } else {
       // ACK with data
       const uint16_t remain_packets = hctsiz.packet_count;
-      if (remain_packets) {
+      if (remain_packets > 0) {
         // still more packet to receive, also reset to start split
         hcsplt.split_compl = 0;
         channel->hcsplt = hcsplt.value;
@@ -945,14 +1021,21 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h
       is_done = true;
     } else if (xfer->err_count == HCD_XFER_ERROR_MAX) {
       xfer->result = XFER_RESULT_FAILED;
+      is_done      = true;
+    } else if (xfer->closing == 1) {
       is_done = true;
     } else {
       // got here due to NAK or NYET
       channel_xfer_in_retry(dwc2, ch_id, hcint);
     }
   } else if (hcint & HCINT_DATATOGGLE_ERR) {
+    channel->hcintmsk &= ~HCINT_DATATOGGLE_ERR;
     xfer->err_count = 0;
-    TU_ASSERT(false);
+    hcsplt.split_compl = 0; // restart with start-split
+    channel->hcsplt = hcsplt.value;
+    channel_disable(dwc2, channel);
+  } else {
+    // nothing to do
   }
   return is_done;
 }
@@ -977,7 +1060,7 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t
     channel_disable(dwc2, channel);
   } else if (hcint & HCINT_NYET) {
     xfer->err_count = 0;
-    if (hcsplt.split_en) {
+    if (hcsplt.split_en == 1u) {
       // retry complete split
       hcsplt.split_compl = 1;
       channel->hcsplt = hcsplt.value;
@@ -1005,6 +1088,8 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t
       is_done = true;
     } else if (xfer->err_count == HCD_XFER_ERROR_MAX) {
       xfer->result = XFER_RESULT_FAILED;
+      is_done      = true;
+    } else if (xfer->closing == 1) {
       is_done = true;
     } else {
       // Got here due to NAK or NYET
@@ -1013,8 +1098,8 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t
   } else if (hcint & HCINT_ACK) {
     xfer->err_count = 0;
     channel->hcintmsk &= ~HCINT_ACK;
-    if (hcsplt.split_en) {
-      if (!hcsplt.split_compl) {
+    if (hcsplt.split_en == 1u) {
+      if (hcsplt.split_compl == 0) {
         // ACK for start split --> do complete split
         hcsplt.split_compl = 1;
         channel->hcsplt = hcsplt.value;
@@ -1026,6 +1111,8 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t
       channel->hctsiz &= ~HCTSIZ_DOPING; // HC already cleared PING bit, but we clear anyway
       channel->hcchar |= HCCHAR_CHENA;
     }
+  } else {
+    // nothing to do
   }
 
   if (is_done) {
@@ -1051,7 +1138,16 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci
   // TU_LOG1("in  hcint = %02lX\r\n", hcint);
 
   if (hcint & HCINT_HALTED) {
-    if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL | HCINT_BABBLE_ERR)) {
+    if (xfer->retry_disabled) {
+      // Halt from our split-NAK throttle disable (below): re-arm the start-split, or let teardown finish
+      // if the endpoint is closing. Programming Guide 3.5 "Halting a Channel" (p73).
+      xfer->retry_disabled = 0;
+      if (xfer->closing) {
+        is_done = true;
+      } else {
+        channel_send_in_token(dwc2, channel);
+      }
+    } else if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL | HCINT_BABBLE_ERR)) {
       const uint16_t remain_bytes = (uint16_t) hctsiz.xfer_size;
       const uint16_t remain_packets = hctsiz.packet_count;
       const uint16_t actual_len = edpt->buflen - remain_bytes;
@@ -1117,11 +1213,23 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci
       channel->hcintmsk &= ~(HCINT_NAK | HCINT_DATATOGGLE_ERR);
       hcsplt.split_compl = 0; // restart with start-split
       channel->hcsplt = hcsplt.value;
-      channel_xfer_in_retry(dwc2, ch_id, hcint);
+      // Persistent split bulk/control IN NAK (e.g. idle polled endpoint): re-enabling immediately storms
+      // the ISR and starves the task. Disable + re-arm on the resulting halt to throttle (like the slave
+      // path); no frame deferral. Programming Guide 3.5 (p73) Note permits disable on NAK/FrmOvrn splits.
+      if ((hcint & HCINT_NAK) && hcsplt.split_en && !channel_is_periodic(channel->hcchar)) {
+        xfer->retry_disabled = 1;
+        channel_disable(dwc2, channel);
+      } else {
+        channel_xfer_in_retry(dwc2, ch_id, hcint);
+      }
     } else if (hcint & HCINT_FARME_OVERRUN) {
       // retry start-split in next binterval
       channel_xfer_in_retry(dwc2, ch_id, hcint);
     }
+
+    if (xfer->closing == 1) {
+      is_done = true;
+    }
   }
 
   return is_done;
@@ -1131,7 +1239,6 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc
   hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
   dwc2_channel_t* channel = &dwc2->channel[ch_id];
   hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
-  const dwc2_channel_char_t hcchar = {.value = channel->hcchar};
   dwc2_channel_split_t hcsplt = {.value = channel->hcsplt};
 
   bool is_done = false;
@@ -1139,7 +1246,16 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc
   // TU_LOG1("out hcint = %02lX\r\n", hcint);
 
   if (hcint & HCINT_HALTED) {
-    if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL)) {
+    if (xfer->retry_disabled) {
+      // Halt from our split-XactErr throttle disable (below): re-issue the start-split (pointers already
+      // rewound), giving the hub TT a recovery gap. Programming Guide 3.5 "Halting a Channel" (p73).
+      xfer->retry_disabled = 0;
+      if (xfer->closing) {
+        is_done = true;
+      } else {
+        channel_xfer_start(dwc2, ch_id);
+      }
+    } else if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL)) {
       is_done = true;
       xfer->err_count = 0;
       if (hcint & HCINT_XFER_COMPLETE) {
@@ -1162,9 +1278,17 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc
          xfer->result = XFER_RESULT_FAILED;
          is_done = true;
        } else {
-         // clean up transfer so far and start again
+         // Rewind, then retry the start-split. Non-periodic SPLIT throttles via channel_disable + re-arm on
+         // the halt (immediate re-fire exhausts the retry budget; the disable gives the hub TT a recovery
+         // gap, like slave). Periodic split is excluded: channel_disable() is a no-op for it, so the halt
+         // never fires and the channel would wedge. Non-split re-inits immediately (Programming Guide 5.1.2.3).
          channel_xfer_out_wrapup(dwc2, ch_id);
-         channel_xfer_start(dwc2, ch_id);
+         if (hcsplt.split_en && !channel_is_periodic(channel->hcchar)) {
+           xfer->retry_disabled = 1;
+           channel_disable(dwc2, channel);
+         } else {
+           channel_xfer_start(dwc2, ch_id);
+         }
        }
      }
     } else if (hcint & HCINT_NYET) {
@@ -1182,6 +1306,16 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc
         channel->hcsplt = hcsplt.value;
         channel->hcchar |= HCCHAR_CHENA;
       }
+    } else if ((hcint & HCINT_NAK) && hcsplt.split_en) {
+      // Split OUT NAK: rewind + retry the start-split, else the channel stalls (Programming Guide 5.1.4.2).
+      // Non-split OUT NAK is core-handled (5.1.2.2), so this is split-only.
+      xfer->err_count = 0;
+      channel_xfer_out_wrapup(dwc2, ch_id);
+      channel_xfer_start(dwc2, ch_id);
+    }
+
+    if (xfer->closing == 1) {
+      is_done = true;
     }
   } else if (hcint & HCINT_ACK) {
     xfer->err_count = 0;
@@ -1227,12 +1361,17 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) {
         } else {
           is_done = handle_channel_in_slave(dwc2, ch_id, hcint);
         }
-        #endif
+  #endif
       }
 
       if (is_done) {
-        const uint8_t ep_addr = tu_edpt_addr(hcchar.ep_num, hcchar.ep_dir);
-        hcd_event_xfer_complete(hcchar.dev_addr, ep_addr, xfer->xferred_bytes, (xfer_result_t)xfer->result, in_isr);
+        if (xfer->closing == 1) {
+          hcd_endpoint_t *edpt = &_hcd_data.edpt[xfer->ep_id];
+          edpt_dealloc(edpt);
+        } else {
+          const uint8_t ep_addr = tu_edpt_addr(hcchar.ep_num, hcchar.ep_dir);
+          hcd_event_xfer_complete(hcchar.dev_addr, ep_addr, xfer->xferred_bytes, (xfer_result_t)xfer->result, in_isr);
+        }
         channel_dealloc(dwc2, ch_id);
       }
     }
@@ -1251,16 +1390,18 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) {
   const uint32_t ucount = (hprt_speed_get(dwc2) == TUSB_SPEED_HIGH ? 1 : 8);
 
   for(uint8_t ep_id = 0; ep_id < CFG_TUH_DWC2_ENDPOINT_MAX; ep_id++) {
-    hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id];
-    if (edpt->hcchar_bm.enable && channel_is_periodic(edpt->hcchar) && edpt->uframe_countdown > 0) {
-      edpt->uframe_countdown -= tu_min32(ucount, edpt->uframe_countdown);
-      if (edpt->uframe_countdown == 0) {
-        if (!edpt_xfer_kickoff(dwc2, ep_id)) {
-          edpt->uframe_countdown = ucount; // failed to start, try again next frame
+    hcd_endpoint_t *edpt = &_hcd_data.edpt[ep_id];
+    if (edpt->closing == 0) {
+      if (edpt->hcchar_bm.enable && channel_is_periodic(edpt->hcchar) && edpt->uframe_countdown > 0) {
+        edpt->uframe_countdown -= tu_min32(ucount, edpt->uframe_countdown);
+        if (edpt->uframe_countdown == 0) {
+          if (!edpt_xfer_kickoff(dwc2, ep_id)) {
+            edpt->uframe_countdown = ucount; // failed to start, try again next frame
+          }
         }
-      }
 
-      more_isr = true;
+        more_isr = true;
+      }
     }
   }
 
@@ -1268,13 +1409,24 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) {
 }
 
 // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit)
+// Databook Table 2-2: System Clock Speeds
+// +-----------+------------------+----------+-----------+-------------------+
+// | PHY       | PHY Clock (MHz)  | Width    | HCFG.Sel  | HFIR (clk cycles) |
+// +-----------+------------------+----------+-----------+-------------------+
+// | HS UTMI+  | 30               | 16-bit   | 30_60     | HS:3749 FS:29999  |
+// | HS UTMI+  | 60               |  8-bit   | 30_60     | HS:7499 FS:59999  |
+// | HS ULPI   | 60               |  8-bit   | 30_60     | HS:7499 FS:59999  |
+// | FS (dead.) | 48               | internal | 48        | FS:47999          |
+// | LS via FS | 48 (6 effective) | internal | 6         | LS:47999          |
+// +-----------+------------------+----------+-----------+-------------------+
+// HFIR = (interval_us * phy_clock) - 1, where interval is 125us (HS) or 1000us (FS/LS)
 static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) {
   uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL;
 
   const dwc2_gusbcfg_t gusbcfg = {.value = dwc2->gusbcfg};
-  uint32_t phy_clock;
+  uint32_t             phy_clock;
 
-  if (gusbcfg.phy_sel) {
+  if (gusbcfg.phy_sel == GUSBCFG_PHYSEL_FULLSPEED) {
     phy_clock = 48; // dedicated FS is 48Mhz
     if (speed == TUSB_SPEED_LOW) {
       hcfg |= HCFG_FSLS_PHYCLK_SEL_6MHZ;
@@ -1282,7 +1434,7 @@ static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) {
       hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ;
     }
   } else {
-    if (gusbcfg.ulpi_utmi_sel) {
+    if (gusbcfg.ulpi_utmi_sel == GUSBCFG_PHYHS_ULPI) {
       phy_clock = 60; // ULPI 8-bit is 60Mhz
     } else {
       // UTMI+ 16-bit is 30Mhz, 8-bit is 60Mhz
@@ -1321,20 +1473,20 @@ static void handle_hprt_irq(uint8_t rhport, bool in_isr) {
   const dwc2_hprt_t hprt_bm = {.value = dwc2->hprt};
   uint32_t hprt = hprt_bm.value & ~HPRT_W1_MASK;
 
-  if (hprt_bm.conn_detected) {
+  if (hprt_bm.conn_detected == 1u) {
     // Port Connect Detect
     hprt |= HPRT_CONN_DETECT;
 
-    if (hprt_bm.conn_status) {
+    if (hprt_bm.conn_status == 1u) {
       hcd_event_device_attach(rhport, in_isr);
     }
   }
 
-  if (hprt_bm.enable_change) {
+  if (hprt_bm.enable_change == 1u) {
     // Port enable change
     hprt |= HPRT_ENABLE_CHANGE;
 
-    if (hprt_bm.enable) {
+    if (hprt_bm.enable == 1u) {
       // Port enable
       const tusb_speed_t speed = hprt_speed_get(dwc2);
       port0_enable(dwc2, speed);
@@ -1360,16 +1512,6 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
 
   // TU_LOG1_HEX(gintsts);
 
-  if (gintsts & GINTSTS_CONIDSTSCHNG) {
-    // Connector ID status change
-    dwc2->gintsts = GINTSTS_CONIDSTSCHNG;
-
-    //if (dwc2->gotgctl)
-    // dwc2->hprt = HPRT_POWER; // power on port to turn on VBUS
-    //dwc2->gintmsk |= GINTMSK_PRTIM;
-    // TODO wait for SRP if OTG
-  }
-
   if (gintsts & GINTSTS_SOF) {
     const bool more_sof = handle_sof_irq(rhport, in_isr);
     if (!more_sof) {
@@ -1393,7 +1535,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
     // Device disconnected
     dwc2->gintsts = GINTSTS_DISCINT;
 
-    if (!(dwc2->hprt & HPRT_CONN_STATUS)) {
+    if (0 == (dwc2->hprt & HPRT_CONN_STATUS)) {
       hcd_event_device_remove(rhport, in_isr);
     }
   }