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authorHa Thach <[email protected]>2023-07-18 16:39:48 +0700
committerGitHub <[email protected]>2023-07-18 16:39:48 +0700
commit2bab947e3824e61b5e8e31392df626147406515d (patch)
tree6f0f3d349e5029ea988e48996c0489393129e807 /src/portable
parent6798e7e059d81268f04a3e206e6c4354b295dbf1 (diff)
parent8b6d0a166b3837e664eeabbada724b678b7fd62d (diff)
Merge pull request #2146 from tannewt/host_cache_align
Fix host buffer alignment setting
Diffstat (limited to 'src/portable')
-rw-r--r--src/portable/chipidea/ci_hs/ci_hs_imxrt.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index c14f00431..96f0ba766 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -78,6 +78,12 @@ TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void const* addr, ui
TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void const* addr, uint32_t data_size) {
const uintptr_t addr32 = (uintptr_t) addr;
if (imxrt_is_cache_mem(addr32)) {
+ // Invalidating does not push cached changes back to RAM so we need to be
+ // *very* careful when we do it. If we're not aligned, then we risk resetting
+ // values back to their RAM state.
+ // if (addr32 % 32 != 0) {
+ // TU_BREAKPOINT();
+ // }
SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
}
}