Merge branch 'master' into cr1901-msp430f5529

18 files changed, 3599 insertions, 1032 deletions

diff --git a/src/portable/microchip/samd51/dcd_samd51.c b/src/portable/microchip/samd/dcd_samd.c
index f58e7cbc7..148995520 100644
--- a/src/portable/microchip/samd51/dcd_samd51.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -26,17 +26,27 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMD51
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAMD21)
 
-#include "device/dcd.h"
 #include "sam.h"
+#include "device/dcd.h"
 
 /*------------------------------------------------------------------*/
 /* MACRO TYPEDEF CONSTANT ENUM
  *------------------------------------------------------------------*/
-static UsbDeviceDescBank sram_registers[8][2];
+static TU_ATTR_ALIGNED(4) UsbDeviceDescBank sram_registers[8][2];
 static TU_ATTR_ALIGNED(4) uint8_t _setup_packet[8];
 
+
+// ready for receiving SETUP packet
+static inline void prepare_setup(void)
+{
+  // Only make sure the EP0 OUT buffer is ready
+  sram_registers[0][0].ADDR.reg = (uint32_t) _setup_packet;
+  sram_registers[0][0].PCKSIZE.bit.MULTI_PACKET_SIZE = sizeof(_setup_packet);
+  sram_registers[0][0].PCKSIZE.bit.BYTE_COUNT = 0;
+}
+
 // Setup the control endpoint 0.
 static void bus_reset(void)
 {
@@ -51,7 +61,7 @@ static void bus_reset(void)
   ep->EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1 | USB_DEVICE_EPINTENSET_RXSTP;
 
   // Prepare for setup packet
-  dcd_edpt_xfer(0, 0, _setup_packet, sizeof(_setup_packet));
+  prepare_setup();
 }
 
 
@@ -69,10 +79,10 @@ void dcd_init (uint8_t rhport)
 
   USB->DEVICE.PADCAL.bit.TRANSP = (*((uint32_t*) USB_FUSES_TRANSP_ADDR) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
   USB->DEVICE.PADCAL.bit.TRANSN = (*((uint32_t*) USB_FUSES_TRANSN_ADDR) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
-  USB->DEVICE.PADCAL.bit.TRIM = (*((uint32_t*) USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos;
+  USB->DEVICE.PADCAL.bit.TRIM   = (*((uint32_t*) USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos;
 
-  USB->DEVICE.QOSCTRL.bit.CQOS = 3;
-  USB->DEVICE.QOSCTRL.bit.DQOS = 3;
+  USB->DEVICE.QOSCTRL.bit.CQOS = 3; // High Quality
+  USB->DEVICE.QOSCTRL.bit.DQOS = 3; // High Quality
 
   // Configure registers
   USB->DEVICE.DESCADD.reg = (uint32_t) &sram_registers;
@@ -81,9 +91,11 @@ void dcd_init (uint8_t rhport)
   while (USB->DEVICE.SYNCBUSY.bit.ENABLE == 1) {}
 
   USB->DEVICE.INTFLAG.reg |= USB->DEVICE.INTFLAG.reg; // clear pending
-  USB->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST;
+  USB->DEVICE.INTENSET.reg = /* USB_DEVICE_INTENSET_SOF | */ USB_DEVICE_INTENSET_EORST;
 }
 
+#if CFG_TUSB_MCU == OPT_MCU_SAMD51
+
 void dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
@@ -102,15 +114,30 @@ void dcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(USB_0_IRQn);
 }
 
+#elif CFG_TUSB_MCU == OPT_MCU_SAMD21
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USB_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB_IRQn);
+}
+#endif
+
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
-  // Response with status first before changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+  (void) dev_addr;
 
-  // Wait for EP0 to finish before switching the address.
-  while (USB->DEVICE.DeviceEndpoint[0].EPSTATUS.bit.BK1RDY == 1) {}
+  // Response with zlp status
+  dcd_edpt_xfer(rhport, 0x80, NULL, 0);
 
-  USB->DEVICE.DADD.reg = USB_DEVICE_DADD_DADD(dev_addr) | USB_DEVICE_DADD_ADDEN;
+  // DCD can only set address after status for this request is complete
+  // do it at dcd_edpt0_status_complete()
 
   // Enable SUSPEND interrupt since the bus signal D+/D- are stable now.
   USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTENCLR_SUSPEND; // clear pending
@@ -135,6 +162,26 @@ void dcd_remote_wakeup(uint8_t rhport)
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
 
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  (void) rhport;
+
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS )
+  {
+    uint8_t const dev_addr = (uint8_t) request->wValue;
+    USB->DEVICE.DADD.reg = USB_DEVICE_DADD_DADD(dev_addr) | USB_DEVICE_DADD_ADDEN;
+  }
+
+  // Just finished status stage, prepare for next setup packet
+  // Note: we may already prepare setup when the last EP0 OUT complete.
+  // but it has no harm to do it again here
+  prepare_setup();
+}
+
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
   (void) rhport;
@@ -181,12 +228,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   UsbDeviceDescBank* bank = &sram_registers[epnum][dir];
   UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
 
-  // A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid
-  // buffer for the control endpoint.
-  if (epnum == 0 && dir == 0 && buffer == NULL) {
-    buffer = _setup_packet;
-  }
-
   bank->ADDR.reg = (uint32_t) buffer;
   if ( dir == TUSB_DIR_OUT )
   {
@@ -233,39 +274,63 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   }
 }
 
-/*------------------------------------------------------------------*/
+//--------------------------------------------------------------------+
+// Interrupt Handler
+//--------------------------------------------------------------------+
+void maybe_transfer_complete(void) {
+  uint32_t epints = USB->DEVICE.EPINTSMRY.reg;
 
-static bool maybe_handle_setup_packet(void) {
-  if (USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.bit.RXSTP)
-  {
-    USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+  for (uint8_t epnum = 0; epnum < USB_EPT_NUM; epnum++) {
+    if ((epints & (1 << epnum)) == 0) {
+      continue;
+    }
 
-    // This copies the data elsewhere so we can reuse the buffer.
-    dcd_event_setup_received(0, (uint8_t*) sram_registers[0][0].ADDR.reg, true);
-    return true;
+    UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
+    uint32_t epintflag = ep->EPINTFLAG.reg;
+
+    // Handle IN completions
+    if ((epintflag & USB_DEVICE_EPINTFLAG_TRCPT1) != 0) {
+      UsbDeviceDescBank* bank = &sram_registers[epnum][TUSB_DIR_IN];
+      uint16_t total_transfer_size = bank->PCKSIZE.bit.BYTE_COUNT;
+
+      dcd_event_xfer_complete(0, epnum | TUSB_DIR_IN_MASK, total_transfer_size, XFER_RESULT_SUCCESS, true);
+
+      ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+    }
+
+    // Handle OUT completions
+    if ((epintflag & USB_DEVICE_EPINTFLAG_TRCPT0) != 0) {
+
+      UsbDeviceDescBank* bank = &sram_registers[epnum][TUSB_DIR_OUT];
+      uint16_t total_transfer_size = bank->PCKSIZE.bit.BYTE_COUNT;
+
+      // A SETUP token can occur immediately after an OUT packet
+      // so make sure we have a valid buffer for the control endpoint.
+      if (epnum == 0) {
+        prepare_setup();
+      }
+
+      dcd_event_xfer_complete(0, epnum, total_transfer_size, XFER_RESULT_SUCCESS, true);
+
+      ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+    }
   }
-  return false;
 }
-/*
- *------------------------------------------------------------------*/
-/* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN,
-USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1,
-USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4,
-USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7,
-USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2,
-USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5,
-USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1,
-USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6,
-USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1,
-USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4,
-USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7,
-USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2,
-USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5,
-USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
-void USB_0_Handler(void) {
+
+
+void dcd_isr (uint8_t rhport)
+{
+  (void) rhport;
+
   uint32_t int_status = USB->DEVICE.INTFLAG.reg & USB->DEVICE.INTENSET.reg;
 
   /*------------- Interrupt Processing -------------*/
+  if ( int_status & USB_DEVICE_INTFLAG_SOF )
+  {
+    USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+  }
+
   // SAMD doesn't distinguish between Suspend and Disconnect state.
   // Both condition will cause SUSPEND interrupt triggered.
   // To prevent being triggered when D+/D- are not stable, SUSPEND interrupt is only
@@ -303,48 +368,44 @@ void USB_0_Handler(void) {
     dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
   }
 
-  // Setup packet received.
-  maybe_handle_setup_packet();
-}
-
-/* USB_SOF_HSOF */
-void USB_1_Handler(void) {
-  USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
-  dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
-}
-
-void transfer_complete(uint8_t direction) {
-  uint32_t epints = USB->DEVICE.EPINTSMRY.reg;
-  for (uint8_t epnum = 0; epnum < USB_EPT_NUM; epnum++) {
-    if ((epints & (1 << epnum)) == 0) {
-      continue;
-    }
+  // Handle SETUP packet
+  if (USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.bit.RXSTP)
+  {
+    // This copies the data elsewhere so we can reuse the buffer.
+    dcd_event_setup_received(0, _setup_packet, true);
 
-    if (direction == TUSB_DIR_OUT && maybe_handle_setup_packet()) {
-      continue;
-    }
-    UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
+    USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+  }
 
-    UsbDeviceDescBank* bank = &sram_registers[epnum][direction];
-    uint16_t total_transfer_size = bank->PCKSIZE.bit.BYTE_COUNT;
+  // Handle complete transfer
+  maybe_transfer_complete();
+}
 
-    uint8_t ep_addr = epnum;
-    if (direction == TUSB_DIR_IN) {
-      ep_addr |= TUSB_DIR_IN_MASK;
-    }
-    dcd_event_xfer_complete(0, ep_addr, total_transfer_size, XFER_RESULT_SUCCESS, true);
+#if CFG_TUSB_MCU == OPT_MCU_SAMD51
 
-    // just finished status stage (total size = 0), prepare for next setup packet
-    if (epnum == 0 && total_transfer_size == 0) {
-      dcd_edpt_xfer(0, 0, _setup_packet, sizeof(_setup_packet));
-    }
+/*
+ *------------------------------------------------------------------*/
+/* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN,
+USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1,
+USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4,
+USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7,
+USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2,
+USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5,
+USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1,
+USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6,
+USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1,
+USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4,
+USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7,
+USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2,
+USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5,
+USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_0_Handler(void) {
+  dcd_isr(0);
+}
 
-    if (direction == TUSB_DIR_IN) {
-      ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
-    } else {
-      ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
-    }
-  }
+/* USB_SOF_HSOF */
+void USB_1_Handler(void) {
+  dcd_isr(0);
 }
 
 // Bank zero is for OUT and SETUP transactions.
@@ -352,7 +413,7 @@ void transfer_complete(uint8_t direction) {
 USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5,
 USB_TRCPT0_6, USB_TRCPT0_7 */
 void USB_2_Handler(void) {
-  transfer_complete(TUSB_DIR_OUT);
+  dcd_isr(0);
 }
 
 // Bank one is used for IN transactions.
@@ -360,7 +421,15 @@ void USB_2_Handler(void) {
 USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5,
 USB_TRCPT1_6, USB_TRCPT1_7 */
 void USB_3_Handler(void) {
-  transfer_complete(TUSB_DIR_IN);
+  dcd_isr(0);
+}
+
+#elif CFG_TUSB_MCU == OPT_MCU_SAMD21
+
+void USB_Handler(void) {
+  dcd_isr(0);
 }
 
 #endif
+
+#endif
diff --git a/src/portable/microchip/samd21/dcd_samd21.c b/src/portable/microchip/samd21/dcd_samd21.c
deleted file mode 100644
index 231abc7d0..000000000
--- a/src/portable/microchip/samd21/dcd_samd21.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2018 Scott Shawcroft for Adafruit Industries
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMD21
-
-#include "device/dcd.h"
-#include "sam.h"
-
-/*------------------------------------------------------------------*/
-/* MACRO TYPEDEF CONSTANT ENUM
- *------------------------------------------------------------------*/
-static TU_ATTR_ALIGNED(4) UsbDeviceDescBank sram_registers[8][2];
-static TU_ATTR_ALIGNED(4) uint8_t _setup_packet[8];
-
-// Setup the control endpoint 0.
-static void bus_reset(void)
-{
-  // Max size of packets is 64 bytes.
-  UsbDeviceDescBank* bank_out = &sram_registers[0][TUSB_DIR_OUT];
-  bank_out->PCKSIZE.bit.SIZE = 0x3;
-  UsbDeviceDescBank* bank_in = &sram_registers[0][TUSB_DIR_IN];
-  bank_in->PCKSIZE.bit.SIZE = 0x3;
-
-  UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[0];
-  ep->EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0x1) | USB_DEVICE_EPCFG_EPTYPE1(0x1);
-  ep->EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1 | USB_DEVICE_EPINTENSET_RXSTP;
-
-  // Prepare for setup packet
-  dcd_edpt_xfer(0, 0, _setup_packet, sizeof(_setup_packet));
-}
-
-
-/*------------------------------------------------------------------*/
-/* Controller API
- *------------------------------------------------------------------*/
-void dcd_init (uint8_t rhport)
-{
-  (void) rhport;
-
-  // Reset to get in a clean state.
-  USB->DEVICE.CTRLA.bit.SWRST = true;
-  while (USB->DEVICE.SYNCBUSY.bit.SWRST == 0) {}
-  while (USB->DEVICE.SYNCBUSY.bit.SWRST == 1) {}
-
-  USB->DEVICE.PADCAL.bit.TRANSP = (*((uint32_t*) USB_FUSES_TRANSP_ADDR) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
-  USB->DEVICE.PADCAL.bit.TRANSN = (*((uint32_t*) USB_FUSES_TRANSN_ADDR) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
-  USB->DEVICE.PADCAL.bit.TRIM = (*((uint32_t*) USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos;
-
-  USB->DEVICE.QOSCTRL.bit.CQOS = USB_QOSCTRL_CQOS_HIGH_Val;
-  USB->DEVICE.QOSCTRL.bit.DQOS = USB_QOSCTRL_DQOS_HIGH_Val;
-
-  // Configure registers
-  USB->DEVICE.DESCADD.reg = (uint32_t) &sram_registers;
-  USB->DEVICE.CTRLB.reg = USB_DEVICE_CTRLB_SPDCONF_FS;
-  USB->DEVICE.CTRLA.reg = USB_CTRLA_MODE_DEVICE | USB_CTRLA_ENABLE | USB_CTRLA_RUNSTDBY;
-  while (USB->DEVICE.SYNCBUSY.bit.ENABLE == 1) {}
-
-  USB->DEVICE.INTFLAG.reg |= USB->DEVICE.INTFLAG.reg; // clear pending
-  USB->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST;
-}
-
-void dcd_int_enable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_EnableIRQ(USB_IRQn);
-}
-
-void dcd_int_disable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_DisableIRQ(USB_IRQn);
-}
-
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
-{
-  // Response with status first before changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-
-  // Wait for EP0 to finish before switching the address.
-  while (USB->DEVICE.DeviceEndpoint[0].EPSTATUS.bit.BK1RDY == 1) {}
-
-  USB->DEVICE.DADD.reg = USB_DEVICE_DADD_DADD(dev_addr) | USB_DEVICE_DADD_ADDEN;
-
-  // Enable SUSPEND interrupt since the bus signal D+/D- are stable now.
-  USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTENCLR_SUSPEND; // clear pending
-  USB->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
-}
-
-void dcd_set_config (uint8_t rhport, uint8_t config_num)
-{
-  (void) rhport;
-  (void) config_num;
-  // Nothing to do
-
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void) rhport;
-
-  USB->DEVICE.CTRLB.bit.UPRSM = 1;
-}
-
-/*------------------------------------------------------------------*/
-/* DCD Endpoint port
- *------------------------------------------------------------------*/
-
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
-{
-  (void) rhport;
-
-  uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
-
-  UsbDeviceDescBank* bank = &sram_registers[epnum][dir];
-  uint32_t size_value = 0;
-  while (size_value < 7) {
-    if (1 << (size_value + 3) == desc_edpt->wMaxPacketSize.size) {
-      break;
-    }
-    size_value++;
-  }
-
-  // unsupported endpoint size
-  if ( size_value == 7 && desc_edpt->wMaxPacketSize.size != 1023 ) return false;
-
-  bank->PCKSIZE.bit.SIZE = size_value;
-
-  UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
-
-  if ( dir == TUSB_DIR_OUT )
-  {
-    ep->EPCFG.bit.EPTYPE0 = desc_edpt->bmAttributes.xfer + 1;
-    ep->EPINTENSET.bit.TRCPT0 = true;
-  }else
-  {
-    ep->EPCFG.bit.EPTYPE1 = desc_edpt->bmAttributes.xfer + 1;
-    ep->EPINTENSET.bit.TRCPT1 = true;
-  }
-
-  return true;
-}
-
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  (void) rhport;
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  UsbDeviceDescBank* bank = &sram_registers[epnum][dir];
-  UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
-
-  // A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid
-  // buffer for the control endpoint.
-  if (epnum == 0 && dir == 0 && buffer == NULL) {
-      buffer = _setup_packet;
-  }
-
-  bank->ADDR.reg = (uint32_t) buffer;
-  if ( dir == TUSB_DIR_OUT )
-  {
-    bank->PCKSIZE.bit.MULTI_PACKET_SIZE = total_bytes;
-    bank->PCKSIZE.bit.BYTE_COUNT = 0;
-    ep->EPSTATUSCLR.reg |= USB_DEVICE_EPSTATUSCLR_BK0RDY;
-    ep->EPINTFLAG.reg |= USB_DEVICE_EPINTFLAG_TRFAIL0;
-  } else
-  {
-    bank->PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
-    bank->PCKSIZE.bit.BYTE_COUNT = total_bytes;
-    // bank->PCKSIZE.bit.AUTO_ZLP = 1;
-    ep->EPSTATUSSET.reg |= USB_DEVICE_EPSTATUSSET_BK1RDY;
-    ep->EPINTFLAG.reg |= USB_DEVICE_EPINTFLAG_TRFAIL1;
-  }
-
-  return true;
-}
-
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
-
-  if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
-      ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
-  } else {
-      ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
-  }
-}
-
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
-
-  if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
-    ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1 | USB_DEVICE_EPSTATUSCLR_DTGLIN;
-  } else {
-    ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0 | USB_DEVICE_EPSTATUSCLR_DTGLOUT;
-  }
-}
-
-/*------------------------------------------------------------------*/
-
-static bool maybe_handle_setup_packet(void) {
-  if (USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.bit.RXSTP)
-  {
-    USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
-
-    // This copies the data elsewhere so we can reuse the buffer.
-    dcd_event_setup_received(0, (uint8_t*) sram_registers[0][0].ADDR.reg, true);
-    return true;
-  }
-  return false;
-}
-
-void maybe_transfer_complete(void) {
-  uint32_t epints = USB->DEVICE.EPINTSMRY.reg;
-
-  for (uint8_t epnum = 0; epnum < USB_EPT_NUM; epnum++) {
-    if ((epints & (1 << epnum)) == 0) {
-      continue;
-    }
-
-    if (maybe_handle_setup_packet()) {
-      continue;
-    }
-
-    UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
-
-    uint32_t epintflag = ep->EPINTFLAG.reg;
-
-    uint16_t total_transfer_size = 0;
-
-    // Handle IN completions
-    if ((epintflag & USB_DEVICE_EPINTFLAG_TRCPT1) != 0) {
-      ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
-
-      UsbDeviceDescBank* bank = &sram_registers[epnum][TUSB_DIR_IN];
-      total_transfer_size = bank->PCKSIZE.bit.BYTE_COUNT;
-
-      uint8_t ep_addr = epnum | TUSB_DIR_IN_MASK;
-      dcd_event_xfer_complete(0, ep_addr, total_transfer_size, XFER_RESULT_SUCCESS, true);
-    }
-
-    // Handle OUT completions
-    if ((epintflag & USB_DEVICE_EPINTFLAG_TRCPT0) != 0) {
-      ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
-
-      UsbDeviceDescBank* bank = &sram_registers[epnum][TUSB_DIR_OUT];
-      total_transfer_size = bank->PCKSIZE.bit.BYTE_COUNT;
-
-      uint8_t ep_addr = epnum;
-      dcd_event_xfer_complete(0, ep_addr, total_transfer_size, XFER_RESULT_SUCCESS, true);
-    }
-
-    // Just finished status stage (total size = 0), prepare for next setup packet
-    // TODO could cause issue with actual zero length data used by class such as DFU
-    if (epnum == 0 && total_transfer_size == 0) {
-      dcd_edpt_xfer(0, 0, _setup_packet, sizeof(_setup_packet));
-    }
-  }
-}
-
-void USB_Handler(void)
-{
-  uint32_t int_status = USB->DEVICE.INTFLAG.reg & USB->DEVICE.INTENSET.reg;
-  USB->DEVICE.INTFLAG.reg = int_status; // clear interrupt
-
-  /*------------- Interrupt Processing -------------*/
-  if ( int_status & USB_DEVICE_INTFLAG_SOF )
-  {
-    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
-  }
-
-  // SAMD doesn't distinguish between Suspend and Disconnect state.
-  // Both condition will cause SUSPEND interrupt triggered.
-  // To prevent being triggered when D+/D- are not stable, SUSPEND interrupt is only
-  // enabled when we received SET_ADDRESS request and cleared on Bus Reset
-  if ( int_status & USB_DEVICE_INTFLAG_SUSPEND )
-  {
-    // Enable wakeup interrupt
-    USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; // clear pending
-    USB->DEVICE.INTENSET.reg = USB_DEVICE_INTFLAG_WAKEUP;
-
-    dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
-  }
-
-  // Wakeup interrupt is only enabled when we got suspended.
-  // Wakeup interrupt will disable itself
-  if ( int_status & USB_DEVICE_INTFLAG_WAKEUP )
-  {
-    // disable wakeup interrupt itself
-    USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTFLAG_WAKEUP;
-    dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
-  }
-
-  if ( int_status & USB_DEVICE_INTFLAG_EORST )
-  {
-    // Disable both suspend and wakeup interrupt
-    USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_SUSPEND;
-
-    bus_reset();
-    dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
-  }
-
-  // Setup packet received.
-  maybe_handle_setup_packet();
-
-  // Handle complete transfer
-  maybe_transfer_complete();
-}
-
-#endif
diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c
new file mode 100644
index 000000000..882072521
--- /dev/null
+++ b/src/portable/microchip/samg/dcd_samg.c
@@ -0,0 +1,467 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_SAMG
+
+#include "sam.h"
+#include "device/dcd.h"
+
+// TODO should support (SAM3S || SAM4S || SAM4E || SAMG55)
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+#define EP_COUNT    6
+
+// Transfer descriptor
+typedef struct
+{
+  uint8_t* buffer;
+  uint16_t total_len;
+  volatile uint16_t actual_len;
+  uint16_t  epsize;
+} xfer_desc_t;
+
+// Endpoint 0-5, each can only be either OUT or In
+xfer_desc_t _dcd_xfer[EP_COUNT];
+
+// Indicate that DATA Toggle for Control Status is incorrect, which must always be DATA1 by USB Specs.
+// However SAMG DToggle is read-only, therefore we must duplicate the status phase ( D0 then D1 )
+// as walk-around to resolve this. The D0 status packet is likely to be discarded by USB Host safely.
+// Note: Only needed for IN Status e.g CDC_SET_LINE_CODING, since out data is sent by host
+volatile bool _walkaround_incorrect_dtoggle_control_status;
+
+void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize)
+{
+  xfer->epsize = epsize;
+}
+
+void xfer_begin(xfer_desc_t* xfer, uint8_t * buffer, uint16_t total_bytes)
+{
+  xfer->buffer     = buffer;
+  xfer->total_len  = total_bytes;
+  xfer->actual_len = 0;
+}
+
+void xfer_end(xfer_desc_t* xfer)
+{
+  xfer->buffer     = NULL;
+  xfer->total_len  = 0;
+  xfer->actual_len = 0;
+}
+
+uint16_t xfer_packet_len(xfer_desc_t* xfer)
+{
+  // also cover zero-length packet
+  return tu_min16(xfer->total_len - xfer->actual_len, xfer->epsize);
+}
+
+void xfer_packet_done(xfer_desc_t* xfer)
+{
+  uint16_t const xact_len = xfer_packet_len(xfer);
+
+  xfer->buffer += xact_len;
+  xfer->actual_len += xact_len;
+}
+
+//------------- Transaction helpers -------------//
+
+// Write data to EP FIFO, return number of written bytes
+static void xact_ep_write(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
+{
+  for(uint16_t i=0; i<xact_len; i++)
+  {
+    UDP->UDP_FDR[epnum] = (uint32_t) buffer[i];
+  }
+}
+
+// Read data from EP FIFO
+static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
+{
+  for(uint16_t i=0; i<xact_len; i++)
+  {
+    buffer[i] = (uint8_t) UDP->UDP_FDR[epnum];
+  }
+}
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+
+// Set up endpoint 0, clear all other endpoints
+static void bus_reset(void)
+{
+  _walkaround_incorrect_dtoggle_control_status = false;
+  tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
+
+  xfer_epsize_set(&_dcd_xfer[0], CFG_TUD_ENDPOINT0_SIZE);
+
+  // Enable EP0 control
+  UDP->UDP_CSR[0] = UDP_CSR_EPEDS_Msk;
+
+  // Enable interrupt : EP0, Suspend, Resume, Wakeup
+  UDP->UDP_IER = UDP_IER_EP0INT_Msk | UDP_IER_RXSUSP_Msk | UDP_IER_RXRSM_Msk | UDP_IER_WAKEUP_Msk;
+
+  // Enable transceiver
+  UDP->UDP_TXVC &= ~UDP_TXVC_TXVDIS_Msk;
+}
+
+// Initialize controller to device mode
+void dcd_init (uint8_t rhport)
+{
+  (void) rhport;
+
+  tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
+
+  // Enable pull-up, disable transceiver
+  UDP->UDP_TXVC = UDP_TXVC_PUON | UDP_TXVC_TXVDIS_Msk;
+}
+
+// Enable device interrupt
+void dcd_int_enable (uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(UDP_IRQn);
+}
+
+// Disable device interrupt
+void dcd_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(UDP_IRQn);
+}
+
+// Receive Set Address request, mcu port must also include status IN response
+void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+  (void) dev_addr;
+
+  // Response with zlp status
+  dcd_edpt_xfer(rhport, 0x80, NULL, 0);
+
+  // DCD can only set address after status for this request is complete.
+  // do it at dcd_edpt0_status_complete()
+}
+
+// Receive Set Configure request
+void dcd_set_config (uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+
+  // Configured State
+//  UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG_Msk;
+}
+
+// Wake up host
+void dcd_remote_wakeup (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  (void) rhport;
+
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD )
+  {
+    if (request->bRequest == TUSB_REQ_SET_ADDRESS)
+    {
+      uint8_t const dev_addr = (uint8_t) request->wValue;
+
+      // Enable addressed state
+      UDP->UDP_GLB_STAT |= UDP_GLB_STAT_FADDEN_Msk;
+
+      // Set new address & Function enable bit
+      UDP->UDP_FADDR = UDP_FADDR_FEN_Msk | UDP_FADDR_FADD(dev_addr);
+    }
+    else if (request->bRequest == TUSB_REQ_SET_CONFIGURATION)
+    {
+      // Configured State
+      UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG_Msk;
+    }
+  }
+}
+
+// Configure endpoint's registers according to descriptor
+// SAMG doesn't support a same endpoint number with IN and OUT
+//    e.g EP1 OUT & EP1 IN cannot exist together
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress);
+  uint8_t const dir   = tu_edpt_dir(ep_desc->bEndpointAddress);
+
+  // TODO Isochronous is not supported yet
+  TU_VERIFY(ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
+  TU_VERIFY(epnum < EP_COUNT);
+
+  // Must not already enabled
+  TU_ASSERT((UDP->UDP_CSR[epnum] & UDP_CSR_EPEDS_Msk) == 0);
+
+  xfer_epsize_set(&_dcd_xfer[epnum], ep_desc->wMaxPacketSize.size);
+
+  // Configure type and eanble EP
+  UDP->UDP_CSR[epnum] = UDP_CSR_EPEDS_Msk | UDP_CSR_EPTYPE(ep_desc->bmAttributes.xfer + 4*dir);
+
+  // Enable EP Interrupt for IN
+  if (dir == TUSB_DIR_IN) UDP->UDP_IER |= (1 << epnum);
+
+  return true;
+}
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  (void) rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  xfer_desc_t* xfer = &_dcd_xfer[epnum];
+  xfer_begin(xfer, buffer, total_bytes);
+
+  if (dir == TUSB_DIR_OUT)
+  {
+    // Clear EP0 direction bit
+    if (epnum == 0) UDP->UDP_CSR[epnum] &= ~UDP_CSR_DIR_Msk;
+
+    // Enable interrupt when starting OUT transfer
+    if (epnum != 0) UDP->UDP_IER |= (1 << epnum);
+  }
+  else
+  {
+    if (epnum == 0)
+    {
+      // Previous EP0 direction is OUT --> This transfer is ZLP control status.
+      if ( !(UDP->UDP_CSR[epnum] & UDP_CSR_DIR_Msk) )
+      {
+        // Set EP0 dir bit
+        UDP->UDP_CSR[epnum] |= UDP_CSR_DIR_Msk;
+
+        // DATA Toggle is 0, USB Specs requires Status Stage must be DATA1
+        // Since SAMG DToggle is read-only, we mark this and implement the walk-around
+        if ( !(UDP->UDP_CSR[epnum] & UDP_CSR_DTGLE_Msk) )
+        {
+          TU_LOG2("Incorrect DATA TOGGLE, Control Status must be DATA1\n");
+
+          // DTGLE is read-only on SAMG, this statement has no effect
+          UDP->UDP_CSR[epnum] |= UDP_CSR_DTGLE_Msk;
+
+          // WALKROUND: duplicate IN transfer to send DATA1 status packet
+          // set flag for irq to skip reporting first incorrect packet
+          _walkaround_incorrect_dtoggle_control_status = true;
+
+          UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
+          while ( UDP->UDP_CSR[epnum] & UDP_CSR_TXPKTRDY_Msk ) {}
+
+          _walkaround_incorrect_dtoggle_control_status = false;
+        }
+      }
+    }
+
+    xact_ep_write(epnum, xfer->buffer, xfer_packet_len(xfer));
+
+    // TX ready for transfer
+    UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
+  }
+
+  return true;
+}
+
+// Stall endpoint
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+
+  // Set force stall bit
+  UDP->UDP_CSR[epnum] |= UDP_CSR_FORCESTALL_Msk;
+}
+
+// clear stall, data toggle is also reset to DATA0
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+
+  // clear stall
+  UDP->UDP_CSR[epnum] &= ~UDP_CSR_FORCESTALL_Msk;
+
+  // must also reset EP to clear data toggle
+  UDP->UDP_RST_EP = tu_bit_set(UDP->UDP_RST_EP, epnum);
+  UDP->UDP_RST_EP = tu_bit_clear(UDP->UDP_RST_EP, epnum);
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_isr(uint8_t rhport)
+{
+  uint32_t const intr_mask   = UDP->UDP_IMR;
+  uint32_t const intr_status = UDP->UDP_ISR & intr_mask;
+
+  // clear interrupt
+  UDP->UDP_ICR = intr_status;
+
+  // Bus reset
+  if (intr_status & UDP_ISR_ENDBUSRES_Msk)
+  {
+    bus_reset();
+    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
+  }
+
+  // SOF
+//  if (intr_status & UDP_ISR_SOFINT_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+
+  // Suspend
+  if (intr_status & UDP_ISR_RXSUSP_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+
+  // Resume
+  if (intr_status & UDP_ISR_RXRSM_Msk)  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+
+  // Wakeup
+  if (intr_status & UDP_ISR_WAKEUP_Msk)  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+
+  //------------- Endpoints -------------//
+
+  if ( intr_status & TU_BIT(0) )
+  {
+    // setup packet
+    if (UDP->UDP_CSR[0] & UDP_CSR_RXSETUP)
+    {
+      // get setup from FIFO
+      uint8_t setup[8];
+      for(uint8_t i=0; i<sizeof(setup); i++)
+      {
+        setup[i] = (uint8_t) UDP->UDP_FDR[0];
+      }
+
+      // notify usbd
+      dcd_event_setup_received(rhport, setup, true);
+
+      // Set EP direction bit according to DATA stage
+      if (setup[0] & 0x80)
+      {
+        UDP->UDP_CSR[0] |= UDP_CSR_DIR_Msk;
+      }else
+      {
+        UDP->UDP_CSR[0] &= ~UDP_CSR_DIR_Msk;
+      }
+
+      // Clear Setup bit & stall bit if needed
+      UDP->UDP_CSR[0] &= ~(UDP_CSR_RXSETUP_Msk | UDP_CSR_FORCESTALL_Msk);
+
+      return;
+    }
+  }
+
+  for(uint8_t epnum = 0; epnum < EP_COUNT; epnum++)
+  {
+    if ( intr_status & TU_BIT(epnum) )
+    {
+      xfer_desc_t* xfer = &_dcd_xfer[epnum];
+
+      //------------- Endpoint IN -------------//
+      if (UDP->UDP_CSR[epnum] & UDP_CSR_TXCOMP_Msk)
+      {
+        xfer_packet_done(xfer);
+
+        uint16_t const xact_len = xfer_packet_len(xfer);
+
+        if (xact_len)
+        {
+          // write to EP fifo
+          xact_ep_write(epnum, xfer->buffer, xact_len);
+
+          // TX ready for transfer
+          UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
+        }else
+        {
+          // WALKAROUND: Skip reporting this incorrect DATA Toggle status IN transfer
+          if ( !(_walkaround_incorrect_dtoggle_control_status && (epnum == 0) && (xfer->actual_len == 0)) )
+          {
+            // xfer is complete
+            dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
+
+            // Required since control OUT can happen right after before stack handle this event
+            xfer_end(xfer);
+          }
+        }
+
+        // Clear TX Complete bit
+        UDP->UDP_CSR[epnum] &= ~UDP_CSR_TXCOMP_Msk;
+      }
+
+      //------------- Endpoint OUT -------------//
+      // Ping-Pong is a MUST for Bulk/Iso
+      // NOTE: When both Bank0 and Bank1 are both set, there is no way to know which one comes first
+      uint32_t const banks_complete = UDP->UDP_CSR[epnum] & (UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk);
+      if (banks_complete)
+      {
+        uint16_t const xact_len = (uint16_t) ((UDP->UDP_CSR[epnum] & UDP_CSR_RXBYTECNT_Msk) >> UDP_CSR_RXBYTECNT_Pos);
+
+        // Read from EP fifo
+        xact_ep_read(epnum, xfer->buffer, xact_len);
+        xfer_packet_done(xfer);
+
+        if ( 0 == xfer_packet_len(xfer) )
+        {
+          // Disable OUT EP interrupt when transfer is complete
+          if (epnum != 0) UDP->UDP_IDR |= (1 << epnum);
+
+          dcd_event_xfer_complete(rhport, epnum, xfer->actual_len, XFER_RESULT_SUCCESS, true);
+          xfer_end(xfer);
+        }
+
+        // Clear DATA Bank0/1 bit
+        UDP->UDP_CSR[epnum] &= ~banks_complete;
+      }
+
+      // Stall sent to host
+      if (UDP->UDP_CSR[epnum] & UDP_CSR_STALLSENT_Msk)
+      {
+        UDP->UDP_CSR[epnum] &= ~UDP_CSR_STALLSENT_Msk;
+      }
+    }
+  }
+}
+
+#endif
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 17140ee75..2ce288d6c 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -31,7 +31,6 @@
 #include "nrf.h"
 #include "nrf_clock.h"
 #include "nrf_power.h"
-#include "nrf_usbd.h"
 #include "nrfx_usbd_errata.h"
 
 #ifdef SOFTDEVICE_PRESENT
@@ -277,8 +276,10 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer->total_len  = total_bytes;
   xfer->actual_len = 0;
 
-  // Control endpoint with zero-length packet --> status stage
-  if ( epnum == 0 && total_bytes == 0 )
+  // Control endpoint with zero-length packet and opposite direction to 1st request byte --> status stage
+  bool const control_status = (epnum == 0 && total_bytes == 0 && dir != tu_edpt_dir(NRF_USBD->BMREQUESTTYPE));
+
+  if ( control_status )
   {
     // Status Phase also require Easy DMA has to be free as well !!!!
     edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
@@ -498,7 +499,8 @@ void USBD_IRQHandler(void)
   if ( int_status & (USBD_INTEN_EPDATA_Msk | USBD_INTEN_EP0DATADONE_Msk) )
   {
     uint32_t data_status = NRF_USBD->EPDATASTATUS;
-    nrf_usbd_epdatastatus_clear(data_status);
+    NRF_USBD->EPDATASTATUS = data_status;
+    __ISB(); __DSB();
 
     // EP0DATADONE is set with either Control Out on IN Data
     // Since EPDATASTATUS cannot be used to determine whether it is control OUT or IN.
@@ -572,7 +574,7 @@ static bool hfclk_running(void)
   }
 #endif
 
-  return nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY);
+  return nrf_clock_hf_is_running(NRF_CLOCK, NRF_CLOCK_HFCLK_HIGH_ACCURACY);
 }
 
 static void hfclk_enable(void)
@@ -588,8 +590,8 @@ static void hfclk_enable(void)
   }
 #endif
 
-  nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED);
-  nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTART);
+  nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
+  nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTART);
 }
 
 static void hfclk_disable(void)
@@ -602,7 +604,7 @@ static void hfclk_disable(void)
   }
 #endif
 
-  nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP);
+  nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
 }
 
 // Power & Clock Peripheral on nRF5x to manage USB
@@ -630,7 +632,8 @@ void tusb_hal_nrf_power_event (uint32_t event)
       if ( !NRF_USBD->ENABLE )
       {
         /* Prepare for READY event receiving */
-        nrf_usbd_eventcause_clear(NRF_USBD_EVENTCAUSE_READY_MASK);
+        NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
+        __ISB(); __DSB(); // for sync
 
         /* Enable the peripheral */
         // ERRATA 171, 187, 166
@@ -667,7 +670,8 @@ void tusb_hal_nrf_power_event (uint32_t event)
           // CRITICAL_REGION_EXIT();
         }
 
-        nrf_usbd_enable();
+        NRF_USBD->ENABLE = 1;
+        __ISB(); __DSB(); // for sync
 
         // Enable HFCLK
         hfclk_enable();
@@ -678,8 +682,8 @@ void tusb_hal_nrf_power_event (uint32_t event)
       /* Waiting for USBD peripheral enabled */
       while ( !(USBD_EVENTCAUSE_READY_Msk & NRF_USBD->EVENTCAUSE) ) { }
 
-      nrf_usbd_eventcause_clear(USBD_EVENTCAUSE_READY_Msk);
-      nrf_usbd_event_clear(USBD_EVENTCAUSE_READY_Msk);
+      NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
+      __ISB(); __DSB(); // for sync
 
       if ( nrfx_usbd_errata_171() )
       {
@@ -719,11 +723,11 @@ void tusb_hal_nrf_power_event (uint32_t event)
         *((volatile uint32_t *) (NRF_USBD_BASE + 0x800)) = 0x7E3;
         *((volatile uint32_t *) (NRF_USBD_BASE + 0x804)) = 0x40;
 
-        __ISB();
-        __DSB();
+        __ISB(); __DSB();
       }
 
-      nrf_usbd_isosplit_set(USBD_ISOSPLIT_SPLIT_HalfIN);
+      // ISO buffer Lower half for IN, upper half for OUT
+      NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_HalfIN;
 
       // Enable interrupt
       NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_EPDATA_Msk |
@@ -737,7 +741,8 @@ void tusb_hal_nrf_power_event (uint32_t event)
       while ( !hfclk_running() ) { }
 
       // Enable pull up
-      nrf_usbd_pullup_enable();
+      NRF_USBD->USBPULLUP = 1;
+      __ISB(); __DSB(); // for sync
     break;
 
     case USB_EVT_REMOVED:
@@ -746,7 +751,8 @@ void tusb_hal_nrf_power_event (uint32_t event)
         // Abort all transfers
 
         // Disable pull up
-        nrf_usbd_pullup_disable();
+        NRF_USBD->USBPULLUP = 0;
+        __ISB(); __DSB(); // for sync
 
         // Disable Interrupt
         NVIC_DisableIRQ(USBD_IRQn);
@@ -754,7 +760,9 @@ void tusb_hal_nrf_power_event (uint32_t event)
         // disable all interrupt
         NRF_USBD->INTENCLR = NRF_USBD->INTEN;
 
-        nrf_usbd_disable();
+        NRF_USBD->ENABLE = 0;
+        __ISB(); __DSB(); // for sync
+
         hfclk_disable();
 
         dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c
new file mode 100644
index 000000000..4e1db24a4
--- /dev/null
+++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c
@@ -0,0 +1,433 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019-2020 Peter Lawrence
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/*
+  Theory of operation:
+
+  The NUC100/NUC120 USBD peripheral has six "EP"s, but each is simplex, 
+  so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to 
+  implement USB EP0.  PERIPH_EP0 and PERIPH_EP1 are used by this driver for 
+  EP0_IN and EP0_OUT respectively.  This leaves up to four for user usage.
+*/
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_NUC120)
+
+#include "device/dcd.h"
+#include "NUC100Series.h"
+
+/* allocation of USBD RAM for Setup, EP0_IN, and and EP_OUT */
+#define PERIPH_SETUP_BUF_BASE  0
+#define PERIPH_SETUP_BUF_LEN   8
+#define PERIPH_EP0_BUF_BASE    (PERIPH_SETUP_BUF_BASE + PERIPH_SETUP_BUF_LEN)
+#define PERIPH_EP0_BUF_LEN     CFG_TUD_ENDPOINT0_SIZE
+#define PERIPH_EP1_BUF_BASE    (PERIPH_EP0_BUF_BASE + PERIPH_EP0_BUF_LEN)
+#define PERIPH_EP1_BUF_LEN     CFG_TUD_ENDPOINT0_SIZE
+#define PERIPH_EP2_BUF_BASE    (PERIPH_EP1_BUF_BASE + PERIPH_EP1_BUF_LEN)
+
+/* rather important info unfortunately not provided by device include files: how much there is */
+#define USBD_BUF_SIZE          512
+
+enum ep_enum
+{
+  PERIPH_EP0 = 0,
+  PERIPH_EP1 = 1,
+  PERIPH_EP2 = 2,
+  PERIPH_EP3 = 3,
+  PERIPH_EP4 = 4,
+  PERIPH_EP5 = 5,
+  PERIPH_MAX_EP,
+};
+
+/* set by dcd_set_address() */
+static volatile uint8_t assigned_address;
+
+/* reset by dcd_init(), this is used by dcd_edpt_open() to assign USBD peripheral buffer addresses */
+static uint32_t bufseg_addr;
+
+/* used by dcd_edpt_xfer() and the ISR to reset the data sync (DATA0/DATA1) in an EP0_IN transfer */
+static bool active_ep0_xfer;
+
+/* RAM table needed to track ongoing transfers performed by dcd_edpt_xfer(), dcd_in_xfer(), and the ISR */
+static struct xfer_ctl_t
+{
+  uint8_t *data_ptr;         /* data_ptr tracks where to next copy data to (for OUT) or from (for IN) */
+  union {
+    uint16_t in_remaining_bytes; /* for IN endpoints, we track how many bytes are left to transfer */
+    uint16_t out_bytes_so_far;   /* but for OUT endpoints, we track how many bytes we've transferred so far */
+  };
+  uint16_t max_packet_size;  /* needed since device driver only finds out this at runtime */
+  uint16_t total_bytes;      /* quantity needed to pass as argument to dcd_event_xfer_complete() (for IN endpoints) */
+} xfer_table[PERIPH_MAX_EP];
+
+/*
+  local helper functions
+*/
+
+static void usb_attach(void)
+{
+  USBD->DRVSE0 &= ~USBD_DRVSE0_DRVSE0_Msk;
+}
+
+static void usb_detach(void)
+{
+  USBD->DRVSE0 |= USBD_DRVSE0_DRVSE0_Msk;
+}
+
+static void usb_control_send_zlp(void)
+{
+  USBD->EP[PERIPH_EP0].CFG |= USBD_CFG_DSQ_SYNC_Msk;
+  USBD->EP[PERIPH_EP0].MXPLD = 0;
+}
+
+/* reconstruct ep_addr from particular USB Configuration Register */
+static uint8_t decode_ep_addr(USBD_EP_T *ep)
+{
+  uint8_t ep_addr = ep->CFG & USBD_CFG_EP_NUM_Msk;
+  if ( USBD_CFG_EPMODE_IN == (ep->CFG & USBD_CFG_STATE_Msk) )
+    ep_addr |= TUSB_DIR_IN_MASK;
+  return ep_addr;
+}
+
+/* map 8-bit ep_addr into peripheral endpoint index (PERIPH_EP0...) */
+static USBD_EP_T *ep_entry(uint8_t ep_addr, bool add)
+{
+  USBD_EP_T *ep;
+  enum ep_enum ep_index;
+
+  for (ep_index = PERIPH_EP0, ep = USBD->EP; ep_index < PERIPH_MAX_EP; ep_index++, ep++)
+  {
+    if (add)
+    {
+      /* take first peripheral endpoint that is unused */
+      if (0 == (ep->CFG & USBD_CFG_STATE_Msk)) return ep;
+    }
+    else
+    {
+      /* find a peripheral endpoint that matches ep_addr */
+      uint8_t candidate_ep_addr = decode_ep_addr(ep);
+      if (candidate_ep_addr == ep_addr) return ep;
+    }
+  }
+
+  return NULL;
+}
+
+/* perform an IN endpoint transfer; this is called by dcd_edpt_xfer() and the ISR  */
+static void dcd_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
+{
+  uint16_t bytes_now = tu_min16(xfer->in_remaining_bytes, xfer->max_packet_size);
+
+  memcpy((uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), xfer->data_ptr, bytes_now);
+  ep->MXPLD = bytes_now;
+}
+
+/* called by dcd_init() as well as by the ISR during a USB bus reset */
+static void bus_reset(void)
+{
+  USBD->STBUFSEG = PERIPH_SETUP_BUF_BASE;
+
+  for (enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
+  {
+    USBD->EP[ep_index].CFG = 0;
+    USBD->EP[ep_index].CFGP = 0;
+  }
+
+  /* allocate the default EP0 endpoints */
+
+  USBD->EP[PERIPH_EP0].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_IN;
+  USBD->EP[PERIPH_EP0].BUFSEG = PERIPH_EP0_BUF_BASE;
+  xfer_table[PERIPH_EP0].max_packet_size = PERIPH_EP0_BUF_LEN;
+
+  USBD->EP[PERIPH_EP1].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_OUT;
+  USBD->EP[PERIPH_EP1].BUFSEG = PERIPH_EP1_BUF_BASE;
+  xfer_table[PERIPH_EP1].max_packet_size = PERIPH_EP1_BUF_LEN;
+
+  /* USB RAM beyond what we've allocated above is available to the user */
+  bufseg_addr = PERIPH_EP2_BUF_BASE;
+
+  /* Reset USB device address */
+  USBD->FADDR = 0;
+
+  /* reset EP0_IN flag */
+  active_ep0_xfer = false;
+}
+
+/* centralized location for USBD interrupt enable bit mask */
+static const uint32_t enabled_irqs = USBD_INTSTS_FLDET_STS_Msk | USBD_INTSTS_BUS_STS_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USB_STS_Msk;
+
+/*
+  NUC100/NUC120 TinyUSB API driver implementation
+*/
+
+void dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+  USBD->ATTR = 0x7D0;
+
+  usb_detach();
+
+  bus_reset();
+
+  usb_attach();
+
+  USBD->INTSTS = enabled_irqs;
+  USBD->INTEN  = enabled_irqs;
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USBD_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USBD_IRQn);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+  usb_control_send_zlp(); /* SET_ADDRESS is the one exception where TinyUSB doesn't use dcd_edpt_xfer() to generate a ZLP */
+  assigned_address = dev_addr;
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+  USBD->ATTR = USBD_ATTR_RWAKEUP_Msk;
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  (void) rhport;
+
+  USBD_EP_T *ep = ep_entry(p_endpoint_desc->bEndpointAddress, true);
+  TU_ASSERT(ep);
+
+  /* mine the data for the information we need */
+  int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  int const size = p_endpoint_desc->wMaxPacketSize.size;
+  tusb_xfer_type_t const type = p_endpoint_desc->bmAttributes.xfer;
+  struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
+
+  /* allocate buffer from USB RAM */
+  ep->BUFSEG = bufseg_addr;
+  bufseg_addr += size;
+  TU_ASSERT(bufseg_addr <= USBD_BUF_SIZE);
+
+  /* construct USB Configuration Register value and then write it */
+  uint32_t cfg = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  cfg |= (TUSB_DIR_IN == dir) ? USBD_CFG_EPMODE_IN : USBD_CFG_EPMODE_OUT;
+  if (TUSB_XFER_ISOCHRONOUS == type)
+    cfg |= USBD_CFG_TYPE_ISO;
+  ep->CFG = cfg;
+
+  /* make a note of the endpoint size */
+  xfer->max_packet_size = size;
+
+  return true;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+  (void) rhport;
+
+  /* mine the data for the information we need */
+  tusb_dir_t dir = tu_edpt_dir(ep_addr);
+  USBD_EP_T *ep = ep_entry(ep_addr, false);
+  struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
+
+  /* store away the information we'll needing now and later */
+  xfer->data_ptr = buffer;
+  xfer->in_remaining_bytes = total_bytes;
+  xfer->total_bytes = total_bytes;
+
+  /* for the first of one or more EP0_IN packets in a message, the first must be DATA1 */
+  if ( (0x80 == ep_addr) && !active_ep0_xfer ) ep->CFG |= USBD_CFG_DSQ_SYNC_Msk;
+
+  if (TUSB_DIR_IN == dir)
+  {
+    dcd_in_xfer(xfer, ep);
+  }
+  else
+  {
+    xfer->out_bytes_so_far = 0;
+    ep->MXPLD = xfer->max_packet_size;
+  }
+
+  return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  USBD_EP_T *ep = ep_entry(ep_addr, false);
+  ep->CFGP |= USBD_CFGP_SSTALL_Msk;
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  USBD_EP_T *ep = ep_entry(ep_addr, false);
+  ep->CFG |= USBD_CFG_CSTALL_Msk;
+}
+
+void USBD_IRQHandler(void)
+{
+  uint32_t status = USBD->INTSTS;
+  uint32_t state = USBD->ATTR & 0xf;
+
+  if(status & USBD_INTSTS_FLDET_STS_Msk)
+  {
+    if(USBD->FLDET & USBD_FLDET_FLDET_Msk)
+    {
+      /* USB connect */
+      USBD->ATTR |= USBD_ATTR_USB_EN_Msk | USBD_ATTR_PHY_EN_Msk;
+    }
+    else
+    {
+      /* USB disconnect */
+      USBD->ATTR &= ~USBD_ATTR_USB_EN_Msk;
+    }
+  }
+
+  if(status & USBD_INTSTS_BUS_STS_Msk)
+  {
+    if(state & USBD_STATE_USBRST)
+    {
+      /* USB bus reset */
+      USBD->ATTR |= USBD_ATTR_USB_EN_Msk | USBD_ATTR_PHY_EN_Msk;
+
+      bus_reset();
+
+      dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+    }
+
+    if(state & USBD_STATE_SUSPEND)
+    {
+      /* Enable USB but disable PHY */
+      USBD->ATTR &= ~USBD_ATTR_PHY_EN_Msk;
+      dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+    }
+
+    if(state & USBD_STATE_RESUME)
+    {
+      /* Enable USB and enable PHY */
+      USBD->ATTR |= USBD_ATTR_USB_EN_Msk | USBD_ATTR_PHY_EN_Msk;
+      dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+    }
+  }
+
+  if(status & USBD_INTSTS_SETUP_Msk)
+  {
+    /* clear the data ready flag of control endpoints */
+    USBD->EP[PERIPH_EP0].CFGP |= USBD_CFGP_CLRRDY_Msk;
+    USBD->EP[PERIPH_EP1].CFGP |= USBD_CFGP_CLRRDY_Msk;
+
+    /* get SETUP packet from USB buffer */
+    dcd_event_setup_received(0, (uint8_t *)USBD_BUF_BASE, true);
+  }
+
+  if(status & USBD_INTSTS_USB_STS_Msk)
+  {
+    if (status & (1UL << USBD_INTSTS_EPEVT_Pos)) /* PERIPH_EP0 (EP0_IN) event: this is treated separately from the rest */
+    {
+      /* given ACK from host has happened, we can now set the address (if not already done) */
+      if((USBD->FADDR != assigned_address) && (USBD->FADDR == 0)) USBD->FADDR = assigned_address;
+
+      uint16_t const available_bytes = USBD->EP[PERIPH_EP0].MXPLD;
+
+      active_ep0_xfer = (available_bytes == xfer_table[PERIPH_EP0].max_packet_size);
+
+      dcd_event_xfer_complete(0, 0x80, available_bytes, XFER_RESULT_SUCCESS, true);
+    }
+
+    /* service PERIPH_EP1 through PERIPH_EP7 */
+    enum ep_enum ep_index;
+    uint32_t mask;
+    struct xfer_ctl_t *xfer;
+    USBD_EP_T *ep;
+    for (ep_index = PERIPH_EP1, mask = (2UL << USBD_INTSTS_EPEVT_Pos), xfer = &xfer_table[PERIPH_EP1], ep = &USBD->EP[PERIPH_EP1]; ep_index < PERIPH_MAX_EP; ep_index++, mask <<= 1, xfer++, ep++)
+    {
+      if(status & mask)
+      {
+        USBD->INTSTS = mask;
+
+        uint16_t const available_bytes = ep->MXPLD;
+        uint8_t const ep_addr = decode_ep_addr(ep);
+        bool const out_ep = !(ep_addr & TUSB_DIR_IN_MASK);
+
+        if (out_ep)
+        {
+          /* copy the data from the PC to the previously provided buffer */
+          memcpy(xfer->data_ptr, (uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), available_bytes);
+          xfer->out_bytes_so_far += available_bytes;
+          xfer->data_ptr += available_bytes;
+
+          /* when the transfer is finished, alert TinyUSB; otherwise, accept more data */
+          if ( (xfer->total_bytes == xfer->out_bytes_so_far) || (available_bytes < xfer->max_packet_size) )
+            dcd_event_xfer_complete(0, ep_addr, xfer->out_bytes_so_far, XFER_RESULT_SUCCESS, true);
+          else
+            ep->MXPLD = xfer->max_packet_size;
+        }
+        else
+        {
+          /* update the bookkeeping to reflect the data that has now been sent to the PC */
+          xfer->in_remaining_bytes -= available_bytes;
+          xfer->data_ptr += available_bytes;
+
+          /* if more data to send, send it; otherwise, alert TinyUSB that we've finished */
+          if (xfer->in_remaining_bytes)
+            dcd_in_xfer(xfer, ep);
+          else
+            dcd_event_xfer_complete(0, ep_addr, xfer->total_bytes, XFER_RESULT_SUCCESS, true);
+        }
+      }
+    }
+  }
+
+  /* acknowledge all interrupts */
+  USBD->INTSTS = status & enabled_irqs;
+}
+
+void dcd_isr(uint8_t rhport)
+{
+  (void) rhport;
+  USBD_IRQHandler();
+}
+
+#endif
diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
new file mode 100644
index 000000000..25d723d96
--- /dev/null
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -0,0 +1,449 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Peter Lawrence
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/*
+  Theory of operation:
+
+  The NUC121/NUC125/NUC126 USBD peripheral has eight "EP"s, but each is simplex, 
+  so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to 
+  implement USB EP0.  PERIPH_EP0 and PERIPH_EP1 are used by this driver for 
+  EP0_IN and EP0_OUT respectively.  This leaves up to six for user usage.
+*/
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && ( (CFG_TUSB_MCU == OPT_MCU_NUC121) || (CFG_TUSB_MCU == OPT_MCU_NUC126) )
+
+#include "device/dcd.h"
+#include "NuMicro.h"
+
+/* allocation of USBD RAM for Setup, EP0_IN, and and EP_OUT */
+#define PERIPH_SETUP_BUF_BASE  0
+#define PERIPH_SETUP_BUF_LEN   8
+#define PERIPH_EP0_BUF_BASE    (PERIPH_SETUP_BUF_BASE + PERIPH_SETUP_BUF_LEN)
+#define PERIPH_EP0_BUF_LEN     CFG_TUD_ENDPOINT0_SIZE
+#define PERIPH_EP1_BUF_BASE    (PERIPH_EP0_BUF_BASE + PERIPH_EP0_BUF_LEN)
+#define PERIPH_EP1_BUF_LEN     CFG_TUD_ENDPOINT0_SIZE
+#define PERIPH_EP2_BUF_BASE    (PERIPH_EP1_BUF_BASE + PERIPH_EP1_BUF_LEN)
+
+/* rather important info unfortunately not provided by device include files: how much there is */
+#define USBD_BUF_SIZE          ((CFG_TUSB_MCU == OPT_MCU_NUC121) ? 768 : 512)
+
+enum ep_enum
+{
+  PERIPH_EP0 = 0,
+  PERIPH_EP1 = 1,
+  PERIPH_EP2 = 2,
+  PERIPH_EP3 = 3,
+  PERIPH_EP4 = 4,
+  PERIPH_EP5 = 5,
+  PERIPH_EP6 = 6,
+  PERIPH_EP7 = 7,
+  PERIPH_MAX_EP,
+};
+
+/* set by dcd_set_address() */
+static volatile uint8_t assigned_address;
+
+/* reset by dcd_init(), this is used by dcd_edpt_open() to assign USBD peripheral buffer addresses */
+static uint32_t bufseg_addr;
+
+/* used by dcd_edpt_xfer() and the ISR to reset the data sync (DATA0/DATA1) in an EP0_IN transfer */
+static bool active_ep0_xfer;
+
+/* RAM table needed to track ongoing transfers performed by dcd_edpt_xfer(), dcd_in_xfer(), and the ISR */
+static struct xfer_ctl_t
+{
+  uint8_t *data_ptr;         /* data_ptr tracks where to next copy data to (for OUT) or from (for IN) */
+  union {
+    uint16_t in_remaining_bytes; /* for IN endpoints, we track how many bytes are left to transfer */
+    uint16_t out_bytes_so_far;   /* but for OUT endpoints, we track how many bytes we've transferred so far */
+  };
+  uint16_t max_packet_size;  /* needed since device driver only finds out this at runtime */
+  uint16_t total_bytes;      /* quantity needed to pass as argument to dcd_event_xfer_complete() (for IN endpoints) */
+} xfer_table[PERIPH_MAX_EP];
+
+/*
+  local helper functions
+*/
+
+static void usb_attach(void)
+{
+  USBD->SE0 &= ~USBD_SE0_SE0_Msk;
+}
+
+static void usb_detach(void)
+{
+  USBD->SE0 |= USBD_SE0_SE0_Msk;
+}
+
+static void usb_control_send_zlp(void)
+{
+  USBD->EP[PERIPH_EP0].CFG |= USBD_CFG_DSQSYNC_Msk;
+  USBD->EP[PERIPH_EP0].MXPLD = 0;
+}
+
+/* reconstruct ep_addr from particular USB Configuration Register */
+static uint8_t decode_ep_addr(USBD_EP_T *ep)
+{
+  uint8_t ep_addr = ep->CFG & USBD_CFG_EPNUM_Msk;
+  if ( USBD_CFG_EPMODE_IN == (ep->CFG & USBD_CFG_STATE_Msk) )
+    ep_addr |= TUSB_DIR_IN_MASK;
+  return ep_addr;
+}
+
+/* map 8-bit ep_addr into peripheral endpoint index (PERIPH_EP0...) */
+static USBD_EP_T *ep_entry(uint8_t ep_addr, bool add)
+{
+  USBD_EP_T *ep;
+  enum ep_enum ep_index;
+
+  for (ep_index = PERIPH_EP0, ep = USBD->EP; ep_index < PERIPH_MAX_EP; ep_index++, ep++)
+  {
+    if (add)
+    {
+      /* take first peripheral endpoint that is unused */
+      if (0 == (ep->CFG & USBD_CFG_STATE_Msk)) return ep;
+    }
+    else
+    {
+      /* find a peripheral endpoint that matches ep_addr */
+      uint8_t candidate_ep_addr = decode_ep_addr(ep);
+      if (candidate_ep_addr == ep_addr) return ep;
+    }
+  }
+
+  return NULL;
+}
+
+/* perform an IN endpoint transfer; this is called by dcd_edpt_xfer() and the ISR  */
+static void dcd_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
+{
+  uint16_t bytes_now = tu_min16(xfer->in_remaining_bytes, xfer->max_packet_size);
+
+  memcpy((uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), xfer->data_ptr, bytes_now);
+  ep->MXPLD = bytes_now;
+}
+
+/* called by dcd_init() as well as by the ISR during a USB bus reset */
+static void bus_reset(void)
+{
+  USBD->STBUFSEG = PERIPH_SETUP_BUF_BASE;
+
+  for (enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
+  {
+    USBD->EP[ep_index].CFG = 0;
+    USBD->EP[ep_index].CFGP = 0;
+  }
+
+  /* allocate the default EP0 endpoints */
+
+  USBD->EP[PERIPH_EP0].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_IN;
+  USBD->EP[PERIPH_EP0].BUFSEG = PERIPH_EP0_BUF_BASE;
+  xfer_table[PERIPH_EP0].max_packet_size = PERIPH_EP0_BUF_LEN;
+
+  USBD->EP[PERIPH_EP1].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_OUT;
+  USBD->EP[PERIPH_EP1].BUFSEG = PERIPH_EP1_BUF_BASE;
+  xfer_table[PERIPH_EP1].max_packet_size = PERIPH_EP1_BUF_LEN;
+
+  /* USB RAM beyond what we've allocated above is available to the user */
+  bufseg_addr = PERIPH_EP2_BUF_BASE;
+
+  /* Reset USB device address */
+  USBD->FADDR = 0;
+
+  /* reset EP0_IN flag */
+  active_ep0_xfer = false;
+}
+
+/* centralized location for USBD interrupt enable bit mask */
+static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk | USBD_INTSTS_SOFIF_Msk;
+
+/*
+  NUC121/NUC125/NUC126 TinyUSB API driver implementation
+*/
+
+void dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+#ifdef SUPPORT_LPM
+  USBD->ATTR = 0x7D0 | USBD_LPMACK;
+#else
+  USBD->ATTR = 0x7D0;
+#endif
+
+  usb_detach();
+
+  bus_reset();
+
+  usb_attach();
+
+  USBD->INTSTS = enabled_irqs;
+  USBD->INTEN  = enabled_irqs;
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USBD_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USBD_IRQn);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+  usb_control_send_zlp(); /* SET_ADDRESS is the one exception where TinyUSB doesn't use dcd_edpt_xfer() to generate a ZLP */
+  assigned_address = dev_addr;
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+  USBD->ATTR = USBD_ATTR_RWAKEUP_Msk;
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  (void) rhport;
+
+  USBD_EP_T *ep = ep_entry(p_endpoint_desc->bEndpointAddress, true);
+  TU_ASSERT(ep);
+
+  /* mine the data for the information we need */
+  int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  int const size = p_endpoint_desc->wMaxPacketSize.size;
+  tusb_xfer_type_t const type = p_endpoint_desc->bmAttributes.xfer;
+  struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
+
+  /* allocate buffer from USB RAM */
+  ep->BUFSEG = bufseg_addr;
+  bufseg_addr += size;
+  TU_ASSERT(bufseg_addr <= USBD_BUF_SIZE);
+
+  /* construct USB Configuration Register value and then write it */
+  uint32_t cfg = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  cfg |= (TUSB_DIR_IN == dir) ? USBD_CFG_EPMODE_IN : USBD_CFG_EPMODE_OUT;
+  if (TUSB_XFER_ISOCHRONOUS == type)
+    cfg |= USBD_CFG_TYPE_ISO;
+  ep->CFG = cfg;
+
+  /* make a note of the endpoint size */
+  xfer->max_packet_size = size;
+
+  return true;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+  (void) rhport;
+
+  /* mine the data for the information we need */
+  tusb_dir_t dir = tu_edpt_dir(ep_addr);
+  USBD_EP_T *ep = ep_entry(ep_addr, false);
+  struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
+
+  /* store away the information we'll needing now and later */
+  xfer->data_ptr = buffer;
+  xfer->in_remaining_bytes = total_bytes;
+  xfer->total_bytes = total_bytes;
+
+  /* for the first of one or more EP0_IN packets in a message, the first must be DATA1 */
+  if ( (0x80 == ep_addr) && !active_ep0_xfer ) ep->CFG |= USBD_CFG_DSQSYNC_Msk;
+
+  if (TUSB_DIR_IN == dir)
+  {
+    dcd_in_xfer(xfer, ep);
+  }
+  else
+  {
+    xfer->out_bytes_so_far = 0;
+    ep->MXPLD = xfer->max_packet_size;
+  }
+
+  return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  USBD_EP_T *ep = ep_entry(ep_addr, false);
+  ep->CFGP |= USBD_CFGP_SSTALL_Msk;
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  USBD_EP_T *ep = ep_entry(ep_addr, false);
+  ep->CFG |= USBD_CFG_CSTALL_Msk;
+}
+
+void USBD_IRQHandler(void)
+{
+  uint32_t status = USBD->INTSTS;
+#ifdef SUPPORT_LPM
+  uint32_t state = USBD->ATTR & 0x300f;
+#else
+  uint32_t state = USBD->ATTR & 0xf;
+#endif
+
+  if(status & USBD_INTSTS_VBDETIF_Msk)
+  {
+    if(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)
+    {
+      /* USB connect */
+      USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
+    }
+    else
+    {
+      /* USB disconnect */
+      USBD->ATTR &= ~USBD_ATTR_USBEN_Msk;
+    }
+  }
+
+  if(status & USBD_INTSTS_BUSIF_Msk)
+  {
+    if(state & USBD_ATTR_USBRST_Msk)
+    {
+      /* USB bus reset */
+      USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
+
+      bus_reset();
+
+      dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+    }
+
+    if(state & USBD_ATTR_SUSPEND_Msk)
+    {
+      /* Enable USB but disable PHY */
+      USBD->ATTR &= ~USBD_ATTR_PHYEN_Msk;
+      dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+    }
+
+    if(state & USBD_ATTR_RESUME_Msk)
+    {
+      /* Enable USB and enable PHY */
+      USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
+      dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+    }
+  }
+
+  if(status & USBD_INTSTS_SETUP_Msk)
+  {
+    /* clear the data ready flag of control endpoints */
+    USBD->EP[PERIPH_EP0].CFGP |= USBD_CFGP_CLRRDY_Msk;
+    USBD->EP[PERIPH_EP1].CFGP |= USBD_CFGP_CLRRDY_Msk;
+
+    /* get SETUP packet from USB buffer */
+    dcd_event_setup_received(0, (uint8_t *)USBD_BUF_BASE, true);
+  }
+
+  if(status & USBD_INTSTS_USBIF_Msk)
+  {
+    if (status & USBD_INTSTS_EPEVT0_Msk) /* PERIPH_EP0 (EP0_IN) event: this is treated separately from the rest */
+    {
+      /* given ACK from host has happened, we can now set the address (if not already done) */
+      if((USBD->FADDR != assigned_address) && (USBD->FADDR == 0)) USBD->FADDR = assigned_address;
+
+      uint16_t const available_bytes = USBD->EP[PERIPH_EP0].MXPLD;
+
+      active_ep0_xfer = (available_bytes == xfer_table[PERIPH_EP0].max_packet_size);
+
+      dcd_event_xfer_complete(0, 0x80, available_bytes, XFER_RESULT_SUCCESS, true);
+    }
+
+    /* service PERIPH_EP1 through PERIPH_EP7 */
+    enum ep_enum ep_index;
+    uint32_t mask;
+    struct xfer_ctl_t *xfer;
+    USBD_EP_T *ep;
+    for (ep_index = PERIPH_EP1, mask = USBD_INTSTS_EPEVT1_Msk, xfer = &xfer_table[PERIPH_EP1], ep = &USBD->EP[PERIPH_EP1]; ep_index <= PERIPH_EP7; ep_index++, mask <<= 1, xfer++, ep++)
+    {
+      if(status & mask)
+      {
+        USBD->INTSTS = mask;
+
+        uint16_t const available_bytes = ep->MXPLD;
+        uint8_t const ep_addr = decode_ep_addr(ep);
+        bool const out_ep = !(ep_addr & TUSB_DIR_IN_MASK);
+
+        if (out_ep)
+        {
+          /* copy the data from the PC to the previously provided buffer */
+          memcpy(xfer->data_ptr, (uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), available_bytes);
+          xfer->out_bytes_so_far += available_bytes;
+          xfer->data_ptr += available_bytes;
+
+          /* when the transfer is finished, alert TinyUSB; otherwise, accept more data */
+          if ( (xfer->total_bytes == xfer->out_bytes_so_far) || (available_bytes < xfer->max_packet_size) )
+            dcd_event_xfer_complete(0, ep_addr, xfer->out_bytes_so_far, XFER_RESULT_SUCCESS, true);
+          else
+            ep->MXPLD = xfer->max_packet_size;
+        }
+        else
+        {
+          /* update the bookkeeping to reflect the data that has now been sent to the PC */
+          xfer->in_remaining_bytes -= available_bytes;
+          xfer->data_ptr += available_bytes;
+
+          /* if more data to send, send it; otherwise, alert TinyUSB that we've finished */
+          if (xfer->in_remaining_bytes)
+            dcd_in_xfer(xfer, ep);
+          else
+            dcd_event_xfer_complete(0, ep_addr, xfer->total_bytes, XFER_RESULT_SUCCESS, true);
+        }
+      }
+    }
+  }
+
+  if(status & USBD_INTSTS_SOFIF_Msk)
+  {
+    /* Start-Of-Frame event */
+    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+  }
+
+  /* acknowledge all interrupts */
+  USBD->INTSTS = status & enabled_irqs;
+}
+
+void dcd_isr(uint8_t rhport)
+{
+  (void) rhport;
+  USBD_IRQHandler();
+}
+
+#endif
diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c
new file mode 100644
index 000000000..e05e73eff
--- /dev/null
+++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c
@@ -0,0 +1,649 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Peter Lawrence
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/*
+  Theory of operation:
+
+  The NUC505 USBD peripheral has twelve "EP"s, where each is simplex, in addition 
+  to dedicated support for the control endpoint (EP0).  The non-user endpoints
+  are referred to as "user" EPs in this code, and follow the datasheet 
+  nomenclature of EPA through EPL.
+*/
+
+/*
+  Note on OPT_MCU_NUC505_USB_DMA: the author suggests against using this option.
+  The DMA functionality of the USBD peripheral does not appear to succeed with
+  transfer lengths that are longer (> 64 bytes) and are not a multiple of 4.
+*/
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_NUC505)
+
+#include "device/dcd.h"
+#include "NUC505Series.h"
+
+/* rather important info unfortunately not provided by device include files */
+#define USBD_BUF_SIZE          2048 /* how much USB buffer space there is */
+#define USBD_MAX_DMA_LEN     0x1000 /* max bytes that can be DMAed at one time */
+
+enum ep_enum
+{
+  PERIPH_EPA = 0,
+  PERIPH_EPB = 1,
+  PERIPH_EPC = 2,
+  PERIPH_EPD = 3,
+  PERIPH_EPE = 4,
+  PERIPH_EPF = 5,
+  PERIPH_EPG = 6,
+  PERIPH_EPH = 7,
+  PERIPH_EPI = 8,
+  PERIPH_EPJ = 9,
+  PERIPH_EPK = 10,
+  PERIPH_EPL = 11,
+  PERIPH_MAX_EP,
+};
+
+static const uint8_t epcfg_eptype_table[] =
+{
+  [TUSB_XFER_CONTROL]     = 0, /* won't happen, since control EPs have dedicated registers */
+  [TUSB_XFER_ISOCHRONOUS] = 3 << USBD_EPCFG_EPTYPE_Pos,
+  [TUSB_XFER_BULK]        = 1 << USBD_EPCFG_EPTYPE_Pos,
+  [TUSB_XFER_INTERRUPT]   = 2 << USBD_EPCFG_EPTYPE_Pos,
+};
+
+static const uint8_t eprspctl_eptype_table[] =
+{
+  [TUSB_XFER_CONTROL]     = 0, /* won't happen, since control EPs have dedicated registers */
+  [TUSB_XFER_ISOCHRONOUS] = 2 << USBD_EPRSPCTL_MODE_Pos, /* Fly Mode */
+  [TUSB_XFER_BULK]        = 0 << USBD_EPRSPCTL_MODE_Pos, /* Auto-Validate Mode */
+  [TUSB_XFER_INTERRUPT]   = 1 << USBD_EPRSPCTL_MODE_Pos, /* Manual-Validate Mode */
+};
+
+/* set by dcd_set_address() */
+static volatile uint8_t assigned_address;
+
+/* reset by bus_reset(), this is used by dcd_edpt_open() to assign USBD peripheral buffer addresses */
+static uint32_t bufseg_addr;
+
+/* RAM table needed to track ongoing transfers performed by dcd_edpt_xfer(), dcd_userEP_in_xfer(), and the ISR */
+static struct xfer_ctl_t
+{
+  uint8_t *data_ptr;         /* data_ptr tracks where to next copy data to (for OUT) or from (for IN) */
+  union {
+    uint16_t in_remaining_bytes; /* for IN endpoints, we track how many bytes are left to transfer */
+    uint16_t out_bytes_so_far;   /* but for OUT endpoints, we track how many bytes we've transferred so far */
+  };
+  uint16_t max_packet_size;  /* needed since device driver only finds out this at runtime */
+  uint16_t total_bytes;      /* quantity needed to pass as argument to dcd_event_xfer_complete() (for IN endpoints) */
+  uint8_t ep_addr;
+  bool dma_requested;
+} xfer_table[PERIPH_MAX_EP];
+
+/* in addition to xfer_table, additional bespoke bookkeeping is maintained for control EP0 IN */
+static struct
+{
+  uint8_t *data_ptr;
+  uint16_t in_remaining_bytes;
+  uint16_t total_bytes;
+} ctrl_in_xfer;
+
+static volatile bool configuration_changed;
+
+static volatile struct xfer_ctl_t *current_dma_xfer;
+
+
+/*
+  local helper functions
+*/
+
+static void usb_attach(void)
+{
+  USBD->PHYCTL |= USBD_PHYCTL_DPPUEN_Msk;
+}
+
+static void usb_control_send_zlp(void)
+{
+  USBD->CEPINTSTS = USBD_CEPINTSTS_STSDONEIF_Msk;
+  USBD->CEPCTL = 0; /* clear NAKCLR bit */
+  USBD->CEPINTEN = USBD_CEPINTEN_STSDONEIEN_Msk;
+}
+
+/* map 8-bit ep_addr into peripheral endpoint index (PERIPH_EPA...) */
+static USBD_EP_T *ep_entry(uint8_t ep_addr, bool add)
+{
+  USBD_EP_T *ep;
+  enum ep_enum ep_index;
+  struct xfer_ctl_t *xfer;
+
+  for (ep_index = PERIPH_EPA, xfer = &xfer_table[PERIPH_EPA], ep = USBD->EP; ep_index < PERIPH_MAX_EP; ep_index++, xfer++, ep++)
+  {
+    if (add)
+    {
+      /* take first peripheral endpoint that is unused */
+      if (0 == (ep->EPCFG & USBD_EPCFG_EPEN_Msk)) return ep;
+    }
+    else
+    {
+      /* find a peripheral endpoint that matches ep_addr */
+      if (xfer->ep_addr == ep_addr) return ep;
+    }
+  }
+
+  return NULL;
+}
+
+/* perform a non-control IN endpoint transfer; this is called by the ISR  */
+static void dcd_userEP_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
+{
+  uint16_t bytes_now = tu_min16(xfer->in_remaining_bytes, xfer->max_packet_size);
+  uint16_t countdown = bytes_now;
+
+  /* precompute what amount of data will be left */
+  xfer->in_remaining_bytes -= bytes_now;
+
+  /*
+  if there will be no more data to send, we replace the BUFEMPTYIF EP interrupt with TXPKIF;
+  that way, we alert TinyUSB as soon as this last packet has been sent
+  */
+  if (0 == xfer->in_remaining_bytes)
+  {
+    ep->EPINTSTS = USBD_EPINTSTS_TXPKIF_Msk;
+    ep->EPINTEN = USBD_EPINTEN_TXPKIEN_Msk;
+  }
+
+  /* provided buffers are thankfully 32-bit aligned, allowing most data to be transfered as 32-bit */
+  while (countdown > 3)
+  {
+    ep->EPDAT = *(uint32_t *)xfer->data_ptr;
+    xfer->data_ptr += 4; countdown -= 4;
+  }
+  while (countdown--)
+    ep->EPDAT_BYTE = *xfer->data_ptr++;
+
+  /* for short packets, we must nudge the peripheral to say 'that's all folks' */
+  if (bytes_now != xfer->max_packet_size)
+    ep->EPRSPCTL = USBD_EPRSPCTL_SHORTTXEN_Msk;
+}
+
+/* called by dcd_init() as well as by the ISR during a USB bus reset */
+static void bus_reset(void)
+{
+  for (enum ep_enum ep_index = PERIPH_EPA; ep_index < PERIPH_MAX_EP; ep_index++)
+  {
+    USBD->EP[ep_index].EPCFG = 0;
+    xfer_table[ep_index].dma_requested = false;
+  }
+
+  USBD->DMACNT = 0;
+  USBD->DMACTL = USBD_DMACTL_DMARST_Msk;
+  USBD->DMACTL = 0;
+
+  /* allocate the default EP0 endpoints */
+
+  USBD->CEPBUFSTART = 0;
+  USBD->CEPBUFEND = 0 + CFG_TUD_ENDPOINT0_SIZE - 1;
+
+  /* USB RAM beyond what we've allocated above is available to the user */
+  bufseg_addr = CFG_TUD_ENDPOINT0_SIZE;
+
+  /* Reset USB device address */
+  USBD->FADDR = 0;
+
+  configuration_changed = false;
+  current_dma_xfer = NULL;
+}
+
+#ifdef OPT_MCU_NUC505_USB_DMA
+/* this must only be called by the ISR; it does its best to share the single DMA engine across all user EPs (IN and OUT) */
+static void service_dma(void)
+{
+  if (current_dma_xfer)
+    return;
+
+  enum ep_enum ep_index;
+  struct xfer_ctl_t *xfer;
+  USBD_EP_T *ep;
+
+  for (ep_index = PERIPH_EPA, xfer = &xfer_table[PERIPH_EPA], ep = &USBD->EP[PERIPH_EPA]; ep_index < PERIPH_MAX_EP; ep_index++, xfer++, ep++)
+  {
+    uint16_t const available_bytes = ep->EPDATCNT & USBD_EPDATCNT_DATCNT_Msk;
+
+    if (!xfer->dma_requested || !available_bytes)
+      continue;
+
+    /*
+    instruct DMA to copy the data from the PC to the previously provided buffer
+    when the bus interrupt DMADONEIEN subsequently fires, the transfer will have finished
+    */
+    USBD->DMACTL = xfer->ep_addr & USBD_DMACTL_EPNUM_Msk;
+    USBD->DMAADDR = (uint32_t)xfer->data_ptr;
+    USBD->DMACNT = available_bytes;
+    USBD->BUSINTSTS = USBD_BUSINTSTS_DMADONEIF_Msk;
+    xfer->out_bytes_so_far += available_bytes;
+    current_dma_xfer = xfer;
+    USBD->DMACTL |= USBD_DMACTL_DMAEN_Msk;
+
+    return;
+  }
+}
+#endif
+
+/* centralized location for USBD interrupt enable bit masks */
+static const uint32_t enabled_irqs = USBD_GINTEN_USBIEN_Msk | \
+  USBD_GINTEN_EPAIEN_Msk | USBD_GINTEN_EPBIEN_Msk | USBD_GINTEN_EPCIEN_Msk | USBD_GINTEN_EPDIEN_Msk | USBD_GINTEN_EPEIEN_Msk | USBD_GINTEN_EPFIEN_Msk | \
+  USBD_GINTEN_EPGIEN_Msk | USBD_GINTEN_EPHIEN_Msk | USBD_GINTEN_EPIIEN_Msk | USBD_GINTEN_EPJIEN_Msk | USBD_GINTEN_EPKIEN_Msk | USBD_GINTEN_EPLIEN_Msk | \
+  USBD_GINTEN_CEPIEN_Msk;
+
+/*
+  NUC505 TinyUSB API driver implementation
+*/
+
+void dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+  /* configure interrupts in their initial state; BUSINTEN and CEPINTEN will be subsequently and dynamically re-written as needed */
+  USBD->GINTEN = enabled_irqs;
+  USBD->BUSINTEN = USBD_BUSINTEN_RSTIEN_Msk | USBD_BUSINTEN_VBUSDETIEN_Msk | USBD_BUSINTEN_RESUMEIEN_Msk | USBD_BUSINTEN_DMADONEIEN_Msk;
+  USBD->CEPINTEN = 0;
+
+  bus_reset();
+
+  usb_attach();
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USBD_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USBD_IRQn);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+  usb_control_send_zlp(); /* SET_ADDRESS is the one exception where TinyUSB doesn't use dcd_edpt_xfer() to generate a ZLP */
+  assigned_address = dev_addr;
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+  configuration_changed = true;
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+  USBD->OPER |= USBD_OPER_RESUMEEN_Msk;
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  (void) rhport;
+
+  USBD_EP_T *ep = ep_entry(p_endpoint_desc->bEndpointAddress, true);
+  TU_ASSERT(ep);
+
+  /* mine the data for the information we need */
+  int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  int const size = p_endpoint_desc->wMaxPacketSize.size;
+  tusb_xfer_type_t const type = p_endpoint_desc->bmAttributes.xfer;
+  struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
+
+  /* allocate buffer from USB RAM */
+  ep->EPBUFSTART = bufseg_addr;
+  bufseg_addr += size;
+  ep->EPBUFEND = bufseg_addr - 1;
+  TU_ASSERT(bufseg_addr <= USBD_BUF_SIZE);
+
+  ep->EPMPS = size;
+
+  ep->EPRSPCTL = USB_EP_RSPCTL_FLUSH | eprspctl_eptype_table[type];
+
+  /* construct USB Configuration Register value and then write it */
+  uint32_t cfg = (uint32_t)tu_edpt_number(p_endpoint_desc->bEndpointAddress) << USBD_EPCFG_EPNUM_Pos;
+  if (TUSB_DIR_IN == dir)
+    cfg |= USBD_EPCFG_EPDIR_Msk;
+  cfg |= epcfg_eptype_table[type] | USBD_EPCFG_EPEN_Msk;
+  ep->EPCFG = cfg;
+
+  /* make a note of the endpoint particulars */
+  xfer->max_packet_size = size;
+  xfer->ep_addr = p_endpoint_desc->bEndpointAddress;
+
+  return true;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+  (void) rhport;
+
+  if (0x80 == ep_addr) /* control EP0 IN */
+  {
+    if (total_bytes)
+    {
+      USBD->CEPCTL = USBD_CEPCTL_FLUSH_Msk;
+      ctrl_in_xfer.data_ptr = buffer;
+      ctrl_in_xfer.in_remaining_bytes = total_bytes;
+      ctrl_in_xfer.total_bytes = total_bytes;
+      USBD->CEPINTSTS = USBD_CEPINTSTS_INTKIF_Msk;
+      USBD->CEPINTEN = USBD_CEPINTEN_INTKIEN_Msk;
+    }
+    else
+    {
+      usb_control_send_zlp();
+    }
+  }
+  else if (0x00 == ep_addr) /* control EP0 OUT */
+  {
+    if (total_bytes)
+    {
+      /* if TinyUSB is asking for EP0 OUT data, it is almost certainly already in the buffer */
+      while (total_bytes < USBD->CEPRXCNT);
+      for (int count = 0; count < total_bytes; count++)
+        *buffer++ = USBD->CEPDAT_BYTE;
+      
+      dcd_event_xfer_complete(0, ep_addr, total_bytes, XFER_RESULT_SUCCESS, true);
+    }
+  }
+  else
+  {
+    /* mine the data for the information we need */
+    tusb_dir_t dir = tu_edpt_dir(ep_addr);
+    USBD_EP_T *ep = ep_entry(ep_addr, false);
+    struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
+
+    /* store away the information we'll needing now and later */
+    xfer->data_ptr = buffer;
+    xfer->in_remaining_bytes = total_bytes;
+    xfer->total_bytes = total_bytes;
+
+    if (TUSB_DIR_IN == dir)
+    {
+      ep->EPINTEN = USBD_EPINTEN_BUFEMPTYIEN_Msk;
+    }
+    else
+    {
+      xfer->out_bytes_so_far = 0;
+      ep->EPINTEN = USBD_EPINTEN_RXPKIEN_Msk;
+    }
+  }
+
+  return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  if (tu_edpt_number(ep_addr))
+  {
+    USBD_EP_T *ep = ep_entry(ep_addr, false);
+    ep->EPRSPCTL = (ep->EPRSPCTL & 0xf7) | USBD_EPRSPCTL_HALT_Msk;
+  }
+  else
+  {
+    USBD->CEPCTL = USBD_CEPCTL_STALLEN_Msk;
+  }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  if (tu_edpt_number(ep_addr))
+  {
+    USBD_EP_T *ep = ep_entry(ep_addr, false);
+    ep->EPRSPCTL = USBD_EPRSPCTL_TOGGLE_Msk;
+  }
+}
+
+void USBD_IRQHandler(void)
+{
+  uint32_t status = USBD->GINTSTS;
+
+  /* USB interrupt */
+  if (status & USBD_GINTSTS_USBIF_Msk)
+  {
+    uint32_t bus_state = USBD->BUSINTSTS;
+
+    if (bus_state & USBD_BUSINTSTS_SOFIF_Msk)
+    {
+      /* Start-Of-Frame event */
+      dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+    }
+
+    if (bus_state & USBD_BUSINTSTS_RSTIF_Msk)
+    {
+      bus_reset();
+
+      USBD->CEPINTEN = USBD_CEPINTEN_SETUPPKIEN_Msk;
+      USBD->BUSINTEN = USBD_BUSINTEN_RSTIEN_Msk | USBD_BUSINTEN_RESUMEIEN_Msk | USBD_BUSINTEN_SUSPENDIEN_Msk | USBD_BUSINTEN_DMADONEIEN_Msk;
+      USBD->CEPINTSTS = 0x1ffc;
+      dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+    }
+
+    if (bus_state & USBD_BUSINTSTS_RESUMEIF_Msk)
+    {
+      USBD->BUSINTEN = USBD_BUSINTEN_RSTIEN_Msk | USBD_BUSINTEN_SUSPENDIEN_Msk | USBD_BUSINTEN_DMADONEIEN_Msk;
+      dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+    }
+
+    if (bus_state & USBD_BUSINTSTS_SUSPENDIF_Msk)
+    {
+      USBD->BUSINTEN = USBD_BUSINTEN_RSTIEN_Msk | USBD_BUSINTEN_RESUMEIEN_Msk | USBD_BUSINTEN_DMADONEIEN_Msk;
+      dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+    }
+
+    if (bus_state & USBD_BUSINTSTS_HISPDIF_Msk)
+    {
+      USBD->CEPINTEN = USBD_CEPINTEN_SETUPPKIEN_Msk;
+    }
+
+    if (bus_state & USBD_BUSINTSTS_DMADONEIF_Msk)
+    {
+#ifdef OPT_MCU_NUC505_USB_DMA
+      if (current_dma_xfer)
+      {
+        current_dma_xfer->dma_requested = false;
+
+        uint16_t available_bytes = USBD->DMACNT & USBD_DMACNT_DMACNT_Msk;
+
+        /* if the most recent DMA finishes the transfer, alert TinyUSB; otherwise, the next RXPKIF/INTKIF endpoint interrupt will prompt the next DMA */
+        if ( (current_dma_xfer->total_bytes == current_dma_xfer->out_bytes_so_far) || (available_bytes < current_dma_xfer->max_packet_size) )
+        {
+          dcd_event_xfer_complete(0, current_dma_xfer->ep_addr, current_dma_xfer->out_bytes_so_far, XFER_RESULT_SUCCESS, true);
+        }
+
+        current_dma_xfer = NULL;
+        service_dma();
+      }
+#endif
+    }
+
+    if (bus_state & USBD_BUSINTSTS_VBUSDETIF_Msk)
+    {
+      if (USBD->PHYCTL & USBD_PHYCTL_VBUSDET_Msk)
+      {
+        /* USB connect */
+        USBD->PHYCTL |= USBD_PHYCTL_PHYEN_Msk | USBD_PHYCTL_DPPUEN_Msk;
+      }
+      else
+      {
+        /* USB disconnect */
+        USBD->PHYCTL &= ~USBD_PHYCTL_DPPUEN_Msk;
+      }
+    }
+
+    USBD->BUSINTSTS = bus_state & (USBD_BUSINTSTS_SOFIF_Msk | USBD_BUSINTSTS_RSTIF_Msk | USBD_BUSINTSTS_RESUMEIF_Msk | USBD_BUSINTSTS_SUSPENDIF_Msk | USBD_BUSINTSTS_HISPDIF_Msk | USBD_BUSINTSTS_DMADONEIF_Msk | USBD_BUSINTSTS_PHYCLKVLDIF_Msk | USBD_BUSINTSTS_VBUSDETIF_Msk);
+  }
+
+  if (status & USBD_GINTSTS_CEPIF_Msk)
+  {
+    uint32_t cep_state = USBD->CEPINTSTS & USBD->CEPINTEN;
+
+    if (cep_state & USBD_CEPINTSTS_SETUPPKIF_Msk)
+    {
+      /* get SETUP packet from USB buffer */
+      uint8_t setup_packet[8];
+      setup_packet[0] = (uint8_t)(USBD->SETUP1_0 >> 0);
+      setup_packet[1] = (uint8_t)(USBD->SETUP1_0 >> 8);
+      setup_packet[2] = (uint8_t)(USBD->SETUP3_2 >> 0);
+      setup_packet[3] = (uint8_t)(USBD->SETUP3_2 >> 8);
+      setup_packet[4] = (uint8_t)(USBD->SETUP5_4 >> 0);
+      setup_packet[5] = (uint8_t)(USBD->SETUP5_4 >> 8);
+      setup_packet[6] = (uint8_t)(USBD->SETUP7_6 >> 0);
+      setup_packet[7] = (uint8_t)(USBD->SETUP7_6 >> 8);
+      dcd_event_setup_received(0, setup_packet, true);
+    }
+    else if (cep_state & USBD_CEPINTSTS_INTKIF_Msk)
+    {
+      USBD->CEPINTSTS = USBD_CEPINTSTS_TXPKIF_Msk;
+
+      if (!(cep_state & USBD_CEPINTSTS_STSDONEIF_Msk))
+      {
+        USBD->CEPINTEN = USBD_CEPINTEN_TXPKIEN_Msk;
+        uint16_t bytes_now = tu_min16(ctrl_in_xfer.in_remaining_bytes, CFG_TUD_ENDPOINT0_SIZE);
+        for (int count = 0; count < bytes_now; count++)
+          USBD->CEPDAT_BYTE = *ctrl_in_xfer.data_ptr++;
+        ctrl_in_xfer.in_remaining_bytes -= bytes_now;
+        USBD_START_CEP_IN(bytes_now);
+      }
+      else
+      {
+        USBD->CEPINTEN = USBD_CEPINTEN_TXPKIEN_Msk | USBD_CEPINTEN_STSDONEIEN_Msk;
+      }
+    }
+    else if (cep_state & USBD_CEPINTSTS_TXPKIF_Msk)
+    {
+      USBD->CEPINTSTS = USBD_CEPINTSTS_STSDONEIF_Msk;
+      USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
+
+      /* alert TinyUSB that the EP0 IN transfer has finished */
+      if ( (0 == ctrl_in_xfer.in_remaining_bytes) || (0 == ctrl_in_xfer.total_bytes) )
+        dcd_event_xfer_complete(0, 0x80, ctrl_in_xfer.total_bytes, XFER_RESULT_SUCCESS, true);
+
+      if (ctrl_in_xfer.in_remaining_bytes)
+      {
+        USBD->CEPINTSTS = USBD_CEPINTSTS_INTKIF_Msk;
+        USBD->CEPINTEN = USBD_CEPINTEN_INTKIEN_Msk;
+      }
+      else
+      {
+        /* TinyUSB does its own fragmentation and ZLP for EP0; a transfer of zero means a ZLP */
+        if (0 == ctrl_in_xfer.total_bytes) USBD->CEPCTL = USBD_CEPCTL_ZEROLEN_Msk;
+
+        USBD->CEPINTSTS = USBD_CEPINTSTS_STSDONEIF_Msk;
+        USBD->CEPINTEN = USBD_CEPINTEN_SETUPPKIEN_Msk | USBD_CEPINTEN_STSDONEIEN_Msk;
+      }
+    }
+    else if (cep_state & USBD_CEPINTSTS_STSDONEIF_Msk)
+    {
+      /* given ACK from host has happened, we can now set the address (if not already done) */
+      if((USBD->FADDR != assigned_address) && (USBD->FADDR == 0)) USBD->FADDR = assigned_address;
+
+      if (configuration_changed)
+      {
+        for (enum ep_enum ep_index = PERIPH_EPA; ep_index < PERIPH_MAX_EP; ep_index++)
+        {
+          if (USBD->EP[ep_index].EPCFG & USBD_EPCFG_EPEN_Msk) USBD->EP[ep_index].EPRSPCTL = USBD_EPRSPCTL_TOGGLE_Msk;
+        }
+        configuration_changed = false;
+      }
+
+      USBD->CEPINTEN = USBD_CEPINTEN_SETUPPKIEN_Msk;
+    }
+
+    USBD->CEPINTSTS = cep_state;
+
+    return;
+  }
+
+  if (status & (USBD_GINTSTS_EPAIF_Msk | USBD_GINTSTS_EPBIF_Msk | USBD_GINTSTS_EPCIF_Msk | USBD_GINTSTS_EPDIF_Msk | USBD_GINTSTS_EPEIF_Msk | USBD_GINTSTS_EPFIF_Msk | USBD_GINTSTS_EPGIF_Msk | USBD_GINTSTS_EPHIF_Msk | USBD_GINTSTS_EPIIF_Msk | USBD_GINTSTS_EPJIF_Msk | USBD_GINTSTS_EPKIF_Msk | USBD_GINTSTS_EPLIF_Msk))
+  {
+    /* service PERIPH_EPA through PERIPH_EPL */
+    enum ep_enum ep_index;
+    uint32_t mask;
+    struct xfer_ctl_t *xfer;
+    USBD_EP_T *ep;
+    for (ep_index = PERIPH_EPA, mask = USBD_GINTSTS_EPAIF_Msk, xfer = &xfer_table[PERIPH_EPA], ep = &USBD->EP[PERIPH_EPA]; ep_index < PERIPH_MAX_EP; ep_index++, mask <<= 1, xfer++, ep++)
+    {
+      if(status & mask)
+      {
+        uint8_t const ep_addr = xfer->ep_addr;
+        bool const out_ep = !(ep_addr & TUSB_DIR_IN_MASK);
+        uint32_t ep_state = ep->EPINTSTS & ep->EPINTEN;
+
+        if (out_ep)
+        {
+#ifdef OPT_MCU_NUC505_USB_DMA
+          xfer->dma_requested = true;
+          service_dma();
+#else
+          uint16_t const available_bytes = ep->EPDATCNT & USBD_EPDATCNT_DATCNT_Msk;
+          /* copy the data from the PC to the previously provided buffer */
+          for (int count = 0; (count < available_bytes) && (xfer->out_bytes_so_far < xfer->total_bytes); count++, xfer->out_bytes_so_far++)
+            *xfer->data_ptr++ = ep->EPDAT_BYTE;
+
+          /* when the transfer is finished, alert TinyUSB; otherwise, continue accepting more data */
+          if ( (xfer->total_bytes == xfer->out_bytes_so_far) || (available_bytes < xfer->max_packet_size) )
+            dcd_event_xfer_complete(0, ep_addr, xfer->out_bytes_so_far, XFER_RESULT_SUCCESS, true);
+#endif
+
+        }
+        else if (ep_state & USBD_EPINTSTS_BUFEMPTYIF_Msk)
+        {
+          /* send any remaining data */
+          dcd_userEP_in_xfer(xfer, ep);
+        }
+        else if (ep_state & USBD_EPINTSTS_TXPKIF_Msk)
+        {
+          /* alert TinyUSB that we've finished */
+          dcd_event_xfer_complete(0, ep_addr, xfer->total_bytes, XFER_RESULT_SUCCESS, true);
+          ep->EPINTEN = 0;
+        }
+
+        ep->EPINTSTS = ep_state;
+      }
+    }
+  }
+}
+
+void dcd_isr(uint8_t rhport)
+{
+  (void) rhport;
+  USBD_IRQHandler();
+}
+
+#endif
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 8c439616a..89a4ba3f8 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -495,7 +495,7 @@ static void dd_complete_isr(uint8_t rhport, uint8_t ep_id)
 }
 
 // main USB IRQ handler
-void hal_dcd_isr(uint8_t rhport)
+void dcd_isr(uint8_t rhport)
 {
   uint32_t const dev_int_status = LPC_USB->DevIntSt & LPC_USB->DevIntEn;
   LPC_USB->DevIntClr = dev_int_status;// Acknowledge handled interrupt
diff --git a/src/portable/nxp/lpc17_40/hal_lpc17_40.c b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
index e83e3e9a4..537b3daba 100644
--- a/src/portable/nxp/lpc17_40/hal_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
@@ -1,7 +1,7 @@
 /* 
  * The MIT License (MIT)
  *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,27 +24,12 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "common/tusb_common.h"
+#include "tusb_option.h"
 
 #if (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
 
 #include "chip.h"
 
-extern void hal_hcd_isr(uint8_t hostid);
-extern void hal_dcd_isr(uint8_t rhport);
-
-void USB_IRQHandler(void)
-{
-  #if TUSB_OPT_HOST_ENABLED
-    hal_hcd_isr(0);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(0);
-  #endif
-}
-
-//FIXME move later
 void hcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
@@ -57,5 +42,5 @@ void hcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(USB_IRQn);
 }
 
-
 #endif
+
diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
deleted file mode 100644
index 3619a7c2b..000000000
--- a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
+++ /dev/null
@@ -1,356 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX)
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include "common/tusb_common.h"
-#include "device/dcd.h"
-#include "dcd_lpc18_43.h"
-
-#include "chip.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-#define QHD_MAX          12
-#define QTD_NEXT_INVALID 0x01
-
-typedef struct {
-  // Must be at 2K alignment
-  dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64);
-  dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32);
-}dcd_data_t;
-
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048) static dcd_data_t dcd_data0;
-#endif
-
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048) static dcd_data_t dcd_data1;
-#endif
-
-static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
-
-static dcd_data_t* const dcd_data_ptr[2] =
-{
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-  &dcd_data0,
-#else
-  NULL,
-#endif
-
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  &dcd_data1
-#else
-  NULL
-#endif
-};
-
-//--------------------------------------------------------------------+
-// CONTROLLER API
-//--------------------------------------------------------------------+
-
-/// follows LPC43xx User Manual 23.10.3
-static void bus_reset(uint8_t rhport)
-{
-  LPC_USBHS_T* lpc_usb = LPC_USB[rhport];
-
-  // The reset value for all endpoint types is the control endpoint. If one endpoint
-  // direction is enabled and the paired endpoint of opposite direction is disabled, then the
-  // endpoint type of the unused direction must bechanged from the control type to any other
-  // type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
-  // for the data PID tracking on the active endpoint.
-
-  // USB0 has 5 but USB1 only has 3 non-control endpoints
-  for( int i=1; i < (rhport ? 6 : 4); i++)
-  {
-    lpc_usb->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
-  }
-
-  //------------- Clear All Registers -------------//
-  lpc_usb->ENDPTNAK       = lpc_usb->ENDPTNAK;
-  lpc_usb->ENDPTNAKEN     = 0;
-  lpc_usb->USBSTS_D       = lpc_usb->USBSTS_D;
-  lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;
-  lpc_usb->ENDPTCOMPLETE  = lpc_usb->ENDPTCOMPLETE;
-
-  while (lpc_usb->ENDPTPRIME);
-  lpc_usb->ENDPTFLUSH = 0xFFFFFFFF;
-  while (lpc_usb->ENDPTFLUSH);
-
-  // read reset bit in portsc
-
-  //------------- Queue Head & Queue TD -------------//
-  dcd_data_t* p_dcd = dcd_data_ptr[rhport];
-  tu_memclr(p_dcd, sizeof(dcd_data_t));
-
-  //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
-	p_dcd->qhd[0].zero_length_termination = p_dcd->qhd[1].zero_length_termination = 1;
-	p_dcd->qhd[0].max_package_size = p_dcd->qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
-	p_dcd->qhd[0].qtd_overlay.next = p_dcd->qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
-
-	p_dcd->qhd[0].int_on_setup = 1; // OUT only
-}
-
-void dcd_init(uint8_t rhport)
-{
-  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
-  dcd_data_t* p_dcd = dcd_data_ptr[rhport];
-
-  tu_memclr(p_dcd, sizeof(dcd_data_t));
-
-  lpc_usb->ENDPOINTLISTADDR = (uint32_t) p_dcd->qhd; // Endpoint List Address has to be 2K alignment
-  lpc_usb->USBSTS_D  = lpc_usb->USBSTS_D;
-  lpc_usb->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
-
-  lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
-  lpc_usb->USBCMD_D |= TU_BIT(0); // connect
-}
-
-void dcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
-}
-
-void dcd_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  // Response with status first before changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-
-  LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
-}
-
-void dcd_set_config(uint8_t rhport, uint8_t config_num)
-{
-  (void) rhport;
-  (void) config_num;
-  // nothing to do
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void) rhport;
-}
-
-//--------------------------------------------------------------------+
-// HELPER
-//--------------------------------------------------------------------+
-// index to bit position in register
-static inline uint8_t ep_idx2bit(uint8_t ep_idx)
-{
-  return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
-}
-
-static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
-{
-  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
-
-  p_qtd->next        = QTD_NEXT_INVALID;
-  p_qtd->active      = 1;
-  p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
-
-  if (data_ptr != NULL)
-  {
-    p_qtd->buffer[0]   = (uint32_t) data_ptr;
-    for(uint8_t i=1; i<5; i++)
-    {
-      p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
-    }
-  }
-}
-
-//--------------------------------------------------------------------+
-// DCD Endpoint Port
-//--------------------------------------------------------------------+
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
-
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
-
-  // data toggle also need to be reset
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
-  LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir  ? 16 : 0));
-}
-
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
-{
-  // TODO not support ISO yet
-  TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
-
-  uint8_t const epnum  = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const dir    = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  uint8_t const ep_idx = 2*epnum + dir;
-
-  // USB0 has 5, USB1 has 3 non-control endpoints
-  TU_ASSERT( epnum <= (rhport ? 3 : 5) );
-
-  //------------- Prepare Queue Head -------------//
-  dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
-  tu_memclr(p_qhd, sizeof(dcd_qhd_t));
-
-  p_qhd->zero_length_termination = 1;
-  p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
-  p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
-
-  // Enable EP Control
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
-
-  return true;
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-  uint8_t const ep_idx = 2*epnum + dir;
-
-  if ( epnum == 0 )
-  {
-    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
-    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
-    while(LPC_USB[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
-  }
-
-  dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
-  dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
-
-  //------------- Prepare qtd -------------//
-  qtd_init(p_qtd, buffer, total_bytes);
-  p_qtd->int_on_complete = true;
-  p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
-
-  // start transfer
-  LPC_USB[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
-
-  return true;
-}
-
-//--------------------------------------------------------------------+
-// ISR
-//--------------------------------------------------------------------+
-void hal_dcd_isr(uint8_t rhport)
-{
-  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
-
-  uint32_t const int_enable = lpc_usb->USBINTR_D;
-  uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
-  lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
-
-  if (int_status == 0) return;// disabled interrupt sources
-
-
-  if (int_status & INT_MASK_RESET)
-  {
-    bus_reset(rhport);
-    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
-  }
-
-  if (int_status & INT_MASK_SUSPEND)
-  {
-    if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
-    {
-      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-      if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
-      {
-        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-      }
-    }
-  }
-
-  // TODO disconnection does not generate interrupt !!!!!!
-//	if (int_status & INT_MASK_PORT_CHANGE)
-//	{
-//	  if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
-//	  {
-//      dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
-//      dcd_event_handler(&event, true);
-//	  }
-//	}
-
-  if (int_status & INT_MASK_USB)
-  {
-    uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
-    lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
-
-    dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
-
-    if (lpc_usb->ENDPTSETUPSTAT)
-    {
-      //------------- Set up Received -------------//
-      // 23.10.10.2 Operational model for setup transfers
-      lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
-
-      dcd_event_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request, true);
-    }
-
-    if ( edpt_complete )
-    {
-      for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
-      {
-        if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) )
-        {
-          // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
-          dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
-
-          uint8_t result = p_qtd->halted  ? XFER_RESULT_STALLED :
-              ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
-
-          uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
-          dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
-        }
-      }
-    }
-  }
-
-  if (int_status & INT_MASK_SOF)
-  {
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-  }
-
-  if (int_status & INT_MASK_NAK) {}
-  if (int_status & INT_MASK_ERROR) TU_ASSERT(false, );
-}
-
-#endif
diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.h b/src/portable/nxp/lpc18_43/dcd_lpc18_43.h
deleted file mode 100644
index 00f4854b1..000000000
--- a/src/portable/nxp/lpc18_43/dcd_lpc18_43.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/** \ingroup group_dcd
- *  \defgroup group_dcd_lpc143xx LPC43xx
- *  @{ */
-
-#ifndef _TUSB_DCD_LPC43XX_H_
-#define _TUSB_DCD_LPC43XX_H_
-
-#include "common/tusb_common.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-/*---------- ENDPTCTRL ----------*/
-enum {
-  ENDPTCTRL_MASK_STALL          = TU_BIT(0),
-  ENDPTCTRL_MASK_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only
-  ENDPTCTRL_MASK_TOGGLE_RESET   = TU_BIT(6),
-  ENDPTCTRL_MASK_ENABLE         = TU_BIT(7)
-};
-
-/*---------- USBCMD ----------*/
-enum {
-  USBCMD_MASK_RUN_STOP         = TU_BIT(0),
-  USBCMD_MASK_RESET            = TU_BIT(1),
-  USBCMD_MASK_SETUP_TRIPWIRE   = TU_BIT(13),
-  USBCMD_MASK_ADD_QTD_TRIPWIRE = TU_BIT(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
-};
-// Interrupt Threshold bit 23:16
-
-/*---------- USBSTS, USBINTR ----------*/
-enum {
-  INT_MASK_USB         = TU_BIT(0),
-  INT_MASK_ERROR       = TU_BIT(1),
-  INT_MASK_PORT_CHANGE = TU_BIT(2),
-  INT_MASK_RESET       = TU_BIT(6),
-  INT_MASK_SOF         = TU_BIT(7),
-  INT_MASK_SUSPEND     = TU_BIT(8),
-  INT_MASK_NAK         = TU_BIT(16)
-};
-
-//------------- PORTSC -------------//
-enum {
-  PORTSC_CURRENT_CONNECT_STATUS_MASK = TU_BIT(0),
-  PORTSC_FORCE_PORT_RESUME_MASK      = TU_BIT(6),
-  PORTSC_SUSPEND_MASK                = TU_BIT(7)
-};
-
-typedef struct
-{
-  // Word 0: Next QTD Pointer
-  uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
-
-  // Word 1: qTQ Token
-  uint32_t                      : 3  ;
-  volatile uint32_t xact_err    : 1  ;
-  uint32_t                      : 1  ;
-  volatile uint32_t buffer_err  : 1  ;
-  volatile uint32_t halted      : 1  ;
-  volatile uint32_t active      : 1  ;
-  uint32_t                      : 2  ;
-  uint32_t iso_mult_override    : 2  ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
-  uint32_t                      : 3  ;
-  uint32_t int_on_complete      : 1  ;
-  volatile uint32_t total_bytes : 15 ;
-  uint32_t                      : 0  ;
-
-  // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
-  uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
-
-  //------------- DCD Area -------------//
-  uint16_t expected_bytes;
-  uint8_t reserved[2];
-} dcd_qtd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
-
-typedef struct
-{
-  // Word 0: Capabilities and Characteristics
-  uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
-  uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
-  uint32_t max_package_size        : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
-  uint32_t                         : 2  ;
-  uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
-  uint32_t iso_mult                : 2  ; ///<
-  uint32_t                         : 0  ;
-
-  // Word 1: Current qTD Pointer
-	volatile uint32_t qtd_addr;
-
-	// Word 2-9: Transfer Overlay
-	volatile dcd_qtd_t qtd_overlay;
-
-	// Word 10-11: Setup request (control OUT only)
-	volatile tusb_control_request_t setup_request;
-
-	//--------------------------------------------------------------------+
-  /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
-	/// thus there are 16 bytes padding free that we can make use of.
-  //--------------------------------------------------------------------+
-	uint8_t reserved[16];
-}  dcd_qhd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_DCD_LPC43XX_H_ */
-
-/** @} */
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
new file mode 100644
index 000000000..d400a30e3
--- /dev/null
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -0,0 +1,579 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC18XX || \
+                                CFG_TUSB_MCU == OPT_MCU_LPC43XX || \
+                                CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "common/tusb_common.h"
+#include "device/dcd.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+  #include "fsl_device_registers.h"
+#else
+  // LPCOpen for 18xx & 43xx
+  #include "chip.h"
+#endif
+
+#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
+  #define CleanInvalidateDCache_by_Addr   SCB_CleanInvalidateDCache_by_Addr
+#else
+  #define CleanInvalidateDCache_by_Addr(_addr, _dsize)
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+// ENDPTCTRL
+enum {
+  ENDPTCTRL_STALL          = TU_BIT(0),
+  ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only
+  ENDPTCTRL_TOGGLE_RESET   = TU_BIT(6),
+  ENDPTCTRL_ENABLE         = TU_BIT(7)
+};
+
+// USBCMD
+enum {
+  USBCMD_RUN_STOP         = TU_BIT(0),
+  USBCMD_RESET            = TU_BIT(1),
+  USBCMD_SETUP_TRIPWIRE   = TU_BIT(13),
+  USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
+};
+// Interrupt Threshold bit 23:16
+
+// USBSTS, USBINTR
+enum {
+  INTR_USB         = TU_BIT(0),
+  INTR_ERROR       = TU_BIT(1),
+  INTR_PORT_CHANGE = TU_BIT(2),
+  INTR_RESET       = TU_BIT(6),
+  INTR_SOF         = TU_BIT(7),
+  INTR_SUSPEND     = TU_BIT(8),
+  INTR_NAK         = TU_BIT(16)
+};
+
+// PORTSC1
+enum {
+  PORTSC1_CURRENT_CONNECT_STATUS = TU_BIT(0),
+  PORTSC1_FORCE_PORT_RESUME      = TU_BIT(6),
+  PORTSC1_SUSPEND                = TU_BIT(7),
+  PORTSC1_FORCE_FULL_SPEED       = TU_BIT(24),
+};
+
+// OTGSC
+enum {
+  OTGSC_VBUS_DISCHARGE          = TU_BIT(0),
+  OTGSC_VBUS_CHARGE             = TU_BIT(1),
+//  OTGSC_HWASSIST_AUTORESET    = TU_BIT(2),
+  OTGSC_OTG_TERMINATION         = TU_BIT(3), ///< Must set to 1 when OTG go to device mode
+  OTGSC_DATA_PULSING            = TU_BIT(4),
+  OTGSC_ID_PULLUP               = TU_BIT(5),
+//  OTGSC_HWASSIT_DATA_PULSE    = TU_BIT(6),
+//  OTGSC_HWASSIT_BDIS_ACONN    = TU_BIT(7),
+  OTGSC_ID                      = TU_BIT(8), ///< 0 = A device, 1 = B Device
+  OTGSC_A_VBUS_VALID            = TU_BIT(9),
+  OTGSC_A_SESSION_VALID         = TU_BIT(10),
+  OTGSC_B_SESSION_VALID         = TU_BIT(11),
+  OTGSC_B_SESSION_END           = TU_BIT(12),
+  OTGSC_1MS_TOGGLE              = TU_BIT(13),
+  OTGSC_DATA_BUS_PULSING_STATUS = TU_BIT(14),
+};
+
+// USBMode
+enum {
+  USBMODE_CM_DEVICE = 2,
+  USBMODE_CM_HOST   = 3,
+
+  USBMODE_SLOM = TU_BIT(3),
+  USBMODE_SDIS = TU_BIT(4),
+
+  USBMODE_VBUS_POWER_SELCT = TU_BIT(5), // Enable for LPC18XX/43XX in host most only
+};
+
+// Device Registers
+typedef struct
+{
+  //------------- ID + HW Parameter Registers-------------//
+  __I  uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
+
+  //------------- Capability Registers-------------//
+  __I  uint8_t  CAPLENGTH;       ///< Capability Registers Length
+  __I  uint8_t  TU_RESERVED[1];
+  __I  uint16_t HCIVERSION;      ///< Host Controller Interface Version
+
+  __I  uint32_t HCSPARAMS;       ///< Host Controller Structural Parameters
+  __I  uint32_t HCCPARAMS;       ///< Host Controller Capability Parameters
+  __I  uint32_t TU_RESERVED[5];
+
+  __I  uint16_t DCIVERSION;      ///< Device Controller Interface Version
+  __I  uint8_t  TU_RESERVED[2];
+
+  __I  uint32_t DCCPARAMS;       ///< Device Controller Capability Parameters
+  __I  uint32_t TU_RESERVED[6];
+
+  //------------- Operational Registers -------------//
+  __IO uint32_t USBCMD;          ///< USB Command Register
+  __IO uint32_t USBSTS;          ///< USB Status Register
+  __IO uint32_t USBINTR;         ///< Interrupt Enable Register
+  __IO uint32_t FRINDEX;         ///< USB Frame Index
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t DEVICEADDR;      ///< Device Address
+  __IO uint32_t ENDPTLISTADDR;   ///< Endpoint List Address
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t BURSTSIZE;       ///< Programmable Burst Size
+  __IO uint32_t TXFILLTUNING;    ///< TX FIFO Fill Tuning
+       uint32_t TU_RESERVED[4];
+  __IO uint32_t ENDPTNAK;        ///< Endpoint NAK
+  __IO uint32_t ENDPTNAKEN;      ///< Endpoint NAK Enable
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t PORTSC1;         ///< Port Status & Control
+  __I  uint32_t TU_RESERVED[7];
+  __IO uint32_t OTGSC;           ///< On-The-Go Status & control
+  __IO uint32_t USBMODE;         ///< USB Device Mode
+  __IO uint32_t ENDPTSETUPSTAT;  ///< Endpoint Setup Status
+  __IO uint32_t ENDPTPRIME;      ///< Endpoint Prime
+  __IO uint32_t ENDPTFLUSH;      ///< Endpoint Flush
+  __I  uint32_t ENDPTSTAT;       ///< Endpoint Status
+  __IO uint32_t ENDPTCOMPLETE;   ///< Endpoint Complete
+  __IO uint32_t ENDPTCTRL[8];    ///< Endpoint Control 0 - 7
+} dcd_registers_t;
+
+
+// Queue Transfer Descriptor
+typedef struct
+{
+  // Word 0: Next QTD Pointer
+  uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
+
+  // Word 1: qTQ Token
+  uint32_t                      : 3  ;
+  volatile uint32_t xact_err    : 1  ;
+  uint32_t                      : 1  ;
+  volatile uint32_t buffer_err  : 1  ;
+  volatile uint32_t halted      : 1  ;
+  volatile uint32_t active      : 1  ;
+  uint32_t                      : 2  ;
+  uint32_t iso_mult_override    : 2  ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
+  uint32_t                      : 3  ;
+  uint32_t int_on_complete      : 1  ;
+  volatile uint32_t total_bytes : 15 ;
+  uint32_t                      : 0  ;
+
+  // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
+  uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
+
+  //------------- DCD Area -------------//
+  uint16_t expected_bytes;
+  uint8_t reserved[2];
+} dcd_qtd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
+
+// Queue Head
+typedef struct
+{
+  // Word 0: Capabilities and Characteristics
+  uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
+  uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
+  uint32_t max_package_size        : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
+  uint32_t                         : 2  ;
+  uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
+  uint32_t iso_mult                : 2  ; ///<
+  uint32_t                         : 0  ;
+
+  // Word 1: Current qTD Pointer
+  volatile uint32_t qtd_addr;
+
+  // Word 2-9: Transfer Overlay
+  volatile dcd_qtd_t qtd_overlay;
+
+  // Word 10-11: Setup request (control OUT only)
+  volatile tusb_control_request_t setup_request;
+
+  //--------------------------------------------------------------------+
+  /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
+  /// thus there are 16 bytes padding free that we can make use of.
+  //--------------------------------------------------------------------+
+  uint8_t reserved[16];
+} dcd_qhd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Variables
+//--------------------------------------------------------------------+
+
+typedef struct
+{
+  dcd_registers_t* regs;  // registers
+  const IRQn_Type irqnum; // IRQ number
+  const uint8_t ep_count;   // Max bi-directional Endpoints
+}dcd_controller_t;
+
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+  // Each endpoint with direction (IN/OUT) occupies a queue head
+  // Therefore QHD_MAX is 2 x max endpoint count
+  #define QHD_MAX  (8*2)
+
+  dcd_controller_t _dcd_controller[] =
+  {
+    // RT1010 and RT1020 only has 1 USB controller
+    #if FSL_FEATURE_SOC_USBHS_COUNT == 1
+      { .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
+    #else
+      { .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
+      { .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
+    #endif
+  };
+
+#else
+  #define QHD_MAX (6*2)
+
+  dcd_controller_t _dcd_controller[] =
+  {
+    { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
+    { .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
+  };
+#endif
+
+#define QTD_NEXT_INVALID 0x01
+
+typedef struct {
+  // Must be at 2K alignment
+  dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64);
+  dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32); // for portability, TinyUSB only queue 1 TD for each Qhd
+}dcd_data_t;
+
+static dcd_data_t _dcd_data CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048);
+
+//--------------------------------------------------------------------+
+// CONTROLLER API
+//--------------------------------------------------------------------+
+
+/// follows LPC43xx User Manual 23.10.3
+static void bus_reset(uint8_t rhport)
+{
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+
+  // The reset value for all endpoint types is the control endpoint. If one endpoint
+  // direction is enabled and the paired endpoint of opposite direction is disabled, then the
+  // endpoint type of the unused direction must be changed from the control type to any other
+  // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
+  // for the data PID tracking on the active endpoint.
+  for( int i=1; i < _dcd_controller[rhport].ep_count; i++)
+  {
+    dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
+  }
+
+  //------------- Clear All Registers -------------//
+  dcd_reg->ENDPTNAK       = dcd_reg->ENDPTNAK;
+  dcd_reg->ENDPTNAKEN     = 0;
+  dcd_reg->USBSTS         = dcd_reg->USBSTS;
+  dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
+  dcd_reg->ENDPTCOMPLETE  = dcd_reg->ENDPTCOMPLETE;
+
+  while (dcd_reg->ENDPTPRIME) {}
+  dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
+  while (dcd_reg->ENDPTFLUSH) {}
+
+  // read reset bit in portsc
+
+  //------------- Queue Head & Queue TD -------------//
+  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
+
+  //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
+  _dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1;
+  _dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
+  _dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
+
+  _dcd_data.qhd[0].int_on_setup = 1; // OUT only
+}
+
+void dcd_init(uint8_t rhport)
+{
+  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
+
+  dcd_registers_t* const dcd_reg = _dcd_controller[rhport].regs;
+
+  // Reset controller
+  dcd_reg->USBCMD |= USBCMD_RESET;
+  while( dcd_reg->USBCMD & USBCMD_RESET ) {}
+
+  // Set mode to device, must be set immediately after reset
+  dcd_reg->USBMODE = USBMODE_CM_DEVICE;
+  dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
+
+  // TODO Force fullspeed on non-highspeed port
+  // dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
+
+  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+
+  dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
+  dcd_reg->USBSTS  = dcd_reg->USBSTS;
+  dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND /*| INTR_SOF*/;
+
+  dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
+  dcd_reg->USBCMD |= TU_BIT(0); // connect
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  // Response with status first before changing device address
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+  // nothing to do
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+}
+
+//--------------------------------------------------------------------+
+// HELPER
+//--------------------------------------------------------------------+
+// index to bit position in register
+static inline uint8_t ep_idx2bit(uint8_t ep_idx)
+{
+  return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
+}
+
+static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
+{
+  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
+
+  p_qtd->next        = QTD_NEXT_INVALID;
+  p_qtd->active      = 1;
+  p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
+
+  if (data_ptr != NULL)
+  {
+    p_qtd->buffer[0]   = (uint32_t) data_ptr;
+    for(uint8_t i=1; i<5; i++)
+    {
+      p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// DCD Endpoint Port
+//--------------------------------------------------------------------+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = tu_edpt_number(ep_addr);
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
+
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = tu_edpt_number(ep_addr);
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
+
+  // data toggle also need to be reset
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
+  dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir  ? 16 : 0));
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  // TODO not support ISO yet
+  TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
+
+  uint8_t const epnum  = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir    = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  uint8_t const ep_idx = 2*epnum + dir;
+
+  // Must not exceed max endpoint number
+  TU_ASSERT( epnum < _dcd_controller[rhport].ep_count );
+
+  //------------- Prepare Queue Head -------------//
+  dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
+  tu_memclr(p_qhd, sizeof(dcd_qhd_t));
+
+  p_qhd->zero_length_termination = 1;
+  p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
+  p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
+
+  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+
+  // Enable EP Control
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
+
+  return true;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const ep_idx = 2*epnum + dir;
+
+  if ( epnum == 0 )
+  {
+    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
+    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
+    while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
+  }
+
+  dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
+  dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
+
+  // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
+  // address to 32-byte boundaries.
+  CleanInvalidateDCache_by_Addr((uint32_t*) buffer, total_bytes + 31);
+
+  //------------- Prepare qtd -------------//
+  qtd_init(p_qtd, buffer, total_bytes);
+  p_qtd->int_on_complete = true;
+  p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
+
+  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+
+  // start transfer
+  dcd_reg->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_isr(uint8_t rhport)
+{
+  dcd_registers_t* const dcd_reg = _dcd_controller[rhport].regs;
+
+  uint32_t const int_enable = dcd_reg->USBINTR;
+  uint32_t const int_status = dcd_reg->USBSTS & int_enable;
+  dcd_reg->USBSTS = int_status; // Acknowledge handled interrupt
+
+  // disabled interrupt sources
+  if (int_status == 0) return;
+
+  if (int_status & INTR_RESET)
+  {
+    bus_reset(rhport);
+    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
+  }
+
+  if (int_status & INTR_SUSPEND)
+  {
+    if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
+    {
+      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+      if ((dcd_reg->DEVICEADDR >> 25) & 0x0f)
+      {
+        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+      }
+    }
+  }
+
+  // Make sure we read the latest version of _dcd_data.
+  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+
+  // TODO disconnection does not generate interrupt !!!!!!
+//	if (int_status & INTR_PORT_CHANGE)
+//	{
+//	  if ( !(dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) )
+//	  {
+//      dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
+//      dcd_event_handler(&event, true);
+//	  }
+//	}
+
+  if (int_status & INTR_USB)
+  {
+    uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
+    dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
+
+    if (dcd_reg->ENDPTSETUPSTAT)
+    {
+      //------------- Set up Received -------------//
+      // 23.10.10.2 Operational model for setup transfers
+      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;// acknowledge
+
+      dcd_event_setup_received(rhport, (uint8_t*) &_dcd_data.qhd[0].setup_request, true);
+    }
+
+    if ( edpt_complete )
+    {
+      for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
+      {
+        if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) )
+        {
+          // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
+          dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
+
+          uint8_t result = p_qtd->halted  ? XFER_RESULT_STALLED :
+              ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
+
+          uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
+          dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
+        }
+      }
+    }
+  }
+
+  if (int_status & INTR_SOF)
+  {
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+
+  if (int_status & INTR_NAK) {}
+  if (int_status & INTR_ERROR) TU_ASSERT(false, );
+}
+
+#endif
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index ec182960e..5eacbe655 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -30,7 +30,7 @@
 
 /**********************************************
  * This driver has been tested with the following MCUs:
- *  - F070, F072, L053
+ *  - F070, F072, L053, F042F6
  *
  * It also should work with minimal changes for any ST MCU with an "USB A"/"PCD"/"HCD" peripheral. This
  *  covers:
@@ -44,6 +44,9 @@
  * L4x2, L4x3                     1024 byte buffer
  *
  * To use this driver, you must:
+ * - If you are using a device with crystal-less USB, set up the clock recovery system (CRS)
+ * - Remap pins to be D+/D- on devices that they are shared (for example: F042Fx)
+ *   - This is different to the normal "alternate function" GPIO interface, needs to go through SYSCFG->CFGRx register
  * - Enable USB clock; Perhaps use __HAL_RCC_USB_CLK_ENABLE();
  * - (Optionally configure GPIO HAL to tell it the USB driver is using the USB pins)
  * - call tusb_init();
@@ -172,7 +175,6 @@ static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t epnum, uint32_t dir)
 
 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
 
-static uint8_t newDADDR; // Used to set the new device address during the CTR IRQ handler
 static uint8_t remoteWakeCountdown; // When wake is requested
 
 // EP Buffers assigned from end of memory location, to minimize their chance of crashing
@@ -295,14 +297,14 @@ void dcd_int_disable(uint8_t rhport)
 // Receive Set Address request, mcu port must also include status IN response
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
-  (void)rhport;
-  // We cannot immediatly change it; it must be queued to change after the STATUS packet is sent.
-  // (CTR handler will actually change the address once it sees that the transmission is complete)
-  newDADDR = dev_addr;
+  (void) rhport;
+  (void) dev_addr;
 
   // Respond with status
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 
+  // DCD can only set address after status for this request is complete.
+  // do it at dcd_edpt0_status_complete()
 }
 
 // Receive Set Config request
@@ -321,29 +323,27 @@ void dcd_remote_wakeup(uint8_t rhport)
   remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms.
 }
 
-// I'm getting a weird warning about missing braces here that I don't
-// know how to fix.
-#if defined(__GNUC__) && (__GNUC__ >= 7)
-#  pragma GCC diagnostic push
-#  pragma GCC diagnostic ignored "-Wmissing-braces"
-#endif
 static const tusb_desc_endpoint_t ep0OUT_desc =
 {
-    .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
-    .bDescriptorType = TUSB_XFER_CONTROL,
-    .bEndpointAddress = 0x00
+  .bLength          = sizeof(tusb_desc_endpoint_t),
+  .bDescriptorType  = TUSB_DESC_ENDPOINT,
+
+  .bEndpointAddress = 0x00,
+  .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
+  .wMaxPacketSize   = { .size = CFG_TUD_ENDPOINT0_SIZE },
+  .bInterval        = 0
 };
 
 static const tusb_desc_endpoint_t ep0IN_desc =
 {
-    .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
-    .bDescriptorType = TUSB_XFER_CONTROL,
-    .bEndpointAddress = 0x80
-};
+  .bLength          = sizeof(tusb_desc_endpoint_t),
+  .bDescriptorType  = TUSB_DESC_ENDPOINT,
 
-#if defined(__GNUC__) && (__GNUC__ >= 7)
-#pragma GCC diagnostic pop
-#endif
+  .bEndpointAddress = 0x80,
+  .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
+  .wMaxPacketSize   = { .size = CFG_TUD_ENDPOINT0_SIZE },
+  .bInterval        = 0
+};
 
 static void dcd_handle_bus_reset(void)
 {
@@ -359,7 +359,7 @@ static void dcd_handle_bus_reset(void)
   ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each)
   dcd_edpt_open (0, &ep0OUT_desc);
   dcd_edpt_open (0, &ep0IN_desc);
-  newDADDR = 0u;
+
   USB->DADDR = USB_DADDR_EF; // Set enable flag, and leaving the device address as zero.
 }
 
@@ -395,13 +395,7 @@ static uint16_t dcd_ep_ctr_handler(void)
         if((xfer->total_len == xfer->queued_len))
         {
           dcd_event_xfer_complete(0u, (uint8_t)(0x80 + EPindex), xfer->total_len, XFER_RESULT_SUCCESS, true);
-          if((newDADDR != 0) && ( xfer->total_len == 0U))
-          {
-            // Delayed setting of the DADDR after the 0-len DATA packet acking the request is sent.
-            reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD);
-            USB->DADDR = (uint16_t)(USB->DADDR | newDADDR); // leave the enable bit set
-            newDADDR = 0;
-          }
+
           if(xfer->total_len == 0) // Probably a status message?
           {
             pcd_clear_rx_dtog(USB,EPindex);
@@ -599,6 +593,24 @@ static void dcd_fs_irqHandler(void) {
 // Endpoint API
 //--------------------------------------------------------------------+
 
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  (void) rhport;
+
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS )
+  {
+    uint8_t const dev_addr = (uint8_t) request->wValue;
+
+    // Setting new address after the whole request is complete
+    reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD);
+    USB->DADDR = (uint16_t)(USB->DADDR | dev_addr); // leave the enable bit set
+  }
+}
+
 // The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers,
 // so I'm using the #define from HAL here, instead.
 
diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index 7929b6916..c16211a9d 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -207,12 +207,8 @@ void dcd_init (uint8_t rhport)
     USB_OTG_GINTMSK_SOFM | USB_OTG_GINTMSK_RXFLVLM /* SB_OTG_GINTMSK_ESUSPM | \
     USB_OTG_GINTMSK_USBSUSPM */;
 
-  // Enable VBUS hardware sensing, enable pullup, enable peripheral.
-#ifdef USB_OTG_GCCFG_VBDEN
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN | USB_OTG_GCCFG_PWRDWN;
-#else
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_PWRDWN;
-#endif
+  // Enable USB transceiver.
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_PWRDWN;
 
   // Soft Connect -> Enable pullup on D+/D-.
   // This step does not appear to be specified in the programmer's model.
@@ -236,7 +232,6 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
   (void) rhport;
 
   USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
-
   dev->DCFG |= (dev_addr << USB_OTG_DCFG_DAD_Pos) & USB_OTG_DCFG_DAD_Msk;
 
   // Response with status after changing device address
diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c
new file mode 100644
index 000000000..102910509
--- /dev/null
+++ b/src/portable/template/dcd_template.c
@@ -0,0 +1,116 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_NONE
+
+#include "device/dcd.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+
+// Initialize controller to device mode
+void dcd_init (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+// Enable device interrupt
+void dcd_int_enable (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+// Disable device interrupt
+void dcd_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+// Receive Set Address request, mcu port must also include status IN response
+void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+  (void) dev_addr;
+}
+
+// Receive Set Configure request
+void dcd_set_config (uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+}
+
+// Wake up host
+void dcd_remote_wakeup (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+  (void) ep_desc;
+  return false;
+}
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  (void) rhport;
+  (void) ep_addr;
+  (void) buffer;
+  (void) total_bytes;
+  return false;
+}
+
+// Stall endpoint
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  (void) ep_addr;
+}
+
+// clear stall, data toggle is also reset to DATA0
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  (void) ep_addr;
+}
+
+#endif
diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c
new file mode 100644
index 000000000..f1b79dcfd
--- /dev/null
+++ b/src/portable/valentyusb/eptri/dcd_eptri.c
@@ -0,0 +1,638 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef DEBUG
+#define DEBUG 0
+#endif
+
+#ifndef LOG_USB
+#define LOG_USB 0
+#endif
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI)
+
+#include "device/dcd.h"
+#include "dcd_eptri.h"
+#include "csr.h"
+#include "irq.h"
+void fomu_error(uint32_t line);
+
+#if LOG_USB
+struct usb_log {
+  uint8_t ep_num;
+  uint8_t size;
+  uint8_t data[66];
+};
+__attribute__((used))
+struct usb_log usb_log[128];
+__attribute__((used))
+uint8_t usb_log_offset;
+
+struct xfer_log {
+  uint8_t ep_num;
+  uint16_t size;
+};
+__attribute__((used))
+struct xfer_log xfer_log[64];
+__attribute__((used))
+uint8_t xfer_log_offset;
+
+__attribute__((used))
+struct xfer_log queue_log[64];
+__attribute__((used))
+uint8_t queue_log_offset;
+#endif
+
+//--------------------------------------------------------------------+
+// SIE Command
+//--------------------------------------------------------------------+
+
+#define EP_SIZE 64
+
+uint16_t volatile rx_buffer_offset[16];
+uint8_t* volatile rx_buffer[16];
+uint16_t volatile rx_buffer_max[16];
+
+volatile uint8_t tx_ep;
+volatile bool tx_active;
+volatile uint16_t tx_buffer_offset[16];
+uint8_t* volatile tx_buffer[16];
+volatile uint16_t tx_buffer_max[16];
+volatile uint8_t reset_count;
+
+#if DEBUG
+__attribute__((used)) uint8_t volatile * last_tx_buffer;
+__attribute__((used)) volatile uint8_t last_tx_ep;
+uint8_t setup_packet_bfr[10];
+#endif
+
+//--------------------------------------------------------------------+
+// PIPE HELPER
+//--------------------------------------------------------------------+
+
+static bool advance_tx_ep(void) {
+  // Move on to the next transmit buffer in a round-robin manner
+  uint8_t prev_tx_ep = tx_ep;
+  for (tx_ep = (tx_ep + 1) & 0xf; tx_ep != prev_tx_ep; tx_ep = ((tx_ep + 1) & 0xf)) {
+    if (tx_buffer[tx_ep])
+      return true;
+  }
+  if (!tx_buffer[tx_ep])
+    return false;
+  return true;
+}
+
+#if LOG_USB
+void xfer_log_append(uint8_t ep_num, uint16_t sz) {
+  xfer_log[xfer_log_offset].ep_num = ep_num;
+  xfer_log[xfer_log_offset].size = sz;
+  xfer_log_offset++;
+  if (xfer_log_offset >= sizeof(xfer_log)/sizeof(*xfer_log))
+    xfer_log_offset = 0;
+}
+
+void queue_log_append(uint8_t ep_num, uint16_t sz) {
+  queue_log[queue_log_offset].ep_num = ep_num;
+  queue_log[queue_log_offset].size = sz;
+  queue_log_offset++;
+  if (queue_log_offset >= sizeof(queue_log)/sizeof(*queue_log))
+    queue_log_offset = 0;
+}
+#endif
+
+static void tx_more_data(void) {
+  // Send more data
+  uint8_t added_bytes;
+  for (added_bytes = 0; (added_bytes < EP_SIZE) && (tx_buffer_offset[tx_ep] < tx_buffer_max[tx_ep]); added_bytes++) {
+#if LOG_USB
+    usb_log[usb_log_offset].data[added_bytes] = tx_buffer[tx_ep][tx_buffer_offset[tx_ep]];
+#endif
+    usb_in_data_write(tx_buffer[tx_ep][tx_buffer_offset[tx_ep]++]);
+  }
+
+#if LOG_USB
+  usb_log[usb_log_offset].ep_num = tu_edpt_addr(tx_ep, TUSB_DIR_IN);
+  usb_log[usb_log_offset].size = added_bytes;
+  usb_log_offset++;
+  if (usb_log_offset >= sizeof(usb_log)/sizeof(*usb_log))
+    usb_log_offset = 0;
+#endif
+
+  // Updating the epno queues the data
+  usb_in_ctrl_write(tx_ep & 0xf);
+}
+
+static void process_tx(void) {
+#if DEBUG
+  // If the system isn't idle, then something is very wrong.
+  uint8_t in_status = usb_in_status_read();
+  if (!(in_status & (1 << CSR_USB_IN_STATUS_IDLE_OFFSET)))
+    fomu_error(__LINE__);
+#endif
+
+  // If the buffer is now empty, search for the next buffer to fill.
+  if (!tx_buffer[tx_ep]) {
+    if (advance_tx_ep())
+      tx_more_data();
+    else
+      tx_active = false;
+    return;
+  }
+
+  if (tx_buffer_offset[tx_ep] >= tx_buffer_max[tx_ep]) {
+#if DEBUG
+    last_tx_buffer = tx_buffer[tx_ep];
+    last_tx_ep = tx_ep;
+#endif
+    tx_buffer[tx_ep] = NULL;
+    uint16_t xferred_bytes = tx_buffer_max[tx_ep];
+    uint8_t xferred_ep = tx_ep;
+
+    if (!advance_tx_ep())
+      tx_active = false;
+#if LOG_USB
+    xfer_log_append(tu_edpt_addr(xferred_ep, TUSB_DIR_IN), xferred_bytes);
+#endif
+    dcd_event_xfer_complete(0, tu_edpt_addr(xferred_ep, TUSB_DIR_IN), xferred_bytes, XFER_RESULT_SUCCESS, true);
+    if (!tx_active)
+      return;
+  }
+
+  tx_more_data();
+  return;
+}
+
+static void process_rx(void) {
+  uint8_t out_status = usb_out_status_read();
+#if DEBUG
+  // If the OUT handler is still waiting to send, don't do anything.
+  if (!(out_status & (1 << CSR_USB_OUT_STATUS_HAVE_OFFSET)))
+    fomu_error(__LINE__);
+    // return;
+#endif
+  uint8_t rx_ep = (out_status >> CSR_USB_OUT_STATUS_EPNO_OFFSET) & 0xf;
+
+  // If the destination buffer doesn't exist, don't drain the hardware
+  // fifo.  Note that this can cause deadlocks if the host is waiting
+  // on some other endpoint's data!
+#if DEBUG
+  if (rx_buffer[rx_ep] == NULL) {
+    fomu_error(__LINE__);
+    return;
+  }
+#endif
+
+  // Drain the FIFO into the destination buffer
+  uint32_t total_read = 0;
+  uint32_t current_offset = rx_buffer_offset[rx_ep];
+#if DEBUG
+  uint8_t test_buffer[256];
+  memset(test_buffer, 0, sizeof(test_buffer));
+  if (current_offset > rx_buffer_max[rx_ep])
+    fomu_error(__LINE__);
+#endif
+#if LOG_USB
+  usb_log[usb_log_offset].ep_num = tu_edpt_addr(rx_ep, TUSB_DIR_OUT);
+  usb_log[usb_log_offset].size = 0;
+#endif
+  while (usb_out_status_read() & (1 << CSR_USB_OUT_STATUS_HAVE_OFFSET)) {
+    uint8_t c = usb_out_data_read();
+#if DEBUG
+    test_buffer[total_read] = c;
+#endif
+    total_read++;
+    if (current_offset < rx_buffer_max[rx_ep]) {
+#if LOG_USB
+      usb_log[usb_log_offset].data[usb_log[usb_log_offset].size++] = c;
+#endif
+      if (rx_buffer[rx_ep] != (volatile uint8_t *)0xffffffff)
+        rx_buffer[rx_ep][current_offset++] = c;
+    }
+  }
+#if LOG_USB
+  usb_log_offset++;
+  if (usb_log_offset >= sizeof(usb_log)/sizeof(*usb_log))
+    usb_log_offset = 0;
+#endif
+#if DEBUG
+  if (total_read > 66)
+    fomu_error(__LINE__);
+  if (total_read < 2)
+    total_read = 2;
+    // fomu_error(__LINE__);
+#endif
+
+  // Strip off the CRC16
+  rx_buffer_offset[rx_ep] += (total_read - 2);
+  if (rx_buffer_offset[rx_ep] > rx_buffer_max[rx_ep])
+    rx_buffer_offset[rx_ep] = rx_buffer_max[rx_ep];
+
+  // If there's no more data, complete the transfer to tinyusb
+  if ((rx_buffer_max[rx_ep] == rx_buffer_offset[rx_ep])
+  // ZLP with less than the total amount of data
+  || ((total_read == 2) && ((rx_buffer_offset[rx_ep] & 63) == 0))
+  // Short read, but not a full packet
+  || (((rx_buffer_offset[rx_ep] & 63) != 0) && (total_read < 66))) {
+#if DEBUG
+    if (rx_buffer[rx_ep] == NULL)
+      fomu_error(__LINE__);
+#endif
+
+    // Free up this buffer.
+    rx_buffer[rx_ep] = NULL;
+    uint16_t len = rx_buffer_offset[rx_ep];
+
+#if DEBUG
+    // Validate that all enabled endpoints have buffers,
+    // and no disabled endpoints have buffers.
+    uint16_t ep_en_mask = usb_out_enable_status_read();
+    int i;
+    for (i = 0; i < 16; i++) {
+      if ((!!(ep_en_mask & (1 << i))) ^ (!!(rx_buffer[i]))) {
+        uint8_t new_status = usb_out_status_read();
+        // Another IRQ came in while we were processing, so ignore this endpoint.
+        if ((new_status & 0x20) && ((new_status & 0xf) == i))
+          continue;
+        fomu_error(__LINE__);
+      }
+    }
+#endif
+#if LOG_USB
+    xfer_log_append(tu_edpt_addr(rx_ep, TUSB_DIR_OUT), len);
+#endif
+    dcd_event_xfer_complete(0, tu_edpt_addr(rx_ep, TUSB_DIR_OUT), len, XFER_RESULT_SUCCESS, true);
+  }
+  else {
+    // If there's more data, re-enable data reception on this endpoint
+    usb_out_ctrl_write((1 << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | rx_ep);
+  }
+
+  // Now that the buffer is drained, clear the pending IRQ.
+  usb_out_ev_pending_write(usb_out_ev_pending_read());
+}
+
+//--------------------------------------------------------------------+
+// CONTROLLER API
+//--------------------------------------------------------------------+
+
+static void dcd_reset(void)
+{
+  reset_count++;
+  usb_setup_ev_enable_write(0);
+  usb_in_ev_enable_write(0);
+  usb_out_ev_enable_write(0);
+
+  usb_address_write(0);
+
+  // Reset all three FIFO handlers
+  usb_setup_ctrl_write(1 << CSR_USB_SETUP_CTRL_RESET_OFFSET);
+  usb_in_ctrl_write(1 << CSR_USB_IN_CTRL_RESET_OFFSET);
+  usb_out_ctrl_write(1 << CSR_USB_OUT_CTRL_RESET_OFFSET);
+
+  memset((void *)rx_buffer, 0, sizeof(rx_buffer));
+  memset((void *)rx_buffer_max, 0, sizeof(rx_buffer_max));
+  memset((void *)rx_buffer_offset, 0, sizeof(rx_buffer_offset));
+
+  memset((void *)tx_buffer, 0, sizeof(tx_buffer));
+  memset((void *)tx_buffer_max, 0, sizeof(tx_buffer_max));
+  memset((void *)tx_buffer_offset, 0, sizeof(tx_buffer_offset));
+  tx_ep = 0;
+  tx_active = false;
+
+  // Enable all event handlers and clear their contents
+  usb_setup_ev_pending_write(0xff);
+  usb_in_ev_pending_write(0xff);
+  usb_out_ev_pending_write(0xff);
+  usb_in_ev_enable_write(1);
+  usb_out_ev_enable_write(1);
+  usb_setup_ev_enable_write(3);
+
+  dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+}
+
+// Initializes the USB peripheral for device mode and enables it.
+void dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+  usb_pullup_out_write(0);
+
+  // Enable all event handlers and clear their contents
+  usb_setup_ev_pending_write(usb_setup_ev_pending_read());
+  usb_in_ev_pending_write(usb_in_ev_pending_read());
+  usb_out_ev_pending_write(usb_out_ev_pending_read());
+  usb_in_ev_enable_write(1);
+  usb_out_ev_enable_write(1);
+  usb_setup_ev_enable_write(3);
+
+  // Turn on the external pullup
+  usb_pullup_out_write(1);
+}
+
+// Enables or disables the USB device interrupt(s). May be used to
+// prevent concurrency issues when mutating data structures shared
+// between main code and the interrupt handler.
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+	irq_setmask(irq_getmask() | (1 << USB_INTERRUPT));
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  irq_setmask(irq_getmask() & ~(1 << USB_INTERRUPT));
+}
+
+// Called when the device is given a new bus address.
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  // Respond with ACK status first before changing device address
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+
+  // Wait for the response packet to get sent
+  while (tx_active)
+    ;
+
+  // Activate the new address
+  usb_address_write(dev_addr);
+}
+
+// Called when the device received SET_CONFIG request, you can leave this
+// empty if your peripheral does not require any specific action.
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+}
+
+// Called to remote wake up host when suspended (e.g hid keyboard)
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+}
+
+//--------------------------------------------------------------------+
+// DCD Endpoint Port
+//--------------------------------------------------------------------+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  (void) rhport;
+  uint8_t ep_num = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t ep_dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+
+  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
+    return false; // Not supported
+
+  if (ep_dir == TUSB_DIR_OUT) {
+    rx_buffer_offset[ep_num] = 0;
+    rx_buffer_max[ep_num] = 0;
+    rx_buffer[ep_num] = NULL;
+  }
+
+  else if (ep_dir == TUSB_DIR_IN) {
+    tx_buffer_offset[ep_num] = 0;
+    tx_buffer_max[ep_num] = 0;
+    tx_buffer[ep_num] = NULL;
+  }
+
+  return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  if (tu_edpt_dir(ep_addr) == TUSB_DIR_OUT) {
+    uint8_t enable = 0;
+    if (rx_buffer[ep_addr])
+      enable = 1;
+    usb_out_ctrl_write((1 << CSR_USB_OUT_CTRL_STALL_OFFSET) | (enable << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | tu_edpt_number(ep_addr));
+  }
+  else
+    usb_in_ctrl_write((1 << CSR_USB_IN_CTRL_STALL_OFFSET) | tu_edpt_number(ep_addr));
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  if (tu_edpt_dir(ep_addr) == TUSB_DIR_OUT) {
+    uint8_t enable = 0;
+    if (rx_buffer[ep_addr])
+      enable = 1;
+    usb_out_ctrl_write((0 << CSR_USB_OUT_CTRL_STALL_OFFSET) | (enable << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | tu_edpt_number(ep_addr));
+  }
+  // IN endpoints will get unstalled when more data is written.
+}
+
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+  uint8_t ep_num = tu_edpt_number(ep_addr);
+  uint8_t ep_dir = tu_edpt_dir(ep_addr);
+  TU_ASSERT(ep_num < 16);
+
+  // Give a nonzero buffer when we transmit 0 bytes, so that the
+  // system doesn't think the endpoint is idle.
+  if ((buffer == NULL) && (total_bytes == 0)) {
+    buffer = (uint8_t *)0xffffffff;
+  }
+
+  TU_ASSERT(buffer != NULL);
+
+  if (ep_dir == TUSB_DIR_IN) {
+    // Wait for the tx pipe to free up
+    uint8_t previous_reset_count = reset_count;
+    // Continue until the buffer is empty, the system is idle, and the fifo is empty.
+    while (tx_buffer[ep_num] != NULL)
+      ;
+
+    dcd_int_disable(0);
+#if LOG_USB
+    queue_log_append(ep_addr, total_bytes);
+#endif
+    // If a reset happens while we're waiting, abort the transfer
+    if (previous_reset_count != reset_count)
+      return true;
+
+    TU_ASSERT(tx_buffer[ep_num] == NULL);
+    tx_buffer_offset[ep_num] = 0;
+    tx_buffer_max[ep_num] = total_bytes;
+    tx_buffer[ep_num] = buffer;
+
+    // If the current buffer is NULL, then that means the tx logic is idle.
+    // Update the tx_ep to point to our endpoint number and queue the data.
+    // Otherwise, let it be and it'll get picked up after the next transfer
+    // finishes.
+    if (!tx_active) {
+      tx_ep = ep_num;
+      tx_active = true;
+      tx_more_data();
+    }
+    dcd_int_enable(0);
+  }
+
+  else if (ep_dir == TUSB_DIR_OUT) {
+    while (rx_buffer[ep_num] != NULL)
+      ;
+
+    TU_ASSERT(rx_buffer[ep_num] == NULL);
+    dcd_int_disable(0);
+#if LOG_USB
+    queue_log_append(ep_addr, total_bytes);
+#endif
+    rx_buffer[ep_num] = buffer;
+    rx_buffer_offset[ep_num] = 0;
+    rx_buffer_max[ep_num] = total_bytes;
+
+    // Enable receiving on this particular endpoint
+    usb_out_ctrl_write((1 << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | ep_num);
+#if DEBUG
+    uint16_t ep_en_mask = usb_out_enable_status_read();
+    int i;
+    for (i = 0; i < 16; i++) {
+      if ((!!(ep_en_mask & (1 << i))) ^ (!!(rx_buffer[i]))) {
+        if (rx_buffer[i] && usb_out_ev_pending_read() && (usb_out_status_read() & 0xf) == i)
+          continue;
+        fomu_error(__LINE__);
+      }
+    }
+#endif
+    dcd_int_enable(0);
+  }
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+
+static void handle_out(void)
+{
+  // An "OUT" transaction just completed so we have new data.
+  // (But only if we can accept the data)
+#if DEBUG
+  if (!usb_out_ev_pending_read())
+    fomu_error(__LINE__);
+  if (!usb_out_ev_enable_read())
+    fomu_error(__LINE__);
+#endif
+  process_rx();
+}
+
+static void handle_in(void)
+{
+#if DEBUG
+  if (!usb_in_ev_pending_read())
+    fomu_error(__LINE__);
+  if (!usb_in_ev_enable_read())
+    fomu_error(__LINE__);
+#endif
+  usb_in_ev_pending_write(usb_in_ev_pending_read());
+  process_tx();
+}
+
+static void handle_reset(void)
+{
+#if DEBUG
+  uint8_t setup_pending   = usb_setup_ev_pending_read() & usb_setup_ev_enable_read();
+  if (!(setup_pending & 2))
+    fomu_error(__LINE__);
+#endif
+  usb_setup_ev_pending_write(2);
+
+  // This event means a bus reset occurred.  Reset everything, and
+  // abandon any further processing.
+  dcd_reset();
+}
+
+static void handle_setup(void)
+{
+#if !DEBUG
+  uint8_t setup_packet_bfr[10];
+#endif
+
+#if DEBUG
+  uint8_t setup_pending   = usb_setup_ev_pending_read() & usb_setup_ev_enable_read();
+  if (!(setup_pending & 1))
+    fomu_error(__LINE__);
+#endif
+
+  // We got a SETUP packet.  Copy it to the setup buffer and clear
+  // the "pending" bit.
+  // Setup packets are always 8 bytes, plus two bytes of crc16.
+  uint32_t setup_length = 0;
+
+#if DEBUG
+  if (!(usb_setup_status_read() & (1 << CSR_USB_SETUP_STATUS_HAVE_OFFSET)))
+    fomu_error(__LINE__);
+#endif
+
+  while (usb_setup_status_read() & (1 << CSR_USB_SETUP_STATUS_HAVE_OFFSET)) {
+    uint8_t c = usb_setup_data_read();
+    if (setup_length < sizeof(setup_packet_bfr))
+      setup_packet_bfr[setup_length] = c;
+    setup_length++;
+  }
+
+  // If we have 10 bytes, that's a full SETUP packet plus CRC16.
+  // Otherwise, it was an RX error.
+  if (setup_length == 10) {
+    dcd_event_setup_received(0, setup_packet_bfr, true);
+  }
+#if DEBUG
+  else {
+    fomu_error(__LINE__);
+  }
+#endif
+
+  usb_setup_ev_pending_write(1);
+}
+void hal_dcd_isr(uint8_t rhport)
+{
+  (void)rhport;
+  uint8_t next_ev;
+  while ((next_ev = usb_next_ev_read())) {
+    switch (next_ev) {
+    case 1 << CSR_USB_NEXT_EV_IN_OFFSET:
+      handle_in();
+      break;
+    case 1 << CSR_USB_NEXT_EV_OUT_OFFSET:
+      handle_out();
+      break;
+    case 1 << CSR_USB_NEXT_EV_SETUP_OFFSET:
+      handle_setup();
+      break;
+    case 1 << CSR_USB_NEXT_EV_RESET_OFFSET:
+      handle_reset();
+      break;
+    }
+  }
+}
+
+#endif
diff --git a/src/portable/nxp/lpc18_43/hal_lpc18_43.c b/src/portable/valentyusb/eptri/dcd_eptri.h
index 3f4e9c23d..0fa6ecc64 100644
--- a/src/portable/nxp/lpc18_43/hal_lpc18_43.c
+++ b/src/portable/valentyusb/eptri/dcd_eptri.h
@@ -24,39 +24,16 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "tusb.h"
+#ifndef _TUSB_DCD_VALENTYUSB_EPTRI_H_
+#define _TUSB_DCD_VALENTYUSB_EPTRI_H_
 
-#if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX)
-
-#include "chip.h"
-
-extern void hal_dcd_isr(uint8_t rhport);
-extern void hal_hcd_isr(uint8_t hostid);
-
-#if CFG_TUSB_RHPORT0_MODE
-void USB0_IRQHandler(void)
-{
-  #if TUSB_OPT_HOST_ENABLED
-    hal_hcd_isr(0);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(0);
-  #endif
-}
+#include "common/tusb_common.h"
+#ifdef __cplusplus
+ extern "C" {
 #endif
 
-#if CFG_TUSB_RHPORT1_MODE
-void USB1_IRQHandler(void)
-{
-  #if TUSB_OPT_HOST_ENABLED
-    hal_hcd_isr(1);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(1);
-  #endif
-}
+#ifdef __cplusplus
+ }
 #endif
 
-#endif
+#endif /* _TUSB_DCD_VALENTYUSB_EPTRI_H_ */
diff --git a/src/portable/valentyusb/eptri/hal_eptri.c b/src/portable/valentyusb/eptri/hal_eptri.c
new file mode 100644
index 000000000..72453affa
--- /dev/null
+++ b/src/portable/valentyusb/eptri/hal_eptri.c
@@ -0,0 +1,33 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "common/tusb_common.h"
+
+#if (CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI)
+
+// No HAL-specific stuff here!
+
+#endif