diff options
| author | hathach <[email protected]> | 2024-11-21 10:15:30 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2024-11-21 10:22:09 +0700 |
| commit | fa523a5682d8dc91cc1c7a63475623743e37ac83 (patch) | |
| tree | bf479ba344d21dff4b6bd761584bc500a188e651 /src/portable | |
| parent | 2571889061f70b9fd425ee4e4174018bf07c5309 (diff) | |
make sure usb buffer occupies whole cache line when DCACHE is enabled for msc,cdc,hid
HIL enable device DMA for p4
Diffstat (limited to 'src/portable')
| -rw-r--r-- | src/portable/synopsys/dwc2/dcd_dwc2.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 363c77761..f2eb80e12 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -58,11 +58,9 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) typedef struct { - CFG_TUD_MEM_ALIGN union { - uint32_t setup_packet[2]; -#if CFG_TUD_MEM_DCACHE_ENABLE - uint8_t setup_packet_cache_padding[CFG_TUD_MEM_DCACHE_LINE_SIZE]; -#endif + union { + CFG_TUD_MEM_ALIGN uint32_t setup_packet[2]; + TUD_DCACHE_PADDING; }; // EP0 transfers are limited to 1 packet - larger sizes has to be split |