diff options
| author | hathach <[email protected]> | 2024-11-14 13:26:11 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2024-11-14 13:26:11 +0700 |
| commit | daef846aa73dc2b8edf5e072832833a6ae68b42a (patch) | |
| tree | 4bece2c6afc2c05c5b56ce896038828ae3c2a242 /src/tusb_option.h | |
| parent | 0569188aed17d19d5954f1e1b911e989814ec93d (diff) | |
rename CFG_TUD_DWC2_DMA to CFG_TUD_DWC2_DMA_ENABLE
Diffstat (limited to 'src/tusb_option.h')
| -rw-r--r-- | src/tusb_option.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/tusb_option.h b/src/tusb_option.h index e9b6a5806..6257a87ba 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -252,8 +252,8 @@ // (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable. // For example, on Cortex-M7 the MPU region can be configured as normal // non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0. -#ifndef CFG_TUD_DWC2_DMA - #define CFG_TUD_DWC2_DMA 0 +#ifndef CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUD_DWC2_DMA_ENABLE 0 #endif // Enable DWC2 Slave mode for host |