diff options
| author | hathach <[email protected]> | 2024-08-17 19:06:19 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2024-08-17 19:06:19 +0700 |
| commit | 123830c1f00813d86d0405dc7a5624ccb1220a31 (patch) | |
| tree | 1025504277fa703b601c8ac90c07c7142548915e /src | |
| parent | a6bee747b6f550e4fdb144c7db4aad70fee5ac69 (diff) | |
remove unused register def
Diffstat (limited to 'src')
| -rw-r--r-- | src/portable/mentor/musb/musb_type.h | 1536 |
1 files changed, 30 insertions, 1506 deletions
diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index 08f26edbd..619eb0108 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -262,9 +262,37 @@ typedef struct TU_ATTR_PACKED { //------------- Non-Indexed Endpoint CSRs -------------// // TI tm4c can access this directly, but should use indexed_csr for portability musb_ep_csr_t abs_csr[16]; // 0x100-0x1FF: EP0-15 CSR + + //------------- DMA -------------// + __IO uint8_t dma_intr; // 0x200: DMA_INTR + __R uint8_t rsv_0x201_0x203[3]; // 0x201-0x203: Reserved + struct { + __IO uint16_t cntl; // 0x204: DMA_CNTL + __IO uint16_t rsv_0x206; // 0x206: Reserved + __IO uint32_t addr; // 0x208: DMA_ADDR + __IO uint32_t count; // 0x20C: DMA_COUNT + __IO uint32_t rsv_0x210; // 0x210: Reserved + }dma[8]; + __R uint32_t rsv_0x284_0x2FF[31]; // 0x284-0x2FF: Reserved + + //------------- Extended -------------// + __R uint32_t rsv_0x300; // 0x300: Reserved + struct { + __IO uint16_t count; // 0x304: REQ_PACKET_COUNT + __R uint16_t rsv_0x306; // 0x306: Reserved + }req_packet[15]; + + __IO uint16_t rx_doulbe_packet_disable; // 0x340: RX_DOUBLE_PACKET_DISABLE + __IO uint16_t tx_double_packet_disable; // 0x342: TX_DOUBLE_PACKET_DISABLE + + __IO uint16_t chirp_timeout; // 0x344: CHIRP_TIMEOUT + __IO uint16_t hs_to_utm; // 0x346: HS_TO_UTM delay + __IO uint16_t hs_timeout_adder; // 0x348: HS_TIMEOUT_ADDER + + __R uint8_t rsv_34A_34f[6]; // 0x34A-0x34F: Reserved } musb_regs_t; -TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x200, "size is not correct"); +TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x350, "size is not correct"); //--------------------------------------------------------------------+ // Helper @@ -568,14 +596,6 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_COUNT0 register. -// -//***************************************************************************** -#define USB_COUNT0_COUNT_M 0x007F // FIFO Count -#define USB_COUNT0_COUNT_S 0 - -//***************************************************************************** -// // The following are defines for the bit fields in the USB_O_TYPE0 register. // //***************************************************************************** @@ -594,14 +614,6 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXMAXP1 register. -// -//***************************************************************************** -#define USB_TXMAXP1_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP1_MAXLOAD_S 0 - -//***************************************************************************** -// // The following are defines for the bit fields in the USB_O_TXCSRL1 register. // //***************************************************************************** @@ -632,14 +644,6 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_RXMAXP1 register. -// -//***************************************************************************** -#define USB_RXMAXP1_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP1_MAXLOAD_S 0 - -//***************************************************************************** -// // The following are defines for the bit fields in the USB_O_RXCSRL1 register. // //***************************************************************************** @@ -669,16 +673,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ #define USB_RXCSRH1_DMAMOD 0x0008 // DMA Request Mode #define USB_RXCSRH1_DTWE 0x0004 // Data Toggle Write Enable #define USB_RXCSRH1_DT 0x0002 // Data Toggle -#define USB_RXCSRH1_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. -// -//***************************************************************************** -#define USB_RXCOUNT1_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT1_COUNT_S 0 +#define USB_RXCSRH1_INCOMPRX 0x0001 // Incomplete RX Transmission Status //***************************************************************************** // @@ -740,896 +735,6 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXMAXP2 register. -// -//***************************************************************************** -#define USB_TXMAXP2_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL2 register. -// -//***************************************************************************** -#define USB_TXCSRL2_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL2_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL2_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL2_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL2_STALL 0x0010 // Send STALL -#define USB_TXCSRL2_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL2_ERROR 0x0004 // Error -#define USB_TXCSRL2_UNDRN 0x0004 // Underrun -#define USB_TXCSRL2_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL2_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH2 register. -// -//***************************************************************************** -#define USB_TXCSRH2_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH2_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH2_MODE 0x0020 // Mode -#define USB_TXCSRH2_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH2_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH2_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH2_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH2_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP2 register. -// -//***************************************************************************** -#define USB_RXMAXP2_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL2 register. -// -//***************************************************************************** -#define USB_RXCSRL2_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL2_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL2_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL2_STALL 0x0020 // Send STALL -#define USB_RXCSRL2_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL2_DATAERR 0x0008 // Data Error -#define USB_RXCSRL2_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL2_ERROR 0x0004 // Error -#define USB_RXCSRL2_OVER 0x0004 // Overrun -#define USB_RXCSRL2_FULL 0x0002 // FIFO Full -#define USB_RXCSRL2_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH2 register. -// -//***************************************************************************** -#define USB_RXCSRH2_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH2_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH2_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH2_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH2_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH2_PIDERR 0x0010 // PID Error -#define USB_RXCSRH2_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH2_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH2_DT 0x0002 // Data Toggle -#define USB_RXCSRH2_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. -// -//***************************************************************************** -#define USB_RXCOUNT2_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT2_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE2 register. -// -//***************************************************************************** -#define USB_TXTYPE2_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE2_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE2_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE2_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE2_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE2_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE2_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE2_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE2_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE2_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE2_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL2_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL2_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL2_NAKLMT_S 0 -#define USB_TXINTERVAL2_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE2 register. -// -//***************************************************************************** -#define USB_RXTYPE2_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE2_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE2_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE2_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE2_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE2_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE2_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE2_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE2_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE2_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE2_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL2_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL2_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL2_TXPOLL_S 0 -#define USB_RXINTERVAL2_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP3 register. -// -//***************************************************************************** -#define USB_TXMAXP3_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL3 register. -// -//***************************************************************************** -#define USB_TXCSRL3_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL3_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL3_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL3_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL3_STALL 0x0010 // Send STALL -#define USB_TXCSRL3_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL3_ERROR 0x0004 // Error -#define USB_TXCSRL3_UNDRN 0x0004 // Underrun -#define USB_TXCSRL3_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL3_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH3 register. -// -//***************************************************************************** -#define USB_TXCSRH3_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH3_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH3_MODE 0x0020 // Mode -#define USB_TXCSRH3_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH3_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH3_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH3_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH3_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP3 register. -// -//***************************************************************************** -#define USB_RXMAXP3_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL3 register. -// -//***************************************************************************** -#define USB_RXCSRL3_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL3_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL3_STALL 0x0020 // Send STALL -#define USB_RXCSRL3_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL3_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL3_DATAERR 0x0008 // Data Error -#define USB_RXCSRL3_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL3_ERROR 0x0004 // Error -#define USB_RXCSRL3_OVER 0x0004 // Overrun -#define USB_RXCSRL3_FULL 0x0002 // FIFO Full -#define USB_RXCSRL3_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH3 register. -// -//***************************************************************************** -#define USB_RXCSRH3_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH3_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH3_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH3_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH3_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH3_PIDERR 0x0010 // PID Error -#define USB_RXCSRH3_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH3_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH3_DT 0x0002 // Data Toggle -#define USB_RXCSRH3_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. -// -//***************************************************************************** -#define USB_RXCOUNT3_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT3_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE3 register. -// -//***************************************************************************** -#define USB_TXTYPE3_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE3_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE3_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE3_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE3_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE3_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE3_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE3_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE3_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE3_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE3_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL3_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL3_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL3_TXPOLL_S 0 -#define USB_TXINTERVAL3_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE3 register. -// -//***************************************************************************** -#define USB_RXTYPE3_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE3_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE3_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE3_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE3_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE3_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE3_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE3_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE3_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE3_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE3_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL3_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL3_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL3_TXPOLL_S 0 -#define USB_RXINTERVAL3_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP4 register. -// -//***************************************************************************** -#define USB_TXMAXP4_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL4 register. -// -//***************************************************************************** -#define USB_TXCSRL4_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL4_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL4_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL4_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL4_STALL 0x0010 // Send STALL -#define USB_TXCSRL4_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL4_ERROR 0x0004 // Error -#define USB_TXCSRL4_UNDRN 0x0004 // Underrun -#define USB_TXCSRL4_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL4_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH4 register. -// -//***************************************************************************** -#define USB_TXCSRH4_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH4_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH4_MODE 0x0020 // Mode -#define USB_TXCSRH4_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH4_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH4_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH4_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH4_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP4 register. -// -//***************************************************************************** -#define USB_RXMAXP4_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL4 register. -// -//***************************************************************************** -#define USB_RXCSRL4_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL4_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL4_STALL 0x0020 // Send STALL -#define USB_RXCSRL4_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL4_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL4_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL4_DATAERR 0x0008 // Data Error -#define USB_RXCSRL4_OVER 0x0004 // Overrun -#define USB_RXCSRL4_ERROR 0x0004 // Error -#define USB_RXCSRL4_FULL 0x0002 // FIFO Full -#define USB_RXCSRL4_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH4 register. -// -//***************************************************************************** -#define USB_RXCSRH4_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH4_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH4_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH4_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH4_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH4_PIDERR 0x0010 // PID Error -#define USB_RXCSRH4_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH4_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH4_DT 0x0002 // Data Toggle -#define USB_RXCSRH4_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. -// -//***************************************************************************** -#define USB_RXCOUNT4_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE4 register. -// -//***************************************************************************** -#define USB_TXTYPE4_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE4_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE4_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE4_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE4_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE4_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE4_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE4_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE4_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE4_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE4_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL4_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL4_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL4_NAKLMT_S 0 -#define USB_TXINTERVAL4_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE4 register. -// -//***************************************************************************** -#define USB_RXTYPE4_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE4_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE4_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE4_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE4_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE4_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE4_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE4_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE4_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE4_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE4_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL4_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL4_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL4_NAKLMT_S 0 -#define USB_RXINTERVAL4_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP5 register. -// -//***************************************************************************** -#define USB_TXMAXP5_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL5 register. -// -//***************************************************************************** -#define USB_TXCSRL5_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL5_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL5_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL5_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL5_STALL 0x0010 // Send STALL -#define USB_TXCSRL5_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL5_ERROR 0x0004 // Error -#define USB_TXCSRL5_UNDRN 0x0004 // Underrun -#define USB_TXCSRL5_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL5_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH5 register. -// -//***************************************************************************** -#define USB_TXCSRH5_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH5_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH5_MODE 0x0020 // Mode -#define USB_TXCSRH5_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH5_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH5_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH5_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH5_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP5 register. -// -//***************************************************************************** -#define USB_RXMAXP5_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL5 register. -// -//***************************************************************************** -#define USB_RXCSRL5_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL5_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL5_STALL 0x0020 // Send STALL -#define USB_RXCSRL5_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL5_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL5_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL5_DATAERR 0x0008 // Data Error -#define USB_RXCSRL5_ERROR 0x0004 // Error -#define USB_RXCSRL5_OVER 0x0004 // Overrun -#define USB_RXCSRL5_FULL 0x0002 // FIFO Full -#define USB_RXCSRL5_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH5 register. -// -//***************************************************************************** -#define USB_RXCSRH5_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH5_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH5_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH5_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH5_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH5_PIDERR 0x0010 // PID Error -#define USB_RXCSRH5_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH5_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH5_DT 0x0002 // Data Toggle -#define USB_RXCSRH5_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. -// -//***************************************************************************** -#define USB_RXCOUNT5_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT5_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE5 register. -// -//***************************************************************************** -#define USB_TXTYPE5_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE5_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE5_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE5_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE5_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE5_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE5_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE5_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE5_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE5_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE5_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE5_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL5 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL5_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL5_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL5_NAKLMT_S 0 -#define USB_TXINTERVAL5_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE5 register. -// -//***************************************************************************** -#define USB_RXTYPE5_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE5_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE5_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE5_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE5_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE5_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE5_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE5_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE5_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE5_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE5_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE5_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL5 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL5_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL5_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL5_TXPOLL_S 0 -#define USB_RXINTERVAL5_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP6 register. -// -//***************************************************************************** -#define USB_TXMAXP6_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL6 register. -// -//***************************************************************************** -#define USB_TXCSRL6_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL6_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL6_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL6_STALL 0x0010 // Send STALL -#define USB_TXCSRL6_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL6_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL6_ERROR 0x0004 // Error -#define USB_TXCSRL6_UNDRN 0x0004 // Underrun -#define USB_TXCSRL6_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL6_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH6 register. -// -//***************************************************************************** -#define USB_TXCSRH6_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH6_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH6_MODE 0x0020 // Mode -#define USB_TXCSRH6_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH6_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH6_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH6_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH6_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP6 register. -// -//***************************************************************************** -#define USB_RXMAXP6_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL6 register. -// -//***************************************************************************** -#define USB_RXCSRL6_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL6_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL6_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL6_STALL 0x0020 // Send STALL -#define USB_RXCSRL6_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL6_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL6_DATAERR 0x0008 // Data Error -#define USB_RXCSRL6_ERROR 0x0004 // Error -#define USB_RXCSRL6_OVER 0x0004 // Overrun -#define USB_RXCSRL6_FULL 0x0002 // FIFO Full -#define USB_RXCSRL6_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH6 register. -// -//***************************************************************************** -#define USB_RXCSRH6_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH6_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH6_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH6_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH6_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH6_PIDERR 0x0010 // PID Error -#define USB_RXCSRH6_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH6_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH6_DT 0x0002 // Data Toggle -#define USB_RXCSRH6_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. -// -//***************************************************************************** -#define USB_RXCOUNT6_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE6 register. -// -//***************************************************************************** -#define USB_TXTYPE6_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE6_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE6_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE6_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE6_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE6_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE6_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE6_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE6_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE6_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE6_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL6_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL6_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL6_TXPOLL_S 0 -#define USB_TXINTERVAL6_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE6 register. -// -//***************************************************************************** -#define USB_RXTYPE6_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE6_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE6_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE6_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE6_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE6_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE6_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE6_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE6_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE6_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE6_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL6_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL6_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL6_NAKLMT_S 0 -#define USB_RXINTERVAL6_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP7 register. -// -//***************************************************************************** -#define USB_TXMAXP7_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL7 register. -// -//***************************************************************************** -#define USB_TXCSRL7_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL7_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL7_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL7_STALL 0x0010 // Send STALL -#define USB_TXCSRL7_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL7_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL7_ERROR 0x0004 // Error -#define USB_TXCSRL7_UNDRN 0x0004 // Underrun -#define USB_TXCSRL7_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL7_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH7 register. -// -//***************************************************************************** -#define USB_TXCSRH7_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH7_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH7_MODE 0x0020 // Mode -#define USB_TXCSRH7_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH7_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH7_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH7_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH7_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP7 register. -// -//***************************************************************************** -#define USB_RXMAXP7_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL7 register. -// -//***************************************************************************** -#define USB_RXCSRL7_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL7_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL7_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL7_STALL 0x0020 // Send STALL -#define USB_RXCSRL7_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL7_DATAERR 0x0008 // Data Error -#define USB_RXCSRL7_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL7_ERROR 0x0004 // Error -#define USB_RXCSRL7_OVER 0x0004 // Overrun -#define USB_RXCSRL7_FULL 0x0002 // FIFO Full -#define USB_RXCSRL7_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH7 register. -// -//***************************************************************************** -#define USB_RXCSRH7_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH7_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH7_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH7_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH7_PIDERR 0x0010 // PID Error -#define USB_RXCSRH7_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH7_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH7_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH7_DT 0x0002 // Data Toggle -#define USB_RXCSRH7_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. -// -//***************************************************************************** -#define USB_RXCOUNT7_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE7 register. -// -//***************************************************************************** -#define USB_TXTYPE7_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE7_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE7_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE7_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE7_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE7_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE7_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE7_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE7_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE7_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE7_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL7_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL7_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL7_NAKLMT_S 0 -#define USB_TXINTERVAL7_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE7 register. -// -//***************************************************************************** -#define USB_RXTYPE7_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE7_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE7_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE7_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE7_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE7_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE7_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE7_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE7_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE7_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE7_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL7_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL7_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL7_NAKLMT_S 0 -#define USB_RXINTERVAL7_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAINTR register. -// -//***************************************************************************** -#define USB_DMAINTR_CH7 0x0080 // Channel 7 DMA Interrupt -#define USB_DMAINTR_CH6 0x0040 // Channel 6 DMA Interrupt -#define USB_DMAINTR_CH5 0x0020 // Channel 5 DMA Interrupt -#define USB_DMAINTR_CH4 0x0010 // Channel 4 DMA Interrupt -#define USB_DMAINTR_CH3 0x0008 // Channel 3 DMA Interrupt -#define USB_DMAINTR_CH2 0x0004 // Channel 2 DMA Interrupt -#define USB_DMAINTR_CH1 0x0002 // Channel 1 DMA Interrupt -#define USB_DMAINTR_CH0 0x0001 // Channel 0 DMA Interrupt - -//***************************************************************************** -// // The following are defines for the bit fields in the USB_O_DMACTL0 register. // //***************************************************************************** @@ -1667,370 +772,6 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACTL1 register. -// -//***************************************************************************** -#define USB_DMACTL1_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL1_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL1_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL1_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL1_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL1_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL1_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL1_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL1_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL1_DIR 0x0002 // DMA Direction -#define USB_DMACTL1_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL1_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR1 register. -// -//***************************************************************************** -#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR1_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT1 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT1_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL2 register. -// -//***************************************************************************** -#define USB_DMACTL2_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL2_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL2_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL2_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL2_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL2_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL2_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL2_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL2_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL2_DIR 0x0002 // DMA Direction -#define USB_DMACTL2_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL2_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR2 register. -// -//***************************************************************************** -#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR2_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT2 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT2_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL3 register. -// -//***************************************************************************** -#define USB_DMACTL3_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL3_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL3_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL3_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL3_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL3_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL3_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL3_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL3_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL3_DIR 0x0002 // DMA Direction -#define USB_DMACTL3_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL3_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR3 register. -// -//***************************************************************************** -#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR3_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT3 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT3_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL4 register. -// -//***************************************************************************** -#define USB_DMACTL4_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL4_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL4_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL4_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL4_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL4_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL4_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL4_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL4_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL4_DIR 0x0002 // DMA Direction -#define USB_DMACTL4_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL4_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR4 register. -// -//***************************************************************************** -#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR4_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT4 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT4_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL5 register. -// -//***************************************************************************** -#define USB_DMACTL5_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL5_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL5_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL5_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL5_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL5_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL5_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL5_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL5_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL5_DIR 0x0002 // DMA Direction -#define USB_DMACTL5_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL5_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR5 register. -// -//***************************************************************************** -#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR5_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT5 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT5_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL6 register. -// -//***************************************************************************** -#define USB_DMACTL6_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL6_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL6_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL6_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL6_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL6_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL6_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL6_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL6_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL6_DIR 0x0002 // DMA Direction -#define USB_DMACTL6_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL6_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR6 register. -// -//***************************************************************************** -#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR6_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT6 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT6_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL7 register. -// -//***************************************************************************** -#define USB_DMACTL7_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL7_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL7_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL7_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL7_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL7_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL7_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL7_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL7_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL7_DIR 0x0002 // DMA Direction -#define USB_DMACTL7_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL7_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR7 register. -// -//***************************************************************************** -#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR7_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT7 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT7_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT1_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT1_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT2_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT2_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT3_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT3_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT4_COUNT_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT5_COUNT_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT5_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT6_COUNT_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT7_COUNT_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_RXDPKTBUFDIS_EP7 0x0080 // EP7 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP6 0x0040 // EP6 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP5 0x0020 // EP5 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP4 0x0010 // EP4 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP3 0x0008 // EP3 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP2 0x0004 // EP2 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP1 0x0002 // EP1 RX Double-Packet Buffer - // Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_TXDPKTBUFDIS_EP7 0x0080 // EP7 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP6 0x0040 // EP6 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP5 0x0020 // EP5 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP4 0x0010 // EP4 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP3 0x0008 // EP3 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP2 0x0004 // EP2 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP1 0x0002 // EP1 TX Double-Packet Buffer - // Disable - -//***************************************************************************** -// // The following are defines for the bit fields in the USB_O_CTO register. // //***************************************************************************** @@ -2054,223 +795,6 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ #define USB_HSBT_HSBT_M 0x000F // High Speed Timeout Adder #define USB_HSBT_HSBT_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMATTR register. -// -//***************************************************************************** -#define USB_LPMATTR_ENDPT_M 0xF000 // Endpoint -#define USB_LPMATTR_RMTWAK 0x0100 // Remote Wake -#define USB_LPMATTR_HIRD_M 0x00F0 // Host Initiated Resume Duration -#define USB_LPMATTR_LS_M 0x000F // Link State -#define USB_LPMATTR_LS_L1 0x0001 // Sleep State (L1) -#define USB_LPMATTR_ENDPT_S 12 -#define USB_LPMATTR_HIRD_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMCNTRL register. -// -//***************************************************************************** -#define USB_LPMCNTRL_NAK 0x0010 // LPM NAK -#define USB_LPMCNTRL_EN_M 0x000C // LPM Enable -#define USB_LPMCNTRL_EN_NONE 0x0000 // LPM and Extended transactions - // are not supported. In this case, - // the USB does not respond to LPM - // transactions and LPM - // transactions cause a timeout -#define USB_LPMCNTRL_EN_EXT 0x0004 // LPM is not supported but - // extended transactions are - // supported. In this case, the USB - // does respond to an LPM - // transaction with a STALL -#define USB_LPMCNTRL_EN_LPMEXT 0x000C // The USB supports LPM extended - // transactions. In this case, the - // USB responds with a NYET or an - // ACK as determined by the value - // of TXLPM and other conditions -#define USB_LPMCNTRL_RES 0x0002 // LPM Resume -#define USB_LPMCNTRL_TXLPM 0x0001 // Transmit LPM Transaction Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMIM register. -// -//***************************************************************************** -#define USB_LPMIM_ERR 0x0020 // LPM Error Interrupt Mask -#define USB_LPMIM_RES 0x0010 // LPM Resume Interrupt Mask -#define USB_LPMIM_NC 0x0008 // LPM NC Interrupt Mask -#define USB_LPMIM_ACK 0x0004 // LPM ACK Interrupt Mask -#define USB_LPMIM_NY 0x0002 // LPM NY Interrupt Mask -#define USB_LPMIM_STALL 0x0001 // LPM STALL Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMRIS register. -// -//***************************************************************************** -#define USB_LPMRIS_ERR 0x0020 // LPM Interrupt Status -#define USB_LPMRIS_RES 0x0010 // LPM Resume Interrupt Status -#define USB_LPMRIS_NC 0x0008 // LPM NC Interrupt Status -#define USB_LPMRIS_ACK 0x0004 // LPM ACK Interrupt Status -#define USB_LPMRIS_NY 0x0002 // LPM NY Interrupt Status -#define USB_LPMRIS_LPMST 0x0001 // LPM STALL Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMFADDR register. -// -//***************************************************************************** -#define USB_LPMFADDR_ADDR_M 0x007F // LPM Function Address -#define USB_LPMFADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPC register. -// -//***************************************************************************** -#define USB_EPC_PFLTACT_M 0x0300 // Power Fault Action -#define USB_EPC_PFLTACT_UNCHG 0x0000 // Unchanged -#define USB_EPC_PFLTACT_TRIS 0x0100 // Tristate -#define USB_EPC_PFLTACT_LOW 0x0200 // Low -#define USB_EPC_PFLTACT_HIGH 0x0300 // High -#define USB_EPC_PFLTAEN 0x0040 // Power Fault Action Enable -#define USB_EPC_PFLTSEN_HIGH 0x0020 // Power Fault Sense -#define USB_EPC_PFLTEN 0x0010 // Power Fault Input Enable -#define USB_EPC_EPENDE 0x0004 // EPEN Drive Enable -#define USB_EPC_EPEN_M 0x0003 // External Power Supply Enable - // Configuration -#define USB_EPC_EPEN_LOW 0x0000 // Power Enable Active Low -#define USB_EPC_EPEN_HIGH 0x0001 // Power Enable Active High -#define USB_EPC_EPEN_VBLOW 0x0002 // Power Enable High if VBUS Low - // (OTG only) -#define USB_EPC_EPEN_VBHIGH 0x0003 // Power Enable High if VBUS High - // (OTG only) - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCRIS register. -// -//***************************************************************************** -#define USB_EPCRIS_PF 0x0001 // USB Power Fault Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCIM register. -// -//***************************************************************************** -#define USB_EPCIM_PF 0x0001 // USB Power Fault Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCISC register. -// -//***************************************************************************** -#define USB_EPCISC_PF 0x0001 // USB Power Fault Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRRIS register. -// -//***************************************************************************** -#define USB_DRRIS_RESUME 0x0001 // RESUME Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRIM register. -// -//***************************************************************************** -#define USB_DRIM_RESUME 0x0001 // RESUME Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRISC register. -// -//***************************************************************************** -#define USB_DRISC_RESUME 0x0001 // RESUME Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_GPCS register. -// -//***************************************************************************** -#define USB_GPCS_DEVMOD_M 0x0007 // Device Mode -#define USB_GPCS_DEVMOD_OTG 0x0000 // Use USB0VBUS and USB0ID pin -#define USB_GPCS_DEVMOD_HOST 0x0002 // Force USB0VBUS and USB0ID low -#define USB_GPCS_DEVMOD_DEV 0x0003 // Force USB0VBUS and USB0ID high -#define USB_GPCS_DEVMOD_HOSTVBUS \ - 0x0004 // Use USB0VBUS and force USB0ID - // low -#define USB_GPCS_DEVMOD_DEVVBUS 0x0005 // Use USB0VBUS and force USB0ID - // high - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDC register. -// -//***************************************************************************** -#define USB_VDC_VBDEN 0x0001 // VBUS Droop Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCRIS register. -// -//***************************************************************************** -#define USB_VDCRIS_VD 0x0001 // VBUS Droop Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCIM register. -// -//***************************************************************************** -#define USB_VDCIM_VD 0x0001 // VBUS Droop Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCISC register. -// -//***************************************************************************** -#define USB_VDCISC_VD 0x0001 // VBUS Droop Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_PP register. -// -//***************************************************************************** -#define USB_PP_ECNT_M 0xFF00 // Endpoint Count -#define USB_PP_USB_M 0x00C0 // USB Capability -#define USB_PP_USB_DEVICE 0x0040 // DEVICE -#define USB_PP_USB_HOSTDEVICE 0x0080 // HOST -#define USB_PP_USB_OTG 0x00C0 // OTG -#define USB_PP_ULPI 0x0020 // ULPI Present -#define USB_PP_PHY 0x0010 // PHY Present -#define USB_PP_TYPE_M 0x000F // Controller Type -#define USB_PP_TYPE_0 0x0000 // The first-generation USB - // controller -#define USB_PP_TYPE_1 0x0001 // The second-generation USB - // controller revision -#define USB_PP_ECNT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_PC register. -// -//***************************************************************************** -#define USB_PC_ULPIEN 0x00010000 // ULPI Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CC register. -// -//***************************************************************************** -#define USB_CC_CLKEN 0x0200 // USB Clock Enable -#define USB_CC_CSD 0x0100 // Clock Source/Direction -#define USB_CC_CLKDIV_M 0x000F // PLL Clock Divisor -#define USB_CC_CLKDIV_S 0 - #ifdef __cplusplus } #endif |