Move interrupt handler into device driver, and rename the OPT_MCU_STM32 constants.

2 files changed, 84 insertions, 2 deletions

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 2b4eea4cb..5e8226563 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -103,7 +103,18 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED) && ((CFG_TUSB_MCU) == (OPT_MCU_STM32_FSDEV))
+#if (TUSB_OPT_DEVICE_ENABLED) && ( \
+    ((CFG_TUSB_MCU) == (OPT_MCU_STM32F0x0)) || ((CFG_TUSB_MCU) == (OPT_MCU_STM32F0x2)) || \
+        ((CFG_TUSB_MCU) == (OPT_MCU_STM32F0x8)) || \
+    ((CFG_TUSB_MCU) == (OPT_MCU_STM32F1x2)) || ((CFG_TUSB_MCU) == (OPT_MCU_STM32F1x3)) || \
+    ((CFG_TUSB_MCU) == (OPT_MCU_STM32F3x2)) || ((CFG_TUSB_MCU) == (OPT_MCU_STM32F3x3)) || \
+    ((CFG_TUSB_MCU) == (OPT_MCU_STM32L0x1)) || ((CFG_TUSB_MCU) == (OPT_MCU_STM32L0x2)) || \
+    ((CFG_TUSB_MCU) == (OPT_MCU_STM32L1x0)) || ((CFG_TUSB_MCU) == (OPT_MCU_STM32L1x1)) || \
+        ((CFG_TUSB_MCU) == (OPT_MCU_STM32L1x2))  || \
+    ((CFG_TUSB_MCU) == (OPT_MCU_STM32L4x2)) || ((CFG_TUSB_MCU) == (OPT_MCU_STM32L4x3)) || \
+    ((CFG_TUSB_MCU) == (OPT_MCU_STM32G1x1)) || ((CFG_TUSB_MCU) == (OPT_MCU_STM32G1x3)) || \
+        ((CFG_TUSB_MCU) == (OPT_MCU_STM32G1x4)) \
+    )
 
 // In order to reduce the dependance on HAL, we undefine this.
 // Some definitions are copied to our private include file.
@@ -778,5 +789,56 @@ static void dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
   }
 }
 
+
+// Interrupt handlers
+#if ((CFG_TUSB_MCU) == (OPT_MCU_STM32F0x0)) || ((CFG_TUSB_MCU) == (OPT_MCU_STM32F0x2)) || \
+       ((CFG_TUSB_MCU) == (OPT_MCU_STM32F0x8)) || \
+	  ((CFG_TUSB_MCU) == (OPT_MCU_STM32L0x1)) || ((CFG_TUSB_MCU) == (OPT_MCU_STM32L0x2))
+void USB_IRQHandler(void)
+{
+  dcd_fs_irqHandler();
+}
+
+#elif ((CFG_TUSB_MCU) == (OPT_MCU_STM32F1x2)) || ((CFG_TUSB_MCU) == (OPT_MCU_STM32F1x3))
+void USB_HP_IRQHandler(void)
+{
+  dcd_fs_irqHandler();
+}
+void USB_LP_IRQHandler(void)
+{
+  dcd_fs_irqHandler();
+}
+void USBWakeUp_IRQHandler(void)
+{
+  dcd_fs_irqHandler();
+}
+#elif((CFG_TUSB_MCU) == (OPT_MCU_STM32F3x2)) || ((CFG_TUSB_MCU) == (OPT_MCU_STM32F3x3))
+// USB defaults to using interrupts 19, 20, and 42 (based on SYSCFG_CFGR1.USB_IT_RMP)
+// FIXME: Do all three need to be handled, or just the LP one?
+// USB high-priority interrupt (Channel 19): Triggered only by a correct
+// transfer event for isochronous and double-buffer bulk transfer to reach
+// the highest possible transfer rate.
+void USB_HP_CAN_TX_IRQHandler(void)
+{
+  dcd_fs_irqHandler();
+}
+
+// USB low-priority interrupt (Channel 20): Triggered by all USB events
+// (Correct transfer, USB reset, etc.). The firmware has to check the
+// interrupt source before serving the interrupt.
+void USB_LP_CAN_RX0_IRQHandler(void)
+{
+  dcd_fs_irqHandler();
+}
+// USB wakeup interrupt (Channel 42): Triggered by the wakeup event from the USB
+// Suspend mode.
+void USBWakeUp_IRQHandler(void)
+{
+  dcd_fs_irqHandler();
+}
+#else
+#error Which IRQ handler do you need?
+#endif
+
 #endif
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 0cd462ed1..9ca4fc56f 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -51,9 +51,29 @@
 #define OPT_MCU_SAMD21        200 ///< MicroChip SAMD21

 #define OPT_MCU_SAMD51        201 ///< MicroChip SAMD51

 

+// ST Synopsis OTG devices

 #define OPT_MCU_STM32F4       300 ///< ST STM32F4

-#define OPT_MCU_STM32_FSDEV   301 ///< ST STM32F3

 #define OPT_MCU_STM32H7       302 ///< ST STM32H7

+// ST FSDEV Devices

+#define OPT_MCU_STM32F0x0     330 ///< ST STM32F0x0

+#define OPT_MCU_STM32F0x2     331 ///< ST STM32F0x2

+#define OPT_MCU_STM32F0x8     332 ///< ST STM32F0x8

+#define OPT_MCU_STM32F1x2     333 ///< ST STM32F1x2

+#define OPT_MCU_STM32F1x3     334 ///< ST STM32F1x3

+#define OPT_MCU_STM32F3x2     335 ///< ST STM32F3x2

+#define OPT_MCU_STM32F3x3     336 ///< ST STM32F3x3

+#define OPT_MCU_STM32L0x1     337 ///< ST STM32L3x1

+#define OPT_MCU_STM32L0x2     338 ///< ST STM32L3x2

+#define OPT_MCU_STM32L1x0     339 ///< ST STM32L1x0

+#define OPT_MCU_STM32L1x1     340 ///< ST STM32L1x1

+#define OPT_MCU_STM32L1x2     341 ///< ST STM32L1x2

+#define OPT_MCU_STM32L4x2     342 ///< ST STM32L4x2

+#define OPT_MCU_STM32L4x3     343 ///< ST STM32L4x3

+#define OPT_MCU_STM32G4x1     344 ///< ST STM32G4x1

+#define OPT_MCU_STM32G4x3     345 ///< ST STM32G4x3

+#define OPT_MCU_STM32G4x4     346 ///< ST STM32G4x4

+

+

 

 /** @} */