Merge pull request #3043 from hathach/hcd-close-ep

feat(host) add endpoint close API and feat(HIL) improvement 

19 files changed, 518 insertions, 393 deletions

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index efb672201..4d19adeb4 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -82,7 +82,7 @@ typedef struct {
 static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
 CFG_TUD_MEM_SECTION static cdcd_epbuf_t _cdcd_epbuf[CFG_TUD_CDC];
 
-static tud_cdc_configure_fifo_t _cdcd_fifo_cfg;
+static tud_cdc_configure_t _cdcd_cfg = TUD_CDC_CONFIGURE_DEFAULT();
 
 static bool _prep_out_transaction(uint8_t itf) {
   const uint8_t rhport = 0;
@@ -119,9 +119,9 @@ static bool _prep_out_transaction(uint8_t itf) {
 // APPLICATION API
 //--------------------------------------------------------------------+
 
-bool tud_cdc_configure_fifo(const tud_cdc_configure_fifo_t* cfg) {
-  TU_VERIFY(cfg);
-  _cdcd_fifo_cfg = (*cfg);
+bool tud_cdc_configure(const tud_cdc_configure_t* driver_cfg) {
+  TU_VERIFY(driver_cfg);
+  _cdcd_cfg = *driver_cfg;
   return true;
 }
 
@@ -175,7 +175,7 @@ void tud_cdc_n_read_flush(uint8_t itf) {
 //--------------------------------------------------------------------+
 uint32_t tud_cdc_n_write(uint8_t itf, const void* buffer, uint32_t bufsize) {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
+  uint16_t wr_count = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
 
   // flush if queue more than packet size
   if (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE
@@ -186,7 +186,7 @@ uint32_t tud_cdc_n_write(uint8_t itf, const void* buffer, uint32_t bufsize) {
     tud_cdc_n_write_flush(itf);
   }
 
-  return ret;
+  return wr_count;
 }
 
 uint32_t tud_cdc_n_write_flush(uint8_t itf) {
@@ -233,8 +233,6 @@ bool tud_cdc_n_write_clear(uint8_t itf) {
 //--------------------------------------------------------------------+
 void cdcd_init(void) {
   tu_memclr(_cdcd_itf, sizeof(_cdcd_itf));
-  tu_memclr(&_cdcd_fifo_cfg, sizeof(_cdcd_fifo_cfg));
-
   for (uint8_t i = 0; i < CFG_TUD_CDC; i++) {
     cdcd_interface_t* p_cdc = &_cdcd_itf[i];
 
@@ -249,10 +247,10 @@ void cdcd_init(void) {
     // Config RX fifo
     tu_fifo_config(&p_cdc->rx_ff, p_cdc->rx_ff_buf, TU_ARRAY_SIZE(p_cdc->rx_ff_buf), 1, false);
 
-    // Config TX fifo as overwritable at initialization and will be changed to non-overwritable
-    // if terminal supports DTR bit. Without DTR we do not know if data is actually polled by terminal.
-    // In this way, the most current data is prioritized.
-    tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true);
+    // TX fifo can be configured to change to overwritable if not connected (DTR bit not set). Without DTR we do not
+    // know if data is actually polled by terminal. This way the most current data is prioritized.
+    // Default: is overwritable
+    tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, _cdcd_cfg.tx_overwritabe_if_not_connected);
 
     #if OSAL_MUTEX_REQUIRED
     osal_mutex_t mutex_rd = osal_mutex_create(&p_cdc->rx_ff_mutex);
@@ -294,13 +292,13 @@ void cdcd_reset(uint8_t rhport) {
     cdcd_interface_t* p_cdc = &_cdcd_itf[i];
 
     tu_memclr(p_cdc, ITF_MEM_RESET_SIZE);
-    if (!_cdcd_fifo_cfg.rx_persistent) {
+    if (!_cdcd_cfg.rx_persistent) {
       tu_fifo_clear(&p_cdc->rx_ff);
     }
-    if (!_cdcd_fifo_cfg.tx_persistent) {
+    if (!_cdcd_cfg.tx_persistent) {
       tu_fifo_clear(&p_cdc->tx_ff);
     }
-    tu_fifo_set_overwritable(&p_cdc->tx_ff, true);
+    tu_fifo_set_overwritable(&p_cdc->tx_ff, _cdcd_cfg.tx_overwritabe_if_not_connected);
   }
 }
 
@@ -414,8 +412,12 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_requ
 
         p_cdc->line_state = (uint8_t) request->wValue;
 
-        // Disable fifo overwriting if DTR bit is set
-        tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
+        // If enabled: fifo overwriting is disabled if DTR bit is set and vice versa
+        if (_cdcd_cfg.tx_overwritabe_if_not_connected) {
+          tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
+        } else {
+          tu_fifo_set_overwritable(&p_cdc->tx_ff, false);
+        }
 
         TU_LOG_DRV("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
 
@@ -496,7 +498,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
       // xferred_bytes is multiple of EP Packet size and not zero
       if (!tu_fifo_count(&p_cdc->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE - 1)))) {
         if (usbd_edpt_claim(rhport, p_cdc->ep_in)) {
-          usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0);
+          TU_ASSERT(usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0));
         }
       }
     }
diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index 2d5ba2575..b653ebd74 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -48,14 +48,24 @@
 //--------------------------------------------------------------------+
 // Driver Configuration
 //--------------------------------------------------------------------+
-
 typedef struct TU_ATTR_PACKED {
-  uint8_t rx_persistent : 1; // keep rx fifo on bus reset or disconnect
-  uint8_t tx_persistent : 1; // keep tx fifo on bus reset or disconnect
-} tud_cdc_configure_fifo_t;
+  uint8_t rx_persistent : 1; // keep rx fifo data even with bus reset or disconnect
+  uint8_t tx_persistent : 1; // keep tx fifo data even with reset or disconnect
+  uint8_t tx_overwritabe_if_not_connected : 1; // if not connected, tx fifo can be overwritten
+} tud_cdc_configure_t;
+
+#define TUD_CDC_CONFIGURE_DEFAULT() { \
+  .rx_persistent = 0, \
+  .tx_persistent = 0, \
+  .tx_overwritabe_if_not_connected = 1, \
+}
+
+// Configure CDC driver behavior
+bool tud_cdc_configure(const tud_cdc_configure_t* driver_cfg);
 
-// Configure CDC FIFOs behavior
-bool tud_cdc_configure_fifo(tud_cdc_configure_fifo_t const* cfg);
+// Backward compatible
+#define tud_cdc_configure_fifo_t tud_cdc_configure_t
+#define tud_cdc_configure_fifo   tud_cdc_configure
 
 //--------------------------------------------------------------------+
 // Application API (Multiple Ports) i.e. CFG_TUD_CDC > 1
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 5f2dcabad..ecf002b09 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -916,8 +916,11 @@ bool tu_fifo_clear(tu_fifo_t *f)
                 Overwritable mode the fifo is set to
  */
 /******************************************************************************/
-bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable)
-{
+bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) {
+  if (f->overwritable == overwritable) {
+    return true;
+  }
+
   _ff_lock(f->mutex_wr);
   _ff_lock(f->mutex_rd);
 
diff --git a/src/device/usbd.c b/src/device/usbd.c
index fb5cec49d..9c381d5e0 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -561,8 +561,7 @@ static void usbd_reset(uint8_t rhport) {
 }
 
 bool tud_task_event_ready(void) {
-  // Skip if stack is not initialized
-  if (!tud_inited()) return false;
+  TU_VERIFY(tud_inited()); // Skip if stack is not initialized
   return !osal_queue_empty(_usbd_q);
 }
 
@@ -684,7 +683,9 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
 
       case USBD_EVENT_FUNC_CALL:
         TU_LOG_USBD("\r\n");
-        if (event.func_call.func) event.func_call.func(event.func_call.param);
+        if (event.func_call.func) {
+          event.func_call.func(event.func_call.param);
+        }
         break;
 
       case DCD_EVENT_SOF:
@@ -701,7 +702,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
 
 #if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
     // return if there is no more events, for application to run other background
-    if (osal_queue_empty(_usbd_q)) return;
+    if (osal_queue_empty(_usbd_q)) { return; }
 #endif
   }
 }
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 56b6fdb5d..aa9e9cf3b 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -165,6 +165,9 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
 // Open an endpoint
 bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc);
 
+// Close an endpoint
+bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr);
+
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index c87f058cd..e60db53da 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -52,21 +52,25 @@ enum {
 // Weak stubs: invoked if no strong implementation is available
 //--------------------------------------------------------------------+
 TU_ATTR_WEAK bool hcd_deinit(uint8_t rhport) {
-  (void) rhport;
-  return false;
+  (void) rhport; return false;
 }
 
 TU_ATTR_WEAK bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
-  (void) rhport;
-  (void) cfg_id;
-  (void) cfg_param;
+  (void) rhport; (void) cfg_id; (void) cfg_param;
   return false;
 }
 
+TU_ATTR_WEAK void tuh_enum_descriptor_device_cb(uint8_t daddr, const tusb_desc_device_t *desc_device) {
+  (void) daddr; (void) desc_device;
+}
+
+TU_ATTR_WEAK bool tuh_enum_descriptor_configuration_cb(uint8_t daddr, uint8_t cfg_index, const tusb_desc_configuration_t *desc_config) {
+  (void) daddr; (void) cfg_index; (void) desc_config;
+  return true;
+}
+
 TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
-  (void) rhport;
-  (void) eventid;
-  (void) in_isr;
+  (void) rhport; (void) eventid; (void) in_isr;
 }
 
 TU_ATTR_WEAK bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
@@ -126,6 +130,7 @@ typedef struct {
   uint8_t  i_manufacturer;
   uint8_t  i_product;
   uint8_t  i_serial;
+  uint8_t  bNumConfigurations;
 
   // Configuration Descriptor
   // uint8_t interface_count; // bNumInterfaces alias
@@ -230,7 +235,6 @@ static usbh_class_driver_t const usbh_class_drivers[] = {
 };
 
 enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
-enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
 // Additional class drivers implemented by application
 tu_static usbh_class_driver_t const * _app_driver = NULL;
@@ -516,7 +520,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
   // Loop until there is no more events in the queue
   while (1) {
     hcd_event_t event;
-    if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) return;
+    if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) { return; }
 
     switch (event.event_id) {
       case HCD_EVENT_DEVICE_ATTACH:
@@ -990,6 +994,12 @@ bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const* desc_ep) {
   return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, desc_ep);
 }
 
+bool tuh_edpt_close(uint8_t daddr, uint8_t ep_addr) {
+  TU_VERIFY(0 != tu_edpt_number(ep_addr)); // cannot close EP0
+  tuh_edpt_abort_xfer(daddr, ep_addr); // abort any pending transfer
+  return hcd_edpt_close(usbh_get_rhport(daddr), daddr, ep_addr);
+}
+
 bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) {
   usbh_device_t* dev = get_device(dev_addr);
   TU_VERIFY(dev);
@@ -1372,8 +1382,8 @@ enum {
   ENUM_CONFIG_DRIVER
 };
 
-static bool enum_request_set_addr(void);
-static bool _parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
+static bool enum_request_set_addr(tusb_desc_device_t const* desc_device);
+static bool enum_parse_configuration_desc (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
 static void enum_full_complete(void);
 
 // process device enumeration
@@ -1489,7 +1499,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
 #endif
 
     case ENUM_SET_ADDR:
-      enum_request_set_addr();
+      enum_request_set_addr((tusb_desc_device_t*) _usbh_epbuf.ctrl);
       break;
 
     case ENUM_GET_DEVICE_DESC: {
@@ -1523,6 +1533,9 @@ static void process_enumeration(tuh_xfer_t* xfer) {
       dev->i_manufacturer = desc_device->iManufacturer;
       dev->i_product = desc_device->iProduct;
       dev->i_serial = desc_device->iSerialNumber;
+      dev->bNumConfigurations = desc_device->bNumConfigurations;
+
+      tuh_enum_descriptor_device_cb(daddr, desc_device); // callback
 
       tuh_descriptor_get_string_langid(daddr, _usbh_epbuf.ctrl, CFG_TUH_ENUMERATION_BUFSIZE,
                                        process_enumeration, ENUM_GET_STRING_MANUFACTURER);
@@ -1574,8 +1587,8 @@ static void process_enumeration(tuh_xfer_t* xfer) {
 
     case ENUM_GET_9BYTE_CONFIG_DESC: {
       // Get 9-byte for total length
-      uint8_t const config_idx = CONFIG_NUM - 1;
-      TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n");
+      uint8_t const config_idx = 0;
+      TU_LOG_USBH("Get Configuration[%u] Descriptor (9 bytes)\r\n", config_idx);
       TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9,
                                                  process_enumeration, ENUM_GET_FULL_CONFIG_DESC),);
       break;
@@ -1585,25 +1598,32 @@ static void process_enumeration(tuh_xfer_t* xfer) {
       uint8_t const* desc_config = _usbh_epbuf.ctrl;
 
       // Use offsetof to avoid pointer to the odd/misaligned address
-      uint16_t const total_len = tu_le16toh(
-          tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)));
+      uint16_t const total_len = tu_le16toh(tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)));
 
       // TODO not enough buffer to hold configuration descriptor
       TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE,);
 
       // Get full configuration descriptor
-      uint8_t const config_idx = CONFIG_NUM - 1;
-      TU_LOG_USBH("Get Configuration[0] Descriptor\r\n");
+      uint8_t const config_idx = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+      TU_LOG_USBH("Get Configuration[%u] Descriptor\r\n", config_idx);
       TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, total_len,
                                                  process_enumeration, ENUM_SET_CONFIG),);
       break;
     }
 
-    case ENUM_SET_CONFIG:
-      // tuh_desc_configuration_cb(daddr, CONFIG_NUM-1, (const tusb_desc_configuration_t*) _usbh_epbuf.ctrl);
-
-      TU_ASSERT(tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER),);
+    case ENUM_SET_CONFIG: {
+      uint8_t config_idx = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+      if (tuh_enum_descriptor_configuration_cb(daddr, config_idx, (const tusb_desc_configuration_t*) _usbh_epbuf.ctrl)) {
+        TU_ASSERT(tuh_configuration_set(daddr, config_idx+1, process_enumeration, ENUM_CONFIG_DRIVER),);
+      } else {
+        config_idx++;
+        TU_ASSERT(config_idx < dev->bNumConfigurations,);
+        TU_LOG_USBH("Get Configuration[%u] Descriptor (9 bytes)\r\n", config_idx);
+        TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9,
+                                                   process_enumeration, ENUM_GET_FULL_CONFIG_DESC),);
+      }
       break;
+    }
 
     case ENUM_CONFIG_DRIVER: {
       TU_LOG_USBH("Device configured\r\n");
@@ -1613,7 +1633,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
 
       // Parse configuration & set up drivers
       // driver_open() must not make any usb transfer
-      TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_epbuf.ctrl),);
+      TU_ASSERT(enum_parse_configuration_desc(daddr, (tusb_desc_configuration_t*) _usbh_epbuf.ctrl),);
 
       // Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8)
       // Since driver can perform control transfer within its set_config, this is done asynchronously.
@@ -1624,14 +1644,11 @@ static void process_enumeration(tuh_xfer_t* xfer) {
     }
 
     default:
-      // stop enumeration if unknown state
-      enum_full_complete();
+      enum_full_complete(); // stop enumeration if unknown state
       break;
   }
 }
 
-
-
 static bool enum_new_device(hcd_event_t* event) {
   _dev0.rhport = event->rhport;
   _dev0.hub_addr = event->connection.hub_addr;
@@ -1701,9 +1718,7 @@ static uint8_t get_new_address(bool is_hub) {
   return 0; // invalid address
 }
 
-static bool enum_request_set_addr(void) {
-  tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl;
-
+static bool enum_request_set_addr(tusb_desc_device_t const* desc_device) {
   // Get new address
   uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
   TU_ASSERT(new_addr != 0);
@@ -1741,7 +1756,7 @@ static bool enum_request_set_addr(void) {
   return true;
 }
 
-static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) {
+static bool enum_parse_configuration_desc(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) {
   usbh_device_t* dev = get_device(dev_addr);
   uint16_t const total_len = tu_le16toh(desc_cfg->wTotalLength);
   uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + total_len;
@@ -1858,7 +1873,9 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) {
       TU_LOG_USBH("HUB address = %u is mounted\r\n", dev_addr);
     }else {
       // Invoke callback if available
-      if (tuh_mount_cb) tuh_mount_cb(dev_addr);
+      if (tuh_mount_cb) {
+        tuh_mount_cb(dev_addr);
+      }
     }
   }
 }
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 52b4f478c..4829a8183 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -33,6 +33,10 @@
 
 #include "common/tusb_common.h"
 
+#if CFG_TUH_MAX3421
+#include "portable/analog/max3421/hcd_max3421.h"
+#endif
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -100,10 +104,13 @@ typedef union {
 //--------------------------------------------------------------------+
 
 // Invoked when enumeration get device descriptor
-// TU_ATTR_WEAK void tuh_descriptor_device_cb(uint8_t daddr, const tusb_desc_device_t *desc_device);
+// Device is not ready to communicate yet, application can copy the descriptor if needed
+void tuh_enum_descriptor_device_cb(uint8_t daddr, const tusb_desc_device_t *desc_device);
 
 // Invoked when enumeration get configuration descriptor
-// TU_ATTR_WEAK void tuh_desc_configuration_cb(uint8_t daddr, uint8_t cfg_index, const tusb_desc_configuration_t *desc_config);
+// For multi-configuration device return false to skip, true to proceed with this configuration (may not be implemented yet)
+// Device is not ready to communicate yet, application can copy the descriptor if needed
+bool tuh_enum_descriptor_configuration_cb(uint8_t daddr, uint8_t cfg_index, const tusb_desc_configuration_t *desc_config);
 
 // Invoked when a device is mounted (configured)
 TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr);
@@ -155,8 +162,7 @@ bool tuh_inited(void);
 void tuh_task_ext(uint32_t timeout_ms, bool in_isr);
 
 // Task function should be called in main/rtos loop
-TU_ATTR_ALWAYS_INLINE static inline
-void tuh_task(void) {
+TU_ATTR_ALWAYS_INLINE static inline void tuh_task(void) {
   tuh_task_ext(UINT32_MAX, false);
 }
 
@@ -197,16 +203,14 @@ bool tuh_mounted(uint8_t daddr);
 bool tuh_connected(uint8_t daddr);
 
 // Check if device is suspended
-TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_suspended(uint8_t daddr) {
+TU_ATTR_ALWAYS_INLINE static inline bool tuh_suspended(uint8_t daddr) {
   // TODO implement suspend & resume on host
   (void) daddr;
   return false;
 }
 
 // Check if device is ready to communicate with
-TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_ready(uint8_t daddr) {
+TU_ATTR_ALWAYS_INLINE static inline bool tuh_ready(uint8_t daddr) {
   return tuh_mounted(daddr) && !tuh_suspended(daddr);
 }
 
@@ -227,6 +231,9 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer);
 // Open a non-control endpoint
 bool tuh_edpt_open(uint8_t daddr, tusb_desc_endpoint_t const * desc_ep);
 
+// Close a non-control endpoint, it will abort any pending transfer
+bool tuh_edpt_close(uint8_t daddr, uint8_t ep_addr);
+
 // Abort a queued transfer. Note: it can only abort transfer that has not been started
 // Return true if a queued transfer is aborted, false if there is no transfer to abort
 bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr);
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index c5e924266..3fbf950a4 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -253,28 +253,6 @@ static tuh_configure_max3421_t _tuh_cfg = {
 };
 
 //--------------------------------------------------------------------+
-// API: SPI transfer with MAX3421E
-// - spi_cs_api(), spi_xfer_api(), int_api(): must be implemented by application
-// - reg_read(), reg_write(): is implemented by this driver, can be used by application
-//--------------------------------------------------------------------+
-
-// API to control MAX3421 SPI CS
-extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
-
-// API to transfer data with MAX3421 SPI
-// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
-extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes);
-
-// API to enable/disable MAX3421 INTR pin interrupt
-extern void tuh_max3421_int_api(uint8_t rhport, bool enabled);
-
-// API to read MAX3421's register. Implemented by TinyUSB
-uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr);
-
-// API to write MAX3421's register. Implemented by TinyUSB
-bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr);
-
-//--------------------------------------------------------------------+
 // SPI Commands and Helper
 //--------------------------------------------------------------------+
 
@@ -632,6 +610,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
   if (daddr == 0 && ep_num == 0) {
     ep = &_hcd_data.ep[0];
   }else {
+    if (NULL != find_ep_not_addr0(daddr, ep_num, ep_dir)) {
+      return false; // endpoint already opened
+    }
     ep = allocate_ep();
     TU_ASSERT(ep);
     ep->daddr = daddr;
@@ -645,6 +626,21 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
   return true;
 }
 
+bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  (void) rhport;
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr);
+  max3421_ep_t * ep = find_ep_not_addr0(daddr, ep_num, ep_dir);
+
+  if (!ep) {
+    return false; // not opened
+  }
+
+  tu_memclr(ep, sizeof(max3421_ep_t));
+
+  return true;
+}
+
 /* The microcontroller repeatedly writes the SNDFIFO register R2 to load the FIFO with up to 64 data bytes.
  * Then the microcontroller writes the SNDBC register, which this does three things:
  * 1. Tells the MAX3421E SIE (Serial Interface Engine) how many bytes in the FIFO to send.
diff --git a/src/portable/analog/max3421/hcd_max3421.h b/src/portable/analog/max3421/hcd_max3421.h
new file mode 100644
index 000000000..4631fa21a
--- /dev/null
+++ b/src/portable/analog/max3421/hcd_max3421.h
@@ -0,0 +1,63 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+#ifndef TUSB_HCD_MAX3421_H
+#define TUSB_HCD_MAX3421_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// SPI transfer API with MAX3421E are implemented by application
+// - spi_cs_api(), spi_xfer_api(), int_api()
+//--------------------------------------------------------------------+
+
+// API to control MAX3421 SPI CS
+extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
+
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes);
+
+// API to enable/disable MAX3421 INTR pin interrupt
+extern void tuh_max3421_int_api(uint8_t rhport, bool enabled);
+
+//--------------------------------------------------------------------+
+// API for read/write MAX3421 registers
+// are implemented by this driver, can be used by application
+//--------------------------------------------------------------------+
+
+// API to read MAX3421's register. Implemented by TinyUSB
+uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr);
+
+// API to write MAX3421's register. Implemented by TinyUSB
+bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 01bbf62bf..292a352fb 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -62,8 +62,7 @@
 #define QHD_MAX      (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB)
 #define QTD_MAX      QHD_MAX
 
-typedef struct
-{
+typedef struct {
   ehci_link_t period_framelist[FRAMELIST_SIZE];
 
   // TODO only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
@@ -139,6 +138,12 @@ static ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
 static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd);
 static void qhd_remove_qtd(ehci_qhd_t *qhd);
+TU_ATTR_ALWAYS_INLINE static inline bool qhd_is_periodic(ehci_qhd_t const *qhd) {
+  return qhd->int_smask != 0;
+}
+TU_ATTR_ALWAYS_INLINE static inline uint8_t qhd_ep_addr(ehci_qhd_t const *qhd) {
+  return tu_edpt_addr(qhd->ep_number, qhd->pid);
+}
 
 TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr);
 TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_find_free (void);
@@ -146,9 +151,10 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
 
 TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms);
 TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport);
-TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
 TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next (ehci_link_t const *p_link);
-static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr);
+TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *entry, uint8_t type);
+TU_ATTR_ALWAYS_INLINE static inline void list_remove(ehci_link_t* head, ehci_link_t* prev, ehci_qhd_t* qhd);
+static void list_remove_qhd_by_addr(ehci_link_t *list_head, uint8_t dev_addr, uint8_t ep_addr);
 
 static void ehci_disable_schedule(ehci_registers_t* regs, bool is_period) {
   // maybe have a timeout for status
@@ -175,15 +181,12 @@ static void ehci_enable_schedule(ehci_registers_t* regs, bool is_period) {
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
-
-uint32_t hcd_frame_number(uint8_t rhport)
-{
+uint32_t hcd_frame_number(uint8_t rhport) {
   (void) rhport;
   return (ehci_data.uframe_number + ehci_data.regs->frame_index) >> 3;
 }
 
-void hcd_port_reset(uint8_t rhport)
-{
+void hcd_port_reset(uint8_t rhport) {
   (void) rhport;
 
   ehci_registers_t* regs = ehci_data.regs;
@@ -204,8 +207,7 @@ void hcd_port_reset(uint8_t rhport)
   regs->portsc = portsc;
 }
 
-void hcd_port_reset_end(uint8_t rhport)
-{
+void hcd_port_reset_end(uint8_t rhport) {
   (void) rhport;
   ehci_registers_t* regs = ehci_data.regs;
 
@@ -221,32 +223,29 @@ void hcd_port_reset_end(uint8_t rhport)
   regs->portsc = portsc;
 }
 
-bool hcd_port_connect_status(uint8_t rhport)
-{
+bool hcd_port_connect_status(uint8_t rhport) {
   (void) rhport;
   return ehci_data.regs->portsc_bm.current_connect_status;
 }
 
-tusb_speed_t hcd_port_speed_get(uint8_t rhport)
-{
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
   (void) rhport;
   return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed
 }
 
 // Close all opened endpoint belong to this device
-void hcd_device_close(uint8_t rhport, uint8_t daddr)
-{
+void hcd_device_close(uint8_t rhport, uint8_t daddr) {
   // skip dev0
   if (daddr == 0) {
     return;
   }
 
-  // Remove from async list
-  list_remove_qhd_by_daddr((ehci_link_t *) list_get_async_head(rhport), daddr);
+  // Remove from async list all endpoints of this device
+  list_remove_qhd_by_addr((ehci_link_t *) list_get_async_head(rhport), daddr, TUSB_INDEX_INVALID_8);
 
-  // Remove from all interval period list
-  for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) {
-    list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr);
+  // Remove from all interval period list of this device
+  for (uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) {
+    list_remove_qhd_by_addr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr, TUSB_INDEX_INVALID_8);
   }
 
   // Async doorbell (EHCI 4.8.2 for operational details)
@@ -358,12 +357,10 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
 }
 
 #if 0
-static void ehci_stop(uint8_t rhport)
-{
+static void ehci_stop(uint8_t rhport) {
   (void) rhport;
 
   ehci_registers_t* regs = ehci_data.regs;
-
   regs->command_bm.run_stop = 0;
 
   // USB Spec: controller has to stop within 16 uframe = 2 frames
@@ -375,41 +372,44 @@ static void ehci_stop(uint8_t rhport)
 // Endpoint API
 //--------------------------------------------------------------------+
 
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
-{
-  (void) rhport;
-
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
   // TODO not support ISO yet
   TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
 
   //------------- Prepare Queue Head -------------//
-  ehci_qhd_t *p_qhd = (ep_desc->bEndpointAddress == 0) ? qhd_control(dev_addr) : qhd_find_free();
+  ehci_qhd_t *p_qhd;
+  if (ep_desc->bEndpointAddress == 0) {
+    p_qhd = qhd_control(dev_addr);
+  } else {
+    TU_VERIFY(NULL == qhd_get_from_addr(dev_addr, ep_desc->bEndpointAddress)); // ep not opened yet
+    p_qhd = qhd_find_free();
+  }
   TU_ASSERT(p_qhd);
-
   qhd_init(p_qhd, dev_addr, ep_desc);
 
-  // control of dev0 is always present as async head
-  if ( dev_addr == 0 ) return true;
+  // control of dev0 always exists as async head
+  if (dev_addr == 0) {
+    return true;
+  }
 
   // Insert to list
   ehci_link_t * list_head = NULL;
-
-  switch (ep_desc->bmAttributes.xfer)
-  {
+  switch (ep_desc->bmAttributes.xfer) {
     case TUSB_XFER_CONTROL:
     case TUSB_XFER_BULK:
-      list_head = (ehci_link_t*) list_get_async_head(rhport);
-    break;
+      list_head = (ehci_link_t *) list_get_async_head(rhport);
+      break;
 
     case TUSB_XFER_INTERRUPT:
       list_head = list_get_period_head(rhport, p_qhd->interval_ms);
-    break;
+      break;
 
     case TUSB_XFER_ISOCHRONOUS:
       // TODO iso is not supported
-    break;
+      break;
 
-    default: break;
+    default:
+      break;
   }
   TU_ASSERT(list_head);
 
@@ -421,8 +421,23 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   return true;
 }
 
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
-{
+bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  ehci_qhd_t* qhd = qhd_get_from_addr(daddr, ep_addr);
+  TU_VERIFY(qhd != NULL);
+
+  ehci_link_t * list_head;
+  if (qhd_is_periodic(qhd)) {
+    // interrupt endpoint
+    list_head = list_get_period_head(rhport, qhd->interval_ms);;
+  } else {
+    list_head = (ehci_link_t *) list_get_async_head(rhport);
+  }
+
+  list_remove_qhd_by_addr(list_head, daddr, ep_addr);
+  return true;
+}
+
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
   (void) rhport;
 
   ehci_qhd_t* qhd = &ehci_data.control[dev_addr].qhd;
@@ -444,14 +459,14 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   return true;
 }
 
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
-{
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   ehci_qhd_t* qhd = qhd_get_from_addr(dev_addr, ep_addr);
+  TU_VERIFY(qhd != NULL);
   ehci_qtd_t* qtd;
 
   if (epnum == 0) {
@@ -540,8 +555,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
 // This isr mean it is safe to modify previously removed queue head from async list.
 // In tinyusb, queue head is only removed when device is unplugged.
 TU_ATTR_ALWAYS_INLINE static inline
-void async_advance_isr(uint8_t rhport)
-{
+void async_advance_isr(uint8_t rhport) {
   (void) rhport;
 
   ehci_qhd_t *qhd_pool = ehci_data.qhd_pool;
@@ -612,8 +626,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-void proccess_async_xfer_isr(ehci_qhd_t * const list_head)
-{
+void proccess_async_xfer_isr(ehci_qhd_t * const list_head) {
   ehci_qhd_t *qhd = list_head;
 
   do {
@@ -623,8 +636,7 @@ void proccess_async_xfer_isr(ehci_qhd_t * const list_head)
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms)
-{
+void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms) {
   uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u);
   ehci_link_t next_link = *list_get_period_head(rhport, interval_ms);
 
@@ -726,51 +738,55 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next(ehci_link_t const *p_
   return (ehci_link_t*) tu_align32(p_link->address);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type)
-{
-  new->address = current->address;
-  current->address = ((uint32_t) new) | (new_type << 1);
+TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *entry, uint8_t type) {
+  entry->address = current->address;
+  current->address = ((uint32_t) entry) | (type << 1);
+}
+
+// Remove a queue head from the list.
+// Per EHCI 4.8.2 the removed qhd's next is linked to list head (which always reachable by Host Controller)
+// TODO support iTD/siTD
+TU_ATTR_ALWAYS_INLINE static inline void list_remove(ehci_link_t* head, ehci_link_t* prev, ehci_qhd_t* qhd) {
+  // TODO deactivate all TD, wait for QHD to inactive before removal
+  prev->address = qhd->next.address;
+
+  // link the removed qhd's next to list head
+  qhd->next.address = ((uint32_t) head) | (EHCI_QTYPE_QHD << 1);
+
+  if (qhd_is_periodic(qhd)) {
+    // period list queue element is guarantee to be free in the next frame (1 ms)
+    qhd->used = 0;
+  } else {
+    // async list use async advance handshake. Mark as removing, will completely re-usable when async advance isr occurs
+    qhd->removing = 1;
+  }
+
+  hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
+  hcd_dcache_clean(prev, sizeof(ehci_qhd_t));
 }
 
-// Remove all queue head belong to this device address
-static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) {
-  ehci_link_t* prev = list_head;
+// Remove queue head belong to this device address
+static void list_remove_qhd_by_addr(ehci_link_t *list_head, uint8_t dev_addr, uint8_t ep_addr) {
+  ehci_link_t *prev = list_head;
 
   while (prev && !prev->terminate) {
-    ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev);
+    ehci_qhd_t *qhd = (ehci_qhd_t *) (uintptr_t) list_next(prev);
 
     // done if loop back to head
-    if ( (uintptr_t) qhd == (uintptr_t) list_head) {
+    if ((uintptr_t) qhd == (uintptr_t) list_head) {
       break;
     }
 
-    if ( qhd->dev_addr == dev_addr ) {
-      // TODO deactivate all TD, wait for QHD to inactive before removal
-      prev->address = qhd->next.address;
-
-      // EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller)
-      qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1);
-
-      if ( qhd->int_smask )
-      {
-        // period list queue element is guarantee to be free in the next frame (1 ms)
-        qhd->used = 0;
-      }else
-      {
-        // async list use async advance handshake
-        // mark as removing, will completely re-usable when async advance isr occurs
-        qhd->removing = 1;
-      }
-
-      hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
-      hcd_dcache_clean(prev, sizeof(ehci_qhd_t));
-    }else {
+    // ep_addr is 0xff means all endpoints of this device address
+    if (qhd->dev_addr == dev_addr &&
+        (ep_addr == TUSB_INDEX_INVALID_8 || qhd_ep_addr(qhd) == ep_addr)) {
+      list_remove(list_head, prev, qhd);
+    } else {
       prev = list_next(prev);
     }
   }
 }
 
-
 //--------------------------------------------------------------------+
 // Queue Header helper
 //--------------------------------------------------------------------+
@@ -782,8 +798,10 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr) {
 
 // Find a free queue head
 TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_find_free(void) {
-  for ( uint32_t i = 0; i < QHD_MAX; i++ ) {
-    if ( !ehci_data.qhd_pool[i].used ) return &ehci_data.qhd_pool[i];
+  for (uint32_t i = 0; i < QHD_MAX; i++) {
+    if (!ehci_data.qhd_pool[i].used) {
+      return &ehci_data.qhd_pool[i];
+    }
   }
   return NULL;
 }
@@ -800,10 +818,9 @@ static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) {
   }
 
   ehci_qhd_t *qhd_pool = ehci_data.qhd_pool;
-
-  for ( uint32_t i = 0; i < QHD_MAX; i++ ) {
-    if ( (qhd_pool[i].dev_addr == dev_addr) &&
-         ep_addr == tu_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) ) {
+  for (uint32_t i = 0; i < QHD_MAX; i++) {
+    if ((qhd_pool[i].dev_addr == dev_addr) &&
+        ep_addr == qhd_ep_addr(&qhd_pool[i])) {
       return &qhd_pool[i];
     }
   }
@@ -812,8 +829,7 @@ static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) {
 }
 
 // Init queue head with endpoint descriptor
-static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
-{
+static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
   // address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise)
   if (dev_addr != 0) {
     tu_memclr(p_qhd, sizeof(ehci_qhd_t));
@@ -830,39 +846,43 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
   p_qhd->ep_number          = tu_edpt_number(ep_desc->bEndpointAddress);
   p_qhd->ep_speed           = devtree_info.speed;
   p_qhd->data_toggle_control= (xfer_type == TUSB_XFER_CONTROL) ? 1 : 0;
-  p_qhd->head_list_flag     = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static asyn list head
+  p_qhd->head_list_flag     = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static async list head
   p_qhd->max_packet_size    = tu_edpt_packet_size(ep_desc);
   p_qhd->fl_ctrl_ep_flag    = ((xfer_type == TUSB_XFER_CONTROL) && (p_qhd->ep_speed != TUSB_SPEED_HIGH))  ? 1 : 0;
   p_qhd->nak_reload         = 0;
 
-  // Bulk/Control -> smask = cmask = 0
-  // TODO Isochronous
-  if (TUSB_XFER_INTERRUPT == xfer_type)
-  {
-    if (TUSB_SPEED_HIGH == p_qhd->ep_speed)
-    {
-      TU_ASSERT( interval <= 16, );
-      if ( interval < 4) // sub millisecond interval
-      {
-        p_qhd->interval_ms = 0;
-        p_qhd->int_smask   = (interval == 1) ? TU_BIN8(11111111) :
-                             (interval == 2) ? TU_BIN8(10101010) : TU_BIN8(01000100);
-      }else
-      {
-        p_qhd->interval_ms = (uint8_t) tu_min16( 1 << (interval-4), 255 );
-        p_qhd->int_smask = TU_BIT(interval % 8);
+  switch (xfer_type) {
+    case TUSB_XFER_CONTROL:
+    case TUSB_XFER_BULK:
+      p_qhd->int_smask = p_qhd->fl_int_cmask = 0;
+      break;
+
+    case TUSB_XFER_INTERRUPT:
+      if (TUSB_SPEED_HIGH == p_qhd->ep_speed) {
+        TU_ASSERT(interval <= 16, );
+        if (interval < 4) {
+          // sub millisecond interval
+          p_qhd->interval_ms = 0;
+          p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) :
+                             (interval == 2) ? TU_BIN8(10101010): TU_BIN8(01000100);
+        } else {
+          p_qhd->interval_ms = (uint8_t) tu_min16(1 << (interval - 4), 255);
+          p_qhd->int_smask = TU_BIT(interval % 8);
+        }
+      } else {
+        TU_ASSERT(0 != interval, );
+        // Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes
+        p_qhd->int_smask = 0x01;
+        p_qhd->fl_int_cmask = TU_BIN8(11100);
+        p_qhd->interval_ms = interval;
       }
-    }else
-    {
-      TU_ASSERT( 0 != interval, );
-      // Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes
-      p_qhd->int_smask    = 0x01;
-      p_qhd->fl_int_cmask = TU_BIN8(11100);
-      p_qhd->interval_ms  = interval;
-    }
-  }else
-  {
-    p_qhd->int_smask = p_qhd->fl_int_cmask = 0;
+      break;
+
+    case TUSB_XFER_ISOCHRONOUS:
+      // TODO not support ISO yet
+      break;
+
+    default: break;
   }
 
   p_qhd->fl_hub_addr  = devtree_info.hub_addr;
@@ -880,8 +900,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
   p_qhd->qtd_overlay.next.terminate      = 1;
   p_qhd->qtd_overlay.alternate.terminate = 1;
 
-  if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT)
-  {
+  if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT) {
     p_qhd->qtd_overlay.ping_err = 1; // do PING for Highspeed Bulk OUT, EHCI section 4.11
   }
 }
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index 457adc1d3..87659701b 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -49,15 +49,14 @@
 
 // TODO merge OHCI with EHCI
 enum {
-  EHCI_MAX_ITD  = 4,
+	EHCI_MAX_ITD  = 4,
   EHCI_MAX_SITD = 16
 };
 
 //--------------------------------------------------------------------+
 // EHCI Data Structure
 //--------------------------------------------------------------------+
-enum
-{
+enum {
   EHCI_QTYPE_ITD = 0 ,
   EHCI_QTYPE_QHD     ,
   EHCI_QTYPE_SITD    ,
@@ -65,8 +64,7 @@ enum
 };
 
 /// EHCI PID
-enum
-{
+enum {
   EHCI_PID_OUT = 0 ,
   EHCI_PID_IN      ,
   EHCI_PID_SETUP
@@ -74,187 +72,182 @@ enum
 
 /// Link pointer
 typedef union {
-	uint32_t address;
-	struct  {
-		uint32_t terminate : 1;
-		uint32_t type      : 2;
-	};
-}ehci_link_t;
+  uint32_t address;
+  struct {
+    uint32_t terminate : 1;
+    uint32_t type      : 2;
+  };
+} ehci_link_t;
 
 TU_VERIFY_STATIC( sizeof(ehci_link_t) == 4, "size is not correct" );
 
 /// Queue Element Transfer Descriptor
 /// Qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with TU_ATTR_ALIGNED(32)
-typedef struct
-{
-	// Word 0: Next QTD Pointer
-	ehci_link_t next;
-
-	// Word 1: Alternate Next QTD Pointer (not used)
-	union{
-	  ehci_link_t alternate;
-	  struct {
-	    uint32_t                : 5;
-	    uint32_t used           : 1;
-	    uint32_t                : 10;
-	    uint32_t expected_bytes : 16;
-	  };
-	};
+typedef struct {
+  // Word 0 Next QTD Pointer
+  ehci_link_t next;
 
-	// Word 2: qTQ Token
-	volatile uint32_t ping_err             : 1  ; ///< For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator
-	volatile uint32_t non_hs_split_state   : 1  ; ///< Used by HC to track the state of split transaction
-	volatile uint32_t non_hs_missed_uframe : 1  ; ///< HC misses a complete split transaction
-	volatile uint32_t xact_err             : 1  ; ///< Error (Timeout, CRC, Bad PID ... )
-	volatile uint32_t babble_err           : 1  ; ///< Babble detected, also set Halted bit to 1
-	volatile uint32_t buffer_err           : 1  ; ///< Data overrun/underrun error
-	volatile uint32_t halted               : 1  ; ///< Serious error or STALL received
-	volatile uint32_t active               : 1  ; ///< Start transfer, clear by HC when complete
+  // Word 1 Alternate Next QTD Pointer (not used)
+  union {
+    ehci_link_t alternate;
+    struct {
+      uint32_t                : 5;
+      uint32_t used           : 1;
+      uint32_t                : 10;
+      uint32_t expected_bytes : 16;
+    };
+  };
 
-	uint32_t pid                           : 2  ; ///< 0: OUT, 1: IN, 2 Setup
-	volatile uint32_t err_count            : 2  ; ///< Error Counter of consecutive errors
-	volatile uint32_t current_page         : 3  ; ///< Index into the qTD buffer pointer list
-	uint32_t int_on_complete               : 1  ; ///< Interrupt on complete
-	volatile uint32_t total_bytes          : 15 ; ///< Transfer bytes, decreased during transaction
-	volatile uint32_t data_toggle          : 1  ; ///< Data Toggle bit
+  // Word 2 qTQ Token
+  volatile uint32_t ping_err             : 1;  // For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator
+  volatile uint32_t non_hs_split_state   : 1;  // Used by HC to track the state of split transaction
+  volatile uint32_t non_hs_missed_uframe : 1;  // HC misses a complete split transaction
+  volatile uint32_t xact_err             : 1;  // Error (Timeout, CRC, Bad PID ... )
+  volatile uint32_t babble_err           : 1;  // Babble detected, also set Halted bit to 1
+  volatile uint32_t buffer_err           : 1;  // Data overrun/underrun error
+  volatile uint32_t halted               : 1;  // Serious error or STALL received
+  volatile uint32_t active               : 1;  // Start transfer, clear by HC when complete
 
+  uint32_t pid                           : 2;  // 0: OUT, 1: IN, 2 Setup
+  volatile uint32_t err_count            : 2;  // Error Counter of consecutive errors
+  volatile uint32_t current_page         : 3;  // Index into the qTD buffer pointer list
+  uint32_t int_on_complete               : 1;  // Interrupt on complete
+  volatile uint32_t total_bytes          : 15; // Transfer bytes, decreased during transaction
+  volatile uint32_t data_toggle          : 1;  // Data Toggle bit
 
-	/// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
-	uint32_t buffer[5];
+  // Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address.
+  // The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
+  uint32_t buffer[5];
 } ehci_qtd_t;
 
 TU_VERIFY_STATIC( sizeof(ehci_qtd_t) == 32, "size is not correct" );
 
 /// Queue Head
-typedef struct TU_ATTR_ALIGNED(32)
-{
-  // Word 0: Next QHD
-	ehci_link_t next;
+typedef struct TU_ATTR_ALIGNED(32) {
+  // Word 0 Next QHD
+  ehci_link_t next;
 
-	// Word 1: Endpoint Characteristics
-	uint32_t dev_addr              : 7  ; ///< device address
-	uint32_t fl_inactive_next_xact : 1  ; ///< Only valid for Periodic with Full/Slow speed
-	uint32_t ep_number             : 4  ; ///< EP number
-	uint32_t ep_speed              : 2  ; ///< 0: Full, 1: Low, 2: High
-	uint32_t data_toggle_control   : 1  ; ///< 0: use DT in qHD, 1: use DT in qTD
-	uint32_t head_list_flag        : 1  ; ///< Head of the queue
-	uint32_t max_packet_size       : 11 ; ///< Max packet size
-	uint32_t fl_ctrl_ep_flag       : 1  ; ///< 1 if is Full/Low speed control endpoint
-	uint32_t nak_reload            : 4  ; ///< Used by HC
+  // Word 1 Endpoint Characteristics
+  uint32_t dev_addr              : 7;  // device address
+  uint32_t fl_inactive_next_xact : 1;  // Only valid for Periodic with Full/Slow speed
+  uint32_t ep_number             : 4;  // EP number
+  uint32_t ep_speed              : 2;  // Full (0), Low (1), High (2)
+  uint32_t data_toggle_control   : 1;  // 0 use DT in qHD, 1 use DT in qTD
+  uint32_t head_list_flag        : 1;  // Head of the queue
+  uint32_t max_packet_size       : 11; // Max packet size
+  uint32_t fl_ctrl_ep_flag       : 1;  // 1 if is Full/Low speed control endpoint
+  uint32_t nak_reload            : 4;  // Used by HC
 
-	// Word 2: Endpoint Capabilities
-	uint32_t int_smask             : 8  ; ///< Interrupt Schedule Mask
-	uint32_t fl_int_cmask          : 8  ; ///< Split Completion Mask for Full/Slow speed
-	uint32_t fl_hub_addr           : 7  ; ///< Hub Address for Full/Slow speed
-	uint32_t fl_hub_port           : 7  ; ///< Hub Port for Full/Slow speed
-	uint32_t mult                  : 2  ; ///< Transaction per micro frame
+  // Word 2 Endpoint Capabilities
+  uint32_t int_smask             : 8;  // Interrupt Schedule Mask
+  uint32_t fl_int_cmask          : 8;  // Split Completion Mask for Full/Slow speed
+  uint32_t fl_hub_addr           : 7;  // Hub Address for Full/Slow speed
+  uint32_t fl_hub_port           : 7;  // Hub Port for Full/Slow speed
+  uint32_t mult                  : 2;  // Transaction per micro frame
 
-	// Word 3: Current qTD Pointer
-	volatile uint32_t qtd_addr;
+  // Word 3 Current qTD Pointer
+  volatile uint32_t qtd_addr;
 
-	// Word 4-11: Transfer Overlay
-	volatile ehci_qtd_t qtd_overlay;
+  // Word 4-11 Transfer Overlay
+  volatile ehci_qtd_t qtd_overlay;
 
-	//--------------------------------------------------------------------+
+  //--------------------------------------------------------------------+
   /// Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes
-	/// thus there are 16 bytes padding free that we can make use of.
+  /// thus there are 16 bytes padding free that we can make use of.
   //--------------------------------------------------------------------+
-	uint8_t used;
-	uint8_t removing; // removed from asyn list, waiting for async advance
-	uint8_t pid;
-	uint8_t interval_ms; // polling interval in frames (or millisecond)
+  uint8_t used;
+  uint8_t removing;// removed from asyn list, waiting for async advance
+  uint8_t pid;
+  uint8_t interval_ms;// polling interval in frames (or millisecond)
 
-	uint8_t TU_RESERVED[4];
+  uint8_t TU_RESERVED[4];
 
   // Attached TD management, note usbh will only queue 1 TD per QHD.
   // buffer for dcache invalidate since td's buffer is modified by HC and finding initial buffer address is not trivial
   uint32_t attached_buffer;
-	ehci_qtd_t * volatile attached_qtd;
+  ehci_qtd_t *volatile attached_qtd;
 } ehci_qhd_t;
-
 TU_VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" );
 
 /// Highspeed Isochronous Transfer Descriptor (section 3.3)
 typedef struct TU_ATTR_ALIGNED(32) {
-	// Word 0: Next Link Pointer
-	ehci_link_t next;
+  // Word 0: Next Link Pointer
+  ehci_link_t next;
 
-	// Word 1-8: iTD Transaction Status and Control List
-	struct  {
-	  // iTD Control
-		volatile uint32_t offset          : 12 ; ///< This field is a value that is an offset, expressed in bytes, from the beginning of a buffer.
-		volatile uint32_t page_select     : 3  ; ///< These bits are set by software to indicate which of the buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6
-             uint32_t int_on_complete : 1  ; ///< If this bit is set to a one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold
-		volatile uint32_t length          : 12 ; ///< For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer
-																						 ///< For an IN, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the number of bytes successfully received. The value in this register is the actual byte count
-		// iTD Status
-		volatile uint32_t error           : 1  ; ///< Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions.
-		volatile uint32_t babble_err      : 1  ; ///< Set to a 1 by the Host Controller during status update when a babble is detected during the transaction
-		volatile uint32_t buffer_err      : 1  ; ///< Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun).
-		volatile uint32_t active          : 1  ; ///< Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller
-	} xact[8];
+  // Word 1-8: iTD Transaction Status and Control List
+  struct {
+    // iTD Control
+    volatile uint32_t offset      : 12; // offset in bytes, from the beginning of a buffer.
+    volatile uint32_t page_select : 3;  // buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6
+    uint32_t int_on_complete      : 1;  // If this bit is set to a one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold
+    volatile uint32_t length      : 12; // For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer
+                                        // For an IN, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the number of bytes successfully received. The value in this register is the actual byte count
+    // iTD Status
+    volatile uint32_t error       : 1;  // Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions.
+    volatile uint32_t babble_err  : 1;  // Set to a 1 by the Host Controller during status update when a babble is detected during the transaction
+    volatile uint32_t buffer_err  : 1;  // Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun).
+    volatile uint32_t active      : 1;  // Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller
+  } xact[8];
 
-	// Word 9-15  Buffer Page Pointer List (Plus)
-	uint32_t BufferPointer[7];
+  // Word 9-15  Buffer Page Pointer List (Plus)
+  uint32_t BufferPointer[7];
 
-//	// FIXME: Store meta data into buffer pointer reserved for saving memory
-//	/*---------- HCD Area ----------*/
-//	uint32_t used;
-//	uint32_t IhdIdx;
-//	uint32_t reserved[6];
+  // FIXME: Store meta data into buffer pointer reserved for saving memory
+  //---------- HCD Area ----------
+  // uint32_t used;
+  // uint32_t IhdIdx;
+  // uint32_t reserved[6];
 } ehci_itd_t;
-
 TU_VERIFY_STATIC( sizeof(ehci_itd_t) == 64, "size is not correct" );
 
 /// Split (Full-Speed) Isochronous Transfer Descriptor
-typedef struct TU_ATTR_ALIGNED(32)
-{
+typedef struct TU_ATTR_ALIGNED(32) {
   // Word 0: Next Link Pointer
-	ehci_link_t next;
+  ehci_link_t next;
 
-	// Word 1: siTD Endpoint Characteristics
-	uint32_t dev_addr    : 7; ///< This field selects the specific device serving as the data source or sink.
-	uint32_t             : 1; ///< reserved
-	uint32_t ep_number   : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink.
-	uint32_t             : 4; ///< This field is reserved and should be set to zero.
-	uint32_t hub_addr    : 7; ///< This field holds the device address of the transaction translators’ hub.
-	uint32_t             : 1; ///< reserved
-	uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator.
-	uint32_t direction   : 1; ///<  0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT.
+  // Word 1: siTD Endpoint Characteristics
+  uint32_t dev_addr    : 7; ///< This field selects the specific device serving as the data source or sink.
+  uint32_t             : 1; ///< reserved
+  uint32_t ep_number   : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink.
+  uint32_t             : 4; ///< This field is reserved and should be set to zero.
+  uint32_t hub_addr    : 7; ///< This field holds the device address of the transaction translators’ hub.
+  uint32_t             : 1; ///< reserved
+  uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator.
+  uint32_t direction   : 1; ///<  0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT.
 
-	// Word 2: Micro-frame Schedule Control
-	uint8_t int_smask   ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions
-	uint8_t fl_int_cmask; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions.
-	uint16_t reserved ; ///< reserved
+  // Word 2: Micro-frame Schedule Control
+  uint8_t int_smask   ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions
+  uint8_t fl_int_cmask; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions.
+  uint16_t reserved ; ///< reserved
 
-	// Word 3: siTD Transfer Status and Control
-	// Status [7:0] TODO identical to qTD Token'status --> refactor later
-	volatile uint32_t                 : 1  ; // reserved
-	volatile uint32_t split_state     : 1  ;
-	volatile uint32_t missed_uframe   : 1  ;
-	volatile uint32_t xact_err        : 1  ;
-	volatile uint32_t babble_err      : 1  ;
-	volatile uint32_t buffer_err      : 1  ;
-	volatile uint32_t error           : 1  ;
-	volatile uint32_t active          : 1  ;
-	// Micro-frame Schedule Control
-	volatile uint32_t cmask_progress  : 8  ; ///< This field is used by the host controller to record which split-completes have been executed. See Section 4.12.3.3.2 for behavioral requirements.
-	volatile uint32_t total_bytes     : 10 ; ///< This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023
-	volatile uint32_t                 : 4  ; ///< reserved
-	volatile uint32_t page_select     : 1  ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer
-					 uint32_t int_on_complete : 1  ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete
-					 uint32_t                 : 0  ; // padding to the end of current storage unit
+  // Word 3: siTD Transfer Status and Control
+  // Status [7:0] TODO identical to qTD Token'status --> refactor later
+  volatile uint32_t                 : 1  ; // reserved
+  volatile uint32_t split_state     : 1  ;
+  volatile uint32_t missed_uframe   : 1  ;
+  volatile uint32_t xact_err        : 1  ;
+  volatile uint32_t babble_err      : 1  ;
+  volatile uint32_t buffer_err      : 1  ;
+  volatile uint32_t error           : 1  ;
+  volatile uint32_t active          : 1  ;
+  // Micro-frame Schedule Control
+  volatile uint32_t cmask_progress  : 8  ; ///< This field is used by the host controller to record which split-completes have been executed. See Section 4.12.3.3.2 for behavioral requirements.
+  volatile uint32_t total_bytes     : 10 ; ///< This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023
+  volatile uint32_t                 : 4  ; ///< reserved
+  volatile uint32_t page_select     : 1  ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer
+           uint32_t int_on_complete : 1  ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete
+           uint32_t                 : 0  ; // padding to the end of current storage unit
 
-	/// Word 4-5: Buffer Pointer List
-	uint32_t buffer[2];		// buffer[1] TP: Transaction Position - T-Count: Transaction Count
+  /// Word 4-5: Buffer Pointer List
+  uint32_t buffer[2];    // buffer[1] TP: Transaction Position - T-Count: Transaction Count
 
-	/*---------- Word 6 ----------*/
-	ehci_link_t back;
+  /*---------- Word 6 ----------*/
+  ehci_link_t back;
 
-	/// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data
-	uint8_t used;
-	uint8_t ihd_idx;
-	uint8_t reserved2[2];
+  /// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data
+  uint8_t used;
+  uint8_t ihd_idx;
+  uint8_t reserved2[2];
 } ehci_sitd_t;
 
 TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" );
@@ -315,8 +308,7 @@ enum {
     EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE
 };
 
-typedef volatile struct
-{
+typedef volatile struct {
   union {
     uint32_t command; // 0x00
 
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 1c0740193..811043d74 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -804,6 +804,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   return true;
 }
 
+bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  (void) rhport; (void) daddr; (void) ep_addr;
+  return false; // TODO not implemented yet
+}
+
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
 {
   (void)rhport;
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 056dbf40b..c3c901c5d 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -541,6 +541,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   return true;
 }
 
+bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  (void) rhport; (void) daddr; (void) ep_addr;
+  return false; // TODO not implemented yet
+}
+
 /* The address of buffer must be aligned to 4 byte boundary. And it must be at least 4 bytes long.
  * DMA writes data in 4 byte unit */
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index ce35eab70..672ad0443 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -451,7 +451,6 @@ static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
-
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
   (void) rhport;
@@ -486,6 +485,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   return true;
 }
 
+bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  (void) rhport; (void) daddr; (void) ep_addr;
+  return false; // TODO not implemented yet
+}
+
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void) rhport;
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 6422afff1..225a44dcf 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -122,6 +122,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const *) desc_ep, need_pre);
 }
 
+bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
+  return pio_usb_host_endpoint_close(pio_rhport, daddr, ep_addr);
+}
+
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen);
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 478c6e789..cd8c905d5 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -514,7 +514,6 @@ void hcd_int_disable(uint8_t rhport)
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
-
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
   (void) rhport;
@@ -535,6 +534,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   return true;
 }
 
+bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  (void) rhport; (void) daddr; (void) ep_addr;
+  return false; // TODO not implemented yet
+}
+
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
   (void) rhport;
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 4c81b05be..3e4b36981 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -718,6 +718,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   return true;
 }
 
+bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  (void) rhport; (void) daddr; (void) ep_addr;
+  return false; // TODO not implemented yet
+}
+
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
 {
   bool r;
diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c
index b13479b02..f0cea529e 100644
--- a/src/portable/synopsys/dwc2/hcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/hcd_dwc2.c
@@ -506,6 +506,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t*
   return true;
 }
 
+bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  (void) rhport; (void) daddr; (void) ep_addr;
+  return false; // TODO not implemented yet
+}
+
 // clean up channel after part of transfer is done but the whole urb is not complete
 static void channel_xfer_out_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) {
   hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c
index d8bca196f..1202c4ef4 100644
--- a/src/portable/template/hcd_template.c
+++ b/src/portable/template/hcd_template.c
@@ -36,24 +36,19 @@
 
 // optional hcd configuration, called by tuh_configure()
 bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
-  (void) rhport;
-  (void) cfg_id;
-  (void) cfg_param;
-
+  (void) rhport; (void) cfg_id; (void) cfg_param;
   return false;
 }
 
 // Initialize controller to host mode
 bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
-  (void) rhport;
-  (void) rh_init;
+  (void) rhport; (void) rh_init;
   return false;
 }
 
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport, bool in_isr) {
-  (void) rhport;
-  (void) in_isr;
+  (void) rhport; (void) in_isr;
 }
 
 // Enable USB interrupt
@@ -69,7 +64,6 @@ void hcd_int_disable(uint8_t rhport) {
 // Get frame number (1ms)
 uint32_t hcd_frame_number(uint8_t rhport) {
   (void) rhport;
-
   return 0;
 }
 
@@ -80,7 +74,6 @@ uint32_t hcd_frame_number(uint8_t rhport) {
 // Get the current connect status of roothub port
 bool hcd_port_connect_status(uint8_t rhport) {
   (void) rhport;
-
   return false;
 }
 
@@ -98,14 +91,12 @@ void hcd_port_reset_end(uint8_t rhport) {
 // Get port link speed
 tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
   (void) rhport;
-
   return TUSB_SPEED_FULL;
 }
 
 // HCD closes all opened endpoints belong to this device
 void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
-  (void) rhport;
-  (void) dev_addr;
+  (void) rhport; (void) dev_addr;
 }
 
 //--------------------------------------------------------------------+
@@ -114,49 +105,37 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
 
 // Open an endpoint
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
-  (void) rhport;
-  (void) dev_addr;
-  (void) ep_desc;
-
+  (void) rhport; (void) dev_addr; (void) ep_desc;
   return false;
 }
 
+bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  (void) rhport; (void) daddr; (void) ep_addr;
+  return false; // TODO not implemented yet
+}
+
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
-  (void) rhport;
-  (void) dev_addr;
-  (void) ep_addr;
-  (void) buffer;
-  (void) buflen;
-
+  (void) rhport; (void) dev_addr; (void) ep_addr; (void) buffer; (void) buflen;
   return false;
 }
 
 // Abort a queued transfer. Note: it can only abort transfer that has not been started
 // Return true if a queued transfer is aborted, false if there is no transfer to abort
 bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
-  (void) rhport;
-  (void) dev_addr;
-  (void) ep_addr;
-
+  (void) rhport; (void) dev_addr; (void) ep_addr;
   return false;
 }
 
 // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
-  (void) rhport;
-  (void) dev_addr;
-  (void) setup_packet;
-
+  (void) rhport; (void) dev_addr; (void) setup_packet;
   return false;
 }
 
 // clear stall, data toggle is also reset to DATA0
 bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
-  (void) rhport;
-  (void) dev_addr;
-  (void) ep_addr;
-
+  (void) rhport; (void) dev_addr; (void) ep_addr;
   return false;
 }