update hcd rusb2 to use tu_hwfifo read/write

6 files changed, 125 insertions, 214 deletions

diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index 967e6702c..5515ffb91 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -233,14 +233,14 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_fifo_write_n(tu_fifo_t *f, const
 //--------------------------------------------------------------------+
 TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_hwfifo_write_from_fifo(volatile void *hwfifo, tu_fifo_t *f, uint16_t n,
                                                                        const tu_hwfifo_access_t *access_mode) {
-  const tu_hwfifo_access_t default_access = {.data_stride = CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE};
+  const tu_hwfifo_access_t default_access = {.data_stride = CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE, .param = 0};
   return tu_fifo_read_n_access_mode(f, (void *)(uintptr_t)hwfifo, n,
                                     (access_mode != NULL) ? access_mode : &default_access);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_hwfifo_read_to_fifo(const volatile void *hwfifo, tu_fifo_t *f,
                                                                     uint16_t n, const tu_hwfifo_access_t *access_mode) {
-  const tu_hwfifo_access_t default_access = {.data_stride = CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE};
+  const tu_hwfifo_access_t default_access = {.data_stride = CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE, .param = 0};
   return tu_fifo_write_n_access_mode(f, (const void *)(uintptr_t)hwfifo, n,
                                      (access_mode != NULL) ? access_mode : &default_access);
 }
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 6722e7a75..e2a51a5ca 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -30,25 +30,7 @@
 #if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2)
 
 #include "device/dcd.h"
-#include "rusb2_type.h"
-
-#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
-  #include "rusb2_rx.h"
-#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
-  #include "rusb2_ra.h"
-  #if defined(RENESAS_CORTEX_M23)
-    #define D0FIFO CFIFO
-    #define D0FIFOSEL CFIFOSEL
-    #define D0FIFOSEL_b CFIFOSEL_b
-    #define D1FIFOSEL CFIFOSEL
-    #define D1FIFOSEL_b CFIFOSEL_b
-    #define D0FIFOCTR CFIFOCTR
-    #define D0FIFOCTR_b CFIFOCTR_b
-  #endif
-
-#else
-  #error "Unsupported MCU"
-#endif
+#include "rusb2_common.h"
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
@@ -57,10 +39,6 @@ enum {
   PIPE_COUNT = 10,
 };
 
-enum {
-  FIFOSEL_BIGEND = (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0)
-};
-
 typedef struct {
   void      *buf;      /* the start address of a transfer data buffer */
   uint16_t  length;    /* the number of bytes in the buffer */
@@ -165,128 +143,9 @@ static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num) {
 }
 
 //--------------------------------------------------------------------+
-// Pipe FIFO
-//--------------------------------------------------------------------+
-#define USE_HWFIFO 1
-  #if !USE_HWFIFO
-// Write data buffer --> hw fifo
-static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len)
-{
-  (void) rusb;
-
-  volatile uint16_t *ff16;
-  volatile uint8_t *ff8;
-
-  const uint8_t *buf8 = (const uint8_t *)buf;
-
-  // Highspeed FIFO is 32-bit
-  if ( rusb2_is_highspeed_reg(rusb) ) {
-    // TODO 32-bit access for better performance
-    volatile uint32_t *ff32 = (volatile uint32_t *)fifo;
-    ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2);
-    ff8  = (volatile uint8_t *) ((uintptr_t) fifo+3);
-
-    while (len >= 4) {
-      *ff32 = tu_unaligned_read32(buf8);
-      buf8 += 4;
-      len -= 4;
-    }
-
-    if (len >= 2) {
-      // switch to 16-bit access
-      rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
-                       (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
-      *ff16 = tu_unaligned_read16(buf8);
-      buf8 += 2;
-      len -= 2;
-    }
-
-    if (len > 0) {
-      *ff8 = *buf8;
-      ++buf8;
-    }
-  } else {
-    ff16 = (volatile uint16_t*) fifo;
-    ff8  = ((volatile uint8_t *)fifo);
-
-    while (len >= 2) {
-      *ff16 = tu_unaligned_read16(buf8);
-      buf8 += 2;
-      len -= 2;
-    }
-
-    if (len > 0) {
-      *ff8 = *buf8;
-      ++buf8;
-    }
-  }
-}
-
-// Write data sw fifo --> hw fifo
-static void pipe_write_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
-  tu_fifo_buffer_info_t info;
-  tu_fifo_get_read_info(f, &info);
-
-  uint16_t cnt_lin = tu_min16(total_len, info.linear.len);
-  uint16_t cnt_wrap = tu_min16(total_len - cnt_lin, info.wrapped.len);
-  uint16_t const cnt_written = cnt_lin + cnt_wrap;
-
-  // Ensure only the last write is odd if total_len is odd
-  if (cnt_wrap == 0) {
-    pipe_write_packet(rusb, info.linear.ptr, fifo, cnt_lin);
-  } else {
-    pipe_write_packet(rusb, info.linear.ptr, fifo, cnt_lin & ~1);
-
-    if (cnt_lin & 1) {
-      uint8_t glue[2] = {info.linear.ptr[cnt_lin & ~1], info.wrapped.ptr[0]};
-      pipe_write_packet(rusb, glue, fifo, 2);
-      cnt_wrap--;
-      info.wrapped.ptr++;
-    }
-
-    pipe_write_packet(rusb, info.wrapped.ptr, fifo, cnt_wrap);
-  }
-  tu_fifo_advance_read_pointer(f, cnt_written);
-}
-
-// Read data buffer <-- hw fifo
-static void pipe_read_packet(rusb2_reg_t *rusb, void *buf, volatile void *fifo, unsigned len) {
-  (void)rusb;
-
-  // TODO 16/32-bit access for better performance
-
-  uint8_t          *p   = (uint8_t *)buf;
-  volatile uint8_t *reg = (volatile uint8_t *)fifo; /* byte access is always at base register address */
-  while (len--) {
-    *p++ = *reg;
-  }
-}
-
-// Read data sw fifo <-- hw fifo
-static void pipe_read_packet_ff(rusb2_reg_t *rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
-  tu_fifo_buffer_info_t info;
-  tu_fifo_get_write_info(f, &info);
-
-  uint16_t count = tu_min16(total_len, info.linear.len);
-  pipe_read_packet(rusb, info.linear.ptr, fifo, count);
-
-  uint16_t rem = total_len - count;
-  if (rem) {
-    rem = tu_min16(rem, info.wrapped.len);
-    pipe_read_packet(rusb, info.wrapped.ptr, fifo, rem);
-    count += rem;
-  }
-
-  tu_fifo_advance_write_pointer(f, count);
-}
-  #endif
-
-
-
-//--------------------------------------------------------------------+
 // Pipe Transfer
 //--------------------------------------------------------------------+
-static bool pipe0_xact_in(rusb2_reg_t *rusb) {
+static bool pipe0_xfer_in(rusb2_reg_t *rusb) {
   pipe_state_t  *pipe = &_dcd.pipe[0];
   const unsigned rem  = pipe->remaining;
 
@@ -330,7 +189,7 @@ static bool pipe0_xact_in(rusb2_reg_t *rusb) {
   return false;
 }
 
-static bool pipe0_xact_out(rusb2_reg_t *rusb) {
+static bool pipe0_xfer_out(rusb2_reg_t *rusb) {
   pipe_state_t  *pipe = &_dcd.pipe[0];
   const unsigned rem  = pipe->remaining;
 
@@ -515,7 +374,7 @@ static bool process_pipe0_xfer(rusb2_reg_t *rusb, int buffer_type, uint8_t ep_ad
     if (ep_addr) {
       /* IN */
       TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80));
-      pipe0_xact_in(rusb);
+      pipe0_xfer_in(rusb);
     }
     rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
   } else {
@@ -588,7 +447,7 @@ static bool process_edpt_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_add
 static void process_pipe0_bemp(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
-  bool         completed = pipe0_xact_in(rusb);
+  bool         completed = pipe0_xfer_in(rusb);
   if (completed) {
     pipe_state_t *pipe = &_dcd.pipe[0];
     dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN),
@@ -611,7 +470,7 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
     if (num) {
       completed = pipe_xfer_out(rusb, num);
     } else {
-      completed = pipe0_xact_out(rusb);
+      completed = pipe0_xfer_out(rusb);
     }
   }
   if (completed) {
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index d70599f5b..4c3315044 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -31,17 +31,9 @@
 
 #include "host/hcd.h"
 #include "host/usbh.h"
-#include "rusb2_type.h"
+#include "rusb2_common.h"
 
-#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
-  #include "rusb2_rx.h"
-#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
-  #include "rusb2_ra.h"
-#else
-  #error "Unsupported MCU"
-#endif
-
-#define TU_RUSB2_HCD_DBG   2
+  #define TU_RUSB2_HCD_DBG 2
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
@@ -164,29 +156,6 @@ static inline void pipe_wait_for_ready(rusb2_reg_t* rusb, unsigned num)
   while (!rusb->D0FIFOCTR_b.FRDY) {}
 }
 
-static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
-{
-  // NOTE: unlike DCD, Highspeed 32-bit FIFO does not need to adjust the fifo address
-  volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
-  uintptr_t addr = (uintptr_t)buf;
-  while (len >= 2) {
-    reg->u16 = *(const uint16_t *)addr;
-    addr += 2;
-    len  -= 2;
-  }
-  if (len) {
-    reg->u8 = *(const uint8_t *)addr;
-    ++addr;
-  }
-}
-
-static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
-{
-  uint8_t *p   = (uint8_t*)buf;
-  volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
-  while (len--) *p++ = *reg;
-}
-
 static bool pipe0_xfer_in(rusb2_reg_t* rusb)
 {
   pipe_state_t *pipe = &_hcd.pipe[0];
@@ -197,8 +166,12 @@ static bool pipe0_xfer_in(rusb2_reg_t* rusb)
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
   if (len) {
+    tu_hwfifo_access_t access_mode = {.data_stride = (rusb2_is_highspeed_reg(rusb) ? 4u : 2u),
+                                      .param       = (uintptr_t)rusb};
+
     rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
-    pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
+    // pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
+    tu_hwfifo_read(&rusb->CFIFO, buf, len, &access_mode);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
@@ -225,7 +198,11 @@ static bool pipe0_xfer_out(rusb2_reg_t* rusb)
   const unsigned len = TU_MIN(mps, rem);
   void          *buf = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
+    tu_hwfifo_access_t access_mode = {.data_stride = (rusb2_is_highspeed_reg(rusb) ? 4u : 2u),
+                                      .param       = (uintptr_t)rusb};
+
+    // pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
+    tu_hwfifo_write(&rusb->CFIFO, buf, len, &access_mode);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
@@ -240,14 +217,24 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
   pipe_state_t  *pipe = &_hcd.pipe[num];
   const unsigned rem  = pipe->remaining;
 
-  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
+  uint16_t fifo_sel = num | FIFOSEL_BIGEND;
+  if (rusb2_is_highspeed_reg(rusb)) {
+    fifo_sel |= RUSB2_FIFOSEL_MBW_32BIT;
+  } else {
+    fifo_sel |= RUSB2_FIFOSEL_MBW_16BIT;
+  }
+  rusb->D0FIFOSEL = fifo_sel;
+
   const unsigned mps  = edpt_max_packet_size(rusb, num);
   pipe_wait_for_ready(rusb, num);
   const unsigned vld  = rusb->D0FIFOCTR_b.DTLN;
   const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
+    // pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
+    tu_hwfifo_access_t access_mode = {.data_stride = (rusb2_is_highspeed_reg(rusb) ? 4u : 2u),
+                                      .param       = (uintptr_t)rusb};
+    tu_hwfifo_read(&rusb->D0FIFO, buf, len, &access_mode);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
@@ -273,13 +260,23 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
     return true;
   }
 
-  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+  uint16_t fifo_sel = num | FIFOSEL_BIGEND;
+  if (rusb2_is_highspeed_reg(rusb)) {
+    fifo_sel |= RUSB2_FIFOSEL_MBW_32BIT;
+  } else {
+    fifo_sel |= RUSB2_FIFOSEL_MBW_16BIT;
+  }
+  rusb->D0FIFOSEL = fifo_sel;
+
   const unsigned mps  = edpt_max_packet_size(rusb, num);
   pipe_wait_for_ready(rusb, num);
   const unsigned len  = TU_MIN(rem, mps);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
+    // pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
+    tu_hwfifo_access_t access_mode = {.data_stride = (rusb2_is_highspeed_reg(rusb) ? 4u : 2u),
+                                      .param       = (uintptr_t)rusb};
+    tu_hwfifo_write(&rusb->D0FIFO, buf, len, &access_mode);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
@@ -294,18 +291,19 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
 static bool process_pipe0_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
 {
   (void)dev_addr;
-
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
   const unsigned dir_in = tu_edpt_dir(ep_addr);
 
+  uint16_t fifo_sel =
+    (rusb2_is_highspeed_reg(rusb) ? RUSB2_FIFOSEL_MBW_32BIT : RUSB2_FIFOSEL_MBW_16BIT) | FIFOSEL_BIGEND;
+
   /* configure fifo direction and access unit settings */
-  if (dir_in) { /* IN, a byte */
-    rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
-    while (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ;
-  } else { /* OUT, 2 bytes */
-    rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
-                         (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
-    while (!(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ;
+  if (dir_in == TUSB_DIR_OUT) {
+    fifo_sel |= RUSB2_CFIFOSEL_ISEL_WRITE;
+  }
+  rusb->CFIFOSEL = fifo_sel;
+  while ((rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) != (fifo_sel & RUSB2_CFIFOSEL_ISEL_WRITE)) {
+    // wait until ISEL_WRITE take effect
   }
 
   pipe_state_t *pipe = &_hcd.pipe[0];
diff --git a/src/portable/renesas/rusb2/rusb2_common.c b/src/portable/renesas/rusb2/rusb2_common.c
index 3ed6f2be1..8addbe4c6 100644
--- a/src/portable/renesas/rusb2/rusb2_common.c
+++ b/src/portable/renesas/rusb2/rusb2_common.c
@@ -25,23 +25,21 @@
  */
 
 #include "tusb_option.h"
-#include "osal/osal.h"
-#include "common/tusb_fifo.h"
 
 #if defined(TUP_USBIP_RUSB2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED)
-#include "rusb2_type.h"
+  #include "osal/osal.h"
+  #include "common/tusb_fifo.h"
 
-#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
-#include "rusb2_rx.h"
+  #include "rusb2_common.h"
 
-#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
-#include "rusb2_ra.h"
+  #if TU_CHECK_MCU(OPT_MCU_RAXXX)
+    #include "rusb2_ra.h"
 
 // USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
 rusb2_controller_t rusb2_controller[] = {
-    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
+  {.reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn},
     #ifdef RUSB2_SUPPORT_HIGHSPEED
-    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
+  {.reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn},
     #endif
 };
 
@@ -50,12 +48,11 @@ void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum);
 void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
   rusb2_controller[rhport].irqnum = irqnum;
 }
+  #endif
 
-#else
-  #error "Unsupported MCU"
-#endif
-
-
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
 static void hwfifo_set_mbw(rusb2_reg_t *rusb, uintptr_t hwfifo, uint16_t mbw) {
   volatile uint16_t *fifo_sel;
   if (hwfifo == (uintptr_t)&rusb->CFIFO) {
diff --git a/src/portable/renesas/rusb2/rusb2_common.h b/src/portable/renesas/rusb2/rusb2_common.h
new file mode 100644
index 000000000..6b8c3d7f2
--- /dev/null
+++ b/src/portable/renesas/rusb2/rusb2_common.h
@@ -0,0 +1,58 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+#pragma once
+
+#include "common/tusb_common.h"
+#include "rusb2_type.h"
+
+#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
+  #include "rusb2_rx.h"
+#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
+  #include "rusb2_ra.h"
+
+  // Hack for D0FIFO definitions on RA Cortex-M23
+  #if defined(RENESAS_CORTEX_M23)
+    #define D0FIFO      CFIFO
+    #define D0FIFOSEL   CFIFOSEL
+    #define D0FIFOSEL_b CFIFOSEL_b
+    #define D1FIFOSEL   CFIFOSEL
+    #define D1FIFOSEL_b CFIFOSEL_b
+    #define D0FIFOCTR   CFIFOCTR
+    #define D0FIFOCTR_b CFIFOCTR_b
+  #endif
+
+#else
+  #error "Unsupported MCU"
+#endif
+
+
+//--------------------------------------------------------------------+
+// Common
+//--------------------------------------------------------------------+
+
+enum {
+  FIFOSEL_BIGEND = (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0)
+};
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index cf685ea3c..21f116857 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -41,10 +41,9 @@ extern "C" {
   #define _ccrx_evenaccess
 #endif
 
-/*--------------------------------------------------------------------*/
-/* Register Definitions                                           */
-/*--------------------------------------------------------------------*/
-
+//--------------------------------------------------------------------+
+// Register Definitions
+//--------------------------------------------------------------------+
 /* Start of definition of packed structs (used by the CCRX toolchain) */
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN