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authorhathach <[email protected]>2024-11-18 23:15:17 +0700
committerhathach <[email protected]>2024-11-18 23:15:17 +0700
commitac9bc01132e3a396ceb977d16b808c4fb6226392 (patch)
tree75d1b3d84090fbfbd7bca43b6b7d62641883028d /src
parent6d4a60d8ac4c0b3e6add8843216e99122b186ee4 (diff)
add CFG_TUD_DWC2_SLAVE_ENABLE = 1 as default
Diffstat (limited to 'src')
-rw-r--r--src/tusb_option.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 6257a87ba..cb4641ad5 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -247,6 +247,10 @@
// USBIP
//--------------------------------------------------------------------+
+#ifndef CFG_TUD_DWC2_SLAVE_ENABLE
+ #define CFG_TUD_DWC2_SLAVE_ENABLE 1
+#endif
+
// DWC2 controller: use DMA for data transfer
// For processors with data cache enabled, USB endpoint buffer region
// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable.