Tune net_lwip_webserver lwIP memory for SuperSpeed on CH569

iperf on the SuperSpeed build is TCP-window-bound (51 Mbit/s with the
6*MSS window). Reclaim RAMX to widen it:

- dcd_ch56x_usbhs: new CFG_TUD_WCH_USBHS_EP_MAX limits usable endpoint
  numbers and scales the static RAMX bounce buffers accordingly
  (default unchanged at 8 endpoints)
- net_lwip_webserver: limit the (fallback) USB2 endpoints to 1-3,
  freeing 4 KB of RAMX; grow the SuperSpeed build to PBUF_POOL_SIZE 9 /
  TCP_WND 9*MSS (the high-speed build keeps 6/6). RAMX 94% of 32 KB.

High-speed fallback verified unchanged on HydraUSB3 (33 Mbit/s, full
enumeration); the SuperSpeed window measurement is pending the rig's SS
lane, which trains only intermittently (analog-marginal path - same
binaries trained and ran 51 Mbit/s earlier the same day).

Co-Authored-By: Claude Fable 5 <[email protected]>
Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

1 files changed, 10 insertions, 2 deletions

diff --git a/src/portable/wch/dcd_ch56x_usbhs.c b/src/portable/wch/dcd_ch56x_usbhs.c
index d465a1c18..e4234e873 100644
--- a/src/portable/wch/dcd_ch56x_usbhs.c
+++ b/src/portable/wch/dcd_ch56x_usbhs.c
@@ -101,9 +101,17 @@ static void ep_mode_set(uint8_t ep_num, tusb_dir_t dir, bool en) {
   }
 }
 
+/* Usable endpoint numbers (0..CFG_TUD_WCH_USBHS_EP_MAX-1): the RAMX bounce buffers scale
+ * with this (1 KB per data endpoint); applications using few endpoints can reduce it to
+ * reclaim RAMX */
+#ifndef CFG_TUD_WCH_USBHS_EP_MAX
+  #define CFG_TUD_WCH_USBHS_EP_MAX EP_MAX
+#endif
+TU_VERIFY_STATIC(CFG_TUD_WCH_USBHS_EP_MAX >= 2 && CFG_TUD_WCH_USBHS_EP_MAX <= EP_MAX, "invalid CFG_TUD_WCH_USBHS_EP_MAX");
+
 /* Endpoint buffers: must be in RAMX and 16-byte aligned (USB DMA constraint) */
 CFG_TUD_WCH_DMA_SECTION TU_ATTR_ALIGNED(16) static uint8_t ep0_buffer[EP0_MAX_SIZE];
-CFG_TUD_WCH_DMA_SECTION TU_ATTR_ALIGNED(16) static uint8_t bounce_buffer[EP_MAX - 1][2][BOUNCE_BUF_SIZE];
+CFG_TUD_WCH_DMA_SECTION TU_ATTR_ALIGNED(16) static uint8_t bounce_buffer[CFG_TUD_WCH_USBHS_EP_MAX - 1][2][BOUNCE_BUF_SIZE];
 static bool ep0_tog;
 static bool ep_data_tog[EP_MAX][2];
 
@@ -316,7 +324,7 @@ bool ch56x_usb2_edpt_open(uint8_t rhport, const tusb_desc_endpoint_t *desc_edpt)
   const uint8_t    ep_num = tu_edpt_number(desc_edpt->bEndpointAddress);
   const tusb_dir_t dir    = tu_edpt_dir(desc_edpt->bEndpointAddress);
 
-  TU_ASSERT(ep_num < EP_MAX);
+  TU_ASSERT(ep_num < CFG_TUD_WCH_USBHS_EP_MAX);
 
   if (ep_num == 0) {
     return true;