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authorhathach <[email protected]>2013-11-01 14:44:14 +0700
committerhathach <[email protected]>2013-11-01 14:44:14 +0700
commitf2ae5b541faba4b0ea28b010cbf9eda53ff59d70 (patch)
tree6063126507c43a7b8e5bc7deaffbe2408c1a36a1 /tinyusb/device/dcd_lpc43xx.c
parentf797c4e02a1a2451e6ba9beca5a1be74fd0bf1ab (diff)
add dcd pipe clear stall
- tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr) but does not take endpoint_handle_t as input complete msc device driver add usbd clear stall endpoint
Diffstat (limited to 'tinyusb/device/dcd_lpc43xx.c')
-rw-r--r--tinyusb/device/dcd_lpc43xx.c26
1 files changed, 16 insertions, 10 deletions
diff --git a/tinyusb/device/dcd_lpc43xx.c b/tinyusb/device/dcd_lpc43xx.c
index fc594d4b5..f7a219ad8 100644
--- a/tinyusb/device/dcd_lpc43xx.c
+++ b/tinyusb/device/dcd_lpc43xx.c
@@ -356,6 +356,15 @@ tusb_error_t dcd_pipe_stall(endpoint_handle_t edpt_hdl)
return TUSB_ERROR_NONE;
}
+tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
+{
+ volatile uint32_t * reg_control = (&LPC_USB0->ENDPTCTRL0) + edpt_phy2log( edpt_addr2phy(edpt_addr) );
+
+ (*reg_control) &= ~(ENDPTCTRL_MASK_STALL << ((edpt_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? 16 : 0));
+
+ return TUSB_ERROR_NONE;
+}
+
endpoint_handle_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc, uint8_t class_code)
{
// TODO USB1 only has 4 non-control enpoint (USB0 has 5)
@@ -446,13 +455,8 @@ tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void* buffer, uint16_t t
}
//------------- Device Controller Driver's Interrupt Handler -------------//
-void xfer_complete_isr(uint8_t coreid, uint8_t reg_complete)
+void xfer_complete_isr(uint8_t coreid, uint32_t reg_complete)
{
- if (reg_complete & BIT_(3+16))
- {
- hal_debugger_breakpoint();
- }
-
// TODO currently exclude control
for(uint8_t ep_idx = 2; ep_idx < DCD_QHD_MAX; ep_idx++)
{
@@ -506,6 +510,7 @@ void dcd_isr(uint8_t coreid)
if (int_status & INT_MASK_USB)
{
+ //------------- Set up Received -------------//
if (LPC_USB0->ENDPTSETUPSTAT)
{ // 23.10.10.2 Operational model for setup transfers
tusb_control_request_t control_request = dcd_data.qhd[0].setup_request;
@@ -527,11 +532,12 @@ void dcd_isr(uint8_t coreid)
usbd_setup_received_isr(coreid, &control_request);
}
- if (LPC_USB0->ENDPTCOMPLETE)
- {
- uint32_t edpt_complete = LPC_USB0->ENDPTCOMPLETE;
- LPC_USB0->ENDPTCOMPLETE = edpt_complete; // acknowledge
+ //------------- Transfer Complete -------------//
+ uint32_t edpt_complete = LPC_USB0->ENDPTCOMPLETE;
+ LPC_USB0->ENDPTCOMPLETE = edpt_complete; // acknowledge
+ if (edpt_complete)
+ {
xfer_complete_isr(coreid, edpt_complete);
}
}