diff options
| author | hathach <[email protected]> | 2013-05-23 14:56:11 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2013-05-23 14:56:11 +0700 |
| commit | 132c3996eae8659f765b3216a4a8926738e8a955 (patch) | |
| tree | c6a7ebb4f5283980a089d7283ab545499a9f97aa /tinyusb/hal | |
| parent | 94fc55ba2c8288d7b50b154b7a1c187ada7fd84d (diff) | |
move scu_pinmux(0x2, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2) to hal/hal_lpc43xx.c
dual host run without problem with mcb4300
Diffstat (limited to 'tinyusb/hal')
| -rw-r--r-- | tinyusb/hal/hal_lpc43xx.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tinyusb/hal/hal_lpc43xx.c b/tinyusb/hal/hal_lpc43xx.c index 0cdf0d725..320be6fd7 100644 --- a/tinyusb/hal/hal_lpc43xx.c +++ b/tinyusb/hal/hal_lpc43xx.c @@ -77,6 +77,8 @@ tusb_error_t hal_init(void) //------------- USB1 Clock, only use on-chip FS PHY -------------// #if TUSB_CFG_CONTROLLER1_MODE + scu_pinmux(0x2, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2); // USB1_VBUS monitor presence, must be high for bus reset occur + /* connect CLK_USB1 to 60 MHz clock */ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_USB1); /* FIXME Run base BASE_USB1_CLK clock from PLL1 (assume PLL1 is 60 MHz, no division required) */ //LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */ |