- addd p_qtd_list_tail to qhd structure for easy queue TD

- move control_request from ehci_data to usbh_device_info_pool
- add test for bulk transfer double (2 consecutive xfers)
- use table (array) structure for class driver, currently included
- refractor extract to function insert_qtd_to_qhd
+ init function
+ install_subtask
--> all class driver function must be declared with WEAK

2 files changed, 34 insertions, 21 deletions

diff --git a/tinyusb/host/ehci/ehci.c b/tinyusb/host/ehci/ehci.c
index d3cf5b6a8..bb12c117e 100644
--- a/tinyusb/host/ehci/ehci.c
+++ b/tinyusb/host/ehci/ehci.c
@@ -273,10 +273,10 @@ tusb_error_t  hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
 
   queue_head_init(p_qhd, dev_addr, max_packet_size, 0, TUSB_XFER_CONTROL);
 
-  //------------- insert to async list -------------//
-  // TODO might need to to disable async list first
   if (dev_addr != 0)
   {
+    //------------- insert to async list -------------//
+    // TODO might need to to disable async list first
     list_insert( (ehci_link_t*) get_async_head(usbh_device_info_pool[dev_addr].core_id),
                  (ehci_link_t*) p_qhd, EHCI_QUEUE_ELEMENT_QHD);
   }
@@ -351,6 +351,7 @@ tusb_error_t  hcd_pipe_control_xfer(uint8_t dev_addr, tusb_std_request_t const *
 
 tusb_error_t  hcd_pipe_control_close(uint8_t dev_addr)
 {
+  //------------- TODO pipe handle validate -------------//
   ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);
 
   p_qhd->qtd_overlay.halted = 1;
@@ -400,9 +401,24 @@ pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_descriptor_endpoint_t const *
   return (pipe_handle_t) { .dev_addr = dev_addr, .xfer_type = p_endpoint_desc->bmAttributes.xfer, .index = index};
 }
 
+static inline void insert_qtd_to_qhd(ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new) ATTR_ALWAYS_INLINE;
+static inline void insert_qtd_to_qhd(ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new)
+{
+  if (p_qhd->p_qtd_list_head == NULL) // empty list
+  {
+    p_qhd->p_qtd_list_head = p_qhd->p_qtd_list_tail = p_qtd_new;
+    p_qhd->qtd_overlay.next.address = (uint32_t) p_qhd->p_qtd_list_head;
+  }else
+  {
+    p_qhd->p_qtd_list_tail->next.address = (uint32_t) p_qtd_new;
+    p_qhd->p_qtd_list_tail = p_qtd_new;
+  }
+}
+
+
 tusb_error_t  hcd_pipe_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes)
 {
-  //------------- pipe handle validate -------------//
+  //------------- TODO pipe handle validate -------------//
 
   //------------- find a free qtd -------------//
   uint8_t index=0;
@@ -413,16 +429,15 @@ tusb_error_t  hcd_pipe_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t t
   ASSERT( index < EHCI_MAX_QTD, TUSB_ERROR_EHCI_NOT_ENOUGH_QTD);
 
   //------------- set up QTD -------------//
-  ehci_qhd_t *p_qhd = &ehci_data.device[pipe_hdl.dev_addr].qhd[index];
-
+  ehci_qhd_t *p_qhd = &ehci_data.device[pipe_hdl.dev_addr].qhd[pipe_hdl.index];
   ehci_qtd_t *p_qtd = &ehci_data.device[pipe_hdl.dev_addr].qtd[index];
+
   queue_td_init(p_qtd, (uint32_t) buffer, total_bytes);
   p_qtd->pid = p_qhd->pid_non_control;
   p_qtd->int_on_complete = 1;
 
-
-  p_qhd->p_qtd_list_head = p_qtd;
-  p_qhd->qtd_overlay.next.address = (uint32_t) p_qtd;
+  //------------- insert TD to TD list -------------//
+  insert_qtd_to_qhd(p_qhd, p_qtd);
 
   return TUSB_ERROR_NONE;
 }
@@ -445,7 +460,7 @@ static inline ehci_qtd_t* get_control_qtds(uint8_t dev_addr)
 
 static inline tusb_std_request_t* const get_control_request_ptr(uint8_t dev_addr)
 {
-  return &ehci_data.control_request[dev_addr];
+  return &usbh_device_info_pool[dev_addr].control_request;
 }
 
 // TODO subject to pure function
@@ -483,7 +498,8 @@ static void queue_head_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, uint16_t max_pa
 
   //------------- HCD Management Data -------------//
   p_qhd->used            = 1;
-  p_qhd->p_qtd_list_head      = NULL;
+  p_qhd->p_qtd_list_head = NULL;
+  p_qhd->p_qtd_list_tail = NULL;
   p_qhd->pid_non_control = (endpoint_addr & 0x80) ? EHCI_PID_IN : EHCI_PID_OUT; // PID for TD under this endpoint
 
 }
diff --git a/tinyusb/host/ehci/ehci.h b/tinyusb/host/ehci/ehci.h
index cfd37c494..290d5f088 100644
--- a/tinyusb/host/ehci/ehci.h
+++ b/tinyusb/host/ehci/ehci.h
@@ -201,10 +201,10 @@ typedef struct {
 	uint8_t list_index;
 	uint8_t reserved;
 
-	ehci_qtd_t *p_qtd_list_head;	// head of the TD list scheduled
+	ehci_qtd_t *p_qtd_list_head;	// head of the scheduled TD list
+	ehci_qtd_t *p_qtd_list_tail;	// tail of the scheduled TD list
+	uint32_t reserved_2;
 
-	volatile uint32_t status; // TODO will remove volatile after remove all HcdQHD function
-	uint16_t *pActualTransferCount; /* total transferred bytes of a usb request */
 }ATTR_ALIGNED(32) ehci_qhd_t;
 
 /// Highspeed Isochronous Transfer Descriptor (section 3.3)
@@ -440,8 +440,7 @@ typedef struct {
   ehci_qhd_t async_head[CONTROLLER_HOST_NUMBER]; /// head qhd of async list, also is used as control endpoint for address 0
   ehci_qhd_t period_head[CONTROLLER_HOST_NUMBER];
 
-  //------------- Data for Address 0 -------------//
-  // qhd: addr0 use async head (dummy) as Queue Head
+  //------------- Data for Address 0 (use async head as its queue head) -------------//
   ehci_qtd_t addr0_qtd[3];
 
   struct {
@@ -450,13 +449,11 @@ typedef struct {
       ehci_qtd_t qtd[3];
     }control;
 
-    ehci_qhd_t  qhd[EHCI_MAX_QHD]   ; ///< Queue Head Pool
-    ehci_qtd_t  qtd[EHCI_MAX_QTD]   ; ///< Queue Element Transfer Pool
-//  ehci_itd_t  itd[EHCI_MAX_ITD]   ; ///< Iso Transfer Pool
-//  ehci_sitd_t sitd[EHCI_MAX_SITD] ; ///< Split (FS) Isochronous Transfer Pool
+    ehci_qhd_t  qhd[EHCI_MAX_QHD]                  ; ///< Queue Head Pool
+    ehci_qtd_t  qtd[EHCI_MAX_QTD] ATTR_ALIGNED(32) ; ///< Queue Element Transfer Pool
+//  ehci_itd_t  itd[EHCI_MAX_ITD]                  ; ///< Iso Transfer Pool
+//  ehci_sitd_t sitd[EHCI_MAX_SITD]                ; ///< Split (FS) Isochronous Transfer Pool
   }device[TUSB_CFG_HOST_DEVICE_MAX];
-
-  tusb_std_request_t control_request[TUSB_CFG_HOST_DEVICE_MAX+1]; // including address zero, 32-byte alignment breaker
 }ehci_data_t;
 
 #ifdef __cplusplus