diff options
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/superpowers/plans/2026-07-23-esp-target-debug-skill.md | 4 | ||||
| -rw-r--r-- | docs/superpowers/plans/2026-07-23-target-debug-skill-enhancement.md | 9 |
2 files changed, 7 insertions, 6 deletions
diff --git a/docs/superpowers/plans/2026-07-23-esp-target-debug-skill.md b/docs/superpowers/plans/2026-07-23-esp-target-debug-skill.md index 8b470eb74..d08902111 100644 --- a/docs/superpowers/plans/2026-07-23-esp-target-debug-skill.md +++ b/docs/superpowers/plans/2026-07-23-esp-target-debug-skill.md @@ -41,7 +41,7 @@ lsusb | grep -i cafe # TinyUSB VID on the DUT port - [x] **Step 3: Attach openocd over USB-SJ while the device runs** ```bash -openocd -f board/esp32p4-builtin.cfg -c 'adapter serial 6055F9F98715' & # gdb :3333 +openocd -f board/esp32p4-builtin.cfg -c 'adapter serial 60:55:F9:F9:87:15' & # gdb :3333 — USB-SJ iSerial = MAC with colons riscv32-esp-elf-gdb -batch -ex 'target extended-remote :3333' -ex 'monitor halt' \ -ex bt -ex 'monitor resume' <p4 elf> ``` @@ -53,7 +53,7 @@ Expected: backtrace with symbols; after resume the CDC device still answers (re- - [x] **Step 1: Breakpoint/watchpoint budget** — RISC-V trigger count: in gdb `monitor riscv info` or set watchpoints until rejection; verify a hardware watchpoint on a TinyUSB variable (e.g. `watch -l` on a usbd counter) reports and hits. - [x] **Step 2: FreeRTOS threads** — `info threads` after halt; expect ESP-IDF tasks incl. the USB task; note whether it works at attach or needs run→stop (mirror the ARM finding). -- [x] **Step 3: Console during traffic** — capture the USB-SJ console tty (the 303a:1001 CDC function) for a few seconds while DUT traffic runs; expect ESP-IDF log lines. Record the /dev node mapping by serial. +- [x] **Step 3: Console during traffic** — OUTCOME: stock builds route the console to UART0 (the CP2102 flasher tty — boot log captured there); the USB-SJ CDC carries no log without sdkconfig `ESP_CONSOLE_USB_SERIAL_JTAG`, which stays (untested) in the skill. - [x] **Step 4: Reflash pristine, release P4 lock.** Evidence appended to `/tmp/esp_evidence.txt`. ### Task 3: P4 apptrace spike — GATED (spec gate 5) diff --git a/docs/superpowers/plans/2026-07-23-target-debug-skill-enhancement.md b/docs/superpowers/plans/2026-07-23-target-debug-skill-enhancement.md index edace21c7..36a3144c2 100644 --- a/docs/superpowers/plans/2026-07-23-target-debug-skill-enhancement.md +++ b/docs/superpowers/plans/2026-07-23-target-debug-skill-enhancement.md @@ -313,8 +313,8 @@ board back; RISC-V ports have no DEMCR — use a breakpoint on the trap handler. Create the fault build (NOT committed): ```bash -python3 test/hil/board_lock.py hold $OB --reason "skill-enhance verify: vector catch" -cd examples/device/cdc_msc +python3 test/hil/board_lock.py hold $JB --reason "skill-enhance verify: vector catch" +cd examples/device/cdc_msc # executed on $JB (stm32f407disco, ARMv7-M) via JLinkExe — see commit evidence # temporary patch — revert after: fault 5 s after boot python3 - <<'EOF' import pathlib @@ -327,12 +327,13 @@ s = s.replace('led_blinking_task();', 'led_blinking_task(); _fault_after_5s();', p.write_text(s) EOF grep -n '_fault_after_5s' src/main.c # expect 3 hits: definition + call + (none in decl block) -cmake -B build-fault -DBOARD=$OB -G Ninja -DCMAKE_BUILD_TYPE=MinSizeRel && cmake --build build-fault +cmake -B build-fault -DBOARD=$JB -G Ninja -DCMAKE_BUILD_TYPE=MinSizeRel && cmake --build build-fault ``` (If `app_led_task`/`board_millis` anchors differ in the current `main.c`, place the same 3-line helper on whatever per-loop task function exists — the fault line `*(volatile uint32_t*)0xCF000000u = 0;` is the payload.) Flash `build-fault`, then: ```bash +# executed variant: DEMCR armed + autopsy via JLinkExe command file on $JB (see commit c1d2d305f evidence); OpenOCD-native form: openocd $OPENOCD_OPTION -c init -c 'cortex_m vector_catch hard_err bus_err' & timeout 60 arm-none-eabi-gdb -batch -ex 'target remote :3333' -ex 'monitor reset run' \ -ex 'shell sleep 8' -ex 'interrupt' \ @@ -343,7 +344,7 @@ Expected: halted in the fault path, CFSR BusFault bits set, **BFAR = 0xCF000000* - [x] **Step 3: Clean up hardware state** -`git checkout -- src/main.c`, delete `build-fault/`, clear DEMCR bits (`set *(unsigned*)0xE000EDFC &= ~0x7F1` via a final gdb attach or power-cycle note), reflash pristine cdc_msc, `board_lock.py release $OB`. +`git checkout -- src/main.c`, delete `build-fault/`, clear DEMCR bits (`set *(unsigned*)0xE000EDFC &= ~0x7F1` via a final gdb attach or power-cycle note), reflash pristine cdc_msc, `board_lock.py release $JB`. - [x] **Step 4: Commit** |