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-rw-r--r--hw/bsp/mcx/boards/mcxn947brk/board.cmake1
-rw-r--r--hw/bsp/mcx/boards/mcxn947brk/board.mk6
-rw-r--r--hw/bsp/mcx/family.cmake2
-rw-r--r--hw/bsp/mcx/mcx.jlinkscript5
4 files changed, 10 insertions, 4 deletions
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
index 7a210628f..650f10967 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.cmake
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
@@ -10,6 +10,7 @@ function(update_board TARGET)
CPU_MCXN947VDF_cm33_core0
# port 1 is highspeed
BOARD_TUD_RHPORT=1
+ BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk
index 69f47b8a8..aaad5e73e 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.mk
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.mk
@@ -4,8 +4,8 @@ PORT ?= 1
CFLAGS += -DCPU_MCXN947VDF_cm33_core0
-JLINK_DEVICE = LPC55S69
-PYOCD_TARGET = LPC55S69
+JLINK_DEVICE = MCXN947_M33_0
+PYOCD_TARGET = MCXN947
# flash using pyocd
-flash: flash-pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 1dbf6f8f7..1c85b51f8 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -14,7 +14,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
+set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
# enable LTO if supported
include(CheckIPOSupported)
diff --git a/hw/bsp/mcx/mcx.jlinkscript b/hw/bsp/mcx/mcx.jlinkscript
new file mode 100644
index 000000000..fd8bcffef
--- /dev/null
+++ b/hw/bsp/mcx/mcx.jlinkscript
@@ -0,0 +1,5 @@
+int SetupTarget(void) {
+ JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
+
+ return 0;
+}