diff options
Diffstat (limited to 'hw')
642 files changed, 30730 insertions, 5192 deletions
diff --git a/hw/bsp/BoardPresets.json b/hw/bsp/BoardPresets.json new file mode 100644 index 000000000..24da362da --- /dev/null +++ b/hw/bsp/BoardPresets.json @@ -0,0 +1,4012 @@ +{ + "version": 6, + "configurePresets": [ + { + "name": "default", + "hidden": true, + "description": "Configure preset for the ${presetName} board", + "generator": "Ninja Multi-Config", + "binaryDir": "${sourceDir}/build/${presetName}", + "cacheVariables": { + "CMAKE_DEFAULT_BUILD_TYPE": "RelWithDebInfo", + "BOARD": "${presetName}" + } + }, + { + "name": "default single", + "hidden": true, + "description": "Configure preset for the ${presetName} board", + "generator": "Ninja", + "binaryDir": "${sourceDir}/build/${presetName}", + "cacheVariables": { + "BOARD": "${presetName}" + } + }, + { + "name": "adafruit_clue", + "inherits": "default" + }, + { + "name": "adafruit_feather_esp32_v2", + "inherits": "default single" + }, + { + "name": "adafruit_feather_esp32s2", + "inherits": "default single" + }, + { + "name": "adafruit_feather_esp32s3", + "inherits": "default single" + }, + { + "name": "adafruit_magtag_29gray", + "inherits": "default" + }, + { + "name": "adafruit_metro_esp32s2", + "inherits": "default single" + }, + { + "name": "apard32690", + "inherits": "default" + }, + { + "name": "arduino_nano33_ble", + "inherits": "default" + }, + { + "name": "atsamd21_xpro", + "inherits": "default" + }, + { + "name": "atsaml21_xpro", + "inherits": "default" + }, + { + "name": "b_g474e_dpow1", + "inherits": "default" + }, + { + "name": "b_u585i_iot2a", + "inherits": "default" + }, + { + "name": "ch32v103r_r1_1v0", + "inherits": "default" + }, + { + "name": "ch32v203c_r0_1v0", + "inherits": "default" + }, + { + "name": "ch32v203g_r0_1v0", + "inherits": "default" + }, + { + "name": "ch32v307v_r1_1v0", + "inherits": "default" + }, + { + "name": "circuitplayground_bluefruit", + "inherits": "default" + }, + { + "name": "circuitplayground_express", + "inherits": "default" + }, + { + "name": "curiosity_nano", + "inherits": "default" + }, + { + "name": "cynthion_d11", + "inherits": "default" + }, + { + "name": "cynthion_d21", + "inherits": "default" + }, + { + "name": "d5035_01", + "inherits": "default" + }, + { + "name": "da14695_dk_usb", + "inherits": "default" + }, + { + "name": "da1469x_dk_pro", + "inherits": "default" + }, + { + "name": "daisyseed", + "inherits": "default" + }, + { + "name": "double_m33_express", + "inherits": "default" + }, + { + "name": "ea4088_quickstart", + "inherits": "default" + }, + { + "name": "ea4357", + "inherits": "default" + }, + { + "name": "ek_tm4c123gxl", + "inherits": "default" + }, + { + "name": "espressif_addax_1", + "inherits": "default single" + }, + { + "name": "espressif_c3_devkitc", + "inherits": "default single" + }, + { + "name": "espressif_c6_devkitc", + "inherits": "default single" + }, + { + "name": "espressif_kaluga_1", + "inherits": "default single" + }, + { + "name": "espressif_p4_function_ev", + "inherits": "default single" + }, + { + "name": "espressif_s2_devkitc", + "inherits": "default single" + }, + { + "name": "espressif_s3_devkitc", + "inherits": "default single" + }, + { + "name": "espressif_s3_devkitm", + "inherits": "default single" + }, + { + "name": "espressif_saola_1", + "inherits": "default single" + }, + { + "name": "f1c100s", + "inherits": "default" + }, + { + "name": "feather_m0_express", + "inherits": "default" + }, + { + "name": "feather_m4_express", + "inherits": "default" + }, + { + "name": "feather_nrf52840_express", + "inherits": "default" + }, + { + "name": "feather_nrf52840_sense", + "inherits": "default" + }, + { + "name": "feather_rp2040_max3421", + "inherits": "default" + }, + { + "name": "feather_stm32f405", + "inherits": "default" + }, + { + "name": "fomu", + "inherits": "default" + }, + { + "name": "frdm_k32l2a4s", + "inherits": "default" + }, + { + "name": "frdm_k32l2b", + "inherits": "default" + }, + { + "name": "frdm_k64f", + "inherits": "default" + }, + { + "name": "frdm_kl25z", + "inherits": "default" + }, + { + "name": "frdm_mcxa153", + "inherits": "default" + }, + { + "name": "frdm_mcxn947", + "inherits": "default" + }, + { + "name": "itsybitsy_m0", + "inherits": "default" + }, + { + "name": "itsybitsy_m4", + "inherits": "default" + }, + { + "name": "itsybitsy_nrf52840", + "inherits": "default" + }, + { + "name": "kuiic", + "inherits": "default" + }, + { + "name": "lpcxpresso11u37", + "inherits": "default" + }, + { + "name": "lpcxpresso11u68", + "inherits": "default" + }, + { + "name": "lpcxpresso1347", + "inherits": "default" + }, + { + "name": "lpcxpresso1549", + "inherits": "default" + }, + { + "name": "lpcxpresso1769", + "inherits": "default" + }, + { + "name": "lpcxpresso18s37", + "inherits": "default" + }, + { + "name": "lpcxpresso43s67", + "inherits": "default" + }, + { + "name": "lpcxpresso51u68", + "inherits": "default" + }, + { + "name": "lpcxpresso54114", + "inherits": "default" + }, + { + "name": "lpcxpresso54608", + "inherits": "default" + }, + { + "name": "lpcxpresso54628", + "inherits": "default" + }, + { + "name": "lpcxpresso55s28", + "inherits": "default" + }, + { + "name": "lpcxpresso55s69", + "inherits": "default" + }, + { + "name": "max32650evkit", + "inherits": "default" + }, + { + "name": "max32650fthr", + "inherits": "default" + }, + { + "name": "max32651evkit", + "inherits": "default" + }, + { + "name": "max32666evkit", + "inherits": "default" + }, + { + "name": "max32666fthr", + "inherits": "default" + }, + { + "name": "max32690evkit", + "inherits": "default" + }, + { + "name": "max78002evkit", + "inherits": "default" + }, + { + "name": "mbed1768", + "inherits": "default" + }, + { + "name": "mcb1800", + "inherits": "default" + }, + { + "name": "mcu_link", + "inherits": "default" + }, + { + "name": "mcxn947brk", + "inherits": "default" + }, + { + "name": "metro_m0_express", + "inherits": "default" + }, + { + "name": "metro_m4_express", + "inherits": "default" + }, + { + "name": "metro_m7_1011", + "inherits": "default" + }, + { + "name": "metro_m7_1011_sd", + "inherits": "default" + }, + { + "name": "mimxrt1010_evk", + "inherits": "default" + }, + { + "name": "mimxrt1015_evk", + "inherits": "default" + }, + { + "name": "mimxrt1020_evk", + "inherits": "default" + }, + { + "name": "mimxrt1024_evk", + "inherits": "default" + }, + { + "name": "mimxrt1050_evkb", + "inherits": "default" + }, + { + "name": "mimxrt1060_evk", + "inherits": "default" + }, + { + "name": "mimxrt1064_evk", + "inherits": "default" + }, + { + "name": "mimxrt1170_evkb", + "inherits": "default" + }, + { + "name": "mm32f327x_mb39", + "inherits": "default" + }, + { + "name": "mm32f327x_pitaya_lite", + "inherits": "default" + }, + { + "name": "msp_exp430f5529lp", + "inherits": "default" + }, + { + "name": "msp_exp432e401y", + "inherits": "default" + }, + { + "name": "nanoch32v203", + "inherits": "default" + }, + { + "name": "pca10056", + "inherits": "default" + }, + { + "name": "pca10059", + "inherits": "default" + }, + { + "name": "pca10095", + "inherits": "default" + }, + { + "name": "pca10100", + "inherits": "default" + }, + { + "name": "pico_sdk", + "inherits": "default" + }, + { + "name": "portenta_c33", + "inherits": "default" + }, + { + "name": "pybadge", + "inherits": "default" + }, + { + "name": "pyboardv11", + "inherits": "default" + }, + { + "name": "pyportal", + "inherits": "default" + }, + { + "name": "qtpy", + "inherits": "default" + }, + { + "name": "ra2a1_ek", + "inherits": "default" + }, + { + "name": "ra4m1_ek", + "inherits": "default" + }, + { + "name": "ra4m3_ek", + "inherits": "default" + }, + { + "name": "ra6m1_ek", + "inherits": "default" + }, + { + "name": "ra6m5_ek", + "inherits": "default" + }, + { + "name": "ra8m1_ek", + "inherits": "default" + }, + { + "name": "raspberry_pi_pico", + "inherits": "default" + }, + { + "name": "raspberry_pi_pico2", + "inherits": "default" + }, + { + "name": "raspberrypi_cm4", + "inherits": "default" + }, + { + "name": "raspberrypi_zero", + "inherits": "default" + }, + { + "name": "raspberrypi_zero2", + "inherits": "default" + }, + { + "name": "samd11_xplained", + "inherits": "default" + }, + { + "name": "same54_xplained", + "inherits": "default" + }, + { + "name": "samg55_xplained", + "inherits": "default" + }, + { + "name": "saml22_feather", + "inherits": "default" + }, + { + "name": "seeeduino_xiao", + "inherits": "default" + }, + { + "name": "sensorwatch_m0", + "inherits": "default" + }, + { + "name": "sipeed_longan_nano", + "inherits": "default" + }, + { + "name": "sparkfun_samd21_mini_usb", + "inherits": "default" + }, + { + "name": "stlinkv3mini", + "inherits": "default" + }, + { + "name": "stm32c071nucleo", + "inherits": "default" + }, + { + "name": "stm32f070rbnucleo", + "inherits": "default" + }, + { + "name": "stm32f072disco", + "inherits": "default" + }, + { + "name": "stm32f072eval", + "inherits": "default" + }, + { + "name": "stm32f103_bluepill", + "inherits": "default" + }, + { + "name": "stm32f103_mini_2", + "inherits": "default" + }, + { + "name": "stm32f103ze_iar", + "inherits": "default" + }, + { + "name": "stm32f207nucleo", + "inherits": "default" + }, + { + "name": "stm32f303disco", + "inherits": "default" + }, + { + "name": "stm32f401blackpill", + "inherits": "default" + }, + { + "name": "stm32f407blackvet", + "inherits": "default" + }, + { + "name": "stm32f407disco", + "inherits": "default" + }, + { + "name": "stm32f411blackpill", + "inherits": "default" + }, + { + "name": "stm32f411disco", + "inherits": "default" + }, + { + "name": "stm32f412disco", + "inherits": "default" + }, + { + "name": "stm32f412nucleo", + "inherits": "default" + }, + { + "name": "stm32f439nucleo", + "inherits": "default" + }, + { + "name": "stm32f723disco", + "inherits": "default" + }, + { + "name": "stm32f746disco", + "inherits": "default" + }, + { + "name": "stm32f746nucleo", + "inherits": "default" + }, + { + "name": "stm32f767nucleo", + "inherits": "default" + }, + { + "name": "stm32f769disco", + "inherits": "default" + }, + { + "name": "stm32g0b1nucleo", + "inherits": "default" + }, + { + "name": "stm32g474nucleo", + "inherits": "default" + }, + { + "name": "stm32g491nucleo", + "inherits": "default" + }, + { + "name": "stm32h503nucleo", + "inherits": "default" + }, + { + "name": "stm32h563nucleo", + "inherits": "default" + }, + { + "name": "stm32h573i_dk", + "inherits": "default" + }, + { + "name": "stm32h723nucleo", + "inherits": "default" + }, + { + "name": "stm32h743eval", + "inherits": "default" + }, + { + "name": "stm32h743nucleo", + "inherits": "default" + }, + { + "name": "stm32h745disco", + "inherits": "default" + }, + { + "name": "stm32h750_weact", + "inherits": "default" + }, + { + "name": "stm32h750bdk", + "inherits": "default" + }, + { + "name": "stm32h7s3nucleo", + "inherits": "default" + }, + { + "name": "stm32l052dap52", + "inherits": "default" + }, + { + "name": "stm32l0538disco", + "inherits": "default" + }, + { + "name": "stm32l412nucleo", + "inherits": "default" + }, + { + "name": "stm32l476disco", + "inherits": "default" + }, + { + "name": "stm32l4p5nucleo", + "inherits": "default" + }, + { + "name": "stm32l4r5nucleo", + "inherits": "default" + }, + { + "name": "stm32u545nucleo", + "inherits": "default" + }, + { + "name": "stm32u575eval", + "inherits": "default" + }, + { + "name": "stm32u575nucleo", + "inherits": "default" + }, + { + "name": "stm32u5a5nucleo", + "inherits": "default" + }, + { + "name": "stm32wb55nucleo", + "inherits": "default" + }, + { + "name": "teensy_35", + "inherits": "default" + }, + { + "name": "teensy_40", + "inherits": "default" + }, + { + "name": "teensy_41", + "inherits": "default" + }, + { + "name": "trinket_m0", + "inherits": "default" + }, + { + "name": "uno_r4", + "inherits": "default" + }, + { + "name": "waveshare_openh743i", + "inherits": "default" + }, + { + "name": "xmc4500_relax", + "inherits": "default" + }, + { + "name": "xmc4700_relax", + "inherits": "default" + } + ], + "buildPresets": [ + { + "name": "adafruit_clue", + "description": "Build preset for the adafruit_clue board", + "configurePreset": "adafruit_clue" + }, + { + "name": "adafruit_feather_esp32_v2", + "description": "Build preset for the adafruit_feather_esp32_v2 board", + "configurePreset": "adafruit_feather_esp32_v2" + }, + { + "name": "adafruit_feather_esp32s2", + "description": "Build preset for the adafruit_feather_esp32s2 board", + "configurePreset": "adafruit_feather_esp32s2" + }, + { + "name": "adafruit_feather_esp32s3", + "description": "Build preset for the adafruit_feather_esp32s3 board", + "configurePreset": "adafruit_feather_esp32s3" + }, + { + "name": "adafruit_magtag_29gray", + "description": "Build preset for the adafruit_magtag_29gray board", + "configurePreset": "adafruit_magtag_29gray" + }, + { + "name": "adafruit_metro_esp32s2", + "description": "Build preset for the adafruit_metro_esp32s2 board", + "configurePreset": "adafruit_metro_esp32s2" + }, + { + "name": "apard32690", + "description": "Build preset for the apard32690 board", + "configurePreset": "apard32690" + }, + { + "name": "arduino_nano33_ble", + "description": "Build preset for the arduino_nano33_ble board", + "configurePreset": "arduino_nano33_ble" + }, + { + "name": "atsamd21_xpro", + "description": "Build preset for the atsamd21_xpro board", + "configurePreset": "atsamd21_xpro" + }, + { + "name": "atsaml21_xpro", + "description": "Build preset for the atsaml21_xpro board", + "configurePreset": "atsaml21_xpro" + }, + { + "name": "b_g474e_dpow1", + "description": "Build preset for the b_g474e_dpow1 board", + "configurePreset": "b_g474e_dpow1" + }, + { + "name": "b_u585i_iot2a", + "description": "Build preset for the b_u585i_iot2a board", + "configurePreset": "b_u585i_iot2a" + }, + { + "name": "ch32v103r_r1_1v0", + "description": "Build preset for the ch32v103r_r1_1v0 board", + "configurePreset": "ch32v103r_r1_1v0" + }, + { + "name": "ch32v203c_r0_1v0", + "description": "Build preset for the ch32v203c_r0_1v0 board", + "configurePreset": "ch32v203c_r0_1v0" + }, + { + "name": "ch32v203g_r0_1v0", + "description": "Build preset for the ch32v203g_r0_1v0 board", + "configurePreset": "ch32v203g_r0_1v0" + }, + { + "name": "ch32v307v_r1_1v0", + "description": "Build preset for the ch32v307v_r1_1v0 board", + "configurePreset": "ch32v307v_r1_1v0" + }, + { + "name": "circuitplayground_bluefruit", + "description": "Build preset for the circuitplayground_bluefruit board", + "configurePreset": "circuitplayground_bluefruit" + }, + { + "name": "circuitplayground_express", + "description": "Build preset for the circuitplayground_express board", + "configurePreset": "circuitplayground_express" + }, + { + "name": "curiosity_nano", + "description": "Build preset for the curiosity_nano board", + "configurePreset": "curiosity_nano" + }, + { + "name": "cynthion_d11", + "description": "Build preset for the cynthion_d11 board", + "configurePreset": "cynthion_d11" + }, + { + "name": "cynthion_d21", + "description": "Build preset for the cynthion_d21 board", + "configurePreset": "cynthion_d21" + }, + { + "name": "d5035_01", + "description": "Build preset for the d5035_01 board", + "configurePreset": "d5035_01" + }, + { + "name": "da14695_dk_usb", + "description": "Build preset for the da14695_dk_usb board", + "configurePreset": "da14695_dk_usb" + }, + { + "name": "da1469x_dk_pro", + "description": "Build preset for the da1469x_dk_pro board", + "configurePreset": "da1469x_dk_pro" + }, + { + "name": "daisyseed", + "description": "Build preset for the daisyseed board", + "configurePreset": "daisyseed" + }, + { + "name": "double_m33_express", + "description": "Build preset for the double_m33_express board", + "configurePreset": "double_m33_express" + }, + { + "name": "ea4088_quickstart", + "description": "Build preset for the ea4088_quickstart board", + "configurePreset": "ea4088_quickstart" + }, + { + "name": "ea4357", + "description": "Build preset for the ea4357 board", + "configurePreset": "ea4357" + }, + { + "name": "ek_tm4c123gxl", + "description": "Build preset for the ek_tm4c123gxl board", + "configurePreset": "ek_tm4c123gxl" + }, + { + "name": "espressif_addax_1", + "description": "Build preset for the espressif_addax_1 board", + "configurePreset": "espressif_addax_1" + }, + { + "name": "espressif_c3_devkitc", + "description": "Build preset for the espressif_c3_devkitc board", + "configurePreset": "espressif_c3_devkitc" + }, + { + "name": "espressif_c6_devkitc", + "description": "Build preset for the espressif_c6_devkitc board", + "configurePreset": "espressif_c6_devkitc" + }, + { + "name": "espressif_kaluga_1", + "description": "Build preset for the espressif_kaluga_1 board", + "configurePreset": "espressif_kaluga_1" + }, + { + "name": "espressif_p4_function_ev", + "description": "Build preset for the espressif_p4_function_ev board", + "configurePreset": "espressif_p4_function_ev" + }, + { + "name": "espressif_s2_devkitc", + "description": "Build preset for the espressif_s2_devkitc board", + "configurePreset": "espressif_s2_devkitc" + }, + { + "name": "espressif_s3_devkitc", + "description": "Build preset for the espressif_s3_devkitc board", + "configurePreset": "espressif_s3_devkitc" + }, + { + "name": "espressif_s3_devkitm", + "description": "Build preset for the espressif_s3_devkitm board", + "configurePreset": "espressif_s3_devkitm" + }, + { + "name": "espressif_saola_1", + "description": "Build preset for the espressif_saola_1 board", + "configurePreset": "espressif_saola_1" + }, + { + "name": "f1c100s", + "description": "Build preset for the f1c100s board", + "configurePreset": "f1c100s" + }, + { + "name": "feather_m0_express", + "description": "Build preset for the feather_m0_express board", + "configurePreset": "feather_m0_express" + }, + { + "name": "feather_m4_express", + "description": "Build preset for the feather_m4_express board", + "configurePreset": "feather_m4_express" + }, + { + "name": "feather_nrf52840_express", + "description": "Build preset for the feather_nrf52840_express board", + "configurePreset": "feather_nrf52840_express" + }, + { + "name": "feather_nrf52840_sense", + "description": "Build preset for the feather_nrf52840_sense board", + "configurePreset": "feather_nrf52840_sense" + }, + { + "name": "feather_rp2040_max3421", + "description": "Build preset for the feather_rp2040_max3421 board", + "configurePreset": "feather_rp2040_max3421" + }, + { + "name": "feather_stm32f405", + "description": "Build preset for the feather_stm32f405 board", + "configurePreset": "feather_stm32f405" + }, + { + "name": "fomu", + "description": "Build preset for the fomu board", + "configurePreset": "fomu" + }, + { + "name": "frdm_k32l2a4s", + "description": "Build preset for the frdm_k32l2a4s board", + "configurePreset": "frdm_k32l2a4s" + }, + { + "name": "frdm_k32l2b", + "description": "Build preset for the frdm_k32l2b board", + "configurePreset": "frdm_k32l2b" + }, + { + "name": "frdm_k64f", + "description": "Build preset for the frdm_k64f board", + "configurePreset": "frdm_k64f" + }, + { + "name": "frdm_kl25z", + "description": "Build preset for the frdm_kl25z board", + "configurePreset": "frdm_kl25z" + }, + { + "name": "frdm_mcxa153", + "description": "Build preset for the frdm_mcxa153 board", + "configurePreset": "frdm_mcxa153" + }, + { + "name": "frdm_mcxn947", + "description": "Build preset for the frdm_mcxn947 board", + "configurePreset": "frdm_mcxn947" + }, + { + "name": "itsybitsy_m0", + "description": "Build preset for the itsybitsy_m0 board", + "configurePreset": "itsybitsy_m0" + }, + { + "name": "itsybitsy_m4", + "description": "Build preset for the itsybitsy_m4 board", + "configurePreset": "itsybitsy_m4" + }, + { + "name": "itsybitsy_nrf52840", + "description": "Build preset for the itsybitsy_nrf52840 board", + "configurePreset": "itsybitsy_nrf52840" + }, + { + "name": "kuiic", + "description": "Build preset for the kuiic board", + "configurePreset": "kuiic" + }, + { + "name": "lpcxpresso11u37", + "description": "Build preset for the lpcxpresso11u37 board", + "configurePreset": "lpcxpresso11u37" + }, + { + "name": "lpcxpresso11u68", + "description": "Build preset for the lpcxpresso11u68 board", + "configurePreset": "lpcxpresso11u68" + }, + { + "name": "lpcxpresso1347", + "description": "Build preset for the lpcxpresso1347 board", + "configurePreset": "lpcxpresso1347" + }, + { + "name": "lpcxpresso1549", + "description": "Build preset for the lpcxpresso1549 board", + "configurePreset": "lpcxpresso1549" + }, + { + "name": "lpcxpresso1769", + "description": "Build preset for the lpcxpresso1769 board", + "configurePreset": "lpcxpresso1769" + }, + { + "name": "lpcxpresso18s37", + "description": "Build preset for the lpcxpresso18s37 board", + "configurePreset": "lpcxpresso18s37" + }, + { + "name": "lpcxpresso43s67", + "description": "Build preset for the lpcxpresso43s67 board", + "configurePreset": "lpcxpresso43s67" + }, + { + "name": "lpcxpresso51u68", + "description": "Build preset for the lpcxpresso51u68 board", + "configurePreset": "lpcxpresso51u68" + }, + { + "name": "lpcxpresso54114", + "description": "Build preset for the lpcxpresso54114 board", + "configurePreset": "lpcxpresso54114" + }, + { + "name": "lpcxpresso54608", + "description": "Build preset for the lpcxpresso54608 board", + "configurePreset": "lpcxpresso54608" + }, + { + "name": "lpcxpresso54628", + "description": "Build preset for the lpcxpresso54628 board", + "configurePreset": "lpcxpresso54628" + }, + { + "name": "lpcxpresso55s28", + "description": "Build preset for the lpcxpresso55s28 board", + "configurePreset": "lpcxpresso55s28" + }, + { + "name": "lpcxpresso55s69", + "description": "Build preset for the lpcxpresso55s69 board", + "configurePreset": "lpcxpresso55s69" + }, + { + "name": "max32650evkit", + "description": "Build preset for the max32650evkit board", + "configurePreset": "max32650evkit" + }, + { + "name": "max32650fthr", + "description": "Build preset for the max32650fthr board", + "configurePreset": "max32650fthr" + }, + { + "name": "max32651evkit", + "description": "Build preset for the max32651evkit board", + "configurePreset": "max32651evkit" + }, + { + "name": "max32666evkit", + "description": "Build preset for the max32666evkit board", + "configurePreset": "max32666evkit" + }, + { + "name": "max32666fthr", + "description": "Build preset for the max32666fthr board", + "configurePreset": "max32666fthr" + }, + { + "name": "max32690evkit", + "description": "Build preset for the max32690evkit board", + "configurePreset": "max32690evkit" + }, + { + "name": "max78002evkit", + "description": "Build preset for the max78002evkit board", + "configurePreset": "max78002evkit" + }, + { + "name": "mbed1768", + "description": "Build preset for the mbed1768 board", + "configurePreset": "mbed1768" + }, + { + "name": "mcb1800", + "description": "Build preset for the mcb1800 board", + "configurePreset": "mcb1800" + }, + { + "name": "mcu_link", + "description": "Build preset for the mcu_link board", + "configurePreset": "mcu_link" + }, + { + "name": "mcxn947brk", + "description": "Build preset for the mcxn947brk board", + "configurePreset": "mcxn947brk" + }, + { + "name": "metro_m0_express", + "description": "Build preset for the metro_m0_express board", + "configurePreset": "metro_m0_express" + }, + { + "name": "metro_m4_express", + "description": "Build preset for the metro_m4_express board", + "configurePreset": "metro_m4_express" + }, + { + "name": "metro_m7_1011", + "description": "Build preset for the metro_m7_1011 board", + "configurePreset": "metro_m7_1011" + }, + { + "name": "metro_m7_1011_sd", + "description": "Build preset for the metro_m7_1011_sd board", + "configurePreset": "metro_m7_1011_sd" + }, + { + "name": "mimxrt1010_evk", + "description": "Build preset for the mimxrt1010_evk board", + "configurePreset": "mimxrt1010_evk" + }, + { + "name": "mimxrt1015_evk", + "description": "Build preset for the mimxrt1015_evk board", + "configurePreset": "mimxrt1015_evk" + }, + { + "name": "mimxrt1020_evk", + "description": "Build preset for the mimxrt1020_evk board", + "configurePreset": "mimxrt1020_evk" + }, + { + "name": "mimxrt1024_evk", + "description": "Build preset for the mimxrt1024_evk board", + "configurePreset": "mimxrt1024_evk" + }, + { + "name": "mimxrt1050_evkb", + "description": "Build preset for the mimxrt1050_evkb board", + "configurePreset": "mimxrt1050_evkb" + }, + { + "name": "mimxrt1060_evk", + "description": "Build preset for the mimxrt1060_evk board", + "configurePreset": "mimxrt1060_evk" + }, + { + "name": "mimxrt1064_evk", + "description": "Build preset for the mimxrt1064_evk board", + "configurePreset": "mimxrt1064_evk" + }, + { + "name": "mimxrt1170_evkb", + "description": "Build preset for the mimxrt1170_evkb board", + "configurePreset": "mimxrt1170_evkb" + }, + { + "name": "mm32f327x_mb39", + "description": "Build preset for the mm32f327x_mb39 board", + "configurePreset": "mm32f327x_mb39" + }, + { + "name": "mm32f327x_pitaya_lite", + "description": "Build preset for the mm32f327x_pitaya_lite board", + "configurePreset": "mm32f327x_pitaya_lite" + }, + { + "name": "msp_exp430f5529lp", + "description": "Build preset for the msp_exp430f5529lp board", + "configurePreset": "msp_exp430f5529lp" + }, + { + "name": "msp_exp432e401y", + "description": "Build preset for the msp_exp432e401y board", + "configurePreset": "msp_exp432e401y" + }, + { + "name": "nanoch32v203", + "description": "Build preset for the nanoch32v203 board", + "configurePreset": "nanoch32v203" + }, + { + "name": "pca10056", + "description": "Build preset for the pca10056 board", + "configurePreset": "pca10056" + }, + { + "name": "pca10059", + "description": "Build preset for the pca10059 board", + "configurePreset": "pca10059" + }, + { + "name": "pca10095", + "description": "Build preset for the pca10095 board", + "configurePreset": "pca10095" + }, + { + "name": "pca10100", + "description": "Build preset for the pca10100 board", + "configurePreset": "pca10100" + }, + { + "name": "pico_sdk", + "description": "Build preset for the pico_sdk board", + "configurePreset": "pico_sdk" + }, + { + "name": "portenta_c33", + "description": "Build preset for the portenta_c33 board", + "configurePreset": "portenta_c33" + }, + { + "name": "pybadge", + "description": "Build preset for the pybadge board", + "configurePreset": "pybadge" + }, + { + "name": "pyboardv11", + "description": "Build preset for the pyboardv11 board", + "configurePreset": "pyboardv11" + }, + { + "name": "pyportal", + "description": "Build preset for the pyportal board", + "configurePreset": "pyportal" + }, + { + "name": "qtpy", + "description": "Build preset for the qtpy board", + "configurePreset": "qtpy" + }, + { + "name": "ra2a1_ek", + "description": "Build preset for the ra2a1_ek board", + "configurePreset": "ra2a1_ek" + }, + { + "name": "ra4m1_ek", + "description": "Build preset for the ra4m1_ek board", + "configurePreset": "ra4m1_ek" + }, + { + "name": "ra4m3_ek", + "description": "Build preset for the ra4m3_ek board", + "configurePreset": "ra4m3_ek" + }, + { + "name": "ra6m1_ek", + "description": "Build preset for the ra6m1_ek board", + "configurePreset": "ra6m1_ek" + }, + { + "name": "ra6m5_ek", + "description": "Build preset for the ra6m5_ek board", + "configurePreset": "ra6m5_ek" + }, + { + "name": "ra8m1_ek", + "description": "Build preset for the ra8m1_ek board", + "configurePreset": "ra8m1_ek" + }, + { + "name": "raspberry_pi_pico", + "description": "Build preset for the raspberry_pi_pico board", + "configurePreset": "raspberry_pi_pico" + }, + { + "name": "raspberry_pi_pico2", + "description": "Build preset for the raspberry_pi_pico2 board", + "configurePreset": "raspberry_pi_pico2" + }, + { + "name": "raspberrypi_cm4", + "description": "Build preset for the raspberrypi_cm4 board", + "configurePreset": "raspberrypi_cm4" + }, + { + "name": "raspberrypi_zero", + "description": "Build preset for the raspberrypi_zero board", + "configurePreset": "raspberrypi_zero" + }, + { + "name": "raspberrypi_zero2", + "description": "Build preset for the raspberrypi_zero2 board", + "configurePreset": "raspberrypi_zero2" + }, + { + "name": "samd11_xplained", + "description": "Build preset for the samd11_xplained board", + "configurePreset": "samd11_xplained" + }, + { + "name": "same54_xplained", + "description": "Build preset for the same54_xplained board", + "configurePreset": "same54_xplained" + }, + { + "name": "samg55_xplained", + "description": "Build preset for the samg55_xplained board", + "configurePreset": "samg55_xplained" + }, + { + "name": "saml22_feather", + "description": "Build preset for the saml22_feather board", + "configurePreset": "saml22_feather" + }, + { + "name": "seeeduino_xiao", + "description": "Build preset for the seeeduino_xiao board", + "configurePreset": "seeeduino_xiao" + }, + { + "name": "sensorwatch_m0", + "description": "Build preset for the sensorwatch_m0 board", + "configurePreset": "sensorwatch_m0" + }, + { + "name": "sipeed_longan_nano", + "description": "Build preset for the sipeed_longan_nano board", + "configurePreset": "sipeed_longan_nano" + }, + { + "name": "sparkfun_samd21_mini_usb", + "description": "Build preset for the sparkfun_samd21_mini_usb board", + "configurePreset": "sparkfun_samd21_mini_usb" + }, + { + "name": "stlinkv3mini", + "description": "Build preset for the stlinkv3mini board", + "configurePreset": "stlinkv3mini" + }, + { + "name": "stm32c071nucleo", + "description": "Build preset for the stm32c071nucleo board", + "configurePreset": "stm32c071nucleo" + }, + { + "name": "stm32f070rbnucleo", + "description": "Build preset for the stm32f070rbnucleo board", + "configurePreset": "stm32f070rbnucleo" + }, + { + "name": "stm32f072disco", + "description": "Build preset for the stm32f072disco board", + "configurePreset": "stm32f072disco" + }, + { + "name": "stm32f072eval", + "description": "Build preset for the stm32f072eval board", + "configurePreset": "stm32f072eval" + }, + { + "name": "stm32f103_bluepill", + "description": "Build preset for the stm32f103_bluepill board", + "configurePreset": "stm32f103_bluepill" + }, + { + "name": "stm32f103_mini_2", + "description": "Build preset for the stm32f103_mini_2 board", + "configurePreset": "stm32f103_mini_2" + }, + { + "name": "stm32f103ze_iar", + "description": "Build preset for the stm32f103ze_iar board", + "configurePreset": "stm32f103ze_iar" + }, + { + "name": "stm32f207nucleo", + "description": "Build preset for the stm32f207nucleo board", + "configurePreset": "stm32f207nucleo" + }, + { + "name": "stm32f303disco", + "description": "Build preset for the stm32f303disco board", + "configurePreset": "stm32f303disco" + }, + { + "name": "stm32f401blackpill", + "description": "Build preset for the stm32f401blackpill board", + "configurePreset": "stm32f401blackpill" + }, + { + "name": "stm32f407blackvet", + "description": "Build preset for the stm32f407blackvet board", + "configurePreset": "stm32f407blackvet" + }, + { + "name": "stm32f407disco", + "description": "Build preset for the stm32f407disco board", + "configurePreset": "stm32f407disco" + }, + { + "name": "stm32f411blackpill", + "description": "Build preset for the stm32f411blackpill board", + "configurePreset": "stm32f411blackpill" + }, + { + "name": "stm32f411disco", + "description": "Build preset for the stm32f411disco board", + "configurePreset": "stm32f411disco" + }, + { + "name": "stm32f412disco", + "description": "Build preset for the stm32f412disco board", + "configurePreset": "stm32f412disco" + }, + { + "name": "stm32f412nucleo", + "description": "Build preset for the stm32f412nucleo board", + "configurePreset": "stm32f412nucleo" + }, + { + "name": "stm32f439nucleo", + "description": "Build preset for the stm32f439nucleo board", + "configurePreset": "stm32f439nucleo" + }, + { + "name": "stm32f723disco", + "description": "Build preset for the stm32f723disco board", + "configurePreset": "stm32f723disco" + }, + { + "name": "stm32f746disco", + "description": "Build preset for the stm32f746disco board", + "configurePreset": "stm32f746disco" + }, + { + "name": "stm32f746nucleo", + "description": "Build preset for the stm32f746nucleo board", + "configurePreset": "stm32f746nucleo" + }, + { + "name": "stm32f767nucleo", + "description": "Build preset for the stm32f767nucleo board", + "configurePreset": "stm32f767nucleo" + }, + { + "name": "stm32f769disco", + "description": "Build preset for the stm32f769disco board", + "configurePreset": "stm32f769disco" + }, + { + "name": "stm32g0b1nucleo", + "description": "Build preset for the stm32g0b1nucleo board", + "configurePreset": "stm32g0b1nucleo" + }, + { + "name": "stm32g474nucleo", + "description": "Build preset for the stm32g474nucleo board", + "configurePreset": "stm32g474nucleo" + }, + { + "name": "stm32g491nucleo", + "description": "Build preset for the stm32g491nucleo board", + "configurePreset": "stm32g491nucleo" + }, + { + "name": "stm32h503nucleo", + "description": "Build preset for the stm32h503nucleo board", + "configurePreset": "stm32h503nucleo" + }, + { + "name": "stm32h563nucleo", + "description": "Build preset for the stm32h563nucleo board", + "configurePreset": "stm32h563nucleo" + }, + { + "name": "stm32h573i_dk", + "description": "Build preset for the stm32h573i_dk board", + "configurePreset": "stm32h573i_dk" + }, + { + "name": "stm32h723nucleo", + "description": "Build preset for the stm32h723nucleo board", + "configurePreset": "stm32h723nucleo" + }, + { + "name": "stm32h743eval", + "description": "Build preset for the stm32h743eval board", + "configurePreset": "stm32h743eval" + }, + { + "name": "stm32h743nucleo", + "description": "Build preset for the stm32h743nucleo board", + "configurePreset": "stm32h743nucleo" + }, + { + "name": "stm32h745disco", + "description": "Build preset for the stm32h745disco board", + "configurePreset": "stm32h745disco" + }, + { + "name": "stm32h750_weact", + "description": "Build preset for the stm32h750_weact board", + "configurePreset": "stm32h750_weact" + }, + { + "name": "stm32h750bdk", + "description": "Build preset for the stm32h750bdk board", + "configurePreset": "stm32h750bdk" + }, + { + "name": "stm32h7s3nucleo", + "description": "Build preset for the stm32h7s3nucleo board", + "configurePreset": "stm32h7s3nucleo" + }, + { + "name": "stm32l052dap52", + "description": "Build preset for the stm32l052dap52 board", + "configurePreset": "stm32l052dap52" + }, + { + "name": "stm32l0538disco", + "description": "Build preset for the stm32l0538disco board", + "configurePreset": "stm32l0538disco" + }, + { + "name": "stm32l412nucleo", + "description": "Build preset for the stm32l412nucleo board", + "configurePreset": "stm32l412nucleo" + }, + { + "name": "stm32l476disco", + "description": "Build preset for the stm32l476disco board", + "configurePreset": "stm32l476disco" + }, + { + "name": "stm32l4p5nucleo", + "description": "Build preset for the stm32l4p5nucleo board", + "configurePreset": "stm32l4p5nucleo" + }, + { + "name": "stm32l4r5nucleo", + "description": "Build preset for the stm32l4r5nucleo board", + "configurePreset": "stm32l4r5nucleo" + }, + { + "name": "stm32u545nucleo", + "description": "Build preset for the stm32u545nucleo board", + "configurePreset": "stm32u545nucleo" + }, + { + "name": "stm32u575eval", + "description": "Build preset for the stm32u575eval board", + "configurePreset": "stm32u575eval" + }, + { + "name": "stm32u575nucleo", + "description": "Build preset for the stm32u575nucleo board", + "configurePreset": "stm32u575nucleo" + }, + { + "name": "stm32u5a5nucleo", + "description": "Build preset for the stm32u5a5nucleo board", + "configurePreset": "stm32u5a5nucleo" + }, + { + "name": "stm32wb55nucleo", + "description": "Build preset for the stm32wb55nucleo board", + "configurePreset": "stm32wb55nucleo" + }, + { + "name": "teensy_35", + "description": "Build preset for the teensy_35 board", + "configurePreset": "teensy_35" + }, + { + "name": "teensy_40", + "description": "Build preset for the teensy_40 board", + "configurePreset": "teensy_40" + }, + { + "name": "teensy_41", + "description": "Build preset for the teensy_41 board", + "configurePreset": "teensy_41" + }, + { + "name": "trinket_m0", + "description": "Build preset for the trinket_m0 board", + "configurePreset": "trinket_m0" + }, + { + "name": "uno_r4", + "description": "Build preset for the uno_r4 board", + "configurePreset": "uno_r4" + }, + { + "name": "waveshare_openh743i", + "description": "Build preset for the waveshare_openh743i board", + "configurePreset": "waveshare_openh743i" + }, + { + "name": "xmc4500_relax", + "description": "Build preset for the xmc4500_relax board", + "configurePreset": "xmc4500_relax" + }, + { + "name": "xmc4700_relax", + "description": "Build preset for the xmc4700_relax board", + "configurePreset": "xmc4700_relax" + } + ], + "workflowPresets": [ + { + "name": "adafruit_clue", + "steps": [ + { + "type": "configure", + "name": "adafruit_clue" + }, + { + "type": "build", + "name": "adafruit_clue" + } + ] + }, + { + "name": "adafruit_feather_esp32_v2", + "steps": [ + { + "type": "configure", + "name": "adafruit_feather_esp32_v2" + }, + { + "type": "build", + "name": "adafruit_feather_esp32_v2" + } + ] + }, + { + "name": "adafruit_feather_esp32s2", + "steps": [ + { + "type": "configure", + "name": "adafruit_feather_esp32s2" + }, + { + "type": "build", + "name": "adafruit_feather_esp32s2" + } + ] + }, + { + "name": "adafruit_feather_esp32s3", + "steps": [ + { + "type": "configure", + "name": "adafruit_feather_esp32s3" + }, + { + "type": "build", + "name": "adafruit_feather_esp32s3" + } + ] + }, + { + "name": "adafruit_magtag_29gray", + "steps": [ + { + "type": "configure", + "name": "adafruit_magtag_29gray" + }, + { + "type": "build", + "name": "adafruit_magtag_29gray" + } + ] + }, + { + "name": "adafruit_metro_esp32s2", + "steps": [ + { + "type": "configure", + "name": "adafruit_metro_esp32s2" + }, + { + "type": "build", + "name": "adafruit_metro_esp32s2" + } + ] + }, + { + "name": "apard32690", + "steps": [ + { + "type": "configure", + "name": "apard32690" + }, + { + "type": "build", + "name": "apard32690" + } + ] + }, + { + "name": "arduino_nano33_ble", + "steps": [ + { + "type": "configure", + "name": "arduino_nano33_ble" + }, + { + "type": "build", + "name": "arduino_nano33_ble" + } + ] + }, + { + "name": "atsamd21_xpro", + "steps": [ + { + "type": "configure", + "name": "atsamd21_xpro" + }, + { + "type": "build", + "name": "atsamd21_xpro" + } + ] + }, + { + "name": "atsaml21_xpro", + "steps": [ + { + "type": "configure", + "name": "atsaml21_xpro" + }, + { + "type": "build", + "name": "atsaml21_xpro" + } + ] + }, + { + "name": "b_g474e_dpow1", + "steps": [ + { + "type": "configure", + "name": "b_g474e_dpow1" + }, + { + "type": "build", + "name": "b_g474e_dpow1" + } + ] + }, + { + "name": "b_u585i_iot2a", + "steps": [ + { + "type": "configure", + "name": "b_u585i_iot2a" + }, + { + "type": "build", + "name": "b_u585i_iot2a" + } + ] + }, + { + "name": "ch32v103r_r1_1v0", + "steps": [ + { + "type": "configure", + "name": "ch32v103r_r1_1v0" + }, + { + "type": "build", + "name": "ch32v103r_r1_1v0" + } + ] + }, + { + "name": "ch32v203c_r0_1v0", + "steps": [ + { + "type": "configure", + "name": "ch32v203c_r0_1v0" + }, + { + "type": "build", + "name": "ch32v203c_r0_1v0" + } + ] + }, + { + "name": "ch32v203g_r0_1v0", + "steps": [ + { + "type": "configure", + "name": "ch32v203g_r0_1v0" + }, + { + "type": "build", + "name": "ch32v203g_r0_1v0" + } + ] + }, + { + "name": "ch32v307v_r1_1v0", + "steps": [ + { + "type": "configure", + "name": "ch32v307v_r1_1v0" + }, + { + "type": "build", + "name": "ch32v307v_r1_1v0" + } + ] + }, + { + "name": "circuitplayground_bluefruit", + "steps": [ + { + "type": "configure", + "name": "circuitplayground_bluefruit" + }, + { + "type": "build", + "name": "circuitplayground_bluefruit" + } + ] + }, + { + "name": "circuitplayground_express", + "steps": [ + { + "type": "configure", + "name": "circuitplayground_express" + }, + { + "type": "build", + "name": "circuitplayground_express" + } + ] + }, + { + "name": "curiosity_nano", + "steps": [ + { + "type": "configure", + "name": "curiosity_nano" + }, + { + "type": "build", + "name": "curiosity_nano" + } + ] + }, + { + "name": "cynthion_d11", + "steps": [ + { + "type": "configure", + "name": "cynthion_d11" + }, + { + "type": "build", + "name": "cynthion_d11" + } + ] + }, + { + "name": "cynthion_d21", + "steps": [ + { + "type": "configure", + "name": "cynthion_d21" + }, + { + "type": "build", + "name": "cynthion_d21" + } + ] + }, + { + "name": "d5035_01", + "steps": [ + { + "type": "configure", + "name": "d5035_01" + }, + { + "type": "build", + "name": "d5035_01" + } + ] + }, + { + "name": "da14695_dk_usb", + "steps": [ + { + "type": "configure", + "name": "da14695_dk_usb" + }, + { + "type": "build", + "name": "da14695_dk_usb" + } + ] + }, + { + "name": "da1469x_dk_pro", + "steps": [ + { + "type": "configure", + "name": "da1469x_dk_pro" + }, + { + "type": "build", + "name": "da1469x_dk_pro" + } + ] + }, + { + "name": "daisyseed", + "steps": [ + { + "type": "configure", + "name": "daisyseed" + }, + { + "type": "build", + "name": "daisyseed" + } + ] + }, + { + "name": "double_m33_express", + "steps": [ + { + "type": "configure", + "name": "double_m33_express" + }, + { + "type": "build", + "name": "double_m33_express" + } + ] + }, + { + "name": "ea4088_quickstart", + "steps": [ + { + "type": "configure", + "name": "ea4088_quickstart" + }, + { + "type": "build", + "name": "ea4088_quickstart" + } + ] + }, + { + "name": "ea4357", + "steps": [ + { + "type": "configure", + "name": "ea4357" + }, + { + "type": "build", + "name": "ea4357" + } + ] + }, + { + "name": "ek_tm4c123gxl", + "steps": [ + { + "type": "configure", + "name": "ek_tm4c123gxl" + }, + { + "type": "build", + "name": "ek_tm4c123gxl" + } + ] + }, + { + "name": "espressif_addax_1", + "steps": [ + { + "type": "configure", + "name": "espressif_addax_1" + }, + { + "type": "build", + "name": "espressif_addax_1" + } + ] + }, + { + "name": "espressif_c3_devkitc", + "steps": [ + { + "type": "configure", + "name": "espressif_c3_devkitc" + }, + { + "type": "build", + "name": "espressif_c3_devkitc" + } + ] + }, + { + "name": "espressif_c6_devkitc", + "steps": [ + { + "type": "configure", + "name": "espressif_c6_devkitc" + }, + { + "type": "build", + "name": "espressif_c6_devkitc" + } + ] + }, + { + "name": "espressif_kaluga_1", + "steps": [ + { + "type": "configure", + "name": "espressif_kaluga_1" + }, + { + "type": "build", + "name": "espressif_kaluga_1" + } + ] + }, + { + "name": "espressif_p4_function_ev", + "steps": [ + { + "type": "configure", + "name": "espressif_p4_function_ev" + }, + { + "type": "build", + "name": "espressif_p4_function_ev" + } + ] + }, + { + "name": "espressif_s2_devkitc", + "steps": [ + { + "type": "configure", + "name": "espressif_s2_devkitc" + }, + { + "type": "build", + "name": "espressif_s2_devkitc" + } + ] + }, + { + "name": "espressif_s3_devkitc", + "steps": [ + { + "type": "configure", + "name": "espressif_s3_devkitc" + }, + { + "type": "build", + "name": "espressif_s3_devkitc" + } + ] + }, + { + "name": "espressif_s3_devkitm", + "steps": [ + { + "type": "configure", + "name": "espressif_s3_devkitm" + }, + { + "type": "build", + "name": "espressif_s3_devkitm" + } + ] + }, + { + "name": "espressif_saola_1", + "steps": [ + { + "type": "configure", + "name": "espressif_saola_1" + }, + { + "type": "build", + "name": "espressif_saola_1" + } + ] + }, + { + "name": "f1c100s", + "steps": [ + { + "type": "configure", + "name": "f1c100s" + }, + { + "type": "build", + "name": "f1c100s" + } + ] + }, + { + "name": "feather_m0_express", + "steps": [ + { + "type": "configure", + "name": "feather_m0_express" + }, + { + "type": "build", + "name": "feather_m0_express" + } + ] + }, + { + "name": "feather_m4_express", + "steps": [ + { + "type": "configure", + "name": "feather_m4_express" + }, + { + "type": "build", + "name": "feather_m4_express" + } + ] + }, + { + "name": "feather_nrf52840_express", + "steps": [ + { + "type": "configure", + "name": "feather_nrf52840_express" + }, + { + "type": "build", + "name": "feather_nrf52840_express" + } + ] + }, + { + "name": "feather_nrf52840_sense", + "steps": [ + { + "type": "configure", + "name": "feather_nrf52840_sense" + }, + { + "type": "build", + "name": "feather_nrf52840_sense" + } + ] + }, + { + "name": "feather_rp2040_max3421", + "steps": [ + { + "type": "configure", + "name": "feather_rp2040_max3421" + }, + { + "type": "build", + "name": "feather_rp2040_max3421" + } + ] + }, + { + "name": "feather_stm32f405", + "steps": [ + { + "type": "configure", + "name": "feather_stm32f405" + }, + { + "type": "build", + "name": "feather_stm32f405" + } + ] + }, + { + "name": "fomu", + "steps": [ + { + "type": "configure", + "name": "fomu" + }, + { + "type": "build", + "name": "fomu" + } + ] + }, + { + "name": "frdm_k32l2a4s", + "steps": [ + { + "type": "configure", + "name": "frdm_k32l2a4s" + }, + { + "type": "build", + "name": "frdm_k32l2a4s" + } + ] + }, + { + "name": "frdm_k32l2b", + "steps": [ + { + "type": "configure", + "name": "frdm_k32l2b" + }, + { + "type": "build", + "name": "frdm_k32l2b" + } + ] + }, + { + "name": "frdm_k64f", + "steps": [ + { + "type": "configure", + "name": "frdm_k64f" + }, + { + "type": "build", + "name": "frdm_k64f" + } + ] + }, + { + "name": "frdm_kl25z", + "steps": [ + { + "type": "configure", + "name": "frdm_kl25z" + }, + { + "type": "build", + "name": "frdm_kl25z" + } + ] + }, + { + "name": "frdm_mcxa153", + "steps": [ + { + "type": "configure", + "name": "frdm_mcxa153" + }, + { + "type": "build", + "name": "frdm_mcxa153" + } + ] + }, + { + "name": "frdm_mcxn947", + "steps": [ + { + "type": "configure", + "name": "frdm_mcxn947" + }, + { + "type": "build", + "name": "frdm_mcxn947" + } + ] + }, + { + "name": "itsybitsy_m0", + "steps": [ + { + "type": "configure", + "name": "itsybitsy_m0" + }, + { + "type": "build", + "name": "itsybitsy_m0" + } + ] + }, + { + "name": "itsybitsy_m4", + "steps": [ + { + "type": "configure", + "name": "itsybitsy_m4" + }, + { + "type": "build", + "name": "itsybitsy_m4" + } + ] + }, + { + "name": "itsybitsy_nrf52840", + "steps": [ + { + "type": "configure", + "name": "itsybitsy_nrf52840" + }, + { + "type": "build", + "name": "itsybitsy_nrf52840" + } + ] + }, + { + "name": "kuiic", + "steps": [ + { + "type": "configure", + "name": "kuiic" + }, + { + "type": "build", + "name": "kuiic" + } + ] + }, + { + "name": "lpcxpresso11u37", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso11u37" + }, + { + "type": "build", + "name": "lpcxpresso11u37" + } + ] + }, + { + "name": "lpcxpresso11u68", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso11u68" + }, + { + "type": "build", + "name": "lpcxpresso11u68" + } + ] + }, + { + "name": "lpcxpresso1347", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso1347" + }, + { + "type": "build", + "name": "lpcxpresso1347" + } + ] + }, + { + "name": "lpcxpresso1549", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso1549" + }, + { + "type": "build", + "name": "lpcxpresso1549" + } + ] + }, + { + "name": "lpcxpresso1769", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso1769" + }, + { + "type": "build", + "name": "lpcxpresso1769" + } + ] + }, + { + "name": "lpcxpresso18s37", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso18s37" + }, + { + "type": "build", + "name": "lpcxpresso18s37" + } + ] + }, + { + "name": "lpcxpresso43s67", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso43s67" + }, + { + "type": "build", + "name": "lpcxpresso43s67" + } + ] + }, + { + "name": "lpcxpresso51u68", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso51u68" + }, + { + "type": "build", + "name": "lpcxpresso51u68" + } + ] + }, + { + "name": "lpcxpresso54114", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso54114" + }, + { + "type": "build", + "name": "lpcxpresso54114" + } + ] + }, + { + "name": "lpcxpresso54608", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso54608" + }, + { + "type": "build", + "name": "lpcxpresso54608" + } + ] + }, + { + "name": "lpcxpresso54628", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso54628" + }, + { + "type": "build", + "name": "lpcxpresso54628" + } + ] + }, + { + "name": "lpcxpresso55s28", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso55s28" + }, + { + "type": "build", + "name": "lpcxpresso55s28" + } + ] + }, + { + "name": "lpcxpresso55s69", + "steps": [ + { + "type": "configure", + "name": "lpcxpresso55s69" + }, + { + "type": "build", + "name": "lpcxpresso55s69" + } + ] + }, + { + "name": "max32650evkit", + "steps": [ + { + "type": "configure", + "name": "max32650evkit" + }, + { + "type": "build", + "name": "max32650evkit" + } + ] + }, + { + "name": "max32650fthr", + "steps": [ + { + "type": "configure", + "name": "max32650fthr" + }, + { + "type": "build", + "name": "max32650fthr" + } + ] + }, + { + "name": "max32651evkit", + "steps": [ + { + "type": "configure", + "name": "max32651evkit" + }, + { + "type": "build", + "name": "max32651evkit" + } + ] + }, + { + "name": "max32666evkit", + "steps": [ + { + "type": "configure", + "name": "max32666evkit" + }, + { + "type": "build", + "name": "max32666evkit" + } + ] + }, + { + "name": "max32666fthr", + "steps": [ + { + "type": "configure", + "name": "max32666fthr" + }, + { + "type": "build", + "name": "max32666fthr" + } + ] + }, + { + "name": "max32690evkit", + "steps": [ + { + "type": "configure", + "name": "max32690evkit" + }, + { + "type": "build", + "name": "max32690evkit" + } + ] + }, + { + "name": "max78002evkit", + "steps": [ + { + "type": "configure", + "name": "max78002evkit" + }, + { + "type": "build", + "name": "max78002evkit" + } + ] + }, + { + "name": "mbed1768", + "steps": [ + { + "type": "configure", + "name": "mbed1768" + }, + { + "type": "build", + "name": "mbed1768" + } + ] + }, + { + "name": "mcb1800", + "steps": [ + { + "type": "configure", + "name": "mcb1800" + }, + { + "type": "build", + "name": "mcb1800" + } + ] + }, + { + "name": "mcu_link", + "steps": [ + { + "type": "configure", + "name": "mcu_link" + }, + { + "type": "build", + "name": "mcu_link" + } + ] + }, + { + "name": "mcxn947brk", + "steps": [ + { + "type": "configure", + "name": "mcxn947brk" + }, + { + "type": "build", + "name": "mcxn947brk" + } + ] + }, + { + "name": "metro_m0_express", + "steps": [ + { + "type": "configure", + "name": "metro_m0_express" + }, + { + "type": "build", + "name": "metro_m0_express" + } + ] + }, + { + "name": "metro_m4_express", + "steps": [ + { + "type": "configure", + "name": "metro_m4_express" + }, + { + "type": "build", + "name": "metro_m4_express" + } + ] + }, + { + "name": "metro_m7_1011", + "steps": [ + { + "type": "configure", + "name": "metro_m7_1011" + }, + { + "type": "build", + "name": "metro_m7_1011" + } + ] + }, + { + "name": "metro_m7_1011_sd", + "steps": [ + { + "type": "configure", + "name": "metro_m7_1011_sd" + }, + { + "type": "build", + "name": "metro_m7_1011_sd" + } + ] + }, + { + "name": "mimxrt1010_evk", + "steps": [ + { + "type": "configure", + "name": "mimxrt1010_evk" + }, + { + "type": "build", + "name": "mimxrt1010_evk" + } + ] + }, + { + "name": "mimxrt1015_evk", + "steps": [ + { + "type": "configure", + "name": "mimxrt1015_evk" + }, + { + "type": "build", + "name": "mimxrt1015_evk" + } + ] + }, + { + "name": "mimxrt1020_evk", + "steps": [ + { + "type": "configure", + "name": "mimxrt1020_evk" + }, + { + "type": "build", + "name": "mimxrt1020_evk" + } + ] + }, + { + "name": "mimxrt1024_evk", + "steps": [ + { + "type": "configure", + "name": "mimxrt1024_evk" + }, + { + "type": "build", + "name": "mimxrt1024_evk" + } + ] + }, + { + "name": "mimxrt1050_evkb", + "steps": [ + { + "type": "configure", + "name": "mimxrt1050_evkb" + }, + { + "type": "build", + "name": "mimxrt1050_evkb" + } + ] + }, + { + "name": "mimxrt1060_evk", + "steps": [ + { + "type": "configure", + "name": "mimxrt1060_evk" + }, + { + "type": "build", + "name": "mimxrt1060_evk" + } + ] + }, + { + "name": "mimxrt1064_evk", + "steps": [ + { + "type": "configure", + "name": "mimxrt1064_evk" + }, + { + "type": "build", + "name": "mimxrt1064_evk" + } + ] + }, + { + "name": "mimxrt1170_evkb", + "steps": [ + { + "type": "configure", + "name": "mimxrt1170_evkb" + }, + { + "type": "build", + "name": "mimxrt1170_evkb" + } + ] + }, + { + "name": "mm32f327x_mb39", + "steps": [ + { + "type": "configure", + "name": "mm32f327x_mb39" + }, + { + "type": "build", + "name": "mm32f327x_mb39" + } + ] + }, + { + "name": "mm32f327x_pitaya_lite", + "steps": [ + { + "type": "configure", + "name": "mm32f327x_pitaya_lite" + }, + { + "type": "build", + "name": "mm32f327x_pitaya_lite" + } + ] + }, + { + "name": "msp_exp430f5529lp", + "steps": [ + { + "type": "configure", + "name": "msp_exp430f5529lp" + }, + { + "type": "build", + "name": "msp_exp430f5529lp" + } + ] + }, + { + "name": "msp_exp432e401y", + "steps": [ + { + "type": "configure", + "name": "msp_exp432e401y" + }, + { + "type": "build", + "name": "msp_exp432e401y" + } + ] + }, + { + "name": "nanoch32v203", + "steps": [ + { + "type": "configure", + "name": "nanoch32v203" + }, + { + "type": "build", + "name": "nanoch32v203" + } + ] + }, + { + "name": "pca10056", + "steps": [ + { + "type": "configure", + "name": "pca10056" + }, + { + "type": "build", + "name": "pca10056" + } + ] + }, + { + "name": "pca10059", + "steps": [ + { + "type": "configure", + "name": "pca10059" + }, + { + "type": "build", + "name": "pca10059" + } + ] + }, + { + "name": "pca10095", + "steps": [ + { + "type": "configure", + "name": "pca10095" + }, + { + "type": "build", + "name": "pca10095" + } + ] + }, + { + "name": "pca10100", + "steps": [ + { + "type": "configure", + "name": "pca10100" + }, + { + "type": "build", + "name": "pca10100" + } + ] + }, + { + "name": "pico_sdk", + "steps": [ + { + "type": "configure", + "name": "pico_sdk" + }, + { + "type": "build", + "name": "pico_sdk" + } + ] + }, + { + "name": "portenta_c33", + "steps": [ + { + "type": "configure", + "name": "portenta_c33" + }, + { + "type": "build", + "name": "portenta_c33" + } + ] + }, + { + "name": "pybadge", + "steps": [ + { + "type": "configure", + "name": "pybadge" + }, + { + "type": "build", + "name": "pybadge" + } + ] + }, + { + "name": "pyboardv11", + "steps": [ + { + "type": "configure", + "name": "pyboardv11" + }, + { + "type": "build", + "name": "pyboardv11" + } + ] + }, + { + "name": "pyportal", + "steps": [ + { + "type": "configure", + "name": "pyportal" + }, + { + "type": "build", + "name": "pyportal" + } + ] + }, + { + "name": "qtpy", + "steps": [ + { + "type": "configure", + "name": "qtpy" + }, + { + "type": "build", + "name": "qtpy" + } + ] + }, + { + "name": "ra2a1_ek", + "steps": [ + { + "type": "configure", + "name": "ra2a1_ek" + }, + { + "type": "build", + "name": "ra2a1_ek" + } + ] + }, + { + "name": "ra4m1_ek", + "steps": [ + { + "type": "configure", + "name": "ra4m1_ek" + }, + { + "type": "build", + "name": "ra4m1_ek" + } + ] + }, + { + "name": "ra4m3_ek", + "steps": [ + { + "type": "configure", + "name": "ra4m3_ek" + }, + { + "type": "build", + "name": "ra4m3_ek" + } + ] + }, + { + "name": "ra6m1_ek", + "steps": [ + { + "type": "configure", + "name": "ra6m1_ek" + }, + { + "type": "build", + "name": "ra6m1_ek" + } + ] + }, + { + "name": "ra6m5_ek", + "steps": [ + { + "type": "configure", + "name": "ra6m5_ek" + }, + { + "type": "build", + "name": "ra6m5_ek" + } + ] + }, + { + "name": "ra8m1_ek", + "steps": [ + { + "type": "configure", + "name": "ra8m1_ek" + }, + { + "type": "build", + "name": "ra8m1_ek" + } + ] + }, + { + "name": "raspberry_pi_pico", + "steps": [ + { + "type": "configure", + "name": "raspberry_pi_pico" + }, + { + "type": "build", + "name": "raspberry_pi_pico" + } + ] + }, + { + "name": "raspberry_pi_pico2", + "steps": [ + { + "type": "configure", + "name": "raspberry_pi_pico2" + }, + { + "type": "build", + "name": "raspberry_pi_pico2" + } + ] + }, + { + "name": "raspberrypi_cm4", + "steps": [ + { + "type": "configure", + "name": "raspberrypi_cm4" + }, + { + "type": "build", + "name": "raspberrypi_cm4" + } + ] + }, + { + "name": "raspberrypi_zero", + "steps": [ + { + "type": "configure", + "name": "raspberrypi_zero" + }, + { + "type": "build", + "name": "raspberrypi_zero" + } + ] + }, + { + "name": "raspberrypi_zero2", + "steps": [ + { + "type": "configure", + "name": "raspberrypi_zero2" + }, + { + "type": "build", + "name": "raspberrypi_zero2" + } + ] + }, + { + "name": "samd11_xplained", + "steps": [ + { + "type": "configure", + "name": "samd11_xplained" + }, + { + "type": "build", + "name": "samd11_xplained" + } + ] + }, + { + "name": "same54_xplained", + "steps": [ + { + "type": "configure", + "name": "same54_xplained" + }, + { + "type": "build", + "name": "same54_xplained" + } + ] + }, + { + "name": "samg55_xplained", + "steps": [ + { + "type": "configure", + "name": "samg55_xplained" + }, + { + "type": "build", + "name": "samg55_xplained" + } + ] + }, + { + "name": "saml22_feather", + "steps": [ + { + "type": "configure", + "name": "saml22_feather" + }, + { + "type": "build", + "name": "saml22_feather" + } + ] + }, + { + "name": "seeeduino_xiao", + "steps": [ + { + "type": "configure", + "name": "seeeduino_xiao" + }, + { + "type": "build", + "name": "seeeduino_xiao" + } + ] + }, + { + "name": "sensorwatch_m0", + "steps": [ + { + "type": "configure", + "name": "sensorwatch_m0" + }, + { + "type": "build", + "name": "sensorwatch_m0" + } + ] + }, + { + "name": "sipeed_longan_nano", + "steps": [ + { + "type": "configure", + "name": "sipeed_longan_nano" + }, + { + "type": "build", + "name": "sipeed_longan_nano" + } + ] + }, + { + "name": "sparkfun_samd21_mini_usb", + "steps": [ + { + "type": "configure", + "name": "sparkfun_samd21_mini_usb" + }, + { + "type": "build", + "name": "sparkfun_samd21_mini_usb" + } + ] + }, + { + "name": "stlinkv3mini", + "steps": [ + { + "type": "configure", + "name": "stlinkv3mini" + }, + { + "type": "build", + "name": "stlinkv3mini" + } + ] + }, + { + "name": "stm32c071nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32c071nucleo" + }, + { + "type": "build", + "name": "stm32c071nucleo" + } + ] + }, + { + "name": "stm32f070rbnucleo", + "steps": [ + { + "type": "configure", + "name": "stm32f070rbnucleo" + }, + { + "type": "build", + "name": "stm32f070rbnucleo" + } + ] + }, + { + "name": "stm32f072disco", + "steps": [ + { + "type": "configure", + "name": "stm32f072disco" + }, + { + "type": "build", + "name": "stm32f072disco" + } + ] + }, + { + "name": "stm32f072eval", + "steps": [ + { + "type": "configure", + "name": "stm32f072eval" + }, + { + "type": "build", + "name": "stm32f072eval" + } + ] + }, + { + "name": "stm32f103_bluepill", + "steps": [ + { + "type": "configure", + "name": "stm32f103_bluepill" + }, + { + "type": "build", + "name": "stm32f103_bluepill" + } + ] + }, + { + "name": "stm32f103_mini_2", + "steps": [ + { + "type": "configure", + "name": "stm32f103_mini_2" + }, + { + "type": "build", + "name": "stm32f103_mini_2" + } + ] + }, + { + "name": "stm32f103ze_iar", + "steps": [ + { + "type": "configure", + "name": "stm32f103ze_iar" + }, + { + "type": "build", + "name": "stm32f103ze_iar" + } + ] + }, + { + "name": "stm32f207nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32f207nucleo" + }, + { + "type": "build", + "name": "stm32f207nucleo" + } + ] + }, + { + "name": "stm32f303disco", + "steps": [ + { + "type": "configure", + "name": "stm32f303disco" + }, + { + "type": "build", + "name": "stm32f303disco" + } + ] + }, + { + "name": "stm32f401blackpill", + "steps": [ + { + "type": "configure", + "name": "stm32f401blackpill" + }, + { + "type": "build", + "name": "stm32f401blackpill" + } + ] + }, + { + "name": "stm32f407blackvet", + "steps": [ + { + "type": "configure", + "name": "stm32f407blackvet" + }, + { + "type": "build", + "name": "stm32f407blackvet" + } + ] + }, + { + "name": "stm32f407disco", + "steps": [ + { + "type": "configure", + "name": "stm32f407disco" + }, + { + "type": "build", + "name": "stm32f407disco" + } + ] + }, + { + "name": "stm32f411blackpill", + "steps": [ + { + "type": "configure", + "name": "stm32f411blackpill" + }, + { + "type": "build", + "name": "stm32f411blackpill" + } + ] + }, + { + "name": "stm32f411disco", + "steps": [ + { + "type": "configure", + "name": "stm32f411disco" + }, + { + "type": "build", + "name": "stm32f411disco" + } + ] + }, + { + "name": "stm32f412disco", + "steps": [ + { + "type": "configure", + "name": "stm32f412disco" + }, + { + "type": "build", + "name": "stm32f412disco" + } + ] + }, + { + "name": "stm32f412nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32f412nucleo" + }, + { + "type": "build", + "name": "stm32f412nucleo" + } + ] + }, + { + "name": "stm32f439nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32f439nucleo" + }, + { + "type": "build", + "name": "stm32f439nucleo" + } + ] + }, + { + "name": "stm32f723disco", + "steps": [ + { + "type": "configure", + "name": "stm32f723disco" + }, + { + "type": "build", + "name": "stm32f723disco" + } + ] + }, + { + "name": "stm32f746disco", + "steps": [ + { + "type": "configure", + "name": "stm32f746disco" + }, + { + "type": "build", + "name": "stm32f746disco" + } + ] + }, + { + "name": "stm32f746nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32f746nucleo" + }, + { + "type": "build", + "name": "stm32f746nucleo" + } + ] + }, + { + "name": "stm32f767nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32f767nucleo" + }, + { + "type": "build", + "name": "stm32f767nucleo" + } + ] + }, + { + "name": "stm32f769disco", + "steps": [ + { + "type": "configure", + "name": "stm32f769disco" + }, + { + "type": "build", + "name": "stm32f769disco" + } + ] + }, + { + "name": "stm32g0b1nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32g0b1nucleo" + }, + { + "type": "build", + "name": "stm32g0b1nucleo" + } + ] + }, + { + "name": "stm32g474nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32g474nucleo" + }, + { + "type": "build", + "name": "stm32g474nucleo" + } + ] + }, + { + "name": "stm32g491nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32g491nucleo" + }, + { + "type": "build", + "name": "stm32g491nucleo" + } + ] + }, + { + "name": "stm32h503nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32h503nucleo" + }, + { + "type": "build", + "name": "stm32h503nucleo" + } + ] + }, + { + "name": "stm32h563nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32h563nucleo" + }, + { + "type": "build", + "name": "stm32h563nucleo" + } + ] + }, + { + "name": "stm32h573i_dk", + "steps": [ + { + "type": "configure", + "name": "stm32h573i_dk" + }, + { + "type": "build", + "name": "stm32h573i_dk" + } + ] + }, + { + "name": "stm32h723nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32h723nucleo" + }, + { + "type": "build", + "name": "stm32h723nucleo" + } + ] + }, + { + "name": "stm32h743eval", + "steps": [ + { + "type": "configure", + "name": "stm32h743eval" + }, + { + "type": "build", + "name": "stm32h743eval" + } + ] + }, + { + "name": "stm32h743nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32h743nucleo" + }, + { + "type": "build", + "name": "stm32h743nucleo" + } + ] + }, + { + "name": "stm32h745disco", + "steps": [ + { + "type": "configure", + "name": "stm32h745disco" + }, + { + "type": "build", + "name": "stm32h745disco" + } + ] + }, + { + "name": "stm32h750_weact", + "steps": [ + { + "type": "configure", + "name": "stm32h750_weact" + }, + { + "type": "build", + "name": "stm32h750_weact" + } + ] + }, + { + "name": "stm32h750bdk", + "steps": [ + { + "type": "configure", + "name": "stm32h750bdk" + }, + { + "type": "build", + "name": "stm32h750bdk" + } + ] + }, + { + "name": "stm32h7s3nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32h7s3nucleo" + }, + { + "type": "build", + "name": "stm32h7s3nucleo" + } + ] + }, + { + "name": "stm32l052dap52", + "steps": [ + { + "type": "configure", + "name": "stm32l052dap52" + }, + { + "type": "build", + "name": "stm32l052dap52" + } + ] + }, + { + "name": "stm32l0538disco", + "steps": [ + { + "type": "configure", + "name": "stm32l0538disco" + }, + { + "type": "build", + "name": "stm32l0538disco" + } + ] + }, + { + "name": "stm32l412nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32l412nucleo" + }, + { + "type": "build", + "name": "stm32l412nucleo" + } + ] + }, + { + "name": "stm32l476disco", + "steps": [ + { + "type": "configure", + "name": "stm32l476disco" + }, + { + "type": "build", + "name": "stm32l476disco" + } + ] + }, + { + "name": "stm32l4p5nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32l4p5nucleo" + }, + { + "type": "build", + "name": "stm32l4p5nucleo" + } + ] + }, + { + "name": "stm32l4r5nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32l4r5nucleo" + }, + { + "type": "build", + "name": "stm32l4r5nucleo" + } + ] + }, + { + "name": "stm32u545nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32u545nucleo" + }, + { + "type": "build", + "name": "stm32u545nucleo" + } + ] + }, + { + "name": "stm32u575eval", + "steps": [ + { + "type": "configure", + "name": "stm32u575eval" + }, + { + "type": "build", + "name": "stm32u575eval" + } + ] + }, + { + "name": "stm32u575nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32u575nucleo" + }, + { + "type": "build", + "name": "stm32u575nucleo" + } + ] + }, + { + "name": "stm32u5a5nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32u5a5nucleo" + }, + { + "type": "build", + "name": "stm32u5a5nucleo" + } + ] + }, + { + "name": "stm32wb55nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32wb55nucleo" + }, + { + "type": "build", + "name": "stm32wb55nucleo" + } + ] + }, + { + "name": "teensy_35", + "steps": [ + { + "type": "configure", + "name": "teensy_35" + }, + { + "type": "build", + "name": "teensy_35" + } + ] + }, + { + "name": "teensy_40", + "steps": [ + { + "type": "configure", + "name": "teensy_40" + }, + { + "type": "build", + "name": "teensy_40" + } + ] + }, + { + "name": "teensy_41", + "steps": [ + { + "type": "configure", + "name": "teensy_41" + }, + { + "type": "build", + "name": "teensy_41" + } + ] + }, + { + "name": "trinket_m0", + "steps": [ + { + "type": "configure", + "name": "trinket_m0" + }, + { + "type": "build", + "name": "trinket_m0" + } + ] + }, + { + "name": "uno_r4", + "steps": [ + { + "type": "configure", + "name": "uno_r4" + }, + { + "type": "build", + "name": "uno_r4" + } + ] + }, + { + "name": "waveshare_openh743i", + "steps": [ + { + "type": "configure", + "name": "waveshare_openh743i" + }, + { + "type": "build", + "name": "waveshare_openh743i" + } + ] + }, + { + "name": "xmc4500_relax", + "steps": [ + { + "type": "configure", + "name": "xmc4500_relax" + }, + { + "type": "build", + "name": "xmc4500_relax" + } + ] + }, + { + "name": "xmc4700_relax", + "steps": [ + { + "type": "configure", + "name": "xmc4700_relax" + }, + { + "type": "build", + "name": "xmc4700_relax" + } + ] + } + ] +} diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 5bcdb7f15..1ba5a1b9d 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -60,19 +60,29 @@ int sys_read(int fhdl, char *buf, size_t count) { int rd = (int) SEGGER_RTT_Read(0, buf, count); return (rd > 0) ? rd : -1; } - #endif #elif defined(LOGGER_SWO) -// Logging with SWO for ARM Cortex -#include "board_mcu.h" +#define ITM_BASE 0xE0000000 +#define ITM_STIM0 (*((volatile uint8_t*)(ITM_BASE + 0))) +#define ITM_TER *((volatile uint32_t*)(ITM_BASE + 0xE00)) +#define ITM_TCR *((volatile uint32_t*)(ITM_BASE + 0xE80)) + +#define ITM_TCR_ITMENA (1 << 0) + +// Logging with SWO for ARM Cortex-M int sys_write (int fhdl, const char *buf, size_t count) { (void) fhdl; uint8_t const* buf8 = (uint8_t const*) buf; - for(size_t i=0; i<count; i++) { - ITM_SendChar(buf8[i]); + if ((ITM_TCR & ITM_TCR_ITMENA) && (ITM_TER & 1ul)) { + for(size_t i=0; i < count; i++) { + while (!(ITM_STIM0 & 1ul)) { + asm("nop"); + } + ITM_STIM0 = buf8[i]; + } } return (int) count; @@ -138,6 +148,9 @@ int board_getchar(void) { return (sys_read(0, &c, 1) > 0) ? (int) c : (-1); } +void board_putchar(int c) { + sys_write(0, (const char*)&c, 1); +} uint32_t tusb_time_millis_api(void) { return board_millis(); @@ -146,7 +159,7 @@ uint32_t tusb_time_millis_api(void) { //-------------------------------------------------------------------- // FreeRTOS hooks //-------------------------------------------------------------------- -#if CFG_TUSB_OS == OPT_OS_FREERTOS && !TUSB_MCU_VENDOR_ESPRESSIF +#if CFG_TUSB_OS == OPT_OS_FREERTOS && !defined(ESP_PLATFORM) #include "FreeRTOS.h" #include "task.h" @@ -228,5 +241,4 @@ void vApplicationSetupTimerInterrupt(void) { } #endif - #endif diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h index eaee1ee97..328fe9363 100644 --- a/hw/bsp/board_api.h +++ b/hw/bsp/board_api.h @@ -38,22 +38,24 @@ extern "C" { #include "tusb.h" -#if CFG_TUSB_OS == OPT_OS_FREERTOS -#if TUSB_MCU_VENDOR_ESPRESSIF - // ESP-IDF need "freertos/" prefix in include path. - // CFG_TUSB_OS_INC_PATH should be defined accordingly. - #include "freertos/FreeRTOS.h" - #include "freertos/semphr.h" - #include "freertos/queue.h" - #include "freertos/task.h" - #include "freertos/timers.h" -#else - #include "FreeRTOS.h" - #include "semphr.h" - #include "queue.h" - #include "task.h" - #include "timers.h" -#endif +#if CFG_TUSB_OS == OPT_OS_ZEPHYR + #include <zephyr/kernel.h> +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + #ifdef ESP_PLATFORM + // ESP-IDF need "freertos/" prefix in include path. + // CFG_TUSB_OS_INC_PATH should be defined accordingly. + #include "freertos/FreeRTOS.h" + #include "freertos/semphr.h" + #include "freertos/queue.h" + #include "freertos/task.h" + #include "freertos/timers.h" + #else + #include "FreeRTOS.h" + #include "semphr.h" + #include "queue.h" + #include "task.h" + #include "timers.h" + #endif #endif // Define the default baudrate @@ -124,6 +126,10 @@ static inline uint32_t board_millis(void) { // Implement your own board_millis() in any of .c file uint32_t board_millis(void); +#elif CFG_TUSB_OS == OPT_OS_ZEPHYR +static inline uint32_t board_millis(void) { + return k_uptime_get_32(); +} #else #error "board_millis() is not implemented for this OS" #endif @@ -189,6 +195,7 @@ static inline void board_delay(uint32_t ms) { // stdio getchar() is blocking, this is non-blocking version int board_getchar(void); +void board_putchar(int c); #ifdef __cplusplus } diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h deleted file mode 100644 index e720cd747..000000000 --- a/hw/bsp/board_mcu.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_MCU_H_ -#define BOARD_MCU_H_ - -#include "tusb_option.h" - -//--------------------------------------------------------------------+ -// Low Level MCU header include. Example should be -// platform independent and mostly doesn't need to include this file. -// However there are still certain situation where this file is needed: -// - FreeRTOSConfig.h to set up correct clock and NVIC interrupts for ARM Cortex -// - SWO logging for Cortex M with ITM_SendChar() / ITM_ReceiveChar() -//--------------------------------------------------------------------+ - -// Include order follows OPT_MCU_ number -#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) || \ - TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC18XX) || \ - TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX) - #include "chip.h" - -#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9) - #include "fsl_device_registers.h" - -#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K) - #include "fsl_device_registers.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NRF5X - #include "nrf.h" - -#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ - CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ - CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21 - #include "sam.h" - -#elif CFG_TUSB_MCU == OPT_MCU_SAMG - #undef LITTLE_ENDIAN // hack to suppress "LITTLE_ENDIAN" redefined - #include "sam.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F0 - #include "stm32f0xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F1 - #include "stm32f1xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F2 - #include "stm32f2xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F3 - #include "stm32f3xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F4 - #include "stm32f4xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F7 - #include "stm32f7xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32G4 - #include "stm32g4xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32H5 - #include "stm32h5xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32H7 - #include "stm32h7xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L0 - #include "stm32l0xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L1 - #include "stm32l1xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L4 - #include "stm32l4xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32WB - #include "stm32wbxx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32U5 - #include "stm32u5xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32G0 - #include "stm32g0xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32C0 - #include "stm32c0xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_CXD56 - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_MSP430x5xx - #include "msp430.h" - -#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4 - #include "msp.h" - -#elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX - #include "fsl_device_registers.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NUC120 - #include "NUC100Series.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NUC121 || CFG_TUSB_MCU == OPT_MCU_NUC126 - #include "NuMicro.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NUC505 - #include "NUC505Series.h" - -#elif CFG_TUSB_MCU == OPT_MCU_ESP32S2 - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_ESP32S3 - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_DA1469X - #include "DA1469xAB.h" - -#elif CFG_TUSB_MCU == OPT_MCU_RP2040 - #include "pico.h" - -#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG - #include "em_device.h" - -#elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_RAXXX - #include "bsp_api.h" - -#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103 - #include "gd32vf103.h" - -#elif CFG_TUSB_MCU == OPT_MCU_MM32F327X - #include "mm32_device.h" - -#elif CFG_TUSB_MCU == OPT_MCU_XMC4000 - #include "xmc_device.h" - -#elif CFG_TUSB_MCU == OPT_MCU_TM4C123 - #include "TM4C123.h" - -#elif CFG_TUSB_MCU == OPT_MCU_CH32F20X - #include "ch32f20x.h" - -#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837) - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 - #include "max32690.h" - -#elif CFG_TUSB_MCU == OPT_MCU_MAX32650 - #include "max32650.h" - -#elif CFG_TUSB_MCU == OPT_MCU_MAX32666 - #include "max32665.h" - -#elif CFG_TUSB_MCU == OPT_MCU_MAX78002 - #include "max78002.h" - -#else - #error "Missing MCU header" -#endif - - -#endif /* BOARD_MCU_H_ */ diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake index 2b8cc19e0..616a83fe2 100644 --- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake +++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR arm1176jzf-s CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU arm1176jzf-s CACHE INTERNAL "System Processor") #set(SUFFIX "") function(update_board TARGET) diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h index 84a106346..40a9dd198 100644 --- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h +++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Raspberry Pi Zero + url: https://www.raspberrypi.org/products/raspberry-pi-zero/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c index 0062e2e83..f8f3b0b70 100644 --- a/hw/bsp/broadcom_32bit/family.c +++ b/hw/bsp/broadcom_32bit/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Raspberry Pi +*/ + #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/broadcom_32bit/family.cmake b/hw/bsp/broadcom_32bit/family.cmake index 93e7d3545..5e57d8b1e 100644 --- a/hw/bsp/broadcom_32bit/family.cmake +++ b/hw/bsp/broadcom_32bit/family.cmake @@ -94,17 +94,17 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_BCM2835 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_BCM2835) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/broadcom_32bit/family.mk b/hw/bsp/broadcom_32bit/family.mk index a282e9961..9d4a3b76c 100644 --- a/hw/bsp/broadcom_32bit/family.mk +++ b/hw/bsp/broadcom_32bit/family.mk @@ -15,7 +15,7 @@ CFLAGS += \ CROSS_COMPILE = arm-none-eabi- # mcu driver cause following warnings -CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls +CFLAGS_GCC += -Wno-error=cast-qual -Wno-error=redundant-decls SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake index 919068f1d..6f1fc0225 100644 --- a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake +++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-a72 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-a72 CACHE INTERNAL "System Processor") set(BCM_VERSION 2711) function(update_board TARGET) diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h index 84a106346..cadad2b27 100644 --- a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h +++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Raspberry CM4 + url: https://www.raspberrypi.org/products/compute-module-4 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake index 85f84e947..80747363a 100644 --- a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake +++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-a53 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-a53 CACHE INTERNAL "System Processor") set(BCM_VERSION 2837) function(update_board TARGET) diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h index 84a106346..e6caa0294 100644 --- a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h +++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Raspberry Zero2 + url: https://www.raspberrypi.org/products/raspberry-pi-zero-2-w +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c index 0062e2e83..f8f3b0b70 100644 --- a/hw/bsp/broadcom_64bit/family.c +++ b/hw/bsp/broadcom_64bit/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Raspberry Pi +*/ + #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/broadcom_64bit/family.cmake b/hw/bsp/broadcom_64bit/family.cmake index d790944bc..1a088c2c0 100644 --- a/hw/bsp/broadcom_64bit/family.cmake +++ b/hw/bsp/broadcom_64bit/family.cmake @@ -101,17 +101,17 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_BCM${BCM_VERSION} ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_BCM${BCM_VERSION}) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/broadcom_64bit/family.mk b/hw/bsp/broadcom_64bit/family.mk index 37d381f9f..1ce80e22b 100644 --- a/hw/bsp/broadcom_64bit/family.mk +++ b/hw/bsp/broadcom_64bit/family.mk @@ -14,7 +14,7 @@ CFLAGS += \ CROSS_COMPILE = aarch64-none-elf- # mcu driver cause following warnings -CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls +CFLAGS_GCC += -Wno-error=cast-qual -Wno-error=redundant-decls SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ diff --git a/hw/bsp/brtmm90x/boards/mm900evxb/board.h b/hw/bsp/brtmm90x/boards/mm900evxb/board.h index 771779108..623033c2c 100644 --- a/hw/bsp/brtmm90x/boards/mm900evxb/board.h +++ b/hw/bsp/brtmm90x/boards/mm900evxb/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MM900EVxB + url: https://brtchip.com/product/mm900ev1b +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c index 4d81e7d52..15ff4b8ee 100644 --- a/hw/bsp/brtmm90x/family.c +++ b/hw/bsp/brtmm90x/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Bridgetek +*/ + #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk index 6df0bfdfe..2de4dc760 100644 --- a/hw/bsp/brtmm90x/family.mk +++ b/hw/bsp/brtmm90x/family.mk @@ -13,7 +13,6 @@ else # The submodule BRTSG-FOSS/ft90x-sdk contains header files and source # code for the Bridgetek SDK. This can be used instead of the prebuilt # library. -DEPS_SUBMODULES += hw/mcu/bridgetek/ft9xx/ft90x-sdk # The SDK can be used to load specific files from the Bridgetek SDK. FT9XX_SDK = hw/mcu/bridgetek/ft9xx/ft90x-sdk/Source INC += "$(TOP)/$(FT9XX_SDK)/include" diff --git a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h index d5849bddb..b855804a9 100644 --- a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h +++ b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h @@ -22,6 +22,11 @@ * THE SOFTWARE. */ +/* metadata: + name: CH32F205r-r0 + url: https://github.com/openwch/ch32f20x +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/ch32f20x/family.c b/hw/bsp/ch32f20x/family.c index 9717832d6..7fef71d47 100644 --- a/hw/bsp/ch32f20x/family.c +++ b/hw/bsp/ch32f20x/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: WCH +*/ + #include "stdio.h" #include "debug_uart.h" diff --git a/hw/bsp/ch32f20x/family.mk b/hw/bsp/ch32f20x/family.mk index c08451b9c..2ff9f79e3 100644 --- a/hw/bsp/ch32f20x/family.mk +++ b/hw/bsp/ch32f20x/family.mk @@ -1,6 +1,5 @@ # Submodules CH32F20X_SDK = hw/mcu/wch/ch32f20x -DEPS_SUBMODULES += $(CH32F20X_SDK) # WCH-SDK paths CH32F20X_SDK_SRC = $(CH32F20X_SDK)/EVT/EXAM/SRC diff --git a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h index 3b1187c3a..1fde4244c 100644 --- a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h +++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: CH32V103R-R1-1v1 + url: https://github.com/openwch/ch32v103/tree/main/SCHPCB/CH32V103R-R1-1v1 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/ch32v10x/family.c b/hw/bsp/ch32v10x/family.c index 15f754e11..f25102494 100644 --- a/hw/bsp/ch32v10x/family.c +++ b/hw/bsp/ch32v10x/family.c @@ -1,3 +1,7 @@ +/* metadata: + manufacturer: WCH +*/ + #include <stdio.h> // https://github.com/openwch/ch32v307/pull/90 diff --git a/hw/bsp/ch32v10x/family.cmake b/hw/bsp/ch32v10x/family.cmake index c0af0ef44..a73898050 100644 --- a/hw/bsp/ch32v10x/family.cmake +++ b/hw/bsp/ch32v10x/family.cmake @@ -9,7 +9,7 @@ set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) set(FAMILY_MCUS CH32V103 CACHE INTERNAL "") @@ -98,15 +98,14 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_CH32V103 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_CH32V103) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/wch/dcd_ch32_usbfs.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h index 692cf11bf..56f49205c 100644 --- a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h +++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: CH32V203C-R0-1v0 + url: https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -8,6 +13,8 @@ extern "C" { #define LED_PORT GPIOA #define LED_PIN GPIO_Pin_0 #define LED_STATE_ON 0 +#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE) +#define LED_MODE GPIO_Mode_Out_OD #define UART_DEV USART1 #define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h index 783831edd..4a040e0df 100644 --- a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h +++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: CH32V203G-R0-1v0 + url: https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -8,6 +13,8 @@ extern "C" { #define LED_PORT GPIOA #define LED_PIN GPIO_Pin_0 #define LED_STATE_ON 0 +#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE) +#define LED_MODE GPIO_Mode_Out_OD #define UART_DEV USART2 #define UART_CLOCK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE) diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h index 64eaf931e..63237861c 100644 --- a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h +++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: nanoCH32V203 + url: https://github.com/wuxx/nanoCH32V203 +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -8,6 +13,8 @@ extern "C" { #define LED_PORT GPIOA #define LED_PIN GPIO_Pin_15 #define LED_STATE_ON 0 +#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE) +#define LED_MODE GPIO_Mode_Out_OD #define UART_DEV USART1 #define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c index 43dd7e032..21ed94b0a 100644 --- a/hw/bsp/ch32v20x/family.c +++ b/hw/bsp/ch32v20x/family.c @@ -1,3 +1,7 @@ +/* metadata: +manufacturer: WCH +*/ + #include <stdio.h> // https://github.com/openwch/ch32v307/pull/90 @@ -92,11 +96,11 @@ void board_init(void) { SysTick_Config(SystemCoreClock / 1000); #endif - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + LED_CLOCK_EN(); GPIO_InitTypeDef GPIO_InitStructure = { .GPIO_Pin = LED_PIN, - .GPIO_Mode = GPIO_Mode_Out_OD, + .GPIO_Mode = LED_MODE, .GPIO_Speed = GPIO_Speed_10MHz, }; GPIO_Init(LED_PORT, &GPIO_InitStructure); diff --git a/hw/bsp/ch32v20x/family.cmake b/hw/bsp/ch32v20x/family.cmake index 380ef190d..a5976e0ea 100644 --- a/hw/bsp/ch32v20x/family.cmake +++ b/hw/bsp/ch32v20x/family.cmake @@ -9,7 +9,7 @@ set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) set(FAMILY_MCUS CH32V20X CACHE INTERNAL "") @@ -123,16 +123,15 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_CH32V20X ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_CH32V20X) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/wch/dcd_ch32_usbfs.c ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h index 7b488096e..491347034 100644 --- a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h +++ b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h @@ -22,6 +22,11 @@ * THE SOFTWARE. */ +/* metadata: + name: CH32V307V-R1-1v0 + url: https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c index adf2dbea5..48eb8a38c 100644 --- a/hw/bsp/ch32v307/family.c +++ b/hw/bsp/ch32v307/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: WCH +*/ + #include "stdio.h" // https://github.com/openwch/ch32v307/pull/90 diff --git a/hw/bsp/ch32v307/family.cmake b/hw/bsp/ch32v307/family.cmake index d603af62d..446e850c5 100644 --- a/hw/bsp/ch32v307/family.cmake +++ b/hw/bsp/ch32v307/family.cmake @@ -8,7 +8,7 @@ set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) set(FAMILY_MCUS CH32V307 CACHE INTERNAL "") @@ -113,15 +113,14 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_CH32V307 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_CH32V307) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/wch/dcd_ch32_usbhs.c ${TOP}/src/portable/wch/dcd_ch32_usbfs.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/da1469x/boards/da14695_dk_usb/board.h b/hw/bsp/da1469x/boards/da14695_dk_usb/board.h index 5efdd43e0..c0810c2b6 100644 --- a/hw/bsp/da1469x/boards/da14695_dk_usb/board.h +++ b/hw/bsp/da1469x/boards/da14695_dk_usb/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: DA14695-00HQDEVKT-U + url: https://www.renesas.com/en/products/wireless-connectivity/bluetooth-low-energy/da14695-00hqdevkt-u-smartbond-da14695-bluetooth-low-energy-52-usb-development-kit +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h index f969acf90..2b61e810e 100644 --- a/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h +++ b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: DA1469x Development Kit Pro + url: https://lpccs-docs.renesas.com/um-b-090-da1469x_getting_started/DA1469x_The_hardware/DA1469x_The_hardware.html +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/da1469x/family.c b/hw/bsp/da1469x/family.c index 70bedf6d9..a64ffce67 100644 --- a/hw/bsp/da1469x/family.c +++ b/hw/bsp/da1469x/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Renesas +*/ + #include "bsp/board_api.h" #include "board.h" #include <hal/hal_gpio.h> diff --git a/hw/bsp/da1469x/family.cmake b/hw/bsp/da1469x/family.cmake index 8c89141fe..20d6cbc44 100644 --- a/hw/bsp/da1469x/family.cmake +++ b/hw/bsp/da1469x/family.cmake @@ -5,7 +5,7 @@ set(MCU_DIR ${TOP}/hw/mcu/dialog/da1469x) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) -set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33-nodsp CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS DA1469X CACHE INTERNAL "") @@ -126,14 +126,13 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_DA1469X ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_DA1469X) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/dialog/da146xx/dcd_da146xx.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h index 0c53df06b..15e5091f9 100644 --- a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather ESP32 v2 + url: https://www.adafruit.com/product/5400 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake new file mode 100644 index 000000000..9adaefb17 --- /dev/null +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake @@ -0,0 +1,3 @@ +# Apply board specific content here +set(IDF_TARGET "esp32c6") +set(MAX3421_HOST 1) diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h new file mode 100644 index 000000000..18b51410d --- /dev/null +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h @@ -0,0 +1,56 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Adafruit Feather EPS32-C6 + url: https://www.adafruit.com/product/5933 +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define NEOPIXEL_PIN 15 + +#define BUTTON_PIN 9 +#define BUTTON_STATE_ACTIVE 0 + +// SPI for USB host shield +#define MAX3421_SPI_HOST SPI2_HOST +#define MAX3421_SCK_PIN 21 +#define MAX3421_MOSI_PIN 22 +#define MAX3421_MISO_PIN 23 +#define MAX3421_CS_PIN 8 +#define MAX3421_INTR_PIN 7 + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h index 9aa2e7535..0f607c755 100644 --- a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather ESP32S2 + url: https://www.adafruit.com/product/5000 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h index 9aa2e7535..35c268cf5 100644 --- a/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather ESP32S3 + url: https://www.adafruit.com/product/5323 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h index 084a7aaf2..b86089400 100644 --- a/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h +++ b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit MagTag 2.9" Grayscale + url: https://www.adafruit.com/product/4800 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h index 137ea71ae..bc45678f7 100644 --- a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h +++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Metro ESP32-S2 + url: https://www.adafruit.com/product/4775 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_addax_1/board.h b/hw/bsp/espressif/boards/espressif_addax_1/board.h index d4690f732..4a4a15e1b 100644 --- a/hw/bsp/espressif/boards/espressif_addax_1/board.h +++ b/hw/bsp/espressif/boards/espressif_addax_1/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif Addax-1 + url: n/a +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h index 243dd47f6..a03cb5052 100644 --- a/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h +++ b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif C3 DevKitC + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c3/esp32-c3-devkitc-02/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h index 243dd47f6..eedd36a89 100644 --- a/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h +++ b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif C6 DevKitC + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c6/esp32-c6-devkitc-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_kaluga_1/board.h b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h index 613e6ae0c..d49dc2af6 100644 --- a/hw/bsp/espressif/boards/espressif_kaluga_1/board.h +++ b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif Kaluga 1 + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-kaluga-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h index e57f7c51f..40c4963d9 100644 --- a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif P4 Function EV + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32p4/esp32-p4-function-ev-board/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -36,9 +41,10 @@ #define BUTTON_PIN 35 #define BUTTON_STATE_ACTIVE 0 -// For CI hardware test, to test both device and host on the same HS port with help of -#define HIL_DEVICE_HOST_MUX_PIN 47 -#define HIL_DEVICE_STATE 1 +// For CI hardware test, to test both device and host on the same HS port with help of TS3USB30 +// https://www.adafruit.com/product/5871 +#define HIL_TS3USB30_MODE_PIN 47 +#define HIL_TS3USB30_MODE_DEVICE 1 #ifdef __cplusplus } diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h index e068efef9..499a626a6 100644 --- a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h +++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif S2 DevKitC + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-devkitc-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -31,13 +36,19 @@ extern "C" { #endif -// Note: On the production version (v1.2) WS2812 is connected to GPIO 18, -// however earlier revision v1.1 WS2812 is connected to GPIO 17 #define NEOPIXEL_PIN 18 #define BUTTON_PIN 0 #define BUTTON_STATE_ACTIVE 0 +// SPI for USB host shield +#define MAX3421_SPI_HOST SPI2_HOST +#define MAX3421_SCK_PIN 36 +#define MAX3421_MOSI_PIN 35 +#define MAX3421_MISO_PIN 37 +#define MAX3421_CS_PIN 15 +#define MAX3421_INTR_PIN 14 + #ifdef __cplusplus } #endif diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h index a319fbc61..d2483c84f 100644 --- a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h +++ b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif S3 DevKitC + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitc-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -31,7 +36,7 @@ extern "C" { #endif -#define NEOPIXEL_PIN 48 +#define NEOPIXEL_PIN 38 #define BUTTON_PIN 0 #define BUTTON_STATE_ACTIVE 0 diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h index a319fbc61..5c1914ebe 100644 --- a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h +++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif S3 DevKitM + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitm-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -44,6 +49,11 @@ #define MAX3421_CS_PIN 15 #define MAX3421_INTR_PIN 14 +// For CI hardware test, to test both device and host on the same HS port with help of TS3USB30 +// https://www.adafruit.com/product/5871 +#define HIL_TS3USB30_MODE_PIN 47 +#define HIL_TS3USB30_MODE_DEVICE 1 + #ifdef __cplusplus } #endif diff --git a/hw/bsp/espressif/boards/espressif_saola_1/board.h b/hw/bsp/espressif/boards/espressif_saola_1/board.h index e068efef9..ea369f19c 100644 --- a/hw/bsp/espressif/boards/espressif_saola_1/board.h +++ b/hw/bsp/espressif/boards/espressif_saola_1/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif S2 Saola 1 + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-saola-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 048b431fb..2a5deed26 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Espressif +*/ + #include "bsp/board_api.h" #include "board.h" @@ -45,7 +49,9 @@ static led_strip_handle_t led_strip; static void max3421_init(void); #endif +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4) static bool usb_init(void); +#endif //--------------------------------------------------------------------+ // Implementation @@ -88,10 +94,10 @@ void board_init(void) { usb_init(); #endif -#ifdef HIL_DEVICE_HOST_MUX_PIN - gpio_reset_pin(HIL_DEVICE_HOST_MUX_PIN); - gpio_set_direction(HIL_DEVICE_HOST_MUX_PIN, GPIO_MODE_OUTPUT); - gpio_set_level(HIL_DEVICE_HOST_MUX_PIN, CFG_TUD_ENABLED ? HIL_DEVICE_STATE : (1-HIL_DEVICE_STATE)); +#ifdef HIL_TS3USB30_MODE_PIN + gpio_reset_pin(HIL_TS3USB30_MODE_PIN); + gpio_set_direction(HIL_TS3USB30_MODE_PIN, GPIO_MODE_OUTPUT); + gpio_set_level(HIL_TS3USB30_MODE_PIN, CFG_TUD_ENABLED ? HIL_TS3USB30_MODE_DEVICE : (1-HIL_TS3USB30_MODE_DEVICE)); #endif #if CFG_TUH_ENABLED && CFG_TUH_MAX3421 @@ -150,6 +156,10 @@ int board_getchar(void) { return getchar(); } +void board_putchar(int c) { + putchar(c); +} + //-------------------------------------------------------------------- // PHY Init //-------------------------------------------------------------------- @@ -158,7 +168,6 @@ int board_getchar(void) { #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 3, 0) #include "esp_private/usb_phy.h" -#include "soc/usb_pins.h" static usb_phy_handle_t phy_hdl; @@ -171,20 +180,14 @@ bool usb_init(void) { // maybe we can use USB_OTG_MODE_DEFAULT and switch using dwc2 driver #if CFG_TUD_ENABLED .otg_mode = USB_OTG_MODE_DEVICE, - .otg_speed = BOARD_TUD_RHPORT ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL, #elif CFG_TUH_ENABLED .otg_mode = USB_OTG_MODE_HOST, - .otg_speed= BOARD_TUH_RHPORT ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL, #endif + // https://github.com/hathach/tinyusb/issues/2943#issuecomment-2601888322 + // Set speed to undefined (auto-detect) to avoid timinng/racing issue with S3 with host such as macOS + .otg_speed = USB_PHY_SPEED_UNDEFINED, }; - // OTG IOs config - // const usb_phy_otg_io_conf_t otg_io_conf = USB_PHY_SELF_POWERED_DEVICE(config->vbus_monitor_io); - // if (config->self_powered) { - // phy_conf.otg_io_conf = &otg_io_conf; - // } - // ESP_RETURN_ON_ERROR(usb_new_phy(&phy_conf, &phy_hdl), TAG, "Install USB PHY failed"); - usb_new_phy(&phy_conf, &phy_hdl); return true; diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake index daa12cdb4..ca9eadaf6 100644 --- a/hw/bsp/espressif/family.cmake +++ b/hw/bsp/espressif/family.cmake @@ -1,5 +1,3 @@ -cmake_minimum_required(VERSION 3.5) - # Apply board specific content i.e IDF_TARGET must be set before project.cmake is included include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake") string(TOUPPER ${IDF_TARGET} FAMILY_MCUS) @@ -32,8 +30,6 @@ endif () # Add example src and bsp directories set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components") - -# set SDKCONFIG for each IDF Target -set(SDKCONFIG ${CMAKE_SOURCE_DIR}/sdkconfig.${IDF_TARGET}) +set(SDKCONFIG ${CMAKE_BINARY_DIR}/sdkconfig) include($ENV{IDF_PATH}/tools/cmake/project.cmake) diff --git a/hw/bsp/espressif/family.mk b/hw/bsp/espressif/family.mk deleted file mode 100644 index 0dc21b8eb..000000000 --- a/hw/bsp/espressif/family.mk +++ /dev/null @@ -1,34 +0,0 @@ -#DEPS_SUBMODULES += - -UF2_FAMILY_ID_esp32s2 = 0xbfdd4eee -UF2_FAMILY_ID_esp32s3 = 0xc47e5767 - -BOARD_CMAKE := $(file < $(TOP)/$(BOARD_PATH)/board.cmake) -ifneq ($(findstring esp32s2,$(BOARD_CMAKE)),) - IDF_TARGET = esp32s2 -else -ifneq ($(findstring esp32s3,$(BOARD_CMAKE)),) - IDF_TARGET = esp32s3 -endif -endif - -.PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu - -all: - idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) build - -build: all - -fullclean: - if test -f sdkconfig; then $(RM) -f sdkconfig ; fi - if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi - idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@ - -clean flash bootloader-flash app-flash erase monitor dfu-flash dfu size size-components size-files: - idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@ - -uf2: $(BUILD)/$(PROJECT).uf2 - -$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin - @echo CREATE $@ - $(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID_$(IDF_TARGET)) -b 0x0 -c -o $@ $^ diff --git a/hw/bsp/f1c100s/boards/f1c100s/board.h b/hw/bsp/f1c100s/boards/f1c100s/board.h index 3b56a3a57..44b78f8fb 100644 --- a/hw/bsp/f1c100s/boards/f1c100s/board.h +++ b/hw/bsp/f1c100s/boards/f1c100s/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: Lctech Pi F1C200s + url: https://linux-sunxi.org/Lctech_Pi_F1C200s +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/f1c100s/family.c b/hw/bsp/f1c100s/family.c index 6df4a0ed8..9e864363f 100644 --- a/hw/bsp/f1c100s/family.c +++ b/hw/bsp/f1c100s/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Sunxi +*/ + #include <stdint.h> #include <malloc.h> #include <irqflags.h> diff --git a/hw/bsp/f1c100s/family.cmake b/hw/bsp/f1c100s/family.cmake index 0903a0143..211c6645c 100644 --- a/hw/bsp/f1c100s/family.cmake +++ b/hw/bsp/f1c100s/family.cmake @@ -5,7 +5,7 @@ set(SDK_DIR ${TOP}/hw/mcu/allwinner/f1c100s) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR arm926ej-s CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU arm926ej-s CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS F1C100S CACHE INTERNAL "") @@ -100,15 +100,15 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_F1C100S ${RTOS}) - target_sources(${TARGET}-tinyusb PRIVATE + family_add_tinyusb(${TARGET} OPT_MCU_F1C100S) + target_sources(${TARGET} PRIVATE ${TOP}/src/portable/sunxi/dcd_sunxi_musb.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 82e3badb3..9ec80df91 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -9,6 +9,13 @@ get_filename_component(TOP ${TOP} ABSOLUTE) set(UF2CONV_PY ${TOP}/tools/uf2/utils/uf2conv.py) #------------------------------------------------------------- +# RTOS +#------------------------------------------------------------- +if (NOT DEFINED RTOS) + set(RTOS noos CACHE STRING "RTOS") +endif () + +#------------------------------------------------------------- # Toolchain # Can be changed via -DTOOLCHAIN=gcc|iar or -DCMAKE_C_COMPILER= #------------------------------------------------------------- @@ -27,11 +34,15 @@ if (DEFINED CMAKE_C_COMPILER) endif () endif () -# default to gcc if (NOT DEFINED TOOLCHAIN) set(TOOLCHAIN gcc) endif () +# Optimization +if (NOT DEFINED CMAKE_BUILD_TYPE OR CMAKE_BUILD_TYPE STREQUAL "") + set(CMAKE_BUILD_TYPE MinSizeRel CACHE STRING "Build type" FORCE) +endif () + #------------------------------------------------------------- # FAMILY and BOARD #------------------------------------------------------------- @@ -53,6 +64,7 @@ if (NOT DEFINED FAMILY) # replace / with ; so that we can get the first element as FAMILY string(REPLACE "/" ";" BOARD_PATH ${BOARD_PATH}) list(GET BOARD_PATH 0 FAMILY) + set(FAMILY ${FAMILY} CACHE STRING "Board family") endif () if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake) @@ -73,33 +85,14 @@ if (NOT NO_WARN_RWX_SEGMENTS_SUPPORTED) set(NO_WARN_RWX_SEGMENTS_SUPPORTED 1) endif() -set(WARNING_FLAGS_GNU - -Wall - -Wextra - -Werror - -Wfatal-errors - -Wdouble-promotion - -Wstrict-prototypes - -Wstrict-overflow - -Werror-implicit-function-declaration - -Wfloat-equal - -Wundef - -Wshadow - -Wwrite-strings - -Wsign-compare - -Wmissing-format-attribute - -Wunreachable-code - -Wcast-align - -Wcast-function-type - -Wcast-qual - -Wnull-dereference - -Wuninitialized - -Wunused - -Wreturn-type - -Wredundant-decls - ) - -set(WARNING_FLAGS_IAR "") +#---------------------------------- +# Zephyr +#---------------------------------- +if (RTOS STREQUAL zephyr) + set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) + set(ZEPHYR_BOARD_ALIASES ${CMAKE_CURRENT_LIST_DIR}/zephyr_board_aliases.cmake) + find_package(Zephyr REQUIRED HINTS ${TOP}/zephyr) +endif () #------------------------------------------------------------- # Functions @@ -177,7 +170,6 @@ endfunction() # Add RTOS to example function(family_add_rtos TARGET RTOS) if (RTOS STREQUAL "freertos") - # freertos config if (NOT TARGET freertos_config) add_library(freertos_config INTERFACE) target_include_directories(freertos_config INTERFACE ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig) @@ -185,12 +177,15 @@ function(family_add_rtos TARGET RTOS) target_link_libraries(freertos_config INTERFACE board_${BOARD}) endif() - # freertos kernel if (NOT TARGET freertos_kernel) add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel) endif () target_link_libraries(${TARGET} PUBLIC freertos_kernel) + target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_FREERTOS) + elseif (RTOS STREQUAL "zephyr") + target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_ZEPHYR) + target_include_directories(${TARGET} PUBLIC ${ZEPHYR_BASE}/include) endif () endfunction() @@ -198,6 +193,7 @@ endfunction() function(family_configure_common TARGET RTOS) family_add_rtos(${TARGET} ${RTOS}) + # Add BOARD_${BOARD} define string(TOUPPER ${BOARD} BOARD_UPPER) string(REPLACE "-" "_" BOARD_UPPER ${BOARD_UPPER}) target_compile_definitions(${TARGET} PUBLIC @@ -210,20 +206,6 @@ function(family_configure_common TARGET RTOS) target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI}) endif() - target_compile_options(${TARGET} PUBLIC ${WARNING_FLAGS_${CMAKE_C_COMPILER_ID}}) - - # Generate linker map file - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${TARGET} PUBLIC "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map") - if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED) - target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") - endif () - elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_options(${TARGET} PUBLIC "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map") - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${TARGET} PUBLIC "LINKER:--map=$<TARGET_FILE:${TARGET}>.map") - endif() - # ETM Trace option if (TRACE_ETM STREQUAL "1") target_compile_definitions(${TARGET} PUBLIC TRACE_ETM) @@ -231,79 +213,101 @@ function(family_configure_common TARGET RTOS) # LOGGER option if (DEFINED LOGGER) + string(TOUPPER ${LOGGER} LOGGER) target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER}) # Add segger rtt to example - if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt") - if (NOT TARGET segger_rtt) - add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c) - target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) -# target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) - endif() - target_link_libraries(${TARGET} PUBLIC segger_rtt) + if(LOGGER STREQUAL "RTT") + target_sources(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c) + target_include_directories(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) +# target_compile_definitions(${TARGET} PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) endif () + else () + target_compile_definitions(${TARGET} PUBLIC LOGGER_UART) endif () - # run size after build - find_program(SIZE_EXE ${CMAKE_SIZE}) - if(NOT ${SIZE_EXE} STREQUAL SIZE_EXE-NOTFOUND) - add_custom_command(TARGET ${TARGET} POST_BUILD - COMMAND ${SIZE_EXE} $<TARGET_FILE:${TARGET}> + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_compile_options(${TARGET} PRIVATE + -Wall + -Wextra + #-Werror + -Wfatal-errors + -Wdouble-promotion + -Wstrict-prototypes + -Wstrict-overflow + -Werror-implicit-function-declaration + -Wfloat-equal + -Wundef + -Wshadow + -Wwrite-strings + -Wsign-compare + -Wmissing-format-attribute + -Wunreachable-code + -Wcast-align + -Wcast-function-type + -Wcast-qual + -Wnull-dereference + -Wuninitialized + -Wunused + -Wunused-function + -Wreturn-type + -Wredundant-decls + -Wmissing-prototypes ) + target_link_options(${TARGET} PUBLIC "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map") + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 + AND NO_WARN_RWX_SEGMENTS_SUPPORTED AND (NOT RTOS STREQUAL zephyr)) + target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") + endif () + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${TARGET} PUBLIC "LINKER:--map=$<TARGET_FILE:${TARGET}>.map") endif () -endfunction() -# Add tinyusb to example -function(family_add_tinyusb TARGET OPT_MCU RTOS) - # tinyusb target is built for each example since it depends on example's tusb_config.h - set(TINYUSB_TARGET_PREFIX ${TARGET}-) - add_library(${TARGET}-tinyusb_config INTERFACE) + # run size after build +# find_program(SIZE_EXE ${CMAKE_SIZE}) +# if(NOT ${SIZE_EXE} STREQUAL SIZE_EXE-NOTFOUND) +# add_custom_command(TARGET ${TARGET} POST_BUILD +# COMMAND ${SIZE_EXE} $<TARGET_FILE:${TARGET}> +# ) +# endif () +endfunction() - # path to tusb_config.h - target_include_directories(${TARGET}-tinyusb_config INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/src) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_MCU=${OPT_MCU}) +# Add tinyusb to target +function(family_add_tinyusb TARGET OPT_MCU) + # tinyusb's CMakeList.txt + add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + # Add TinyUSB sources, include and common define + tinyusb_target_add(${TARGET}) + target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_MCU=${OPT_MCU}) if (DEFINED LOG) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG}) - if (LOG STREQUAL "4") - # no inline for debug level 4 - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE TU_ATTR_ALWAYS_INLINE=) + target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_DEBUG=${LOG}) + if (LOG STREQUAL "4") # no inline for debug level 4 + target_compile_definitions(${TARGET} PUBLIC TU_ATTR_ALWAYS_INLINE=) endif () endif() - if (RTOS STREQUAL "freertos") - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_OS=OPT_OS_FREERTOS) - endif () - - # tinyusb's CMakeList.txt - add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) - - if (RTOS STREQUAL "freertos") - # link tinyusb with freeRTOS kernel - target_link_libraries(${TARGET}-tinyusb PUBLIC freertos_kernel) - endif () - # use max3421 as host controller if (MAX3421_HOST STREQUAL "1") - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUH_MAX3421=1) - target_sources(${TARGET}-tinyusb PUBLIC + target_compile_definitions(${TARGET} PUBLIC CFG_TUH_MAX3421=1) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/analog/max3421/hcd_max3421.c ) endif () - - # compile define from command line - if(DEFINED CFLAGS_CLI) - separate_arguments(CFLAGS_CLI) - target_compile_options(${TARGET}-tinyusb PUBLIC ${CFLAGS_CLI}) - endif() - endfunction() # Add bin/hex output function(family_add_bin_hex TARGET) - add_custom_command(TARGET ${TARGET} POST_BUILD - COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin - COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex - VERBATIM) + if (CMAKE_C_COMPILER_ID STREQUAL "IAR") + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND ${CMAKE_OBJCOPY} --bin $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin + COMMAND ${CMAKE_OBJCOPY} --ihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex + VERBATIM) + else() + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin + COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex + VERBATIM) + endif() endfunction() # Add uf2 output @@ -314,10 +318,10 @@ function(family_add_uf2 TARGET FAMILY_ID) VERBATIM) endfunction() -#---------------------------------- +#------------------------------------------------------- # Example Target Configure (Default rule) # These function can be redefined in FAMILY/family.cmake -#---------------------------------- +#-------------------------------------------------------- function(family_configure_example TARGET RTOS) # empty function, should be redefined in FAMILY/family.cmake @@ -399,7 +403,11 @@ endfunction() # Add flash jlink target function(family_flash_jlink TARGET) if (NOT DEFINED JLINKEXE) - set(JLINKEXE JLinkExe) + if(CMAKE_HOST_WIN32) + set(JLINKEXE JLink.exe) + else() + set(JLINKEXE JLinkExe) + endif() endif () if (NOT DEFINED JLINK_IF) @@ -411,26 +419,28 @@ function(family_flash_jlink TARGET) endif () separate_arguments(OPTION_LIST UNIX_COMMAND ${JLINK_OPTION}) + if (RTOS STREQUAL zephyr) + set(BINARY_TARGET zephyr_final) + set(NAME_TARGET ${CMAKE_PROJECT_NAME}) + else () + set(BINARY_TARGET ${TARGET}) + set(NAME_TARGET ${TARGET}) + endif () + file(GENERATE - OUTPUT $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink + OUTPUT $<TARGET_FILE_DIR:${BINARY_TARGET}>/${BINARY_TARGET}.jlink CONTENT "halt -loadfile $<TARGET_FILE:${TARGET}> +loadfile $<TARGET_FILE:${BINARY_TARGET}> r go exit" ) - add_custom_target(${TARGET}-jlink - DEPENDS ${TARGET} - COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink + add_custom_target(${NAME_TARGET}-jlink + DEPENDS ${BINARY_TARGET} + COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $<TARGET_FILE_DIR:${BINARY_TARGET}>/${BINARY_TARGET}.jlink VERBATIM ) - - # optional flash post build -# add_custom_command(TARGET ${TARGET} POST_BUILD -# COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink -# VERBATIM -# ) endfunction() @@ -470,13 +480,17 @@ function(family_flash_openocd TARGET) set(OPENOCD_OPTION2 "") endif () + if (DEFINED OPENOCD_SERIAL) + set(OPENOCD_OPTION "-c \"adapter serial ${OPENOCD_SERIAL}\" ${OPENOCD_OPTION}") + endif () + separate_arguments(OPTION_LIST UNIX_COMMAND ${OPENOCD_OPTION}) separate_arguments(OPTION_LIST2 UNIX_COMMAND ${OPENOCD_OPTION2}) # note skip verify since it has issue with rp2040 add_custom_target(${TARGET}-openocd DEPENDS ${TARGET} - COMMAND ${OPENOCD} -c "tcl_port disabled" -c "gdb_port disabled" ${OPTION_LIST} -c init -c halt -c "program $<TARGET_FILE:${TARGET}>" -c reset ${OPTION_LIST2} -c exit + COMMAND ${OPENOCD} -c "tcl_port disabled; gdb_port disabled" ${OPTION_LIST} -c "init; halt; program $<TARGET_FILE:${TARGET}>" -c reset ${OPTION_LIST2} -c exit VERBATIM ) endfunction() @@ -496,10 +510,16 @@ endfunction() # Add flash openocd adi (Analog Devices) target # included with msdk or compiled from release branch of https://github.com/analogdevicesinc/openocd function(family_flash_openocd_adi TARGET) - if (DEFINED $ENV{MAXIM_PATH}) - # use openocd from msdk - set(OPENOCD ENV{MAXIM_PATH}/Tools/OpenOCD/openocd) - set(OPENOCD_OPTION2 "-s ENV{MAXIM_PATH}/Tools/OpenOCD/scripts") + if (DEFINED MAXIM_PATH) + # use openocd from msdk with MAXIM_PATH cmake variable first if the user specified it + set(OPENOCD ${MAXIM_PATH}/Tools/OpenOCD/openocd) + set(OPENOCD_OPTION2 "-s ${MAXIM_PATH}/Tools/OpenOCD/scripts") + elseif (DEFINED ENV{MAXIM_PATH}) + # use openocd from msdk with MAXIM_PATH environment variable. Normalize + # since msdk can be Windows (MinGW) or Linux + file(TO_CMAKE_PATH "$ENV{MAXIM_PATH}" MAXIM_PATH_NORM) + set(OPENOCD ${MAXIM_PATH_NORM}/Tools/OpenOCD/openocd) + set(OPENOCD_OPTION2 "-s ${MAXIM_PATH_NORM}/Tools/OpenOCD/scripts") else() # compiled from source if (NOT DEFINED OPENOCD_ADI_PATH) @@ -606,7 +626,6 @@ function(family_flash_msp430flasher TARGET) ) endfunction() - function(family_flash_uniflash TARGET) if (NOT DEFINED DSLITE) set(DSLITE dslite.sh) diff --git a/hw/bsp/fomu/boards/fomu/board.h b/hw/bsp/fomu/boards/fomu/board.h index 666ba1d98..2651c823d 100644 --- a/hw/bsp/fomu/boards/fomu/board.h +++ b/hw/bsp/fomu/boards/fomu/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: fomu + url: https://tomu.im/fomu.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/fomu/family.c b/hw/bsp/fomu/family.c index ccf2b12f4..61943cb01 100644 --- a/hw/bsp/fomu/family.c +++ b/hw/bsp/fomu/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Tomu +*/ + #include <stdint.h> #include <stdbool.h> #include "csr.h" diff --git a/hw/bsp/fomu/family.cmake b/hw/bsp/fomu/family.cmake index 8d5ab144c..639373695 100644 --- a/hw/bsp/fomu/family.cmake +++ b/hw/bsp/fomu/family.cmake @@ -4,7 +4,7 @@ include_guard() include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR rv32i-ilp32 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU rv32i-ilp32 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) set(FAMILY_MCUS VALENTYUSB_EPTRI CACHE INTERNAL "") @@ -77,14 +77,13 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_VALENTYUSB_EPTRI ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_VALENTYUSB_EPTRI) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/valentyusb/eptri/dcd_eptri.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h index fae7c40b7..cb564a340 100644 --- a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h +++ b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: Sipeed Longan Nano + url: https://longan.sipeed.com/en/ +*/ + #ifndef _NUCLEI_SDK_HAL_H #define _NUCLEI_SDK_HAL_H diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c index d4a819fb3..9d15755fc 100644 --- a/hw/bsp/gd32vf103/family.c +++ b/hw/bsp/gd32vf103/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: GigaDevice +*/ + #include "drv_usb_hw.h" #include "drv_usb_dev.h" diff --git a/hw/bsp/gd32vf103/family.cmake b/hw/bsp/gd32vf103/family.cmake index 1441e41de..a47871b38 100644 --- a/hw/bsp/gd32vf103/family.cmake +++ b/hw/bsp/gd32vf103/family.cmake @@ -7,7 +7,7 @@ set(SOC_DIR ${SDK_DIR}/SoC/gd32vf103) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) set(FAMILY_MCUS GD32VF103 CACHE INTERNAL "") @@ -105,17 +105,17 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_GD32VF103 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_GD32VF103) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.h b/hw/bsp/imxrt/boards/metro_m7_1011/board.h index 24141f5f4..ccc4d6b9a 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board.h +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Metro M7 1011 + url: https://www.adafruit.com/product/5600 +*/ + #ifndef BOARD_M7_1011_H_ #define BOARD_M7_1011_H_ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h index 343e17f81..04d5b01b5 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h +++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Metro M7 1011 SD + url: https://www.adafruit.com/product/5600 +*/ + #ifndef BOARD_METRO_M7_1011_SD_H_ #define BOARD_METRO_M7_1011_SD_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h index da12075a0..6b9ec0ae1 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1010 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1010-evaluation-kit:MIMXRT1010-EVK +*/ + #ifndef BOARD_MIMXRT1010_EVK_H_ #define BOARD_MIMXRT1010_EVK_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h index 6ac78453f..e2ec4e627 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1015 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1015-EVK +*/ + #ifndef BOARD_MIMXRT1015_EVK_H_ #define BOARD_MIMXRT1015_EVK_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c index ae1aa7fb1..b9e4851bf 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c @@ -15,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v11.0 +product: Clocks v15.0 processor: MIMXRT1015xxxxx package_id: MIMXRT1015DAF5A mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 24.12.10 board: MIMXRT1015-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h index 2acdb16a7..cccbe487a 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h @@ -36,39 +36,39 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AOI, ARM, BEE, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, NVIC, OCOTP, PWM1, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TRNG, USB, WDOG1, WDOG2, XBARA, XBARB */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB */ /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. */ diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c index 97224a332..76c1dae70 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v13.1 +product: Pins v17.0 processor: MIMXRT1015xxxxx package_id: MIMXRT1015DAF5A mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 24.12.10 board: MIMXRT1015-EVK external_user_signals: {} pin_labels: @@ -32,6 +32,7 @@ power_domains: {NVCC_GPIO: '3.3'} * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); + BOARD_InitDEBUG_UARTPins(); } /* @@ -40,8 +41,6 @@ BOARD_InitPins: - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '1', peripheral: GPIO2, signal: 'gpio_io, 09', pin_signal: GPIO_EMC_09, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_47K_Ohm} - - {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, pull_up_down_config: Pull_Down_100K_Ohm} - - {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06} - {pin_num: '21', peripheral: GPIO3, signal: 'gpio_io, 21', pin_signal: GPIO_SD_B1_01, direction: OUTPUT} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ @@ -73,15 +72,11 @@ void BOARD_InitPins(void) { /* Initialize GPIO functionality on GPIO_SD_B1_01 (pin 21) */ GPIO_PinInit(GPIO3, 21U, &USER_LED_config); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_GPIO3_IO21, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U); IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0x70B0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitQSPIPins: @@ -113,6 +108,30 @@ void BOARD_InitQSPIPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, 0U); } +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, slew_rate: Slow} + - {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U); +} /*********************************************************************************************************************** * EOF **********************************************************************************************************************/ diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h index c9cbe3b72..2f3bf2c4c 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h @@ -37,7 +37,7 @@ extern "C" { */ void BOARD_InitBootPins(void); -/* GPIO_EMC_09 (number 1), USER_BUTTON */ +/* GPIO_EMC_09 (number 1), USER_BUTTON/SW4 */ /* Routed pin properties */ #define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */ #define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ @@ -51,16 +51,6 @@ void BOARD_InitBootPins(void); #define BOARD_INITPINS_USER_BUTTON_PIN 9U /*!< PORT pin number */ #define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 9U) /*!< PORT pin mask */ -/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */ -/* Routed pin properties */ -#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ - -/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */ -/* Routed pin properties */ -#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ - /* GPIO_SD_B1_01 (number 21), GPIO SD_B1_01 */ /* Routed pin properties */ #define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO3 /*!< Peripheral name */ @@ -69,6 +59,7 @@ void BOARD_InitBootPins(void); /* Symbols to be used with GPIO driver */ #define BOARD_INITPINS_USER_LED_GPIO GPIO3 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ #define BOARD_INITPINS_USER_LED_GPIO_PIN 21U /*!< GPIO pin number */ #define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 21U) /*!< GPIO pin mask */ #define BOARD_INITPINS_USER_LED_PORT GPIO3 /*!< PORT peripheral base pointer */ @@ -119,6 +110,23 @@ void BOARD_InitPins(void); */ void BOARD_InitQSPIPins(void); +/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + +/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + #if defined(__cplusplus) } #endif diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex index 88265d32e..917bed375 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex @@ -1,5 +1,5 @@ <?xml version="1.0" encoding= "UTF-8" ?> -<configuration name="MIMXRT1015-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="4be4468a-3124-4ac9-9d4f-05d5f8ad6399" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> +<configuration name="MIMXRT1015-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="4be4468a-3124-4ac9-9d4f-05d5f8ad6399" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <common> <processor>MIMXRT1015xxxxx</processor> <package>MIMXRT1015DAF5A</package> @@ -13,19 +13,18 @@ </common> <preferences> <validate_boot_init_only>true</validate_boot_init_only> - <generate_extended_information>false</generate_extended_information> <generate_code_modified_registers_only>false</generate_code_modified_registers_only> <update_include_paths>true</update_include_paths> <generate_registers_defines>false</generate_registers_defines> </preferences> <tools> - <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> <generated_project_files> <file path="board/pin_mux.c" update_enabled="true"/> <file path="board/pin_mux.h" update_enabled="true"/> </generated_project_files> <pins_profile> - <processor_version>13.0.2</processor_version> + <processor_version>24.12.10</processor_version> <pin_labels> <pin_label pin_num="21" pin_signal="GPIO_SD_B1_01" label="GPIO SD_B1_01" identifier="USER_LED"/> </pin_labels> @@ -45,12 +44,7 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> - <feature name="initialized" evaluation="equal"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> @@ -79,12 +73,6 @@ <pin_feature name="pull_up_down_config" value="Pull_Up_47K_Ohm"/> </pin_features> </pin> - <pin peripheral="LPUART1" signal="RX" pin_num="68" pin_signal="GPIO_AD_B0_07"> - <pin_features> - <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> - </pin_features> - </pin> - <pin peripheral="LPUART1" signal="TX" pin_num="72" pin_signal="GPIO_AD_B0_06"/> <pin peripheral="GPIO3" signal="gpio_io, 21" pin_num="21" pin_signal="GPIO_SD_B1_01"> <pin_features> <pin_feature name="direction" value="OUTPUT"/> @@ -100,7 +88,7 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins"> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitQSPIPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> @@ -125,15 +113,52 @@ <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="8" pin_signal="GPIO_SD_B1_11"/> </pins> </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="RX" pin_num="68" pin_signal="GPIO_AD_B0_07"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="LPUART1" signal="TX" pin_num="72" pin_signal="GPIO_AD_B0_06"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + </pins> + </function> </functions_list> </pins> - <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <clocks name="Clocks" version="15.0" enabled="true" update_project_code="true"> <generated_project_files> <file path="board/clock_config.c" update_enabled="true"/> <file path="board/clock_config.h" update_enabled="true"/> </generated_project_files> <clocks_profile> - <processor_version>13.0.2</processor_version> + <processor_version>24.12.10</processor_version> </clocks_profile> <clock_configurations> <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h index 4f4593524..3f9c97e11 100644 --- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1020 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1020-EVK +*/ + #ifndef BOARD_MIMXRT1020_EVK_H_ #define BOARD_MIMXRT1020_EVK_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h index 27a64b464..39e63c472 100644 --- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1024 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1024-evaluation-kit:MIMXRT1024-EVK +*/ + #ifndef BOARD_MIMXRT1024_EVK_H_ #define BOARD_MIMXRT1024_EVK_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h index 97d1e446c..de7ab0535 100644 --- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1050 Evaluation Kit revB + url: https://www.nxp.com/part/IMXRT1050-EVKB +*/ + #ifndef BOARD_MIMXRT1050_EVKB_H_ #define BOARD_MIMXRT1050_EVKB_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h index 40b99860f..5bbacadaf 100644 --- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1060 Evaluation Kit revB + url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1060-EVKB +*/ + #ifndef BOARD_MIMXRT1060_EVKB_H_ #define BOARD_MIMXRT1060_EVKB_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h index 7fca5adef..6dc01e3e7 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1064 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1064-EVK +*/ + #ifndef BOARD_MIMXRT1064_EVKB_H_ #define BOARD_MIMXRT1064_EVKB_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c index 778ab02f2..be684faee 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c @@ -15,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v11.0 +product: Clocks v15.0 processor: MIMXRT1064xxxxA package_id: MIMXRT1064DVL6A mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 24.12.10 board: MIMXRT1064-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h index 7ce24b6f4..2fa713c0d 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h @@ -36,56 +36,56 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */ +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL /* Clock consumers of ENET2_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL /* Clock consumers of ENET2_REF_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL /* Clock consumers of ENET2_TX_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET, ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, ENET2, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO10, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ /*! @brief Arm PLL set for BOARD_BootClockRUN configuration. */ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c index 8e975dc72..60c4bab37 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v13.1 +product: Pins v17.0 processor: MIMXRT1064xxxxA package_id: MIMXRT1064DVL6A mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 24.12.10 board: MIMXRT1064-EVK pin_labels: - {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED} @@ -81,7 +81,6 @@ void BOARD_InitPins(void) { IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitDEBUG_UARTPins: @@ -109,7 +108,6 @@ void BOARD_InitDEBUG_UARTPins(void) { IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitSDRAMPins: @@ -209,7 +207,6 @@ void BOARD_InitSDRAMPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_SEMC_DQS, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitCSIPins: @@ -267,7 +264,6 @@ void BOARD_InitCSIPins(void) { IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitLCDPins: @@ -360,7 +356,6 @@ void BOARD_InitLCDPins(void) { IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitCANPins: @@ -384,7 +379,6 @@ void BOARD_InitCANPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitENETPins: @@ -424,7 +418,6 @@ void BOARD_InitENETPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitUSDHCPins: @@ -458,7 +451,6 @@ void BOARD_InitUSDHCPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitQSPIPins: @@ -491,7 +483,6 @@ void BOARD_InitQSPIPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); } - /*********************************************************************************************************************** * EOF **********************************************************************************************************************/ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h index bf494b6f6..be1461f16 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h @@ -47,6 +47,7 @@ void BOARD_InitBootPins(void); /* Symbols to be used with GPIO driver */ #define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ #define BOARD_INITPINS_USER_LED_GPIO_PIN 9U /*!< GPIO pin number */ #define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */ #define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex index 3f0948101..58247fa5b 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex @@ -1,5 +1,5 @@ <?xml version="1.0" encoding= "UTF-8" ?> -<configuration name="MIMXRT1064-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="d75e55f6-68ab-46ef-814b-b94593af7f06" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> +<configuration name="MIMXRT1064-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="d75e55f6-68ab-46ef-814b-b94593af7f06" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <common> <processor>MIMXRT1064xxxxA</processor> <package>MIMXRT1064DVL6A</package> @@ -13,19 +13,18 @@ </common> <preferences> <validate_boot_init_only>true</validate_boot_init_only> - <generate_extended_information>false</generate_extended_information> <generate_code_modified_registers_only>false</generate_code_modified_registers_only> <update_include_paths>true</update_include_paths> <generate_registers_defines>false</generate_registers_defines> </preferences> <tools> - <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> <generated_project_files> <file path="board/pin_mux.c" update_enabled="true"/> <file path="board/pin_mux.h" update_enabled="true"/> </generated_project_files> <pins_profile> - <processor_version>13.0.2</processor_version> + <processor_version>24.12.10</processor_version> <pin_labels> <pin_label pin_num="F14" pin_signal="GPIO_AD_B0_09" label="JTAG_TDI/J21[5]/ENET_RST/J22[5]" identifier="USER_LED"/> <pin_label pin_num="L6" pin_signal="WAKEUP" label="SD_PWREN" identifier="USER_BUTTON"/> @@ -41,7 +40,7 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> @@ -84,7 +83,7 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> @@ -137,7 +136,7 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins"> + <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSDRAMPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> @@ -204,12 +203,12 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitCSIPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> </dependency> - <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitCSIPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> @@ -277,7 +276,7 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins"> + <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitLCDPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> @@ -450,7 +449,7 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins"> + <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitCANPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> @@ -479,7 +478,7 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins"> + <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitENETPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> @@ -516,7 +515,7 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins"> + <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSDHCPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> @@ -550,7 +549,7 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins"> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitQSPIPins"> <feature name="initialized" evaluation="equal"> <data>true</data> </feature> @@ -578,13 +577,13 @@ </function> </functions_list> </pins> - <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <clocks name="Clocks" version="15.0" enabled="true" update_project_code="true"> <generated_project_files> <file path="board/clock_config.c" update_enabled="true"/> <file path="board/clock_config.h" update_enabled="true"/> </generated_project_files> <clocks_profile> - <processor_version>13.0.2</processor_version> + <processor_version>24.12.10</processor_version> </clocks_profile> <clock_configurations> <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> @@ -751,10 +750,7 @@ <dcdx_configurations/> </dcdx> <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true"> - <generated_project_files> - <file path="board/peripherals.c" update_enabled="true"/> - <file path="board/peripherals.h" update_enabled="true"/> - </generated_project_files> + <generated_project_files/> <peripherals_profile> <processor_version>13.0.2</processor_version> </peripherals_profile> diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake index 692d9e498..d5629f8ba 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake @@ -1,8 +1,17 @@ set(MCU_VARIANT MIMXRT1176) -set(MCU_CORE _cm7) -set(JLINK_DEVICE MIMXRT1176xxxA_M7) -set(PYOCD_TARGET mimxrt1170_cm7) +if (M4 STREQUAL "1") + set(MCU_CORE _cm4) + set(JLINK_CORE _M4) + set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_ram.ld) + set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") +else () + set(MCU_CORE _cm7) + set(JLINK_CORE _M7) +endif() + +set(JLINK_DEVICE MIMXRT1176xxxA${JLINK_CORE}) +set(PYOCD_TARGET mimxrt1170${MCU_CORE}) set(NXPLINK_DEVICE MIMXRT1176xxxxx:MIMXRT1170-EVK) function(update_board TARGET) @@ -10,7 +19,7 @@ function(update_board TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkbmimxrt1170_flexspi_nor_config.c ) target_compile_definitions(${TARGET} PUBLIC - CPU_MIMXRT1176DVMAA_cm7 + CPU_MIMXRT1176DVMAA${MCU_CORE} BOARD_TUD_RHPORT=0 BOARD_TUH_RHPORT=1 ) diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h index 303935517..c5d54b7a7 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1070 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVKB +*/ + #ifndef BOARD_MIMXRT1170_EVKB_H_ #define BOARD_MIMXRT1170_EVKB_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk index e8500a4c9..8270ae587 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk @@ -1,12 +1,22 @@ -CFLAGS += -DCPU_MIMXRT1176DVMAA_cm7 MCU_VARIANT = MIMXRT1176 -MCU_CORE = _cm7 + +ifeq ($(M4), 1) + MCU_CORE = _cm4 + JLINK_CORE = _M4 + CPU_CORE = cortex-m4 + LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx${MCU_CORE}_ram.ld +else + MCU_CORE = _cm7 + JLINK_CORE = _M7 +endif + +CFLAGS += -DCPU_MIMXRT1176DVMAA$(MCU_CORE) # For flash-jlink target -JLINK_DEVICE = MIMXRT1176xxxA_M7 +JLINK_DEVICE = MIMXRT1176xxxA$(JLINK_CORE) # For flash-pyocd target -PYOCD_TARGET = mimxrt1170_cm7 +PYOCD_TARGET = mimxrt1170$(MCU_CORE) BOARD_TUD_RHPORT = 0 BOARD_TUH_RHPORT = 1 diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c index 88b3b3770..4f06299de 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c @@ -11,11 +11,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v12.0 +product: Clocks v15.0 processor: MIMXRT1176xxxxx package_id: MIMXRT1176DVMAA mcu_data: ksdk2_0 -processor_version: 14.0.1 +processor_version: 24.12.10 board: MIMXRT1170-EVKB * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -335,7 +335,6 @@ void BOARD_BootClockRUN(void) /* Init OSC RC 400M */ CLOCK_OSC_EnableOscRc400M(); - CLOCK_OSC_GateOscRc400M(false); /* Init OSC RC 48M */ CLOCK_OSC_EnableOsc48M(true); @@ -349,22 +348,29 @@ void BOARD_BootClockRUN(void) { } - /* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ + /* Switch core M7 clock root to OscRC48MDiv2 first */ #if __CORTEX_M == 7 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + /* Switch core M7 systick clock root to OscRC48MDiv2 first */ +#if __CORTEX_M == 7 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); #endif + /* Switch core M4 clock root to OscRC48MDiv2 first */ #if __CORTEX_M == 4 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); +#endif + /* Switch the Bus_Lpsr clock root to OscRC48MDiv2 first */ +#if __CORTEX_M == 4 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h index 4a4d35eaa..f68724314 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h @@ -48,7 +48,7 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */ #define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */ #define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL /* Clock consumers of AXI_CLK_ROOT output : FLEXRAM */ -#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, ENET_QOS, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */ +#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, ENET_QOS, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IEE__IEE_RT1170, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */ #define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL /* Clock consumers of BUS_LPSR_CLK_ROOT output : CAN3, GPIO10, GPIO11, GPIO12, GPIO7, GPIO8, GPIO9, IOMUXC_LPSR, LPI2C5, LPI2C6, LPSPI5, LPSPI6, LPUART11, LPUART12, MUA, MUB, PDM, PIT2, RDC, RTWDOG4, SAI4, SNVS, XRDC2_D0, XRDC2_D1 */ #define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL /* Clock consumers of CAN1_CLK_ROOT output : CAN1 */ #define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL /* Clock consumers of CAN2_CLK_ROOT output : CAN2 */ diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c index 81ffb35e3..5e8cb91c1 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v14.0 +product: Pins v17.0 processor: MIMXRT1176xxxxx package_id: MIMXRT1176DVMAA mcu_data: ksdk2_0 -processor_version: 14.0.1 +processor_version: 24.12.10 board: MIMXRT1170-EVKB external_user_signals: {} pin_labels: @@ -31,6 +31,7 @@ pin_labels: * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); + BOARD_InitDEBUG_UARTPins(); } /* @@ -38,10 +39,6 @@ void BOARD_InitBootPins(void) { BOARD_InitPins: - options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} - pin_list: - - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, - open_drain: Disable, drive_strength: High, slew_rate: Slow} - - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, - open_drain: Disable, drive_strength: High, slew_rate: Slow} - {pin_num: M13, peripheral: GPIO9, signal: 'gpio_io, 03', pin_signal: GPIO_AD_04, identifier: USER_LED, direction: OUTPUT, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper} - {pin_num: T8, peripheral: GPIO13, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT, pull_up_down_config: Pull_Up} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** @@ -78,28 +75,56 @@ void BOARD_InitPins(void) { IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 is configured as GPIO9_IO03 */ 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG is configured as GPIO13_IO00 */ 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 PAD functional properties : */ 0x02U); /* Slew Rate Field: Slow Slew Rate Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz + Pull / Keep Select Field: Pull Disable Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled Domain write protection: Both cores are allowed Domain write protection lock: Neither of DWP bits is locked */ IOMUXC_SetPinConfig( + IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */ + 0x0EU); /* Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain SNVS Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} +- pin_list: + - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, pull_keeper_select: Keeper, slew_rate: Slow} + - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, pull_keeper_select: Keeper, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins, assigned for the Cortex-M7F core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */ 0x02U); /* Slew Rate Field: Slow Slew Rate Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz + Pull / Keep Select Field: Pull Disable Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled Domain write protection: Both cores are allowed @@ -108,22 +133,12 @@ void BOARD_InitPins(void) { IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */ 0x02U); /* Slew Rate Field: Slow Slew Rate Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz + Pull / Keep Select Field: Pull Disable Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled Domain write protection: Both cores are allowed Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */ - 0x0EU); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull up - Open Drain SNVS Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ } - /*********************************************************************************************************************** * EOF **********************************************************************************************************************/ diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h index 550bd1474..0e0368ef6 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h @@ -25,16 +25,6 @@ extern "C" { */ void BOARD_InitBootPins(void); -/* GPIO_AD_25 (coord M15), LPUART1_RXD */ -/* Routed pin properties */ -#define BOARD_INITPINS_LPUART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_LPUART1_RXD_SIGNAL RXD /*!< Signal name */ - -/* GPIO_AD_24 (coord L13), LPUART1_TXD */ -/* Routed pin properties */ -#define BOARD_INITPINS_LPUART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_LPUART1_TXD_SIGNAL TXD /*!< Signal name */ - /* GPIO_AD_04 (coord M13), SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7] */ /* Routed pin properties */ #define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO9 /*!< Peripheral name */ @@ -43,10 +33,11 @@ void BOARD_InitBootPins(void); /* Symbols to be used with GPIO driver */ #define BOARD_INITPINS_USER_LED_GPIO GPIO9 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ #define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */ #define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */ -/* WAKEUP (coord T8), USER_BUTTON */ +/* WAKEUP (coord T8), USER_BUTTON/SW7 */ /* Routed pin properties */ #define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO13 /*!< Peripheral name */ #define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ @@ -63,6 +54,22 @@ void BOARD_InitBootPins(void); */ void BOARD_InitPins(void); /* Function assigned for the Cortex-M7F */ +/* GPIO_AD_24 (coord L13), LPUART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_TXD_SIGNAL TXD /*!< Signal name */ + +/* GPIO_AD_25 (coord M15), LPUART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_RXD_SIGNAL RXD /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M7F */ + #if defined(__cplusplus) } #endif diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex index e68b9ea7e..de6b12394 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex @@ -1,5 +1,5 @@ <?xml version="1.0" encoding= "UTF-8" ?> -<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_14 http://mcuxpresso.nxp.com/XSD/mex_configuration_14.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="14" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_14" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> +<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <common> <processor>MIMXRT1176xxxxx</processor> <package>MIMXRT1176DVMAA</package> @@ -13,24 +13,22 @@ </common> <preferences> <validate_boot_init_only>true</validate_boot_init_only> - <generate_extended_information>false</generate_extended_information> <generate_code_modified_registers_only>false</generate_code_modified_registers_only> <update_include_paths>true</update_include_paths> <generate_registers_defines>false</generate_registers_defines> </preferences> <tools> - <pins name="Pins" version="14.0" enabled="true" update_project_code="true"> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> <generated_project_files> <file path="board/pin_mux.c" update_enabled="true"/> <file path="board/pin_mux.h" update_enabled="true"/> </generated_project_files> <pins_profile> - <processor_version>14.0.1</processor_version> + <processor_version>24.12.10</processor_version> <pin_labels> <pin_label pin_num="M13" pin_signal="GPIO_AD_04" label="SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7]" identifier="SIM1_PD;LED;USER_LED"/> </pin_labels> <external_user_signals> - <routingDetailsColumns/> <properties/> </external_user_signals> <power_domains/> @@ -44,11 +42,6 @@ <enableClock>true</enableClock> </options> <dependencies> - <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> - <feature name="initialized" evaluation="equal"> - <data>true</data> - </feature> - </dependency> <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> <feature name="enabled" evaluation="equal" configuration="cm7"> <data>true</data> @@ -66,51 +59,70 @@ </dependency> </dependencies> <pins> - <pin peripheral="LPUART1" signal="RXD" pin_num="M15" pin_signal="GPIO_AD_25"> + <pin peripheral="GPIO9" signal="gpio_io, 03" pin_num="M13" pin_signal="GPIO_AD_04"> <pin_features> - <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="identifier" value="USER_LED"/> + <pin_feature name="direction" value="OUTPUT"/> <pin_feature name="pull_up_down_config" value="Pull_Down"/> <pin_feature name="pull_keeper_select" value="Keeper"/> - <pin_feature name="open_drain" value="Disable"/> - <pin_feature name="drive_strength" value="High"/> - <pin_feature name="slew_rate" value="Slow"/> </pin_features> </pin> - <pin peripheral="LPUART1" signal="TXD" pin_num="L13" pin_signal="GPIO_AD_24"> + <pin peripheral="GPIO13" signal="gpio_io, 00" pin_num="T8" pin_signal="WAKEUP"> <pin_features> - <pin_feature name="software_input_on" value="Disable"/> - <pin_feature name="pull_up_down_config" value="Pull_Down"/> - <pin_feature name="pull_keeper_select" value="Keeper"/> - <pin_feature name="open_drain" value="Disable"/> - <pin_feature name="drive_strength" value="High"/> - <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="pull_up_down_config" value="Pull_Up"/> </pin_features> </pin> - <pin peripheral="GPIO9" signal="gpio_io, 03" pin_num="M13" pin_signal="GPIO_AD_04"> + </pins> + </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm7</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="TXD" pin_num="L13" pin_signal="GPIO_AD_24"> <pin_features> - <pin_feature name="identifier" value="USER_LED"/> - <pin_feature name="direction" value="OUTPUT"/> - <pin_feature name="pull_up_down_config" value="Pull_Down"/> <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="slew_rate" value="Slow"/> </pin_features> </pin> - <pin peripheral="GPIO13" signal="gpio_io, 00" pin_num="T8" pin_signal="WAKEUP"> + <pin peripheral="LPUART1" signal="RXD" pin_num="M15" pin_signal="GPIO_AD_25"> <pin_features> - <pin_feature name="direction" value="INPUT"/> - <pin_feature name="pull_up_down_config" value="Pull_Up"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="slew_rate" value="Slow"/> </pin_features> </pin> </pins> </function> </functions_list> </pins> - <clocks name="Clocks" version="12.0" enabled="true" update_project_code="true"> + <clocks name="Clocks" version="15.0" enabled="true" update_project_code="true"> <generated_project_files> <file path="board/clock_config.c" update_enabled="true"/> <file path="board/clock_config.h" update_enabled="true"/> </generated_project_files> <clocks_profile> - <processor_version>14.0.1</processor_version> + <processor_version>24.12.10</processor_version> </clocks_profile> <clock_configurations> <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> diff --git a/hw/bsp/imxrt/boards/teensy_40/board.h b/hw/bsp/imxrt/boards/teensy_40/board.h index 4a173c834..ae749e894 100644 --- a/hw/bsp/imxrt/boards/teensy_40/board.h +++ b/hw/bsp/imxrt/boards/teensy_40/board.h @@ -24,11 +24,14 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Teensy 4.0 + url: https://www.pjrc.com/store/teensy40.html +*/ #ifndef BOARD_H_ #define BOARD_H_ - // required since iMXRT MCUX-SDK include this file for board size #define BOARD_FLASH_SIZE (2 * 1024 * 1024) diff --git a/hw/bsp/imxrt/boards/teensy_41/board.h b/hw/bsp/imxrt/boards/teensy_41/board.h index 358684126..1bc022c54 100644 --- a/hw/bsp/imxrt/boards/teensy_41/board.h +++ b/hw/bsp/imxrt/boards/teensy_41/board.h @@ -24,11 +24,14 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Teensy 4.1 + url: https://www.pjrc.com/store/teensy41.html +*/ #ifndef BOARD_H_ #define BOARD_H_ - // required since iMXRT MCUX-SDK include this file for board size #define BOARD_FLASH_SIZE (8 * 1024 * 1024) diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index 6087ee37d..7e4734a66 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "bsp/board_api.h" #include "board/clock_config.h" #include "board/pin_mux.h" @@ -31,23 +35,36 @@ // Suppress warning caused by mcu driver #ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wunused-parameter" + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wunused-parameter" #endif +#include "fsl_clock.h" #include "fsl_device_registers.h" #include "fsl_gpio.h" #include "fsl_iomuxc.h" -#include "fsl_clock.h" #include "fsl_lpuart.h" #include "fsl_ocotp.h" #ifdef __GNUC__ -#pragma GCC diagnostic pop + #pragma GCC diagnostic pop #endif +/* --- Note about USB buffer RAM --- + For M7 core it's recommended to put USB buffer in DTCM for better performance (flexspi_nor linker default) + Otherwise you have to put the buffer in a non-cacheable section by configurate MPU manually or using BOARD_ConfigMPU(): + - Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) + - (IAR only) Change __NCACHE_REGION_SIZE in linker script to cover the size of non-cacheable section, multiple of 2^N + + For secondary M4 core, the USB controller doesn't support transfer from DTCM so OCRAM must be used: + - __NCACHE_REGION_SIZE is defined by the linker script by default + - Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) +*/ + +// static void BOARD_ConfigMPU(void); + // needed by fsl_flexspi_nor_boot -TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 }; +TU_ATTR_USED const uint8_t dcd_data[] = {0x00}; //--------------------------------------------------------------------+ // @@ -59,20 +76,20 @@ TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 }; #endif static void init_usb_phy(uint8_t usb_id) { - USBPHY_Type* usb_phy; + USBPHY_Type *usb_phy; if (usb_id == 0) { usb_phy = USBPHY1; CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ); } - #ifdef USBPHY2 +#ifdef USBPHY2 else if (usb_id == 1) { usb_phy = USBPHY2; CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ); } - #endif +#endif else { return; } @@ -91,14 +108,9 @@ static void init_usb_phy(uint8_t usb_id) { usb_phy->TX = phytx; } -void board_init(void) -{ - // make sure the dcache is on. -#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT - if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) SCB_EnableDCache(); -#endif - - BOARD_InitPins(); +void board_init(void) { + // BOARD_ConfigMPU(); + BOARD_InitBootPins(); BOARD_BootClockRUN(); SystemCoreClockUpdate(); @@ -113,9 +125,9 @@ void board_init(void) #elif CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) NVIC_SetPriority(USB_OTG1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#ifdef USBPHY2 + #ifdef USBPHY2 NVIC_SetPriority(USB_OTG2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif + #endif #endif board_led_write(true); @@ -127,16 +139,16 @@ void board_init(void) uart_config.enableTx = true; uart_config.enableRx = true; - if ( kStatus_Success != LPUART_Init(UART_PORT, &uart_config, UART_CLK_ROOT) ) { + if (kStatus_Success != LPUART_Init(UART_PORT, &uart_config, UART_CLK_ROOT)) { // failed to init uart, probably baudrate is not supported // TU_BREAKPOINT(); } //------------- USB -------------// // Note: RT105x RT106x and later have dual USB controllers. - init_usb_phy(0); // USB0 + init_usb_phy(0);// USB0 #ifdef USBPHY2 - init_usb_phy(1); // USB1 + init_usb_phy(1);// USB1 #endif } @@ -166,18 +178,18 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; - #if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL +#if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk)); - #else +#else OCOTP_Init(OCOTP, 0u); - #endif +#endif // Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info) // into 8 bit wide destination, avoiding punning. for (int i = 0; i < 4; ++i) { uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1); for (int j = 0; j < 4; j++) { - id[i*4+j] = wr & 0xff; + id[i * 4 + j] = wr & 0xff; wr >>= 8; } } @@ -186,7 +198,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) { return 16; } -int board_uart_read(uint8_t* buf, int len) { +int board_uart_read(uint8_t *buf, int len) { int count = 0; while (count < len) { @@ -209,8 +221,8 @@ int board_uart_read(uint8_t* buf, int len) { return count; } -int board_uart_write(void const * buf, int len) { - LPUART_WriteBlocking(UART_PORT, (uint8_t const*)buf, len); +int board_uart_write(void const *buf, int len) { + LPUART_WriteBlocking(UART_PORT, (uint8_t const *) buf, len); return len; } @@ -237,9 +249,392 @@ TU_ATTR_UNUSED void _start(void) { } #ifdef __clang__ -void _exit (int __status) { +void _exit(int __status) { while (1) {} } #endif +#endif + +//-------------------------------------------------------------------- +// MPU configuration +//-------------------------------------------------------------------- +#if 0 // TODO move to per board specific +#if __CORTEX_M == 7 +static void BOARD_ConfigMPU(void) { + #if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_unused$$Base[]; + extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; + uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base; + uint32_t size = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); + #elif defined(__MCUXPRESSO) + #if defined(__USE_SHMEM) + extern uint32_t __base_rpmsg_sh_mem; + extern uint32_t __top_rpmsg_sh_mem; + uint32_t nonCacheStart = (uint32_t) (&__base_rpmsg_sh_mem); + uint32_t size = (uint32_t) (&__top_rpmsg_sh_mem) - nonCacheStart; + #else + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION); + uint32_t size = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart; + #endif + #elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START; + uint32_t size = (uint32_t) __NCACHE_REGION_SIZE; + #endif + volatile uint32_t i = 0; + + #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + /* Disable I cache and D cache */ + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_DisableICache(); + } + #endif + #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_DisableDCache(); + } + #endif + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, + * SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches + * disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and + * Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outer cache + * policy. + * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf> + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in + * mpu_armv7.h. + */ + + /* + * Add default region to deny access to whole address space to workaround speculative prefetch. + * Refer to Arm errata 1013783-B for more details. + * + */ + /* Region 0 setting: Instruction access disabled, No data access permission. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH + /* Region 6 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 7 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB); + #else + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); + #endif + + #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB); + #endif + + #ifdef USE_SDRAM + #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH + /* Region 9 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB); + #else + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); + #endif + #endif + + while ((size >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % size)); + assert(size == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } + + /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB); + + /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); + + /* Region 13 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); + /* Region 14 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); + + /* Region 15 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enable I cache and D cache */ + #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + SCB_EnableDCache(); + #endif + #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + SCB_EnableICache(); + #endif +} + +#elif __CORTEX_M == 4 + +static void BOARD_ConfigMPU(void) { + #if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_unused$$Base[]; + extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; + uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base; + uint32_t nonCacheSize = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); + #elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION); + uint32_t nonCacheSize = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart; + #elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START; + uint32_t nonCacheSize = (uint32_t) __NCACHE_REGION_SIZE; + #endif + #if defined(__USE_SHMEM) + #if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; + /* RPMSG_SH_MEM_unused is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ + extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[]; + extern uint32_t Image$$RPMSG_SH_MEM_unused$$ZI$$Limit[]; + uint32_t rpmsgShmemStart = (uint32_t) Image$$RPMSG_SH_MEM$$Base; + uint32_t rpmsgShmemSize = (uint32_t) Image$$RPMSG_SH_MEM_unused$$ZI$$Limit - rpmsgShmemStart; + #elif defined(__MCUXPRESSO) + extern uint32_t __base_rpmsg_sh_mem; + extern uint32_t __top_rpmsg_sh_mem; + uint32_t rpmsgShmemStart = (uint32_t) (&__base_rpmsg_sh_mem); + uint32_t rpmsgShmemSize = (uint32_t) (&__top_rpmsg_sh_mem) - rpmsgShmemStart; + #elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __RPMSG_SH_MEM_START[]; + extern uint32_t __RPMSG_SH_MEM_SIZE[]; + uint32_t rpmsgShmemStart = (uint32_t) __RPMSG_SH_MEM_START; + uint32_t rpmsgShmemSize = (uint32_t) __RPMSG_SH_MEM_SIZE; + #endif + #endif + uint32_t i = 0; + + /* Only config non-cacheable region on system bus */ + assert(nonCacheStart >= 0x20000000); + + /* Disable code bus cache */ + if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR)) { + /* Enable the processor code bus to push all modified lines. */ + LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK); + /* Now disable the cache. */ + LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; + } + + /* Disable system bus cache */ + if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR)) { + /* Enable the processor system bus to push all modified lines. */ + LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK); + /* Now disable the cache. */ + LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK; + } + + /* Disable MPU */ + ARM_MPU_Disable(); + + #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH + /* Region 0 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 1 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x20300000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB); + + /* Region 2 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB); + + while ((nonCacheSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % nonCacheSize)); + assert(nonCacheSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 3 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(3, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + + #if defined(__USE_SHMEM) + i = 0; + + while ((rpmsgShmemSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 4 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(4, rpmsgShmemStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + #endif + #else + while ((nonCacheSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % nonCacheSize)); + assert(nonCacheSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 0 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(0, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + + #if defined(__USE_SHMEM) + i = 0; + + while ((rpmsgShmemSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 1 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(1, rpmsgShmemStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + #endif + #endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enables the processor system bus to invalidate all lines in both ways. + and Initiate the processor system bus cache command. */ + LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK; + /* Wait until the cache command completes */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK); + /* Now enable the system bus cache. */ + LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK; + + /* Enables the processor code bus to invalidate all lines in both ways. + and Initiate the processor code bus code cache command. */ + LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); + /* Now enable the code bus cache. */ + LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; +} +#endif #endif diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index d917e9777..6224b63a4 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -8,7 +8,9 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(MCU_VARIANT_WITH_CORE ${MCU_VARIANT}${MCU_CORE}) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") +if (NOT DEFINED CMAKE_SYSTEM_CPU) + set(CMAKE_SYSTEM_CPU cortex-m7 CACHE INTERNAL "System Processor") +endif () set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "") @@ -25,13 +27,13 @@ function(add_board_target BOARD_TARGET) # LD_FILE and STARTUP_FILE can be defined in board.cmake if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID}) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.ld) - #set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld) + set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.icf) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID}) set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S) - #set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S) + set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/startup_${MCU_VARIANT_WITH_CORE}.s) endif () set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) @@ -58,13 +60,21 @@ function(add_board_target BOARD_TARGET) endif() endforeach() + target_compile_definitions(${BOARD_TARGET} PUBLIC - __ARMVFP__=0 - __ARMFPV5__=0 - XIP_EXTERNAL_FLASH=1 - XIP_BOOT_HEADER_ENABLE=1 __STARTUP_CLEAR_BSS + CFG_TUSB_MEM_SECTION=__attribute__\(\(section\(\"NonCacheable\"\)\)\) ) + + if (NOT M4 STREQUAL "1") + target_compile_definitions(${BOARD_TARGET} PUBLIC + __ARMVFP__=0 + __ARMFPV5__=0 + XIP_EXTERNAL_FLASH=1 + XIP_BOOT_HEADER_ENABLE=1 + ) + endif () + target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board @@ -113,8 +123,6 @@ function(family_configure_example TARGET RTOS) # Board target add_board_target(board_${BOARD}) - #---------- Port Specific ---------- - # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c @@ -128,18 +136,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX ${RTOS}) - target_sources(${TARGET}-tinyusb PRIVATE + family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX) + target_sources(${TARGET} PRIVATE ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c ${TOP}/src/portable/ehci/ehci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk index f00afb6a4..9a2c37121 100644 --- a/hw/bsp/imxrt/family.mk +++ b/hw/bsp/imxrt/family.mk @@ -1,6 +1,5 @@ UF2_FAMILY_ID = 0x4fb2d5bd SDK_DIR = hw/mcu/nxp/mcux-sdk -DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5 include $(TOP)/$(BOARD_PATH)/board.mk @@ -9,12 +8,17 @@ MCU_VARIANT_WITH_CORE = ${MCU_VARIANT}${MCU_CORE} MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT) CFLAGS += \ + -D__STARTUP_CLEAR_BSS \ + -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX \ + -DCFG_TUSB_MEM_SECTION='__attribute__((section("NonCacheable")))' \ + +ifneq ($(M4), 1) +CFLAGS += \ -D__ARMVFP__=0 \ -D__ARMFPV5__=0 \ - -D__STARTUP_CLEAR_BSS \ -DXIP_EXTERNAL_FLASH=1 \ - -DXIP_BOOT_HEADER_ENABLE=1 \ - -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX + -DXIP_BOOT_HEADER_ENABLE=1 +endif ifdef BOARD_TUD_RHPORT CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT) diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/board.h b/hw/bsp/kinetis_k/boards/frdm_k64f/board.h index ae8c66182..75a10f961 100644 --- a/hw/bsp/kinetis_k/boards/frdm_k64f/board.h +++ b/hw/bsp/kinetis_k/boards/frdm_k64f/board.h @@ -22,6 +22,11 @@ * THE SOFTWARE. */ +/* metadata: + name: Freedom K64F + url: https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/kinetis_k/boards/teensy_35/board.h b/hw/bsp/kinetis_k/boards/teensy_35/board.h index f8173447a..4718a0241 100644 --- a/hw/bsp/kinetis_k/boards/teensy_35/board.h +++ b/hw/bsp/kinetis_k/boards/teensy_35/board.h @@ -22,6 +22,11 @@ * THE SOFTWARE. */ +/* metadata: + name: Teensy 3.5 + url: https://www.pjrc.com/store/teensy35.html +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/kinetis_k/family.c b/hw/bsp/kinetis_k/family.c index 30dfe6d76..59d80fa18 100644 --- a/hw/bsp/kinetis_k/family.c +++ b/hw/bsp/kinetis_k/family.c @@ -23,6 +23,10 @@ * THE SOFTWARE. */ +/* metadata: + manufacturer: NXP +*/ + #include "bsp/board_api.h" #include "board.h" #include "fsl_device_registers.h" diff --git a/hw/bsp/kinetis_k/family.cmake b/hw/bsp/kinetis_k/family.cmake index c30268629..ce91777c9 100644 --- a/hw/bsp/kinetis_k/family.cmake +++ b/hw/bsp/kinetis_k/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS KINETIS_K CACHE INTERNAL "") @@ -97,17 +97,17 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c ${TOP}/src/portable/nxp/khci/hcd_khci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) if (DEFINED TEENSY_MCU) diff --git a/hw/bsp/kinetis_k/family.mk b/hw/bsp/kinetis_k/family.mk index 844ce332e..e95cdb717 100644 --- a/hw/bsp/kinetis_k/family.mk +++ b/hw/bsp/kinetis_k/family.mk @@ -1,5 +1,4 @@ SDK_DIR = hw/mcu/nxp/mcux-sdk -DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5 MCU_DIR = $(SDK_DIR)/devices/${MCU_VARIANT} include $(TOP)/$(BOARD_PATH)/board.mk diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h index 16f832722..9e2534307 100644 --- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Freedom K32L2A4S + url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-K32L2A4S +*/ #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk index c4dc65b63..fb3eb2a03 100644 --- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk @@ -3,7 +3,7 @@ MCU = K32L2A41A CFLAGS += -DCPU_K32L2A41VLH1A # mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual +CFLAGS_GCC += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual # All source paths should be relative to the top level. LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h index 790d6fcb0..854340d6d 100644 --- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Freedom K32L2B3 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/nxp-freedom-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3 +*/ #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/board.h b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h index ec3702376..f5895fc65 100644 --- a/hw/bsp/kinetis_k32l2/boards/kuiic/board.h +++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Kuiic + url: https://github.com/nxf58843/kuiic +*/ #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/kinetis_k32l2/family.c b/hw/bsp/kinetis_k32l2/family.c index 92f5ba6d3..2fcc1b2af 100644 --- a/hw/bsp/kinetis_k32l2/family.c +++ b/hw/bsp/kinetis_k32l2/family.c @@ -25,6 +25,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "fsl_gpio.h" #include "fsl_port.h" #include "fsl_clock.h" diff --git a/hw/bsp/kinetis_k32l2/family.cmake b/hw/bsp/kinetis_k32l2/family.cmake index 406ae99d3..946614a03 100644 --- a/hw/bsp/kinetis_k32l2/family.cmake +++ b/hw/bsp/kinetis_k32l2/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS KINETIS_K32L CACHE INTERNAL "") @@ -92,21 +92,20 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K32L ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K32L) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/khci/dcd_khci.c ${TOP}/src/portable/nxp/khci/hcd_khci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_flash_jlink(${TARGET}) + family_add_bin_hex(${TARGET}) if (DEFINED TEENSY_MCU) - family_add_bin_hex(${TARGET}) family_flash_teensy(${TARGET}) endif () endfunction() diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h index 23f144666..b03fe91a8 100644 --- a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h +++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h @@ -22,6 +22,11 @@ * THE SOFTWARE. */ +/* metadata: + name: fomu + url: https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/kinetis_kl/family.c b/hw/bsp/kinetis_kl/family.c index 254a95176..fe864f3a0 100644 --- a/hw/bsp/kinetis_kl/family.c +++ b/hw/bsp/kinetis_kl/family.c @@ -23,6 +23,10 @@ * THE SOFTWARE. */ +/* metadata: + manufacturer: NXP +*/ + #include "bsp/board_api.h" #include "board.h" #include "fsl_device_registers.h" diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake index 85a913d54..51a646258 100644 --- a/hw/bsp/kinetis_kl/family.cmake +++ b/hw/bsp/kinetis_kl/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS KINETIS_KL CACHE INTERNAL "") @@ -96,16 +96,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c ${TOP}/src/portable/nxp/khci/hcd_khci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/kinetis_kl/family.mk b/hw/bsp/kinetis_kl/family.mk index 1fdce981a..8d113aecf 100644 --- a/hw/bsp/kinetis_kl/family.mk +++ b/hw/bsp/kinetis_kl/family.mk @@ -1,5 +1,4 @@ SDK_DIR = hw/mcu/nxp/mcux-sdk -DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5 MCU_DIR = $(SDK_DIR)/devices/$(MCU) include $(TOP)/$(BOARD_PATH)/board.mk diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h index 930462f28..c8a48eecb 100644 --- a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h +++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: LPCXpresso11U37 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13074 +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h index a12fcbef1..50141e4a5 100644 --- a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h +++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: LPCXpresso11U68 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13058 +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/lpc11/family.c b/hw/bsp/lpc11/family.c index e75bc4919..b5371632c 100644 --- a/hw/bsp/lpc11/family.c +++ b/hw/bsp/lpc11/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" @@ -38,6 +42,10 @@ #include "bsp/board_api.h" #include "board.h" +extern void USB_IRQHandler(void); +extern void SysTick_Handler(void); +void SystemInit(void); + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/lpc11/family.cmake b/hw/bsp/lpc11/family.cmake index 818600656..6781b20c6 100644 --- a/hw/bsp/lpc11/family.cmake +++ b/hw/bsp/lpc11/family.cmake @@ -11,7 +11,7 @@ else() endif() # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC11UXX CACHE INTERNAL "") @@ -49,7 +49,10 @@ function(add_board_target BOARD_TARGET) update_board(${BOARD_TARGET}) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib) + target_compile_options(${BOARD_TARGET} PUBLIC + -nostdlib + -Wno-error=incompatible-pointer-types + ) target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" --specs=nosys.specs --specs=nano.specs @@ -90,16 +93,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC11UXX ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_LPC11UXX) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc13/boards/lpcxpresso1347/board.h b/hw/bsp/lpc13/boards/lpcxpresso1347/board.h index 71e608b46..acf29fdc6 100644 --- a/hw/bsp/lpc13/boards/lpcxpresso1347/board.h +++ b/hw/bsp/lpc13/boards/lpcxpresso1347/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: LPCXpresso1347 + url: https://www.nxp.com/products/no-longer-manufactured/lpcxpresso-board-for-lpc1347:OM13045 +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk b/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk index 31eb2f28f..8513c24ca 100644 --- a/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk +++ b/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/nxp/lpcopen - CFLAGS += \ -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' diff --git a/hw/bsp/lpc13/family.c b/hw/bsp/lpc13/family.c index 7e04c1cf5..1faa54485 100644 --- a/hw/bsp/lpc13/family.c +++ b/hw/bsp/lpc13/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "chip.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/lpc13/family.cmake b/hw/bsp/lpc13/family.cmake index f7f5c0180..e3c0b18c7 100644 --- a/hw/bsp/lpc13/family.cmake +++ b/hw/bsp/lpc13/family.cmake @@ -8,7 +8,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC13XX CACHE INTERNAL "") @@ -87,16 +87,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC13XX ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_LPC13XX) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc13/family.mk b/hw/bsp/lpc13/family.mk index 4f8b48c4b..7ff2c058a 100644 --- a/hw/bsp/lpc13/family.mk +++ b/hw/bsp/lpc13/family.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/nxp/lpcopen - MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m3 diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/board.h b/hw/bsp/lpc15/boards/lpcxpresso1549/board.h index 5ed5b75b2..1be2045a9 100644 --- a/hw/bsp/lpc15/boards/lpcxpresso1549/board.h +++ b/hw/bsp/lpc15/boards/lpcxpresso1549/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso1549 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13056 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c index b9ce39648..e23fdec43 100644 --- a/hw/bsp/lpc15/family.c +++ b/hw/bsp/lpc15/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstrict-prototypes" diff --git a/hw/bsp/lpc15/family.cmake b/hw/bsp/lpc15/family.cmake index 61b47d852..761c5a619 100644 --- a/hw/bsp/lpc15/family.cmake +++ b/hw/bsp/lpc15/family.cmake @@ -8,7 +8,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC15XX CACHE INTERNAL "") @@ -89,16 +89,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC15XX ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_LPC15XX) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk index b83e008e8..3267e973a 100644 --- a/hw/bsp/lpc15/family.mk +++ b/hw/bsp/lpc15/family.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/nxp/lpcopen - include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m3 @@ -15,7 +13,7 @@ CFLAGS += \ LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs # mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual +CFLAGS_GCC += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual MCU_DIR = hw/mcu/nxp/lpcopen/lpc15xx/lpc_chip_15xx diff --git a/hw/bsp/lpc17/boards/lpcxpresso1769/board.h b/hw/bsp/lpc17/boards/lpcxpresso1769/board.h index d6aa98ed9..6f5c12854 100644 --- a/hw/bsp/lpc17/boards/lpcxpresso1769/board.h +++ b/hw/bsp/lpc17/boards/lpcxpresso1769/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso1769 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13000 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc17/boards/mbed1768/board.h b/hw/bsp/lpc17/boards/mbed1768/board.h index 2b3ddc905..2c75cede4 100644 --- a/hw/bsp/lpc17/boards/mbed1768/board.h +++ b/hw/bsp/lpc17/boards/mbed1768/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: mbed 1768 + url: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1700-arm-cortex-m3/arm-mbed-lpc1768-board:OM11043 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc17/family.c b/hw/bsp/lpc17/family.c index 79281ba41..7d3231f6a 100644 --- a/hw/bsp/lpc17/family.c +++ b/hw/bsp/lpc17/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "chip.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/lpc17/family.cmake b/hw/bsp/lpc17/family.cmake index cccfdac9f..771a0f405 100644 --- a/hw/bsp/lpc17/family.cmake +++ b/hw/bsp/lpc17/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC175X_6X CACHE INTERNAL "") @@ -86,18 +86,18 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC175X_6X ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_LPC175X_6X) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c ${TOP}/src/portable/ohci/ohci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc17/family.mk b/hw/bsp/lpc17/family.mk index d719a47b7..e8d707ea5 100644 --- a/hw/bsp/lpc17/family.mk +++ b/hw/bsp/lpc17/family.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/nxp/lpcopen - MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m3 @@ -13,7 +11,7 @@ CFLAGS += \ -DRTC_EV_SUPPORT=0 # lpc_types.h cause following errors -CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual +CFLAGS_GCC += -Wno-error=strict-prototypes -Wno-error=cast-qual # caused by freeRTOS port !! CFLAGS += -Wno-error=maybe-uninitialized diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h index f4c85ddc9..2cf4dbdf8 100644 --- a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h +++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso18s37 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso18s37-development-board:OM13076 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc18/boards/mcb1800/board.h b/hw/bsp/lpc18/boards/mcb1800/board.h index 93b3cd112..dba7a62a3 100644 --- a/hw/bsp/lpc18/boards/mcb1800/board.h +++ b/hw/bsp/lpc18/boards/mcb1800/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Keil MCB1800 + url: https://www.keil.com/arm/mcb1800/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c index 55ef31ee4..0db5c83b6 100644 --- a/hw/bsp/lpc18/family.c +++ b/hw/bsp/lpc18/family.c @@ -24,10 +24,19 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "chip.h" #include "bsp/board_api.h" #include "board.h" +extern void USB0_IRQHandler(void); +extern void USB1_IRQHandler(void); +extern void SysTick_Handler(void); +void SystemInit(void); + //--------------------------------------------------------------------+ // USB Interrupt Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake index 309186667..6af1149bf 100644 --- a/hw/bsp/lpc18/family.cmake +++ b/hw/bsp/lpc18/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC18XX CACHE INTERNAL "") @@ -84,17 +84,17 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c ${TOP}/src/portable/ehci/ehci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk index f625e926a..3bbafed11 100644 --- a/hw/bsp/lpc18/family.mk +++ b/hw/bsp/lpc18/family.mk @@ -1,4 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/nxp/lpcopen MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx include $(TOP)/$(BOARD_PATH)/board.mk @@ -12,7 +11,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_LPC18XX # mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=cast-qual +CFLAGS_GCC += -Wno-error=unused-parameter -Wno-error=cast-qual LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.h b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h index d5489c154..ede0a306d 100644 --- a/hw/bsp/lpc40/boards/ea4088_quickstart/board.h +++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Embedded Artists LPC4088 QuickStart Board + url: https://www.embeddedartists.com/products/lpc4088-quickstart-board/ +*/ + #ifndef EA4088QS__BOARD_H #define EA4088QS__BOARD_H diff --git a/hw/bsp/lpc40/family.c b/hw/bsp/lpc40/family.c index d6c8ef32a..b8bc99452 100644 --- a/hw/bsp/lpc40/family.c +++ b/hw/bsp/lpc40/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "chip.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake index 4c14da8a7..3a680eae6 100644 --- a/hw/bsp/lpc40/family.cmake +++ b/hw/bsp/lpc40/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC40XX CACHE INTERNAL "") @@ -87,18 +87,18 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC40XX ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_LPC40XX) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c ${TOP}/src/portable/ohci/ohci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc40/family.mk b/hw/bsp/lpc40/family.mk index ef9fe57b2..c72631235 100644 --- a/hw/bsp/lpc40/family.mk +++ b/hw/bsp/lpc40/family.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/nxp/lpcopen - MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m4 @@ -13,7 +11,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_LPC40XX # mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual +CFLAGS_GCC += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs diff --git a/hw/bsp/lpc43/boards/ea4357/board.h b/hw/bsp/lpc43/boards/ea4357/board.h index fb52e32a7..fca617361 100644 --- a/hw/bsp/lpc43/boards/ea4357/board.h +++ b/hw/bsp/lpc43/boards/ea4357/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Embedded Artists LPC4357 Development Kit + url: https://www.embeddedartists.com/products/lpc4357-developers-kit/ +*/ + #ifndef _BOARD_EA4357_H #define _BOARD_EA4357_H diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h index 4dd90fe29..4427905e8 100644 --- a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h +++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso43S67 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso43s67-development-board:OM13084 +*/ + #ifndef _BOARD_LPCXPRESSO43S67_H_ #define _BOARD_LPCXPRESSO43S67_H_ diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c index dfee9f5ea..591090c36 100644 --- a/hw/bsp/lpc43/family.c +++ b/hw/bsp/lpc43/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + // Suppress warning caused by mcu driver #ifdef __GNUC__ #pragma GCC diagnostic push @@ -43,6 +47,11 @@ const uint32_t OscRateIn = 12000000; const uint32_t ExtRateIn = 0; +extern void USB0_IRQHandler(void); +extern void USB1_IRQHandler(void); +extern void SysTick_Handler(void); +void SystemInit(void); + /*------------------------------------------------------------------*/ /* BOARD API *------------------------------------------------------------------*/ diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake index 2bacd9ea4..23c4aecea 100644 --- a/hw/bsp/lpc43/family.cmake +++ b/hw/bsp/lpc43/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC43XX CACHE INTERNAL "") @@ -51,7 +51,10 @@ function(add_board_target BOARD_TARGET) update_board(${BOARD_TARGET}) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib) + target_compile_options(${BOARD_TARGET} PUBLIC + -nostdlib + -Wno-error=incompatible-pointer-types + ) target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" --specs=nosys.specs --specs=nano.specs @@ -92,17 +95,17 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC43XX ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_LPC43XX) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c ${TOP}/src/portable/ehci/ehci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc43/family.mk b/hw/bsp/lpc43/family.mk index 84e7c30b3..39be867d1 100644 --- a/hw/bsp/lpc43/family.mk +++ b/hw/bsp/lpc43/family.mk @@ -1,20 +1,18 @@ -DEPS_SUBMODULES += hw/mcu/nxp/lpcopen SDK_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx include ${TOP}/${BOARD_PATH}/board.mk CPU_CORE ?= cortex-m4 CFLAGS += \ - -flto \ - -nostdlib \ -DCORE_M4 \ -D__USE_LPCOPEN \ -DCFG_TUSB_MCU=OPT_MCU_LPC43XX # mcu driver cause following warnings -CFLAGS += \ +CFLAGS_GCC += \ + -flto \ + -nostdlib \ -Wno-error=unused-parameter \ - -Wno-error=strict-prototypes \ -Wno-error=cast-qual \ -Wno-error=incompatible-pointer-types \ diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h index 0a3b37fda..151fae24b 100644 --- a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h +++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: LPCXpresso51u68 + url: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpcxpresso51u68-for-the-lpc51u68-mcus:OM40005 +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/lpc51/family.c b/hw/bsp/lpc51/family.c index a0667a741..0afe33d41 100644 --- a/hw/bsp/lpc51/family.c +++ b/hw/bsp/lpc51/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "fsl_device_registers.h" #include "fsl_gpio.h" #include "fsl_power.h" diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake index b9dd8829e..09d97d256 100644 --- a/hw/bsp/lpc51/family.cmake +++ b/hw/bsp/lpc51/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC51 CACHE INTERNAL "") @@ -36,7 +36,7 @@ function(add_board_target BOARD_TARGET) # driver ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c - ${SDK_DIR}/drivers/flexcomm/fsl_usart.c + ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c # mcu ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c @@ -106,16 +106,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC51 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_LPC51) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) diff --git a/hw/bsp/lpc51/family.mk b/hw/bsp/lpc51/family.mk index b41b5438e..91d1261cb 100644 --- a/hw/bsp/lpc51/family.mk +++ b/hw/bsp/lpc51/family.mk @@ -28,15 +28,16 @@ SRC_C += \ $(MCU_DIR)/drivers/fsl_reset.c \ $(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \ $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ - $(SDK_DIR)/drivers/flexcomm/fsl_usart.c + $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(MCU_DIR) \ $(TOP)/$(MCU_DIR)/drivers \ $(TOP)/$(SDK_DIR)/drivers/common \ $(TOP)/$(SDK_DIR)/drivers/flexcomm \ + $(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \ $(TOP)/$(SDK_DIR)/drivers/lpc_iocon \ $(TOP)/$(SDK_DIR)/drivers/lpc_gpio diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h index b1ad4258c..c43ca9d7d 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso54114 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54114-board:OM13089 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h index 8bbe18155..e985e97e0 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso54608 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-development-board-for-lpc5460x-mcus:OM13092 +*/ + #ifndef BOARD_LPCXPRESSO54608_H_ #define BOARD_LPCXPRESSO54608_H_ diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h index 670277512..837d26aef 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso54628 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54628-development-board:OM13098 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c index 5e6ff2231..9b9b5841b 100644 --- a/hw/bsp/lpc54/family.c +++ b/hw/bsp/lpc54/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "fsl_device_registers.h" #include "fsl_gpio.h" #include "fsl_power.h" diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake index 5c61a07f0..66320870a 100644 --- a/hw/bsp/lpc54/family.cmake +++ b/hw/bsp/lpc54/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC54 CACHE INTERNAL "") @@ -44,7 +44,7 @@ function(add_board_target BOARD_TARGET) ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c ${SDK_DIR}/drivers/common/fsl_common_arm.c ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c - ${SDK_DIR}/drivers/flexcomm/fsl_usart.c + ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c # mcu ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c @@ -56,6 +56,7 @@ function(add_board_target BOARD_TARGET) # driver ${SDK_DIR}/drivers/common ${SDK_DIR}/drivers/flexcomm + ${SDK_DIR}/drivers/flexcomm/usart ${SDK_DIR}/drivers/lpc_iocon ${SDK_DIR}/drivers/lpc_gpio ${SDK_DIR}/drivers/lpuart @@ -139,16 +140,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC54 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_LPC54) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk index ea4c9c39c..94168f6b2 100644 --- a/hw/bsp/lpc54/family.mk +++ b/hw/bsp/lpc54/family.mk @@ -1,5 +1,4 @@ SDK_DIR = hw/mcu/nxp/mcux-sdk -DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5 include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m4 @@ -36,7 +35,7 @@ SRC_C += \ $(MCU_DIR)/drivers/fsl_reset.c \ $(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \ $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ - $(SDK_DIR)/drivers/flexcomm/fsl_usart.c \ + $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \ $(SDK_DIR)/drivers/common/fsl_common_arm.c INC += \ @@ -46,6 +45,7 @@ INC += \ $(TOP)/$(MCU_DIR)/drivers \ $(TOP)/$(SDK_DIR)/drivers/common \ $(TOP)/$(SDK_DIR)/drivers/flexcomm \ + $(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \ $(TOP)/$(SDK_DIR)/drivers/lpc_iocon \ $(TOP)/$(SDK_DIR)/drivers/lpc_gpio diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.h b/hw/bsp/lpc55/boards/double_m33_express/board.h index 975e74e92..dc11e47fc 100644 --- a/hw/bsp/lpc55/boards/double_m33_express/board.h +++ b/hw/bsp/lpc55/boards/double_m33_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Double M33 Express + url: https://www.crowdsupply.com/steiert-solutions/double-m33-express +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h index f85701b08..907aee6a4 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso55s28 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s28-development-board:LPC55S28-EVK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h index f85701b08..e18d5bbad 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso55s69 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc55/boards/mcu_link/board.h b/hw/bsp/lpc55/boards/mcu_link/board.h index 5e17cf9fd..1d71b3e79 100644 --- a/hw/bsp/lpc55/boards/mcu_link/board.h +++ b/hw/bsp/lpc55/boards/mcu_link/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MCU Link + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcu-link-debug-probe:MCU-LINK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c index 68ccf52d5..dbf8d71b7 100644 --- a/hw/bsp/lpc55/family.c +++ b/hw/bsp/lpc55/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "bsp/board_api.h" #include "board.h" #include "fsl_device_registers.h" diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index 21c57fc1f..a89548635 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC55 CACHE INTERNAL "") @@ -44,7 +44,7 @@ function(add_board_target BOARD_TARGET) ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c ${SDK_DIR}/drivers/common/fsl_common_arm.c ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c - ${SDK_DIR}/drivers/flexcomm/fsl_usart.c + ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c # mcu ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c @@ -56,9 +56,9 @@ function(add_board_target BOARD_TARGET) # driver ${SDK_DIR}/drivers/common ${SDK_DIR}/drivers/flexcomm + ${SDK_DIR}/drivers/flexcomm/usart ${SDK_DIR}/drivers/lpc_iocon ${SDK_DIR}/drivers/lpc_gpio - ${SDK_DIR}/drivers/lpuart ${SDK_DIR}/drivers/sctimer # mcu ${SDK_DIR}/devices/${MCU_VARIANT} @@ -140,16 +140,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC55 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_LPC55) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk index d82e85904..fadf852cd 100644 --- a/hw/bsp/lpc55/family.mk +++ b/hw/bsp/lpc55/family.mk @@ -1,6 +1,5 @@ UF2_FAMILY_ID = 0x2abc77ec SDK_DIR = hw/mcu/nxp/mcux-sdk -DEPS_SUBMODULES += lib/CMSIS_5 lib/sct_neopixel $(SDK_DIR) include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m33 @@ -45,7 +44,7 @@ SRC_C += \ $(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \ $(SDK_DIR)/drivers/common/fsl_common_arm.c \ $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ - $(SDK_DIR)/drivers/flexcomm/fsl_usart.c \ + $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \ lib/sct_neopixel/sct_neopixel.c INC += \ @@ -55,11 +54,10 @@ INC += \ $(TOP)/$(MCU_DIR) \ $(TOP)/$(MCU_DIR)/drivers \ $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/flexcomm \ + $(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \ + $(TOP)/$(SDK_DIR)/drivers/flexcomm/ \ $(TOP)/$(SDK_DIR)/drivers/lpc_iocon \ $(TOP)/$(SDK_DIR)/drivers/lpc_gpio \ $(TOP)/$(SDK_DIR)/drivers/sctimer SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S - -LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a diff --git a/hw/bsp/max32650/README.md b/hw/bsp/max32650/README.md deleted file mode 100644 index ca66a1ac4..000000000 --- a/hw/bsp/max32650/README.md +++ /dev/null @@ -1,46 +0,0 @@ -# Analog Devices MAX32650/1/2 - -This BSP is for working with the Analog Devices -[MAX32650](https://www.analog.com/en/products/max32650.html), -[MAX32651](https://www.analog.com/en/products/max32651.html) and -[MAX32652](https://www.analog.com/en/products/max32652.html) -microcontrollers. The following boards are supported: - * [MAX32650EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html) - * [MAX32650FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html) - * [MAX32651EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html) (Secure Bootloader) - -This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device -interfaces and hardware abstraction layers. This source code package is fetched -as part of the get-deps script. - -The microcontrollers utilize the standard GNU ARM toolchain. If this toolchain -is not already available on your build machine, it can be installed by using the -bundled MSDK installation. Details on downloading and installing can be found -in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/). - -## Flashing - -### MAX32650 and MAX32652 - -The default flashing behavior in this BSP for the MAX32650 and MAX32652 is to -utilize JLink. This can be done by running the `flash` or `flash-jlink` rule -for Makefiles, or the `<target>-jlink` target for CMake. - -Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP -compatible debug probe. However, at the time of writing, the necessary flashing -algorithms for OpenOCD have not yet been incorporated into the OpenOCD master -branch. To utilize the provided debug probes, please install the bundled MSDK -package which includes the appropriate OpenOCD modifications. To leverage this -OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake -target. - -### MAX32651 - -The MAX32651 features an integrated secure bootloader which requires the -application image be signed prior to flashing. Both the Makefile and CMake -scripts account for this signing automatically when building for the -MAX32651EVKIT. - -To flash the signed image, the MSDK's OpenOCD variant must be used. To flash -the MAX32651EVKIT please install the bundled MSDK, and utilize the `flash-msdk` -and `<target>-msdk` rule and target. diff --git a/hw/bsp/max32650/boards/max32650evkit/board.cmake b/hw/bsp/max32650/boards/max32650evkit/board.cmake deleted file mode 100644 index fffdcc9fb..000000000 --- a/hw/bsp/max32650/boards/max32650evkit/board.cmake +++ /dev/null @@ -1,10 +0,0 @@ -# Use the standard, non-secure linker file -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld) - -function(update_board_extras TARGET) - #No extra arguments -endfunction() - -function(prepare_image TARGET_IN) - #No signing required -endfunction() diff --git a/hw/bsp/max32650/boards/max32650evkit/board.mk b/hw/bsp/max32650/boards/max32650evkit/board.mk deleted file mode 100644 index 0bc210e11..000000000 --- a/hw/bsp/max32650/boards/max32650evkit/board.mk +++ /dev/null @@ -1,2 +0,0 @@ -# Use the standard, non-secure linker file -LD_FILE = $(BOARD_PATH)/max32650.ld diff --git a/hw/bsp/max32650/boards/max32650fthr/board.cmake b/hw/bsp/max32650/boards/max32650fthr/board.cmake deleted file mode 100644 index fffdcc9fb..000000000 --- a/hw/bsp/max32650/boards/max32650fthr/board.cmake +++ /dev/null @@ -1,10 +0,0 @@ -# Use the standard, non-secure linker file -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld) - -function(update_board_extras TARGET) - #No extra arguments -endfunction() - -function(prepare_image TARGET_IN) - #No signing required -endfunction() diff --git a/hw/bsp/max32650/boards/max32650fthr/board.mk b/hw/bsp/max32650/boards/max32650fthr/board.mk deleted file mode 100644 index 0bc210e11..000000000 --- a/hw/bsp/max32650/boards/max32650fthr/board.mk +++ /dev/null @@ -1,2 +0,0 @@ -# Use the standard, non-secure linker file -LD_FILE = $(BOARD_PATH)/max32650.ld diff --git a/hw/bsp/max32650/boards/max32650fthr/max32650.ld b/hw/bsp/max32650/boards/max32650fthr/max32650.ld deleted file mode 100644 index 0e56a91ec..000000000 --- a/hw/bsp/max32650/boards/max32650fthr/max32650.ld +++ /dev/null @@ -1,119 +0,0 @@ -MEMORY { - ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */ - FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00300000 /* 3MB flash */ - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */ -} - -SECTIONS { - .text : - { - _text = .; - KEEP(*(.isr_vector)) - *(.text*) /* program code */ - *(.rodata*) /* read-only data: "const" */ - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* C++ Exception handling */ - KEEP(*(.eh_frame*)) - _etext = .; - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - /* it's used for C++ exception handling */ - /* we need to keep this to avoid overlapping */ - .ARM.exidx : - { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > FLASH - - .data : - { - _data = ALIGN(., 4); - *(vtable) - *(.data*) /*read-write initialized data: initialized global variable*/ - *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ - *(.flashprog*) /* Flash program */ - - - /* These array sections are used by __libc_init_array to call static C++ constructors */ - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - _edata = ALIGN(., 4); - } > SRAM AT>FLASH - __load_data = LOADADDR(.data); - .bss : - { - . = ALIGN(4); - _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ - *(COMMON) - _ebss = ALIGN(., 4); - } > SRAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > SRAM - - .heap (COPY): - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - *(.heap*) - __HeapLimit = ABSOLUTE(__StackLimit); - } > SRAM - - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") -} diff --git a/hw/bsp/max32650/family.c b/hw/bsp/max32650/family.c deleted file mode 100644 index bb382cdd4..000000000 --- a/hw/bsp/max32650/family.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() -#endif - -#include "gpio.h" -#include "mxc_sys.h" -#include "mxc_device.h" -#include "uart.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "board.h" -#include "bsp/board_api.h" - - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB_IRQHandler(void) { - tud_int_handler(0); -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ -mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM); - -void board_init(void) { -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif - mxc_gpio_cfg_t gpioConfig; - - // LED - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_OUT; - gpioConfig.mask = LED_PIN; - gpioConfig.pad = MXC_GPIO_PAD_NONE; - gpioConfig.port = LED_PORT; - gpioConfig.vssel = LED_VDDIO; - MXC_GPIO_Config(&gpioConfig); - board_led_write(false); - - // Button - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_IN; - gpioConfig.mask = BUTTON_PIN; - gpioConfig.pad = BUTTON_PULL; - gpioConfig.port = BUTTON_PORT; - gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO; - MXC_GPIO_Config(&gpioConfig); - - // UART - MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE); - - //USB - // Startup the HIRC96M clock if it's not on already - if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC96_EN)) { - MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN; - MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC96_RDY); - } - - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); - MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) { -#if LED_STATE_ON - state = !state; -#endif - if (state) { - MXC_GPIO_OutClr(LED_PORT, LED_PIN); - } else { - MXC_GPIO_OutSet(LED_PORT, LED_PIN); - } -} - -uint32_t board_button_read(void) { - uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; - return BUTTON_STATE_ACTIVE == state; -} - -size_t board_get_unique_id(uint8_t id[], size_t max_len) { - uint8_t hw_id[13];//USN Buffer - MXC_SYS_GetUSN(hw_id, 13); - - size_t act_len = TU_MIN(max_len, 13); - memcpy(id, hw_id, act_len); - return act_len; -} - -int board_uart_read(uint8_t *buf, int len) { - int uart_val; - int act_len = 0; - - while (act_len < len) { - if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { - break; - } else { - *buf++ = (uint8_t) uart_val; - act_len++; - } - } - return act_len; -} - -int board_uart_write(void const *buf, int len) { - int act_len = 0; - const uint8_t *ch_ptr = (const uint8_t *) buf; - while (act_len < len) { - MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); - act_len++; - } - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; - -void SysTick_Handler(void) { - system_ticks++; -} - -uint32_t board_millis(void) { - return system_ticks; -} -#endif - -void HardFault_Handler(void) { - __asm("BKPT #0\n"); -} - -// Required by __libc_init_array in startup code if we are compiling using -// -nostdlib/-nostartfiles. -void _init(void) { -} diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake deleted file mode 100644 index 48853b92c..000000000 --- a/hw/bsp/max32650/family.cmake +++ /dev/null @@ -1,169 +0,0 @@ -include_guard() - -set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) -set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) -set(CMSIS_5 ${TOP}/lib/CMSIS_5) - -# include board specific information and functions -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) - -# Get the linker file -set(LD_FILE_Clang ${LD_FILE_GNU}) - -# toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") -set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(JLINK_DEVICE max32650) -set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32650.cfg") - -set(FAMILY_MCUS MAX32650 CACHE INTERNAL "") - -function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - TARGET=MAX32650 - TARGET_REV=0x4131 - MXC_ASSERT_ENABLE - MAX32650 - IAR_PRAGMAS=0 - CFG_TUSB_MCU=OPT_MCU_MAX32650 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - ) - - # Run any board specific updates - update_board_extras(${TARGET}) -endfunction() - -#------------------------------------ -# BOARD_TARGET -#------------------------------------ -# only need to be built ONCE for all examples -function(add_board_target BOARD_TARGET) - if (TARGET ${BOARD_TARGET}) - return() - endif () - - # Startup & Linker script - set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S) - set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - - set(PERIPH_SRC ${MAX32_PERIPH}/Source) - add_library(${BOARD_TARGET} STATIC - ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/heap.c - ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/header_MAX32650.c - ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/system_max32650.c - ${PERIPH_SRC}/SYS/mxc_assert.c - ${PERIPH_SRC}/SYS/mxc_delay.c - ${PERIPH_SRC}/SYS/mxc_lock.c - ${PERIPH_SRC}/SYS/nvic_table.c - ${PERIPH_SRC}/SYS/pins_me10.c - ${PERIPH_SRC}/SYS/sys_me10.c - ${PERIPH_SRC}/TPU/tpu_me10.c - ${PERIPH_SRC}/TPU/tpu_reva.c - ${PERIPH_SRC}/FLC/flc_common.c - ${PERIPH_SRC}/FLC/flc_me10.c - ${PERIPH_SRC}/FLC/flc_reva.c - ${PERIPH_SRC}/GPIO/gpio_common.c - ${PERIPH_SRC}/GPIO/gpio_me10.c - ${PERIPH_SRC}/GPIO/gpio_reva.c - ${PERIPH_SRC}/ICC/icc_me10.c - ${PERIPH_SRC}/ICC/icc_reva.c - ${PERIPH_SRC}/ICC/icc_common.c - ${PERIPH_SRC}/UART/uart_common.c - ${PERIPH_SRC}/UART/uart_me10.c - ${PERIPH_SRC}/UART/uart_reva.c - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${MAX32_CMSIS}/Include - ${MAX32_CMSIS}/Device/Maxim/MAX32650/Include - ${MAX32_PERIPH}/Include/MAX32650 - ${PERIPH_SRC}/SYS - ${PERIPH_SRC}/GPIO - ${PERIPH_SRC}/TPU - ${PERIPH_SRC}/ICC - ${PERIPH_SRC}/FLC - ${PERIPH_SRC}/UART - ) - - target_compile_options(${BOARD_TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - update_board(${BOARD_TARGET}) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - -nostartfiles - --specs=nosys.specs --specs=nano.specs - -u sb_header #Needed when linking libraries to not lose the Signing header - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_Clang}" - ) - endif () -endfunction() - - -#------------------------------------ -# Functions -#------------------------------------ -function(family_configure_example TARGET RTOS) - family_configure_common(${TARGET} ${RTOS}) - - # Board target - add_board_target(board_${BOARD}) - - #---------- Port Specific ---------- - # These files are built for each example since it depends on example's tusb_config.h - target_sources(${TARGET} PUBLIC - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ) - target_include_directories(${TARGET} PUBLIC - # family, hw, board - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ) - - # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX32650 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/mentor/musb/dcd_musb.c - ) - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - target_compile_options(${TARGET}-tinyusb PRIVATE - -Wno-error=strict-prototypes - ) - - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) - - # Flashing - family_flash_jlink(${TARGET}) - family_flash_openocd_adi(${TARGET}) - - # Add the optional MSDK OpenOCD flashing - family_flash_msdk(${TARGET}) -endfunction() - -function(family_flash_msdk TARGET) - # Prepare the image (signed) if the board requires it - prepare_image(${TARGET}) - - set(MAXIM_PATH "$ENV{MAXIM_PATH}") - add_custom_target(${TARGET}-msdk - DEPENDS ${TARGET} - COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts - -f interface/cmsis-dap.cfg -f target/max32650.cfg - -c "program $<TARGET_FILE:${TARGET}> verify; init; reset; exit" - VERBATIM - ) -endfunction() diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk deleted file mode 100644 index d2fc293e4..000000000 --- a/hw/bsp/max32650/family.mk +++ /dev/null @@ -1,140 +0,0 @@ -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 - -# Important locations in the hw support for MCU -MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS -MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers - -# Add any board specific make rules -include $(TOP)/$(BOARD_PATH)/board.mk - -CPU_CORE ?= cortex-m4 -PORT ?= 0 - -# GCC -SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S - -# -------------- -# Compiler Flags -# -------------- -# Flags for the MAX32650/1/2 SDK -CFLAGS += -DTARGET=MAX32650 \ - -DTARGET_REV=0x4131 \ - -DMXC_ASSERT_ENABLE \ - -DMAX32650 \ - -DIAR_PRAGMAS=0 - -# Flags for TUSB features -CFLAGS += \ - -DCFG_TUSB_MCU=OPT_MCU_MAX32650 \ - -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - -# mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes \ - -Wno-error=unused-parameter \ - -Wno-error=cast-align \ - -Wno-error=cast-qual \ - -Wno-error=sign-compare - -LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs - -# Configure the flash rule. By default, use JLink. -SIGNED_BUILD ?= 0 -DEFAULT_FLASH = flash-jlink - -# If the applications needs to be signed (for the MAX32651), sign it first and -# then need to use MSDK's OpenOCD to flash it -# Also need to include the __SLA_FWK__ define to enable the signed header into -# memory -ifeq ($(SIGNED_BUILD), 1) -# Extra definitions to build for the secure part -CFLAGS += -D__SLA_FWK__ -DEFAULT_FLASH := sign-build flash-msdk -endif - -# For flash-jlink target -JLINK_DEVICE = max32650 - -# Configure the flash rule -flash: $(DEFAULT_FLASH) - -# ----------------- -# Sources & Include -# ----------------- -PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source -SRC_C += \ - src/portable/mentor/musb/dcd_musb.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/heap.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/system_max32650.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/header_MAX32650.c \ - $(PERIPH_SRC)/SYS/mxc_assert.c \ - $(PERIPH_SRC)/SYS/mxc_delay.c \ - $(PERIPH_SRC)/SYS/mxc_lock.c \ - $(PERIPH_SRC)/SYS/nvic_table.c \ - $(PERIPH_SRC)/SYS/pins_me10.c \ - $(PERIPH_SRC)/SYS/sys_me10.c \ - $(PERIPH_SRC)/FLC/flc_common.c \ - $(PERIPH_SRC)/FLC/flc_me10.c \ - $(PERIPH_SRC)/FLC/flc_reva.c \ - $(PERIPH_SRC)/GPIO/gpio_common.c \ - $(PERIPH_SRC)/GPIO/gpio_me10.c \ - $(PERIPH_SRC)/GPIO/gpio_reva.c \ - $(PERIPH_SRC)/ICC/icc_me10.c \ - $(PERIPH_SRC)/ICC/icc_reva.c \ - $(PERIPH_SRC)/ICC/icc_common.c \ - $(PERIPH_SRC)/TPU/tpu_me10.c \ - $(PERIPH_SRC)/TPU/tpu_reva.c \ - $(PERIPH_SRC)/UART/uart_common.c \ - $(PERIPH_SRC)/UART/uart_me10.c \ - $(PERIPH_SRC)/UART/uart_reva.c \ - -INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(MAX32_CMSIS)/Include \ - $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32650/Include \ - $(TOP)/$(MAX32_PERIPH)/Include/MAX32650 \ - $(PERIPH_SRC)/SYS \ - $(PERIPH_SRC)/GPIO \ - $(PERIPH_SRC)/ICC \ - $(PERIPH_SRC)/FLC \ - $(PERIPH_SRC)/TPU \ - $(PERIPH_SRC)/UART - - -# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the -# MAX32651 has a secure bootloader which requires the image to be signed before -# loading into flash. All MAX32651EVKIT's have the same key for evaluation -# purposes, so create a special flash rule to sign the binary and flash using -# the MSDK. -MCU_PATH = $(TOP)/hw/mcu/analog/max32/ -# Assume no extension for sign utility -SIGN_EXE = sign_app -ifeq ($(OS), Windows_NT) -# Must use .exe extension on Windows, since the binaries -# for Linux may live in the same place. -SIGN_EXE := sign_app.exe -else -UNAME = $(shell uname -s) -ifneq ($(findstring MSYS_NT,$(UNAME)),) -# Must also use .exe extension for MSYS2 -SIGN_EXE := sign_app.exe -endif -endif - -# Rule to sign the build. This will in-place modify the existing .elf file -# an populate the .sig section with the signature value -sign-build: $(BUILD)/$(PROJECT).elf - $(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin - $(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 \ - key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \ - ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin - $(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig - -# Optional flash option when running within an installed MSDK to use OpenOCD -# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. -# If the MSDK is installed, flash-msdk can be run to utilize the the modified -# openocd with the algorithms -MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: $(BUILD)/$(PROJECT).elf - $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ - -f interface/cmsis-dap.cfg -f target/max32650.cfg \ - -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" diff --git a/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h deleted file mode 100644 index e5a76af85..000000000 --- a/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.0 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. If you wish to use our Amazon - * FreeRTOS name, please do so in a fair use way that does not cause confusion. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -// skip if included from IAR assembler -#ifndef __IASMARM__ - #include "mxc_device.h" -#endif - -/* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) - -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#define configCPU_CLOCK_HZ SystemCoreClock -#define configTICK_RATE_HZ ( 1000 ) -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) -#define configMAX_TASK_NAME_LEN 16 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 4 -#define configUSE_QUEUE_SETS 0 -#define configUSE_TIME_SLICING 0 -#define configUSE_NEWLIB_REENTRANT 0 -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 - -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configSUPPORT_DYNAMIC_ALLOCATION 0 - -/* Hook function related definitions. */ -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configCHECK_HANDLER_INSTALLATION 0 - -/* Run time and task stats gathering related definitions. */ -#define configGENERATE_RUN_TIME_STATS 0 -#define configRECORD_STACK_HIGH_ADDRESS 1 -#define configUSE_TRACE_FACILITY 1 // legacy trace -#define configUSE_STATS_FORMATTING_FUNCTIONS 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES 2 - -/* Software timer related definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) -#define configTIMER_QUEUE_LENGTH 32 -#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE - -/* Optional functions - most linkers will remove unused functions anyway. */ -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY -#define INCLUDE_xResumeFromISR 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 0 -#define INCLUDE_xTaskGetIdleTaskHandle 0 -#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 -#define INCLUDE_pcTaskGetTaskName 0 -#define INCLUDE_eTaskGetState 0 -#define INCLUDE_xEventGroupSetBitFromISR 0 -#define INCLUDE_xTimerPendFunctionCall 0 - -/* FreeRTOS hooks to NVIC vectors */ -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler -#define vPortSVCHandler SVC_Handler - -//--------------------------------------------------------------------+ -// Interrupt nesting behavior configuration. -//--------------------------------------------------------------------+ - -// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header -#define configPRIO_BITS __NVIC_PRIO_BITS - -/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1) - -/* The highest interrupt priority that can be used by any interrupt service -routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL -INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER -PRIORITY THAN THIS! (higher priorities are lower numeric values. */ -#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 - -/* Interrupt priorities used by the kernel port layer itself. These are generic -to all Cortex-M ports, and do not rely on any particular library functions. */ -#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) - -/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! -See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ -#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) - -#endif diff --git a/hw/bsp/max32666/README.md b/hw/bsp/max32666/README.md deleted file mode 100644 index 902d82e25..000000000 --- a/hw/bsp/max32666/README.md +++ /dev/null @@ -1,32 +0,0 @@ -# Analog Devices MAX32665/6 - -This BSP is for working with the Analog Devices -[MAX32665](https://www.analog.com/en/products/max32665.html) and -[MAX32666](https://www.analog.com/en/products/max32666.html) microcontrollers. -The following boards are supported: - * [MAX32666EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html) - * [MAX32666FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html) - - -This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device -interfaces and hardware abstraction layers. This source code package is fetched -as part of the get-deps script. - -The microcontrollers utilize the standard GNU ARM toolchain. If this toolchain -is not already available on your build machine, it can be installed by using the -bundled MSDK installation. Details on downloading and installing can be found -in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/). - -## Flashing - -The default flashing behavior in this BSP is to utilize JLink. This can be done -by running the `flash` or `flash-jlink` rule for Makefiles, or the -`<target>-jlink` target for CMake. - -Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP -compatible debug probe. However, at the time of writing, the necessary flashing -algorithms for OpenOCD have not yet been incorporated into the OpenOCD master -branch. To utilize the provided debug probes, please install the bundled MSDK -package which includes the appropriate OpenOCD modifications. To leverage this -OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake -target. diff --git a/hw/bsp/max32666/boards/max32666evkit/board.cmake b/hw/bsp/max32666/boards/max32666evkit/board.cmake deleted file mode 100644 index 9dc6962eb..000000000 --- a/hw/bsp/max32666/boards/max32666evkit/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# Nothing to be done at the board level diff --git a/hw/bsp/max32666/boards/max32666evkit/board.mk b/hw/bsp/max32666/boards/max32666evkit/board.mk deleted file mode 100644 index a813a5327..000000000 --- a/hw/bsp/max32666/boards/max32666evkit/board.mk +++ /dev/null @@ -1 +0,0 @@ -# No specific build requirements for the board. diff --git a/hw/bsp/max32666/boards/max32666fthr/board.cmake b/hw/bsp/max32666/boards/max32666fthr/board.cmake deleted file mode 100644 index 9dc6962eb..000000000 --- a/hw/bsp/max32666/boards/max32666fthr/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# Nothing to be done at the board level diff --git a/hw/bsp/max32666/boards/max32666fthr/board.mk b/hw/bsp/max32666/boards/max32666fthr/board.mk deleted file mode 100644 index a813a5327..000000000 --- a/hw/bsp/max32666/boards/max32666fthr/board.mk +++ /dev/null @@ -1 +0,0 @@ -# No specific build requirements for the board. diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake deleted file mode 100644 index fb8c32295..000000000 --- a/hw/bsp/max32666/family.cmake +++ /dev/null @@ -1,147 +0,0 @@ -include_guard() - -set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) -set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) -set(CMSIS_5 ${TOP}/lib/CMSIS_5) - -# include board specific -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) - -# Get the linker file from current location (family) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32666.ld) -set(LD_FILE_Clang ${LD_FILE_GNU}) - -# toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") -set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(JLINK_DEVICE max32666) -set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32665.cfg") - -set(FAMILY_MCUS MAX32666 CACHE INTERNAL "") - -function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - TARGET=MAX32665 - TARGET_REV=0x4131 - MXC_ASSERT_ENABLE - MAX32665 - IAR_PRAGMAS=0 - CFG_TUSB_MCU=OPT_MCU_MAX32666 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - ) -endfunction() - -#------------------------------------ -# BOARD_TARGET -#------------------------------------ -# only need to be built ONCE for all examples -function(add_board_target BOARD_TARGET) - if (TARGET ${BOARD_TARGET}) - return() - endif () - - # Startup & Linker script - set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S) - set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - - set(PERIPH_SRC ${MAX32_PERIPH}/Source) - add_library(${BOARD_TARGET} STATIC - ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/heap.c - ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/system_max32665.c - ${PERIPH_SRC}/SYS/mxc_assert.c - ${PERIPH_SRC}/SYS/mxc_delay.c - ${PERIPH_SRC}/SYS/mxc_lock.c - ${PERIPH_SRC}/SYS/nvic_table.c - ${PERIPH_SRC}/SYS/pins_me14.c - ${PERIPH_SRC}/SYS/sys_me14.c - ${PERIPH_SRC}/TPU/tpu_me14.c - ${PERIPH_SRC}/TPU/tpu_reva.c - ${PERIPH_SRC}/FLC/flc_common.c - ${PERIPH_SRC}/FLC/flc_me14.c - ${PERIPH_SRC}/FLC/flc_reva.c - ${PERIPH_SRC}/GPIO/gpio_common.c - ${PERIPH_SRC}/GPIO/gpio_me14.c - ${PERIPH_SRC}/GPIO/gpio_reva.c - ${PERIPH_SRC}/ICC/icc_me14.c - ${PERIPH_SRC}/ICC/icc_reva.c - ${PERIPH_SRC}/UART/uart_common.c - ${PERIPH_SRC}/UART/uart_me14.c - ${PERIPH_SRC}/UART/uart_reva.c - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${MAX32_CMSIS}/Include - ${MAX32_CMSIS}/Device/Maxim/MAX32665/Include - ${MAX32_PERIPH}/Include/MAX32665 - ${PERIPH_SRC}/SYS - ${PERIPH_SRC}/GPIO - ${PERIPH_SRC}/TPU - ${PERIPH_SRC}/ICC - ${PERIPH_SRC}/FLC - ${PERIPH_SRC}/UART - ) - - target_compile_options(${BOARD_TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - update_board(${BOARD_TARGET}) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - -nostartfiles - --specs=nosys.specs --specs=nano.specs - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_Clang}" - ) - endif () -endfunction() - - -#------------------------------------ -# Functions -#------------------------------------ -function(family_configure_example TARGET RTOS) - family_configure_common(${TARGET} ${RTOS}) - - # Board target - add_board_target(board_${BOARD}) - - #---------- Port Specific ---------- - # These files are built for each example since it depends on example's tusb_config.h - target_sources(${TARGET} PUBLIC - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ) - target_include_directories(${TARGET} PUBLIC - # family, hw, board - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ) - - # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX32666 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/mentor/musb/dcd_musb.c - ) - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - target_compile_options(${TARGET}-tinyusb PRIVATE - -Wno-error=strict-prototypes - ) - - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) - - # Flashing - family_flash_jlink(${TARGET}) - family_flash_openocd_adi(${TARGET}) -endfunction() diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk deleted file mode 100644 index b4f7d1e57..000000000 --- a/hw/bsp/max32666/family.mk +++ /dev/null @@ -1,93 +0,0 @@ -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 - -# Important locations in the hw support for MCU -MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS -MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers - -# Add any board specific make rules -include $(TOP)/$(BOARD_PATH)/board.mk - -CPU_CORE ?= cortex-m4 -PORT ?= 0 - -# GCC -SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S -LD_FILE = $(FAMILY_PATH)/max32666.ld - -# -------------- -# Compiler Flags -# -------------- -# Flags for the MAX32665/6 SDK -CFLAGS += -DTARGET=MAX32665 \ - -DTARGET_REV=0x4131 \ - -DMXC_ASSERT_ENABLE \ - -DMAX32665 \ - -DIAR_PRAGMAS=0 - -# Flags for TUSB features -CFLAGS += \ - -DCFG_TUSB_MCU=OPT_MCU_MAX32666 \ - -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - -# mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes \ - -Wno-error=unused-parameter \ - -Wno-error=cast-align \ - -Wno-error=cast-qual -LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs - -# For flash-jlink target -JLINK_DEVICE = max32666 - -# flash target using Jlink by default -flash: flash-jlink - -# Optional flash option when running within an installed MSDK to use OpenOCD -# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. -# If the MSDK is installed, flash-msdk can be run to utilize the the modified -# openocd with the algorithms -MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: $(BUILD)/$(PROJECT).elf - $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ - -f interface/cmsis-dap.cfg -f target/max32665.cfg \ - -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" - -# ----------------- -# Sources & Include -# ----------------- -PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source -SRC_C += \ - src/portable/mentor/musb/dcd_musb.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/heap.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/system_max32665.c \ - $(PERIPH_SRC)/SYS/mxc_assert.c \ - $(PERIPH_SRC)/SYS/mxc_delay.c \ - $(PERIPH_SRC)/SYS/mxc_lock.c \ - $(PERIPH_SRC)/SYS/nvic_table.c \ - $(PERIPH_SRC)/SYS/pins_me14.c \ - $(PERIPH_SRC)/SYS/sys_me14.c \ - $(PERIPH_SRC)/FLC/flc_common.c \ - $(PERIPH_SRC)/FLC/flc_me14.c \ - $(PERIPH_SRC)/FLC/flc_reva.c \ - $(PERIPH_SRC)/GPIO/gpio_common.c \ - $(PERIPH_SRC)/GPIO/gpio_me14.c \ - $(PERIPH_SRC)/GPIO/gpio_reva.c \ - $(PERIPH_SRC)/ICC/icc_me14.c \ - $(PERIPH_SRC)/ICC/icc_reva.c \ - $(PERIPH_SRC)/TPU/tpu_me14.c \ - $(PERIPH_SRC)/TPU/tpu_reva.c \ - $(PERIPH_SRC)/UART/uart_common.c \ - $(PERIPH_SRC)/UART/uart_me14.c \ - $(PERIPH_SRC)/UART/uart_reva.c \ - -INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(MAX32_CMSIS)/Include \ - $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32665/Include \ - $(TOP)/$(MAX32_PERIPH)/Include/MAX32665 \ - $(PERIPH_SRC)/SYS \ - $(PERIPH_SRC)/GPIO \ - $(PERIPH_SRC)/ICC \ - $(PERIPH_SRC)/FLC \ - $(PERIPH_SRC)/TPU \ - $(PERIPH_SRC)/UART diff --git a/hw/bsp/max32690/README.md b/hw/bsp/max32690/README.md deleted file mode 100644 index 081ae0ad4..000000000 --- a/hw/bsp/max32690/README.md +++ /dev/null @@ -1,31 +0,0 @@ -# Analog Devices MAX32690 - -This BSP is for working with the Analog Devices -[MAX32690](https://www.analog.com/en/products/max32690.html) microcontroller. -The following boards are supported: - * [MAX32690EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html) - * [AD-APARD32690-SL](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html) - - -This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device -interfaces and hardware abstraction layers. This source code package is fetched -as part of the get-deps script. - -The microcontroller utilizes the standard GNU ARM toolchain. If this toolchain -is not already available on your build machine, it can be installed by using the -bundled MSDK installation. Details on downloading and installing can be found -in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/). - -## Flashing - -The default flashing behavior in this BSP is to utilize JLink. This can be done -by running the `flash` or `flash-jlink` rule for Makefiles, or the -`<target>-jlink` target for CMake. - -Both the Evaluation Kit and APARD boards are shipped with a CMSIS-DAP -compatible debug probe. However, at the time of writing, the necessary flashing -algorithms for OpenOCD have not yet been incorporated into the OpenOCD master -branch. To utilize the provided debug probes, please install the bundled MSDK -package which includes the appropriate OpenOCD modifications. To leverage this -OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake -target. diff --git a/hw/bsp/max32690/boards/apard32690/board.cmake b/hw/bsp/max32690/boards/apard32690/board.cmake deleted file mode 100644 index 9dc6962eb..000000000 --- a/hw/bsp/max32690/boards/apard32690/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# Nothing to be done at the board level diff --git a/hw/bsp/max32690/boards/apard32690/board.mk b/hw/bsp/max32690/boards/apard32690/board.mk deleted file mode 100644 index a813a5327..000000000 --- a/hw/bsp/max32690/boards/apard32690/board.mk +++ /dev/null @@ -1 +0,0 @@ -# No specific build requirements for the board. diff --git a/hw/bsp/max32690/boards/max32690evkit/board.cmake b/hw/bsp/max32690/boards/max32690evkit/board.cmake deleted file mode 100644 index 9dc6962eb..000000000 --- a/hw/bsp/max32690/boards/max32690evkit/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# Nothing to be done at the board level diff --git a/hw/bsp/max32690/boards/max32690evkit/board.mk b/hw/bsp/max32690/boards/max32690evkit/board.mk deleted file mode 100644 index a813a5327..000000000 --- a/hw/bsp/max32690/boards/max32690evkit/board.mk +++ /dev/null @@ -1 +0,0 @@ -# No specific build requirements for the board. diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c deleted file mode 100644 index 2418168d4..000000000 --- a/hw/bsp/max32690/family.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() -#endif - -#include "gpio.h" -#include "mxc_sys.h" -#include "mcr_regs.h" -#include "mxc_device.h" -#include "uart.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "board.h" -#include "bsp/board_api.h" - - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB_IRQHandler(void) { - tud_int_handler(0); -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ -mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM); - -void board_init(void) { -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif - mxc_gpio_cfg_t gpioConfig; - - // LED - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_OUT; - gpioConfig.mask = LED_PIN; - gpioConfig.pad = MXC_GPIO_PAD_NONE; - gpioConfig.port = LED_PORT; - gpioConfig.vssel = LED_VDDIO; - MXC_GPIO_Config(&gpioConfig); - board_led_write(false); - - // Button - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_IN; - gpioConfig.mask = BUTTON_PIN; - gpioConfig.pad = BUTTON_PULL; - gpioConfig.port = BUTTON_PORT; - gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO; - MXC_GPIO_Config(&gpioConfig); - - // UART - MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK); - - //USB - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO); - MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) { -#if LED_STATE_ON - state = !state; -#endif - if (state) { - MXC_GPIO_OutClr(LED_PORT, LED_PIN); - } else { - MXC_GPIO_OutSet(LED_PORT, LED_PIN); - } -} - -uint32_t board_button_read(void) { - uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; - return BUTTON_STATE_ACTIVE == state; -} - -size_t board_get_unique_id(uint8_t id[], size_t max_len) { - uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checksum buffer */ - MXC_SYS_GetUSN(hw_id, NULL); - - size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); - memcpy(id, hw_id, act_len); - return act_len; -} - -int board_uart_read(uint8_t *buf, int len) { - int uart_val; - int act_len = 0; - - while (act_len < len) { - if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { - break; - } else { - *buf++ = (uint8_t) uart_val; - act_len++; - } - } - return act_len; -} - -int board_uart_write(void const *buf, int len) { - int act_len = 0; - const uint8_t *ch_ptr = (const uint8_t *) buf; - while (act_len < len) { - MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); - act_len++; - } - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; - -void SysTick_Handler(void) { - system_ticks++; -} - -uint32_t board_millis(void) { - return system_ticks; -} -#endif - -void HardFault_Handler(void) { - __asm("BKPT #0\n"); -} - -// Required by __libc_init_array in startup code if we are compiling using -// -nostdlib/-nostartfiles. -void _init(void) { -} diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake deleted file mode 100644 index 96dcfedff..000000000 --- a/hw/bsp/max32690/family.cmake +++ /dev/null @@ -1,152 +0,0 @@ -include_guard() - -set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) -set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) -set(CMSIS_5 ${TOP}/lib/CMSIS_5) - -# include board specific -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) - -# Get the linker file from current location (family) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32690.ld) -set(LD_FILE_Clang ${LD_FILE_GNU}) - -# toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") -set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(JLINK_DEVICE max32690) -set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32690.cfg") - -set(FAMILY_MCUS MAX32690 CACHE INTERNAL "") - -function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - TARGET=MAX32690 - TARGET_REV=0x4131 - MXC_ASSERT_ENABLE - MAX32690 - FLASH_ORIGIN=0x10000000 - FLASH_SIZE=0x340000 - SRAM_ORIGIN=0x20000000 - SRAM_SIZE=0x100000 - IAR_PRAGMAS=0 - CFG_TUSB_MCU=OPT_MCU_MAX32690 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - ) -endfunction() - -#------------------------------------ -# BOARD_TARGET -#------------------------------------ -# only need to be built ONCE for all examples -function(add_board_target BOARD_TARGET) - if (TARGET ${BOARD_TARGET}) - return() - endif () - - # Startup & Linker script - set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S) - set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - - set(PERIPH_SRC ${MAX32_PERIPH}/Source) - add_library(${BOARD_TARGET} STATIC - ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/heap.c - ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/system_max32690.c - ${PERIPH_SRC}/SYS/mxc_assert.c - ${PERIPH_SRC}/SYS/mxc_delay.c - ${PERIPH_SRC}/SYS/mxc_lock.c - ${PERIPH_SRC}/SYS/nvic_table.c - ${PERIPH_SRC}/SYS/pins_me18.c - ${PERIPH_SRC}/SYS/sys_me18.c - ${PERIPH_SRC}/CTB/ctb_me18.c - ${PERIPH_SRC}/CTB/ctb_reva.c - ${PERIPH_SRC}/CTB/ctb_common.c - ${PERIPH_SRC}/FLC/flc_common.c - ${PERIPH_SRC}/FLC/flc_me18.c - ${PERIPH_SRC}/FLC/flc_reva.c - ${PERIPH_SRC}/GPIO/gpio_common.c - ${PERIPH_SRC}/GPIO/gpio_me18.c - ${PERIPH_SRC}/GPIO/gpio_reva.c - ${PERIPH_SRC}/ICC/icc_me18.c - ${PERIPH_SRC}/ICC/icc_reva.c - ${PERIPH_SRC}/UART/uart_common.c - ${PERIPH_SRC}/UART/uart_me18.c - ${PERIPH_SRC}/UART/uart_revb.c - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${MAX32_CMSIS}/Include - ${MAX32_CMSIS}/Device/Maxim/MAX32690/Include - ${MAX32_PERIPH}/Include/MAX32690 - ${PERIPH_SRC}/SYS - ${PERIPH_SRC}/GPIO - ${PERIPH_SRC}/CTB - ${PERIPH_SRC}/ICC - ${PERIPH_SRC}/FLC - ${PERIPH_SRC}/UART - ) - - target_compile_options(${BOARD_TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - update_board(${BOARD_TARGET}) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - -nostartfiles - --specs=nosys.specs --specs=nano.specs - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_Clang}" - ) - endif () -endfunction() - - -#------------------------------------ -# Functions -#------------------------------------ -function(family_configure_example TARGET RTOS) - family_configure_common(${TARGET} ${RTOS}) - - # Board target - add_board_target(board_${BOARD}) - - #---------- Port Specific ---------- - # These files are built for each example since it depends on example's tusb_config.h - target_sources(${TARGET} PUBLIC - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ) - target_include_directories(${TARGET} PUBLIC - # family, hw, board - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ) - - # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX32690 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/mentor/musb/dcd_musb.c - ) - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - target_compile_options(${TARGET}-tinyusb PRIVATE - -Wno-error=strict-prototypes - ) - - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) - - # Flashing - family_flash_jlink(${TARGET}) - family_flash_openocd_adi(${TARGET}) -endfunction() diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk deleted file mode 100644 index d4df8ef2f..000000000 --- a/hw/bsp/max32690/family.mk +++ /dev/null @@ -1,101 +0,0 @@ -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 - -# Important locations in the hw support for MCU -MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS -MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers - -# Add any board specific make rules -include $(TOP)/$(BOARD_PATH)/board.mk - -CPU_CORE ?= cortex-m4 -PORT ?= 0 - -# GCC -SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S -LD_FILE = $(FAMILY_PATH)/max32690.ld - -# -------------- -# Compiler Flags -# -------------- -# Flags for the MAX32690 SDK -CFLAGS += -DTARGET=MAX32690 \ - -DTARGET_REV=0x4131 \ - -DMXC_ASSERT_ENABLE \ - -DMAX32690 \ - -DFLASH_ORIGIN=0x10000000 \ - -DFLASH_SIZE=0x340000 \ - -DSRAM_ORIGIN=0x20000000 \ - -DSRAM_SIZE=0x100000 \ - -DIAR_PRAGMAS=0 - -# Flags for TUSB features -CFLAGS += \ - -DCFG_TUSB_MCU=OPT_MCU_MAX32690 \ - -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter \ - -Wno-error=strict-prototypes \ - -Wno-error=old-style-declaration \ - -Wno-error=sign-compare \ - -Wno-error=cast-qual \ - -Wno-lto-type-mismatch - -LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs - -# For flash-jlink target -JLINK_DEVICE = max32690 - -# flash target using Jlink by default -flash: flash-jlink - -# Optional flash option when running within an installed MSDK to use OpenOCD -# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. -# If the MSDK is installed, flash-msdk can be run to utilize the the modified -# openocd with the algorithms -MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: $(BUILD)/$(PROJECT).elf - $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ - -f interface/cmsis-dap.cfg -f target/max32690.cfg \ - -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" - -# ----------------- -# Sources & Include -# ----------------- -PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source -SRC_C += \ - src/portable/mentor/musb/dcd_musb.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/heap.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/system_max32690.c \ - $(PERIPH_SRC)/SYS/mxc_assert.c \ - $(PERIPH_SRC)/SYS/mxc_delay.c \ - $(PERIPH_SRC)/SYS/mxc_lock.c \ - $(PERIPH_SRC)/SYS/nvic_table.c \ - $(PERIPH_SRC)/SYS/pins_me18.c \ - $(PERIPH_SRC)/SYS/sys_me18.c \ - $(PERIPH_SRC)/CTB/ctb_me18.c \ - $(PERIPH_SRC)/CTB/ctb_reva.c \ - $(PERIPH_SRC)/CTB/ctb_common.c \ - $(PERIPH_SRC)/FLC/flc_common.c \ - $(PERIPH_SRC)/FLC/flc_me18.c \ - $(PERIPH_SRC)/FLC/flc_reva.c \ - $(PERIPH_SRC)/GPIO/gpio_common.c \ - $(PERIPH_SRC)/GPIO/gpio_me18.c \ - $(PERIPH_SRC)/GPIO/gpio_reva.c \ - $(PERIPH_SRC)/ICC/icc_me18.c \ - $(PERIPH_SRC)/ICC/icc_reva.c \ - $(PERIPH_SRC)/UART/uart_common.c \ - $(PERIPH_SRC)/UART/uart_me18.c \ - $(PERIPH_SRC)/UART/uart_revb.c \ - -INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(MAX32_CMSIS)/Include \ - $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32690/Include \ - $(TOP)/$(MAX32_PERIPH)/Include/MAX32690 \ - $(PERIPH_SRC)/SYS \ - $(PERIPH_SRC)/GPIO \ - $(PERIPH_SRC)/CTB \ - $(PERIPH_SRC)/ICC \ - $(PERIPH_SRC)/FLC \ - $(PERIPH_SRC)/UART diff --git a/hw/bsp/max78002/README.md b/hw/bsp/max78002/README.md deleted file mode 100644 index 4fb1bede4..000000000 --- a/hw/bsp/max78002/README.md +++ /dev/null @@ -1,28 +0,0 @@ -# Analog Devices MAX78002 - -This BSP is for working with the Analog Devices -[MAX78002](https://www.analog.com/en/products/max78002.html) AI microcontroller. -The following boards are supported: - * [MAX78002EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html) - -This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device -interfaces and hardware abstraction layers. This source code package is fetched -as part of the get-deps script. - -The microcontroller utilizes the standard GNU ARM toolchain. If this toolchain -is not already available on your build machine, it can be installed by using the -bundled MSDK installation. Details on downloading and installing can be found -in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/). - -## Flashing - -The default flashing behavior in this BSP is to utilize JLink. This can be done -by running the `flash` or `flash-jlink` rule for Makefiles, or the -`<target>-jlink` target for CMake. - -The Evaluation Kit is shipped with a CMSIS-DAP compatible debug probe. However, -at the time of writing, the necessary flashing algorithms for OpenOCD have not -yet been incorporated into the OpenOCD master branch. To utilize the provided -debug probes, please install the bundled MSDK package which includes the -appropriate OpenOCD modifications. To leverage this OpenOCD instance, run the -`flash-msdk` Makefile rule, or `<target>-msdk` CMake target. diff --git a/hw/bsp/max78002/boards/max78002evkit/board.cmake b/hw/bsp/max78002/boards/max78002evkit/board.cmake deleted file mode 100644 index 9dc6962eb..000000000 --- a/hw/bsp/max78002/boards/max78002evkit/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# Nothing to be done at the board level diff --git a/hw/bsp/max78002/boards/max78002evkit/board.mk b/hw/bsp/max78002/boards/max78002evkit/board.mk deleted file mode 100644 index a813a5327..000000000 --- a/hw/bsp/max78002/boards/max78002evkit/board.mk +++ /dev/null @@ -1 +0,0 @@ -# No specific build requirements for the board. diff --git a/hw/bsp/max78002/family.c b/hw/bsp/max78002/family.c deleted file mode 100644 index 8d51f141c..000000000 --- a/hw/bsp/max78002/family.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() -#endif - -#include "gpio.h" -#include "mxc_sys.h" -#include "mcr_regs.h" -#include "mxc_device.h" -#include "uart.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "board.h" -#include "bsp/board_api.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB_IRQHandler(void) { - tud_int_handler(0); -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ -mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM); - -void board_init(void) { -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif - mxc_gpio_cfg_t gpioConfig; - - // LED - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_OUT; - gpioConfig.mask = LED_PIN; - gpioConfig.pad = MXC_GPIO_PAD_NONE; - gpioConfig.port = LED_PORT; - gpioConfig.vssel = LED_VDDIO; - MXC_GPIO_Config(&gpioConfig); - board_led_write(false); - - // Button - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_IN; - gpioConfig.mask = BUTTON_PIN; - gpioConfig.pad = BUTTON_PULL; - gpioConfig.port = BUTTON_PORT; - gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO; - MXC_GPIO_Config(&gpioConfig); - - // UART - MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK); - UART_PORT->vssel |= UART_VDDIO_BITS; //Set necessary bits to 3.3V - - //USB - MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) { -#if LED_STATE_ON - state = !state; -#endif - if (state) { - MXC_GPIO_OutClr(LED_PORT, LED_PIN); - } else { - MXC_GPIO_OutSet(LED_PORT, LED_PIN); - } -} - -uint32_t board_button_read(void) { - uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; - return BUTTON_STATE_ACTIVE == state; -} - -size_t board_get_unique_id(uint8_t id[], size_t max_len) { - uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checksum buffer */ - MXC_SYS_GetUSN(hw_id, NULL); - - size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); - memcpy(id, hw_id, act_len); - return act_len; -} - -int board_uart_read(uint8_t *buf, int len) { - int uart_val; - int act_len = 0; - - while (act_len < len) { - if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { - break; - } else { - *buf++ = (uint8_t) uart_val; - act_len++; - } - } - return act_len; -} - -int board_uart_write(void const *buf, int len) { - int act_len = 0; - const uint8_t *ch_ptr = (const uint8_t *) buf; - while (act_len < len) { - MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); - act_len++; - } - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; - -void SysTick_Handler(void) { - system_ticks++; -} - -uint32_t board_millis(void) { - return system_ticks; -} -#endif - -void HardFault_Handler(void) { - __asm("BKPT #0\n"); -} - -// Required by __libc_init_array in startup code if we are compiling using -// -nostdlib/-nostartfiles. -void _init(void) { -} diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake deleted file mode 100644 index 446930bd8..000000000 --- a/hw/bsp/max78002/family.cmake +++ /dev/null @@ -1,166 +0,0 @@ -include_guard() - -set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) -set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) -set(CMSIS_5 ${TOP}/lib/CMSIS_5) - -# include board specific -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) - -# Get the linker file from current location (family) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max78002.ld) -set(LD_FILE_Clang ${LD_FILE_GNU}) - -# toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") -set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(JLINK_DEVICE max78000) - -set(FAMILY_MCUS MAX78002 CACHE INTERNAL "") - -function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - TARGET=MAX78002 - TARGET_REV=0x4131 - MXC_ASSERT_ENABLE - MAX78002 - IAR_PRAGMAS=0 - CFG_TUSB_MCU=OPT_MCU_MAX78002 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - ) -endfunction() - -#------------------------------------ -# BOARD_TARGET -#------------------------------------ -# only need to be built ONCE for all examples -function(add_board_target BOARD_TARGET) - if (TARGET ${BOARD_TARGET}) - return() - endif () - - # Startup & Linker script - set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S) - set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - - set(PERIPH_SRC ${MAX32_PERIPH}/Source) - add_library(${BOARD_TARGET} STATIC - ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/heap.c - ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/system_max78002.c - ${PERIPH_SRC}/SYS/mxc_assert.c - ${PERIPH_SRC}/SYS/mxc_delay.c - ${PERIPH_SRC}/SYS/mxc_lock.c - ${PERIPH_SRC}/SYS/nvic_table.c - ${PERIPH_SRC}/SYS/pins_ai87.c - ${PERIPH_SRC}/SYS/sys_ai87.c - ${PERIPH_SRC}/AES/aes_ai87.c - ${PERIPH_SRC}/AES/aes_revb.c - ${PERIPH_SRC}/FLC/flc_common.c - ${PERIPH_SRC}/FLC/flc_ai87.c - ${PERIPH_SRC}/FLC/flc_reva.c - ${PERIPH_SRC}/GPIO/gpio_common.c - ${PERIPH_SRC}/GPIO/gpio_ai87.c - ${PERIPH_SRC}/GPIO/gpio_reva.c - ${PERIPH_SRC}/ICC/icc_ai87.c - ${PERIPH_SRC}/ICC/icc_reva.c - ${PERIPH_SRC}/TRNG/trng_ai87.c - ${PERIPH_SRC}/TRNG/trng_revb.c - ${PERIPH_SRC}/UART/uart_common.c - ${PERIPH_SRC}/UART/uart_ai87.c - ${PERIPH_SRC}/UART/uart_revb.c - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${MAX32_CMSIS}/Include - ${MAX32_CMSIS}/Device/Maxim/MAX78002/Include - ${MAX32_PERIPH}/Include/MAX78002 - ${PERIPH_SRC}/SYS - ${PERIPH_SRC}/GPIO - ${PERIPH_SRC}/AES - ${PERIPH_SRC}/TRNG - ${PERIPH_SRC}/ICC - ${PERIPH_SRC}/FLC - ${PERIPH_SRC}/UART - ) - - target_compile_options(${BOARD_TARGET} PRIVATE - -Wno-error=strict-prototypes - -Wno-error=redundant-decls - ) - update_board(${BOARD_TARGET}) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - -nostartfiles - --specs=nosys.specs --specs=nano.specs - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_Clang}" - ) - endif () -endfunction() - - -#------------------------------------ -# Functions -#------------------------------------ -function(family_configure_example TARGET RTOS) - family_configure_common(${TARGET} ${RTOS}) - - # Board target - add_board_target(board_${BOARD}) - - #---------- Port Specific ---------- - # These files are built for each example since it depends on example's tusb_config.h - target_sources(${TARGET} PUBLIC - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ) - target_include_directories(${TARGET} PUBLIC - # family, hw, board - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ) - - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - -Wno-error=redundant-decls - ) - - - # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX78002 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/mentor/musb/dcd_musb.c - ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - target_compile_options(${TARGET}-tinyusb PRIVATE - -Wno-error=strict-prototypes - -Wno-error=redundant-decls - ) - - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) - - # Flashing - family_flash_jlink(${TARGET}) - family_flash_msdk(${TARGET}) -endfunction() - -# Add flash msdk target -function(family_flash_msdk TARGET) - set(MAXIM_PATH "$ENV{MAXIM_PATH}") - - add_custom_target(${TARGET}-msdk - DEPENDS ${TARGET} - COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts - -f interface/cmsis-dap.cfg -f target/max78002.cfg - -c "program $<TARGET_FILE:${TARGET}> verify; init; reset; exit" - VERBATIM - ) -endfunction() diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk deleted file mode 100644 index 997816261..000000000 --- a/hw/bsp/max78002/family.mk +++ /dev/null @@ -1,99 +0,0 @@ -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 - -# Important locations in the hw support for MCU -MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS -MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers - -# Add any board specific make rules -include $(TOP)/$(BOARD_PATH)/board.mk - -CPU_CORE ?= cortex-m4 -PORT ?= 0 - -# GCC -SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S -LD_FILE = $(FAMILY_PATH)/max78002.ld - -# -------------- -# Compiler Flags -# -------------- -# Flags for the MAX78002 SDK -CFLAGS += -DTARGET=MAX78002 \ - -DTARGET_REV=0x4131 \ - -DMXC_ASSERT_ENABLE \ - -DMAX78002 \ - -DIAR_PRAGMAS=0 - -# Flags for TUSB features -CFLAGS += \ - -DCFG_TUSB_MCU=OPT_MCU_MAX78002 \ - -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - -# mcu driver cause following warnings -CFLAGS += -Wno-error=redundant-decls \ - -Wno-error=strict-prototypes \ - -Wno-error=unused-parameter \ - -Wno-error=enum-conversion \ - -Wno-error=sign-compare \ - -Wno-error=cast-qual - -LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs - -# For flash-jlink target -JLINK_DEVICE = max78000 - -# flash target using Jlink by default -flash: flash-jlink - -# Optional flash option when running within an installed MSDK to use OpenOCD -# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. -# If the MSDK is installed, flash-msdk can be run to utilize the the modified -# openocd with the algorithms -MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: $(BUILD)/$(PROJECT).elf - $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ - -f interface/cmsis-dap.cfg -f target/max78002.cfg \ - -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" - -# ----------------- -# Sources & Include -# ----------------- -PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source -SRC_C += \ - src/portable/mentor/musb/dcd_musb.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/heap.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/system_max78002.c \ - $(PERIPH_SRC)/SYS/mxc_assert.c \ - $(PERIPH_SRC)/SYS/mxc_delay.c \ - $(PERIPH_SRC)/SYS/mxc_lock.c \ - $(PERIPH_SRC)/SYS/nvic_table.c \ - $(PERIPH_SRC)/SYS/pins_ai87.c \ - $(PERIPH_SRC)/SYS/sys_ai87.c \ - $(PERIPH_SRC)/AES/aes_ai87.c \ - $(PERIPH_SRC)/AES/aes_revb.c \ - $(PERIPH_SRC)/FLC/flc_common.c \ - $(PERIPH_SRC)/FLC/flc_ai87.c \ - $(PERIPH_SRC)/FLC/flc_reva.c \ - $(PERIPH_SRC)/GPIO/gpio_common.c \ - $(PERIPH_SRC)/GPIO/gpio_ai87.c \ - $(PERIPH_SRC)/GPIO/gpio_reva.c \ - $(PERIPH_SRC)/ICC/icc_ai87.c \ - $(PERIPH_SRC)/ICC/icc_reva.c \ - $(PERIPH_SRC)/TRNG/trng_ai87.c \ - $(PERIPH_SRC)/TRNG/trng_revb.c \ - $(PERIPH_SRC)/UART/uart_common.c \ - $(PERIPH_SRC)/UART/uart_ai87.c \ - $(PERIPH_SRC)/UART/uart_revb.c \ - -INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(MAX32_CMSIS)/Include \ - $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX78002/Include \ - $(TOP)/$(MAX32_PERIPH)/Include/MAX78002 \ - $(PERIPH_SRC)/SYS \ - $(PERIPH_SRC)/GPIO \ - $(PERIPH_SRC)/AES \ - $(PERIPH_SRC)/ICC \ - $(PERIPH_SRC)/FLC \ - $(PERIPH_SRC)/TRNG \ - $(PERIPH_SRC)/UART diff --git a/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/maxim/FreeRTOSConfig/FreeRTOSConfig.h index e5a76af85..e5a76af85 100644 --- a/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/maxim/FreeRTOSConfig/FreeRTOSConfig.h diff --git a/hw/bsp/maxim/README.md b/hw/bsp/maxim/README.md new file mode 100644 index 000000000..e2983e899 --- /dev/null +++ b/hw/bsp/maxim/README.md @@ -0,0 +1,43 @@ +# Analog Devices MAXIM + +This BSP is for working with the Analog microcontrollers + - [MAX32650](https://www.analog.com/en/products/max32650.html), + - [MAX32651](https://www.analog.com/en/products/max32651.html) + - [MAX32652](https://www.analog.com/en/products/max32652.html) + - [MAX32665](https://www.analog.com/en/products/max32665.html) + - [MAX32666](https://www.analog.com/en/products/max32666.html) + - [MAX32690](https://www.analog.com/en/products/max32690.html) + - [MAX78002](https://www.analog.com/en/products/max78002.html) AI microcontroller. + +The following boards are supported: + * [MAX32650EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html) + * [MAX32650FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html) + * [MAX32651EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html) (Secure Bootloader) + * [MAX32666EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html) + * [MAX32666FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html) + * [MAX32690EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html) + * [AD-APARD32690-SL](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html) + * [MAX78002EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html) + +This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device +interfaces and hardware abstraction layers. This source code package is fetched +as part of the get-deps script. + +The microcontroller utilizes the standard GNU ARM toolchain. If this toolchain +is not already available on your build machine, it can be installed by using the +bundled MSDK installation. Details on downloading and installing can be found +in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/). + +## Flashing + +The default flashing behavior in this BSP is to utilize JLink. This can be done +by running the `flash` or `flash-jlink` rule for Makefiles, or the +`<target>-jlink` target for CMake. + +Most the Evaluation Kit and boards are shipped with a CMSIS-DAP +compatible debug probe. However, at the time of writing, the necessary flashing +algorithms for OpenOCD have not yet been incorporated into the OpenOCD master +branch. To utilize the provided debug probes, please install the bundled MSDK +package which includes the appropriate OpenOCD modifications. To leverage this +OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-openocd` CMake +target. diff --git a/hw/bsp/maxim/boards/apard32690/board.cmake b/hw/bsp/maxim/boards/apard32690/board.cmake new file mode 100644 index 000000000..a03d05f8d --- /dev/null +++ b/hw/bsp/maxim/boards/apard32690/board.cmake @@ -0,0 +1,4 @@ +set(MAX_DEVICE max32690) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/max32690/boards/apard32690/board.h b/hw/bsp/maxim/boards/apard32690/board.h index f94097ca9..19f74bf56 100644 --- a/hw/bsp/max32690/boards/apard32690/board.h +++ b/hw/bsp/maxim/boards/apard32690/board.h @@ -24,11 +24,15 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: APARD32690-SL + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ -#include "gpio.h" -#include "mxc_sys.h" +#include "max32690.h" #ifdef __cplusplus extern "C" { diff --git a/hw/bsp/maxim/boards/apard32690/board.mk b/hw/bsp/maxim/boards/apard32690/board.mk new file mode 100644 index 000000000..d8a0c9cae --- /dev/null +++ b/hw/bsp/maxim/boards/apard32690/board.mk @@ -0,0 +1 @@ +MAX_DEVICE = max32690 diff --git a/hw/bsp/maxim/boards/max32650evkit/board.cmake b/hw/bsp/maxim/boards/max32650evkit/board.cmake new file mode 100644 index 000000000..59721e756 --- /dev/null +++ b/hw/bsp/maxim/boards/max32650evkit/board.cmake @@ -0,0 +1,8 @@ +set(MAX_DEVICE max32650) + +function(update_board TARGET) +endfunction() + +function(prepare_image TARGET_IN) + #No signing required +endfunction() diff --git a/hw/bsp/max32650/boards/max32650evkit/board.h b/hw/bsp/maxim/boards/max32650evkit/board.h index 196abdaca..0dfc074fa 100644 --- a/hw/bsp/max32650/boards/max32650evkit/board.h +++ b/hw/bsp/maxim/boards/max32650evkit/board.h @@ -24,11 +24,15 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32650 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ -#include "gpio.h" -#include "mxc_sys.h" +#include "max32650.h" #ifdef __cplusplus extern "C" { diff --git a/hw/bsp/maxim/boards/max32650evkit/board.mk b/hw/bsp/maxim/boards/max32650evkit/board.mk new file mode 100644 index 000000000..3a4108005 --- /dev/null +++ b/hw/bsp/maxim/boards/max32650evkit/board.mk @@ -0,0 +1 @@ +MAX_DEVICE = max32650 diff --git a/hw/bsp/maxim/boards/max32650fthr/board.cmake b/hw/bsp/maxim/boards/max32650fthr/board.cmake new file mode 100644 index 000000000..59721e756 --- /dev/null +++ b/hw/bsp/maxim/boards/max32650fthr/board.cmake @@ -0,0 +1,8 @@ +set(MAX_DEVICE max32650) + +function(update_board TARGET) +endfunction() + +function(prepare_image TARGET_IN) + #No signing required +endfunction() diff --git a/hw/bsp/max32650/boards/max32650fthr/board.h b/hw/bsp/maxim/boards/max32650fthr/board.h index d80a8fcae..af0fa1c39 100644 --- a/hw/bsp/max32650/boards/max32650fthr/board.h +++ b/hw/bsp/maxim/boards/max32650fthr/board.h @@ -24,11 +24,15 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32650 Feather + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ -#include "gpio.h" -#include "mxc_sys.h" +#include "max32650.h" #ifdef __cplusplus extern "C" { diff --git a/hw/bsp/maxim/boards/max32650fthr/board.mk b/hw/bsp/maxim/boards/max32650fthr/board.mk new file mode 100644 index 000000000..3a4108005 --- /dev/null +++ b/hw/bsp/maxim/boards/max32650fthr/board.mk @@ -0,0 +1 @@ +MAX_DEVICE = max32650 diff --git a/hw/bsp/max32650/boards/max32651evkit/board.cmake b/hw/bsp/maxim/boards/max32651evkit/board.cmake index bd8077a42..773989126 100644 --- a/hw/bsp/max32650/boards/max32651evkit/board.cmake +++ b/hw/bsp/maxim/boards/max32651evkit/board.cmake @@ -1,22 +1,23 @@ +set(MAX_DEVICE max32650) + # Use the secure linker file -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32651.ld) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/max32651.ld) -function(update_board_extras TARGET) +function(update_board TARGET) # for the signed target, need to add the __SLA_FWK__ define target_compile_definitions(${TARGET} PUBLIC __SLA_FWK__ ) endfunction() -function(prepare_image TARGET_IN) - #For the signed target, set up a POST_BUILD command to sign the elf file once - #created +function(sign_image TARGET_IN) + #For the signed target, set up a POST_BUILD command to sign the elf file once created if((WIN32) OR (MINGW) OR (MSYS)) set(SIGN_EXE "sign_app.exe") else() set(SIGN_EXE "sign_app") endif() - set(MCU_PATH "${TOP}/hw/mcu/analog/max32/") + set(MCU_PATH "${TOP}/hw/mcu/analog/msdk/") # Custom POST_BUILD command add_custom_command( diff --git a/hw/bsp/max32650/boards/max32651evkit/board.h b/hw/bsp/maxim/boards/max32651evkit/board.h index 196abdaca..dbf2a4b7c 100644 --- a/hw/bsp/max32650/boards/max32651evkit/board.h +++ b/hw/bsp/maxim/boards/max32651evkit/board.h @@ -24,11 +24,15 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32651 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ -#include "gpio.h" -#include "mxc_sys.h" +#include "max32650.h" #ifdef __cplusplus extern "C" { diff --git a/hw/bsp/max32650/boards/max32651evkit/board.mk b/hw/bsp/maxim/boards/max32651evkit/board.mk index b609598c1..5d4971148 100644 --- a/hw/bsp/max32650/boards/max32651evkit/board.mk +++ b/hw/bsp/maxim/boards/max32651evkit/board.mk @@ -1,5 +1,7 @@ +MAX_DEVICE = max32650 + # Use the secure linker file -LD_FILE = $(BOARD_PATH)/max32651.ld +LD_FILE = $(FAMILY_PATH)/linker/max32651.ld # Let the family script know the build needs to be signed SIGNED_BUILD := 1 diff --git a/hw/bsp/maxim/boards/max32666evkit/board.cmake b/hw/bsp/maxim/boards/max32666evkit/board.cmake new file mode 100644 index 000000000..e7116b603 --- /dev/null +++ b/hw/bsp/maxim/boards/max32666evkit/board.cmake @@ -0,0 +1,4 @@ +set(MAX_DEVICE max32665) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/max32666/boards/max32666evkit/board.h b/hw/bsp/maxim/boards/max32666evkit/board.h index 0ab1483b8..42965d3c5 100644 --- a/hw/bsp/max32666/boards/max32666evkit/board.h +++ b/hw/bsp/maxim/boards/max32666evkit/board.h @@ -24,11 +24,15 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32666 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ -#include "gpio.h" -#include "mxc_sys.h" +#include "max32665.h" #ifdef __cplusplus extern "C" { diff --git a/hw/bsp/maxim/boards/max32666evkit/board.mk b/hw/bsp/maxim/boards/max32666evkit/board.mk new file mode 100644 index 000000000..a1cf3045d --- /dev/null +++ b/hw/bsp/maxim/boards/max32666evkit/board.mk @@ -0,0 +1 @@ +MAX_DEVICE = max32665 diff --git a/hw/bsp/maxim/boards/max32666fthr/board.cmake b/hw/bsp/maxim/boards/max32666fthr/board.cmake new file mode 100644 index 000000000..e7116b603 --- /dev/null +++ b/hw/bsp/maxim/boards/max32666fthr/board.cmake @@ -0,0 +1,4 @@ +set(MAX_DEVICE max32665) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/max32666/boards/max32666fthr/board.h b/hw/bsp/maxim/boards/max32666fthr/board.h index c719b748a..fbb217949 100644 --- a/hw/bsp/max32666/boards/max32666fthr/board.h +++ b/hw/bsp/maxim/boards/max32666fthr/board.h @@ -24,11 +24,15 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32666 Feather + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ -#include "gpio.h" -#include "mxc_sys.h" +#include "max32665.h" #ifdef __cplusplus extern "C" { diff --git a/hw/bsp/maxim/boards/max32666fthr/board.mk b/hw/bsp/maxim/boards/max32666fthr/board.mk new file mode 100644 index 000000000..a1cf3045d --- /dev/null +++ b/hw/bsp/maxim/boards/max32666fthr/board.mk @@ -0,0 +1 @@ +MAX_DEVICE = max32665 diff --git a/hw/bsp/maxim/boards/max32690evkit/board.cmake b/hw/bsp/maxim/boards/max32690evkit/board.cmake new file mode 100644 index 000000000..a03d05f8d --- /dev/null +++ b/hw/bsp/maxim/boards/max32690evkit/board.cmake @@ -0,0 +1,4 @@ +set(MAX_DEVICE max32690) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/max32690/boards/max32690evkit/board.h b/hw/bsp/maxim/boards/max32690evkit/board.h index 05d60f220..41c73621f 100644 --- a/hw/bsp/max32690/boards/max32690evkit/board.h +++ b/hw/bsp/maxim/boards/max32690evkit/board.h @@ -24,16 +24,20 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32690 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ -#include "gpio.h" -#include "mxc_sys.h" - #ifdef __cplusplus extern "C" { #endif +#include "max32690.h" + // LED #define LED_PORT MXC_GPIO0 #define LED_PIN MXC_GPIO_PIN_14 diff --git a/hw/bsp/maxim/boards/max32690evkit/board.mk b/hw/bsp/maxim/boards/max32690evkit/board.mk new file mode 100644 index 000000000..d8a0c9cae --- /dev/null +++ b/hw/bsp/maxim/boards/max32690evkit/board.mk @@ -0,0 +1 @@ +MAX_DEVICE = max32690 diff --git a/hw/bsp/maxim/boards/max78002evkit/board.cmake b/hw/bsp/maxim/boards/max78002evkit/board.cmake new file mode 100644 index 000000000..dd4c3c215 --- /dev/null +++ b/hw/bsp/maxim/boards/max78002evkit/board.cmake @@ -0,0 +1,4 @@ +set(MAX_DEVICE max78002) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/max78002/boards/max78002evkit/board.h b/hw/bsp/maxim/boards/max78002evkit/board.h index f8102c394..8c1fc13d4 100644 --- a/hw/bsp/max78002/boards/max78002evkit/board.h +++ b/hw/bsp/maxim/boards/max78002evkit/board.h @@ -24,11 +24,15 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX78002 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ -#include "gpio.h" -#include "mxc_sys.h" +#include "max78002.h" #ifdef __cplusplus extern "C" { diff --git a/hw/bsp/maxim/boards/max78002evkit/board.mk b/hw/bsp/maxim/boards/max78002evkit/board.mk new file mode 100644 index 000000000..b19e95187 --- /dev/null +++ b/hw/bsp/maxim/boards/max78002evkit/board.mk @@ -0,0 +1 @@ +MAX_DEVICE = max78002 diff --git a/hw/bsp/max32666/family.c b/hw/bsp/maxim/family.c index f96393fe1..0ef6b8c4d 100644 --- a/hw/bsp/max32666/family.c +++ b/hw/bsp/maxim/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Analog Devices +*/ + #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() @@ -31,7 +35,9 @@ #include "gpio.h" #include "mxc_sys.h" +#if __has_include("mcr_regs.h") #include "mcr_regs.h" +#endif #include "mxc_device.h" #include "uart.h" @@ -84,16 +90,45 @@ void board_init(void) { MXC_GPIO_Config(&gpioConfig); // UART +#if MAX_PERIPH_ID == 14 MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, UART_MAP); +#elif MAX_PERIPH_ID == 18 || MAX_PERIPH_ID == 87 + MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK); + #if MAX_PERIPH_ID == 87 + UART_PORT->vssel |= UART_VDDIO_BITS; // Set necessary bits to 3.3V + #endif +#endif //USB +#if defined(MAX32650) // Startup the HIRC96M clock if it's not on already - if (!(MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC96M_EN)) { - MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC96M_EN; + if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC96_EN)) { + MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN; + MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC96_RDY); } + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); + MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB); +#elif defined(MAX32665) || defined(MAX32666) + // Startup the HIRC96M clock if it's not on already + if (!(MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC96M_EN)) { + MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC96M_EN; + } MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB); + +#elif defined(MAX32690) + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO); + MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB); + +# elif defined(MAX78002) + MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); +#else + #error "Unsupported MAXIM MCU for board_dfu_init" +#endif } //--------------------------------------------------------------------+ @@ -117,13 +152,18 @@ uint32_t board_button_read(void) { } size_t board_get_unique_id(uint8_t id[], size_t max_len) { - uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checksum buffer */ - MXC_SYS_GetUSN(hw_id, NULL); +#if defined(MAX32650) + // USN is 13 bytes on this device + MXC_SYS_GetUSN(id, 13); + return 13; +#else + uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN]; //USN Buffer + MXC_SYS_GetUSN(hw_id, NULL); // 2nd parameter is optional checksum buffer size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); memcpy(id, hw_id, act_len); return act_len; +#endif } int board_uart_read(uint8_t *buf, int len) { diff --git a/hw/bsp/maxim/family.cmake b/hw/bsp/maxim/family.cmake new file mode 100644 index 000000000..75daec753 --- /dev/null +++ b/hw/bsp/maxim/family.cmake @@ -0,0 +1,196 @@ +include_guard() + +# stub: overridden by board.cmake if needed +function(sign_image TARGET_IN) +endfunction() + +set(MSDK_LIB ${TOP}/hw/mcu/analog/msdk/Libraries) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +string(TOUPPER ${MAX_DEVICE} MAX_DEVICE_UPPER) +cmake_print_variables(MAX_DEVICE MAX_DEVICE_UPPER) + +set(JLINK_DEVICE ${MAX_DEVICE}) +set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/${MAX_DEVICE}.cfg") + +set(FAMILY_MCUS ${MAX_DEVICE_UPPER} CACHE INTERNAL "") + +if (${MAX_DEVICE} STREQUAL "max32650") + set(PERIPH_ID 10) + set(PERIPH_SUFFIX "me") +elseif (${MAX_DEVICE} STREQUAL "max32665" OR ${MAX_DEVICE} STREQUAL "max32666") + set(PERIPH_ID 14) + set(PERIPH_SUFFIX "me") +elseif (${MAX_DEVICE} STREQUAL "max32690") + set(PERIPH_ID 18) + set(PERIPH_SUFFIX "me") +elseif (${MAX_DEVICE} STREQUAL "max78002") + set(PERIPH_ID 87) + set(PERIPH_SUFFIX "ai") +else() + message(FATAL_ERROR "Unsupported MAX device: ${MAX_DEVICE}") +endif() + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/GCC/startup_${MAX_DEVICE}.S) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + + if (NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MAX_DEVICE}.ld) + endif () + set(LD_FILE_Clang ${LD_FILE_GNU}) + + # Common + add_library(${BOARD_TARGET} STATIC + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/heap.c + ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/system_${MAX_DEVICE}.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_assert.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_delay.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_lock.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/nvic_table.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/pins_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/sys_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_common.c + ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_reva.c + ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_common.c + ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_reva.c + ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_reva.c + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_common.c + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_${PERIPH_SUFFIX}${PERIPH_ID}.c + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${MSDK_LIB}/CMSIS/5.9.0/Core/Include + ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Include + ${MSDK_LIB}/PeriphDrivers/Include/${MAX_DEVICE_UPPER} + ${MSDK_LIB}/PeriphDrivers/Source/SYS + ${MSDK_LIB}/PeriphDrivers/Source/GPIO + ${MSDK_LIB}/PeriphDrivers/Source/ICC + ${MSDK_LIB}/PeriphDrivers/Source/FLC + ${MSDK_LIB}/PeriphDrivers/Source/UART + ) + + # device specific + if (${MAX_DEVICE} STREQUAL "max32650" OR + ${MAX_DEVICE} STREQUAL "max32665" OR ${MAX_DEVICE} STREQUAL "max32666") + target_sources(${BOARD_TARGET} PRIVATE + ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_common.c + ${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_reva.c + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_reva.c + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${MSDK_LIB}/PeriphDrivers/Source/TPU + ) + elseif (${MAX_DEVICE} STREQUAL "max32690") + target_sources(${BOARD_TARGET} PRIVATE + ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_reva.c + ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_common.c + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${MSDK_LIB}/PeriphDrivers/Source/CTB + ) + elseif (${MAX_DEVICE} STREQUAL "max78002") + target_sources(${BOARD_TARGET} PRIVATE + ${MSDK_LIB}/PeriphDrivers/Source/AES/aes_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/AES/aes_revb.c + ${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_revb.c + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${MSDK_LIB}/PeriphDrivers/Source/AES + ${MSDK_LIB}/PeriphDrivers/Source/TRNG + ) + else() + message(FATAL_ERROR "Unsupported MAX device: ${MAX_DEVICE}") + endif() + + target_compile_definitions(${BOARD_TARGET} PUBLIC + TARGET=${MAX_DEVICE_UPPER} + TARGET_REV=0x4131 + MXC_ASSERT_ENABLE + ${MAX_DEVICE_UPPER} + IAR_PRAGMAS=0 + MAX_PERIPH_ID=${PERIPH_ID} + BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + ) + target_compile_options(${BOARD_TARGET} PRIVATE + -Wno-error=strict-prototypes + ) + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_${MAX_DEVICE_UPPER}) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/mentor/musb/dcd_musb.c + ) + target_compile_options(${TARGET} PRIVATE + -Wno-error=strict-prototypes + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) + + sign_image(${TARGET}) # for secured device such as max32651 + family_flash_openocd_adi(${TARGET}) +endfunction() diff --git a/hw/bsp/maxim/family.mk b/hw/bsp/maxim/family.mk new file mode 100644 index 000000000..3ddf8cf39 --- /dev/null +++ b/hw/bsp/maxim/family.mk @@ -0,0 +1,190 @@ +MSDK_LIB = hw/mcu/analog/msdk/Libraries + +# Add any board specific make rules +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 +PORT ?= 0 +JLINK_DEVICE = ${MAX_DEVICE} +MAX_DEVICE_UPPER = $(call to_upper,${MAX_DEVICE}) + +ifeq ($(MAX_DEVICE),max32650) + PERIPH_ID = 10 + PERIPH_SUFFIX = me +endif + +ifneq ($(filter $(MAX_DEVICE),max32665 max32666),) + PERIPH_ID = 14 + PERIPH_SUFFIX = me +endif + +ifeq ($(MAX_DEVICE),max32690) + PERIPH_ID = 18 + PERIPH_SUFFIX = me +endif + +ifeq ($(MAX_DEVICE),max78002) + PERIPH_ID = 87 + PERIPH_SUFFIX = ai +endif + +ifndef PERIPH_ID + $(error Unsupported MAX device: ${MAX_DEVICE}) +endif + +# Configure the flash rule. By default, use JLink. +SIGNED_BUILD ?= 0 +DEFAULT_FLASH = flash-jlink + +# -------------- +# Compiler Flags +# -------------- +CFLAGS += \ + -DTARGET=${MAX_DEVICE_UPPER}\ + -DTARGET_REV=0x4131 \ + -DMXC_ASSERT_ENABLE \ + -D${MAX_DEVICE_UPPER} \ + -DIAR_PRAGMAS=0 \ + -DMAX_PERIPH_ID=${PERIPH_ID} \ + -DCFG_TUSB_MCU=OPT_MCU_${MAX_DEVICE_UPPER} \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + +# mcu driver cause following warnings +CFLAGS += \ + -Wno-error=old-style-declaration \ + -Wno-error=redundant-decls \ + -Wno-error=strict-prototypes \ + -Wno-error=unused-parameter \ + -Wno-error=cast-align \ + -Wno-error=cast-qual \ + -Wno-error=sign-compare \ + -Wno-error=enum-conversion \ + +LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs +LD_FILE_GCC ?= $(FAMILY_PATH)/linker/${MAX_DEVICE}.ld + +# If the applications needs to be signed (for the MAX32651), sign it first and +# then need to use MSDK's OpenOCD to flash it +# Also need to include the __SLA_FWK__ define to enable the signed header into +# memory +ifeq ($(SIGNED_BUILD), 1) +# Extra definitions to build for the secure part +CFLAGS += -D__SLA_FWK__ +DEFAULT_FLASH := sign-build flash-msdk +endif + +# ----------------- +# Sources & Include +# ----------------- + +# common +SRC_C += \ + src/portable/mentor/musb/dcd_musb.c \ + ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/heap.c \ + ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/system_${MAX_DEVICE}.c \ + ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_assert.c \ + ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_delay.c \ + ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_lock.c \ + ${MSDK_LIB}/PeriphDrivers/Source/SYS/nvic_table.c \ + ${MSDK_LIB}/PeriphDrivers/Source/SYS/pins_${PERIPH_SUFFIX}${PERIPH_ID}.c \ + ${MSDK_LIB}/PeriphDrivers/Source/SYS/sys_${PERIPH_SUFFIX}${PERIPH_ID}.c \ + ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_common.c \ + ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_${PERIPH_SUFFIX}${PERIPH_ID}.c \ + ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_reva.c \ + ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_common.c \ + ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_${PERIPH_SUFFIX}${PERIPH_ID}.c \ + ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_reva.c \ + ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_${PERIPH_SUFFIX}${PERIPH_ID}.c \ + ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_reva.c \ + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_common.c \ + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_${PERIPH_SUFFIX}${PERIPH_ID}.c \ + +SRC_S_GCC += ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/GCC/startup_${MAX_DEVICE}.S + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/${MSDK_LIB}/CMSIS/5.9.0/Core/Include \ + $(TOP)/${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Include \ + $(TOP)/${MSDK_LIB}/PeriphDrivers/Include/${MAX_DEVICE_UPPER} \ + $(TOP)/${MSDK_LIB}/PeriphDrivers/Source/SYS \ + $(TOP)/${MSDK_LIB}/PeriphDrivers/Source/GPIO \ + $(TOP)/${MSDK_LIB}/PeriphDrivers/Source/ICC \ + $(TOP)/${MSDK_LIB}/PeriphDrivers/Source/FLC \ + $(TOP)/${MSDK_LIB}/PeriphDrivers/Source/UART \ + +# device specific +ifneq ($(filter $(MAX_DEVICE),max32650 max32665 max32666),) + SRC_C += \ + ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_common.c \ + ${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_${PERIPH_SUFFIX}${PERIPH_ID}.c \ + ${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_reva.c \ + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_reva.c \ + + INC += $(TOP)/${MSDK_LIB}/PeriphDrivers/Source/TPU +endif + +ifeq (${MAX_DEVICE},max32690) + SRC_C += \ + ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_${PERIPH_SUFFIX}${PERIPH_ID}.c \ + ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_reva.c \ + ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_common.c \ + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c \ + + INC += ${TOP}/${MSDK_LIB}/PeriphDrivers/Source/CTB +endif + +ifeq (${MAX_DEVICE},max78002) + SRC_C += \ + ${MSDK_LIB}/PeriphDrivers/Source/AES/aes_${PERIPH_SUFFIX}${PERIPH_ID}.c \ + ${MSDK_LIB}/PeriphDrivers/Source/AES/aes_revb.c \ + ${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_${PERIPH_SUFFIX}${PERIPH_ID}.c \ + ${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_revb.c \ + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c \ + + INC += \ + ${TOP}/${MSDK_LIB}/PeriphDrivers/Source/AES \ + ${TOP}/${MSDK_LIB}/PeriphDrivers/Source/TRNG +endif + + +# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the +# MAX32651 has a secure bootloader which requires the image to be signed before +# loading into flash. All MAX32651EVKIT's have the same key for evaluation +# purposes, so create a special flash rule to sign the binary and flash using +# the MSDK. +MCU_PATH = $(TOP)/hw/mcu/analog/msdk/ +# Assume no extension for sign utility +SIGN_EXE = sign_app +ifeq ($(OS), Windows_NT) +# Must use .exe extension on Windows, since the binaries +# for Linux may live in the same place. +SIGN_EXE := sign_app.exe +else +UNAME = $(shell uname -s) +ifneq ($(findstring MSYS_NT,$(UNAME)),) +# Must also use .exe extension for MSYS2 +SIGN_EXE := sign_app.exe +endif +endif + +# Rule to sign the build. This will in-place modify the existing .elf file +# an populate the .sig section with the signature value +sign-build: $(BUILD)/$(PROJECT).elf + $(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin + $(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 \ + key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \ + ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin + $(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig + +# Optional flash option when running within an installed MSDK to use OpenOCD +# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. +# If the MSDK is installed, flash-msdk can be run to utilize the the modified +# openocd with the algorithms +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +flash-msdk: $(BUILD)/$(PROJECT).elf + $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ + -f interface/cmsis-dap.cfg -f target/max32650.cfg \ + -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" + +# Configure the flash rule +flash: $(DEFAULT_FLASH) diff --git a/hw/bsp/max32650/boards/max32650evkit/max32650.ld b/hw/bsp/maxim/linker/max32650.ld index 0e56a91ec..0e56a91ec 100644 --- a/hw/bsp/max32650/boards/max32650evkit/max32650.ld +++ b/hw/bsp/maxim/linker/max32650.ld diff --git a/hw/bsp/max32650/boards/max32651evkit/max32651.ld b/hw/bsp/maxim/linker/max32651.ld index 3921d10f2..3921d10f2 100644 --- a/hw/bsp/max32650/boards/max32651evkit/max32651.ld +++ b/hw/bsp/maxim/linker/max32651.ld diff --git a/hw/bsp/max32666/max32666.ld b/hw/bsp/maxim/linker/max32665.ld index 06c124247..06c124247 100644 --- a/hw/bsp/max32666/max32666.ld +++ b/hw/bsp/maxim/linker/max32665.ld diff --git a/hw/bsp/max32690/max32690.ld b/hw/bsp/maxim/linker/max32690.ld index 64b906a54..64b906a54 100644 --- a/hw/bsp/max32690/max32690.ld +++ b/hw/bsp/maxim/linker/max32690.ld diff --git a/hw/bsp/max78002/max78002.ld b/hw/bsp/maxim/linker/max78002.ld index e5c4866ee..e5c4866ee 100644 --- a/hw/bsp/max78002/max78002.ld +++ b/hw/bsp/maxim/linker/max78002.ld diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.h b/hw/bsp/mcx/boards/frdm_mcxa153/board.h index e207d89d9..86f987de9 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board.h +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Freedom MCXA153 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA153 +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -34,10 +39,10 @@ extern "C" { // LED #define LED_GPIO GPIO3 #define LED_CLK kCLOCK_GateGPIO3 -#define LED_PIN 12 // red +#define LED_PIN 12 //red #define LED_STATE_ON 0 -// ISP button (Dummy, use unused pin +// ISP button #define BUTTON_GPIO GPIO3 #define BUTTON_CLK kCLOCK_GateGPIO3 #define BUTTON_PIN 29 //sw2 diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c index f16bc51f6..5a132dc67 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c +++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c @@ -45,14 +45,13 @@ processor_version: 0.13.0 * Variables ******************************************************************************/ /* System clock frequency. */ -//uint32_t SystemCoreClock; +//extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { - BOARD_BootClockFRO96M(); } /******************************************************************************* @@ -386,7 +385,6 @@ void BOARD_BootClockFRO64M(void) /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockFRO96M -called_from_default_init: true outputs: - {id: CLK_1M_clock.outFreq, value: 1 MHz} - {id: CLK_48M_clock.outFreq, value: 48 MHz} diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c index cc8f56e63..47709951b 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c +++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c @@ -4,7 +4,6 @@ * * SPDX-License-Identifier: BSD-3-Clause */ - /*********************************************************************************************************************** * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. @@ -18,16 +17,13 @@ product: Pins v14.0 processor: MCXA153 package_id: MCXA153VLH mcu_data: ksdk2_0 -processor_version: 0.14.3 -pin_labels: -- {pin_num: '38', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, label: LED_RED, identifier: LED_RED} +processor_version: 0.14.4 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ #include "fsl_common.h" #include "fsl_port.h" -#include "fsl_gpio.h" #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ @@ -47,8 +43,10 @@ void BOARD_InitBootPins(void) BOARD_InitPins: - options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} - pin_list: - - {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'false', slew_rate: fast, - open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal} + - {pin_num: '51', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + - {pin_num: '52', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ @@ -61,15 +59,6 @@ BOARD_InitPins: * END ****************************************************************************************************************/ void BOARD_InitPins(void) { - RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn); - RESET_PeripheralReset(kPORT0_RST_SHIFT_RSTn); - CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); - CLOCK_AttachClk(kFRO12M_to_LPUART0); - - /* write to PORT0: Peripheral clock is enabled */ - CLOCK_EnableClock(kCLOCK_GatePORT0); - - /* Write to GPIO3: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GateGPIO3); /* Write to PORT3: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GatePORT3); @@ -78,30 +67,13 @@ void BOARD_InitPins(void) /* PORT3 peripheral is released from reset */ RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); - const port_pin_config_t port3_12_pin38_config = {/* Internal pull-up/down resistor is disabled */ - kPORT_PullDisable, - /* Low internal pull resistor value is selected. */ - kPORT_LowPullResistor, - /* Fast slew rate is configured */ - kPORT_FastSlewRate, - /* Passive input filter is disabled */ - kPORT_PassiveFilterDisable, - /* Open drain output is disabled */ - kPORT_OpenDrainDisable, - /* Low drive strength is configured */ - kPORT_LowDriveStrength, - /* Normal drive strength is configured */ - kPORT_NormalDriveStrength, - /* Pin is configured as P3_12 */ - kPORT_MuxAlt0, - /* Digital input enabled */ - kPORT_InputBufferEnable, - /* Digital input is not inverted */ - kPORT_InputNormal, - /* Pin Control Register fields [15:0] are not locked */ - kPORT_UnlockRegister}; - /* PORT3_12 (pin 38) is configured as P3_12 */ - PORT_SetPinConfig(PORT3, 12U, &port3_12_pin38_config); + + /* Write to PORT0: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT0); + /* LPUART0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); + /* PORT0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, @@ -152,7 +124,6 @@ void BOARD_InitPins(void) kPORT_UnlockRegister}; /* PORT0_3 (pin 52) is configured as LPUART0_TXD */ PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config); - } /*********************************************************************************************************************** * EOF diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h index 06b6fdee9..2c0e617a5 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h +++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h @@ -1,9 +1,13 @@ /* - * Copyright 2022 NXP + * Copyright 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ #ifndef _PIN_MUX_H_ #define _PIN_MUX_H_ diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake new file mode 100644 index 000000000..a6aa6c2e4 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake @@ -0,0 +1,21 @@ +set(MCU_VARIANT MCXA156) +set(MCU_CORE MCXA156) + +set(JLINK_DEVICE MCXA156_M33) +set(PYOCD_TARGET MCXA156) +set(NXPLINK_DEVICE MCXA156:MCXA156) + +set(PORT 0) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + CPU_MCXA156VLH + BOARD_TUD_RHPORT=0 + BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED + CFG_EXAMPLE_VIDEO_READONLY + ) + target_sources(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c + ) +endfunction() diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.h b/hw/bsp/mcx/boards/frdm_mcxa156/board.h new file mode 100644 index 000000000..6c19797c6 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.h @@ -0,0 +1,69 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Freedom MCXA156 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA156 +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_GPIO GPIO3 +#define LED_CLK kCLOCK_GateGPIO3 +#define LED_PIN 12 // red +#define LED_STATE_ON 0 + +// ISP button +#define BUTTON_GPIO GPIO0 +#define BUTTON_CLK kCLOCK_GateGPIO0 +#define BUTTON_PIN 6 //SW3 +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_DEV LPUART0 + +static inline void board_uart_init_clock(void) { + /* attach 12 MHz clock to LPUART0 (debug console) */ + CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); + CLOCK_AttachClk(kFRO12M_to_LPUART0); + + RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn); +} + +// XTAL +#define XTAL0_CLK_HZ (24 * 1000 * 1000U) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.mk b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk new file mode 100644 index 000000000..d4a59b32a --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk @@ -0,0 +1,14 @@ +MCU_VARIANT = MCXA156 +MCU_CORE = MCXA156 +PORT = 0 + +CPU_CORE = cortex-m33-nodsp-nofp +CFLAGS += \ + -DCPU_MCXA156VLH \ + -DCFG_TUSB_MCU=OPT_MCU_MCXA15 \ + +JLINK_DEVICE = MCXA156 +PYOCD_TARGET = MCXA156 + +# flash using pyocd +flash: flash-jlink diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c new file mode 100644 index 000000000..f549af243 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c @@ -0,0 +1,482 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + * + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v13.0 +processor: MCXA156 +package_id: MCXA156VLL +mcu_data: ksdk2_0 +processor_version: 0.15.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_clock.h" +#include "clock_config.h" +#include "fsl_spc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +//extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockFRO96M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CPU_clock.outFreq, value: 12 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: MAIN_clock.outFreq, value: 12 MHz} +- {id: Slow_clock.outFreq, value: 3 MHz} +- {id: System_clock.outFreq, value: 12 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: SCGMode, value: SIRC} +- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SCG.SCSSEL.sel, value: SCG.SIRC} +- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO24M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO24M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 24 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 48 MHz} +- {id: Slow_clock.outFreq, value: 6 MHz} +- {id: System_clock.outFreq, value: 24 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +void BOARD_BootClockFRO24M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO48M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO48M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 48 MHz} +- {id: Slow_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 48 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +void BOARD_BootClockFRO48M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO64M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO64M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 64 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz} +- {id: FRO_HF_clock.outFreq, value: 64 MHz} +- {id: MAIN_clock.outFreq, value: 64 MHz} +- {id: Slow_clock.outFreq, value: 16 MHz} +- {id: System_clock.outFreq, value: 64 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: VDD_CORE, value: voltage_1v1} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FROHFDIV.scale, value: '1', locked: true} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} +sources: +- {id: SCG.FIRC.outFreq, value: 64 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +void BOARD_BootClockFRO64M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO96M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO96M +called_from_default_init: true +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 96 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz} +- {id: FRO_HF_clock.outFreq, value: 96 MHz} +- {id: MAIN_clock.outFreq, value: 96 MHz} +- {id: Slow_clock.outFreq, value: 24 MHz} +- {id: System_clock.outFreq, value: 96 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: VDD_CORE, value: voltage_1v1} +- {id: CLKOUTDIV_HALT, value: Enable} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FROHFDIV.scale, value: '1', locked: true} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} +sources: +- {id: SCG.FIRC.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +void BOARD_BootClockFRO96M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK; +} diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h new file mode 100644 index 000000000..3f5dfefda --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h @@ -0,0 +1,169 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO24M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO24M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO48M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO64M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK 64000000U /*!< Core clock frequency: 64000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO64M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO96M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c new file mode 100644 index 000000000..de35103a6 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c @@ -0,0 +1,144 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v15.0 +processor: MCXA156 +package_id: MCXA156VLL +mcu_data: ksdk2_0 +processor_version: 0.15.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_port.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '78', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + - {pin_num: '79', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) +{ + + RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn); + CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); + CLOCK_AttachClk(kFRO12M_to_LPUART0); + + /* GPIO3: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GateGPIO3); + /* PORT3: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT3); + /* GPIO3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); + /* PORT3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); + + /* GPIO3: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GateGPIO0); + /* PORT3: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT0); + /* GPIO3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn); + /* PORT3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); + + /* PORT0: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT0); + /* LPUART0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); + /* PORT0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); + + const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */ + kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + kPORT_NormalDriveStrength, + /* Pin is configured as LPUART0_RXD */ + kPORT_MuxAlt2, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT0_2 (pin 78) is configured as LPUART0_RXD */ + PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config); + + const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */ + kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + kPORT_NormalDriveStrength, + /* Pin is configured as LPUART0_TXD */ + kPORT_MuxAlt2, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT0_3 (pin 79) is configured as LPUART0_TXD */ + PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h new file mode 100644 index 000000000..fb7d1fc04 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h @@ -0,0 +1,51 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.h b/hw/bsp/mcx/boards/frdm_mcxn947/board.h index acb73363f..bb15620ef 100644 --- a/hw/bsp/mcx/boards/frdm_mcxn947/board.h +++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Freedom MCXN947 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXN947 +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -44,17 +49,22 @@ #define BUTTON_STATE_ACTIVE 0 // UART -#define UART_DEV LPUART4 +#define UART_DEV LPUART4 +#define LP_FLEXCOMM_INST 4 + +#include "fsl_lpflexcomm.h" static inline void board_uart_init_clock(void) { + /* attach FRO 12M to FLEXCOMM4 */ + + LP_FLEXCOMM_Init(LP_FLEXCOMM_INST, LP_FLEXCOMM_PERIPH_LPUART); + CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u); CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn); -} -//#define UART_RX_PINMUX 0, 24, IOCON_PIO_DIG_FUNC1_EN -//#define UART_TX_PINMUX 0, 25, IOCON_PIO_DIG_FUNC1_EN +} // XTAL #define XTAL0_CLK_HZ (24 * 1000 * 1000U) diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.h b/hw/bsp/mcx/boards/mcxn947brk/board.h index eae98bfa7..eef281787 100644 --- a/hw/bsp/mcx/boards/mcxn947brk/board.h +++ b/hw/bsp/mcx/boards/mcxn947brk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MCXN947 Breakout + url: n/a +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/mcx/drivers/spc/fsl_spc.c b/hw/bsp/mcx/drivers/spc/fsl_spc.c new file mode 100644 index 000000000..b16ca5fc5 --- /dev/null +++ b/hw/bsp/mcx/drivers/spc/fsl_spc.c @@ -0,0 +1,1680 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcx_spc" +#endif + +/* + * $Coverage Justification Reference$ + * + * $Justification spc_c_ref_1$ + * The SPC busy status flag is too short to get coverage data. + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Gets selected power domain's requested low power mode. + * + * param base SPC peripheral base address. + * param powerDomainId Power Domain Id, please refer to spc_power_domain_id_t. + * + * return The selected power domain's requested low power mode, please refer to spc_power_domain_low_power_mode_t. + */ +spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + + uint32_t val; + + val = ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_LP_MODE_MASK) >> SPC_PD_STATUS_LP_MODE_SHIFT); + return (spc_power_domain_low_power_mode_t)val; +} + +/*! + * brief Gets Isolation status for each power domains. + * + * This function gets the status which indicates whether certain + * peripheral and the IO pads are in a latched state as a result + * of having been in POWERDOWN mode. + * + * param base SPC peripheral base address. + * return Current isolation status for each power domains. + */ +uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base) +{ + uint32_t reg; + + reg = base->SC; + return (uint8_t)((reg & SPC_SC_ISO_CLR_MASK) >> SPC_SC_ISO_CLR_SHIFT); +} + +/*! + * brief Configs Low power request output pin. + * + * This function configs the low power request output pin + * + * param base SPC peripheral base address. + * param config Pointer the spc_LowPower_Request_config_t structure. + */ +void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config) +{ + assert(config != NULL); + + uint32_t reg; + + reg = base->LPREQ_CFG; + reg &= ~(SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL_MASK | SPC_LPREQ_CFG_LPREQOV_MASK); + + if (config->enable) + { + reg |= SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL((uint8_t)(config->polarity)) | + SPC_LPREQ_CFG_LPREQOV((uint8_t)(config->override)); + } + else + { + reg &= ~SPC_LPREQ_CFG_LPREQOE_MASK; + } + + base->LPREQ_CFG = reg; +} + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * param base SPC peripheral base address. + * param config Pointer to the structure in type of spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config) +{ + assert(config != NULL); + + uint32_t reg; + + reg = (base->VDD_CORE_GLITCH_DETECT_SC) & + ~(SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK); + + reg |= SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT(config->rippleCounterSelect) | + SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT(config->resetTimeoutValue) | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE(config->enableReset) | + SPC_VDD_CORE_GLITCH_DETECT_SC_IE(config->enableInterrupt); + + base->VDD_CORE_GLITCH_DETECT_SC = reg; +} +#endif + +/*! + * brief Set SRAM operate voltage. + * + * param base SPC peripheral base address. + * param config The pointer to spc_sram_voltage_config_t, specifies the configuration of sram voltage. + */ +void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + reg |= SPC_SRAMCTL_VSM(config->operateVoltage); + + base->SRAMCTL = reg; + + if (config->requestVoltageUpdate) + { + base->SRAMCTL |= SPC_SRAMCTL_REQ_MASK; + while ((base->SRAMCTL & SPC_SRAMCTL_ACK_MASK) == 0UL) + { + /* Wait until acknowledged */ + ; + } + base->SRAMCTL &= ~SPC_SRAMCTL_REQ_MASK; + } +} + +/*! + * brief Configs Bandgap mode in Active mode. + * + * @note To disable bandgap in Active mode: + * 1. Disable all LVD's and HVD's in active mode; + * 2. Disable Glitch detect; + * 3. Configure LDO's and DCDC to low drive strength in active mode; + * 4. Invoke this function to disable bandgap in active mode; + * otherwise the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * param base SPC peripheral base address. + * param mode The Bandgap mode be selected. + * + * retval kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode. + * retval kStatus_Success Config Bandgap mode in Active power mode successful. + */ +status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode) +{ + uint32_t reg; + uint32_t state; + + reg = base->ACTIVE_CFG; + + if (mode == kSPC_BandgapDisabled) + { + state = SPC_GetActiveModeVoltageDetectStatus(base); + + /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */ + if (state != 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) == + SPC_ACTIVE_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) == SPC_ACTIVE_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalVoltage)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) == + SPC_ACTIVE_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + } + + reg &= ~SPC_ACTIVE_CFG_BGMODE_MASK; + reg |= SPC_ACTIVE_CFG_BGMODE(mode); + + base->ACTIVE_CFG = reg; + + return kStatus_Success; +} + +/*! + * brief Configs Bandgap mode in Low Power mode. + * + * @note To disable Bandgap in Low-power mode: + * 1. Disable all LVD's ad HVD's in low power mode; + * 2. Disable Glitch detect in low power mode; + * 3. Configure LDO's and DCDC to low drive strength in low power mode; + * 4. Disable bandgap in low power mode; + * Otherwise, the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * param base SPC peripheral base address. + * param mode The Bandgap mode be selected. + * + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * retval kStatus_Success Config Bandgap mode in Low Power power mode successful. + */ +status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode) +{ + uint32_t reg; + uint32_t state; + + reg = base->LP_CFG; + + if (mode == kSPC_BandgapDisabled) + { + state = (uint32_t)SPC_GetLowPowerModeVoltageDetectStatus(base); + + /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */ + if (state != 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) == SPC_LP_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if ((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) == SPC_LP_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + if ((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) == + SPC_LP_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ + if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif + } + + reg &= ~SPC_LP_CFG_BGMODE_MASK; + reg |= SPC_LP_CFG_BGMODE(mode); + base->LP_CFG = reg; + + return kStatus_Success; +} + +/*! + * brief Configs CORE voltage detect options. + * + * This function configs CORE voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_core_voltage_detect_config_t structure. + */ +void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_CORE_CFG_HVDIE(1U) : SPC_VD_CORE_CFG_HVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_CORE_CFG_HVDRE(1U) : SPC_VD_CORE_CFG_HVDRE(0U); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_CORE_CFG_LVDIE(1U) : SPC_VD_CORE_CFG_LVDIE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_CORE_CFG_LVDRE(1U) : SPC_VD_CORE_CFG_LVDRE(0U); + + base->VD_CORE_CFG = reg; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) +/*! + * brief Enables the Core High Voltage Detector in Active mode. + * + * note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in active mode. + * false - Disable Core High voltage detector in active mode. + * + * retval kStatus_Success Enable Core High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the Core High Voltage Detector in Low Power mode. + * + * note If the CORE_LDO high voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each regulator + * must not set to low in low power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in low power mode. + * false - Disable Core High voltage detector in low power mode. + * + * retval kStatus_Success Enable Core High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_CORE_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_CORE_HVDE_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/*! + * brief Enables the Core VDD Low Voltage Detector in Active mode. + * + * note If the Core VDD high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core LVD. + * true - Enable Core Low voltage detector in active mode. + * false - Disable Core Low voltage detector in active mode. + * + * retval kStatus_Success Enable Core Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the Core Low Voltage Detector in Low Power mode. + * + * note If the Core VDD low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core Low voltage detector in low power mode. + * false - Disable Core Low voltage detector in low power mode. + * + * retval kStatus_Success Enable Core Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_CORE_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_CORE_LVDE_MASK; + } + + return status; +} + +/*! + * brief Set system VDD Low-voltage level selection. + * + * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level + * must be done after disabling the System VDD low voltage reset and interrupt. + * + * @deprecated In latest RM, reserved for all devices, will removed in next release. + * + * param base SPC peripheral base address. + * param level System VDD Low-Voltage level selection. See @ref spc_low_voltage_level_select_t for details. + */ +void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level) +{ + (void)level; + (void)base; + + /* + uint32_t reg; + + reg = base->VD_SYS_CFG; + + base->VD_SYS_CFG &= ~(SPC_VD_SYS_CFG_LVDRE_MASK | SPC_VD_SYS_CFG_LVDIE_MASK); + reg |= SPC_VD_SYS_CFG_LVSEL(level); + + base->VD_SYS_CFG = reg; */ +} + +/*! + * brief Configs SYS VDD voltage detect options. + * + * This function config SYS voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_system_voltage_detect_config_t structure. + */ +void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_SYS_CFG_HVDIE(1U) : SPC_VD_SYS_CFG_HVDIE(0U); + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_SYS_CFG_LVDIE(1U) : SPC_VD_SYS_CFG_LVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_SYS_CFG_HVDRE(1U) : SPC_VD_SYS_CFG_HVDRE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_SYS_CFG_LVDRE(1U) : SPC_VD_SYS_CFG_LVDRE(0U); + + base->VD_SYS_CFG = reg; + + (void)(config->level); + /* SPC_SetSystemVDDLowVoltageLevel(base, config->level); */ +} + +/*! + * brief Enables the System VDD High Voltage Detector in Active mode. + * + * note If the System_LDO high voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of + * each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in active mode. + * false - Disable System High voltage detector in active mode. + * + * retval kStatus_Success Enable System High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System VDD Low Voltage Detector in Active mode. + * + * note If the System_LDO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System LVD. + * true - Enable System Low voltage detector in active mode. + * false - Disable System Low voltage detector in active mode. + * + * retval kStatus_Success Enable the System Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System VDD High Voltage Detector in Low Power mode. + * + * note If the System_LDO high voltage detect is enabled in low power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in low power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in low power mode. + * false - Disable System High voltage detector in low power mode. + * + * retval kStatus_Success Enable System High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SYS_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SYS_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System VDD Low Voltage Detector in Low Power mode. + * + * note If the System_LDO low voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System Low voltage detector in low power mode. + * false - Disable System Low voltage detector in low power mode. + * + * retval kStatus_Success Enable System Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SYS_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SYS_LVDE_MASK; + } + + return status; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * brief Set IO VDD Low-Voltage level selection. + * + * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level + * must be done after disabling the IO VDD low voltage reset and interrupt. + * + * param base SPC peripheral base address. + * param level IO VDD Low-voltage level selection. + */ +void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level) +{ + uint32_t reg; + + reg = base->VD_IO_CFG; + + base->VD_IO_CFG &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_LVSEL_MASK); + reg |= SPC_VD_IO_CFG_LVSEL(level); + + base->VD_IO_CFG = reg; +} + +/*! + * brief Configs IO VDD voltage detect options. + * + * This function config IO voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_IO_voltage_detect_config_t structure. + */ +void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + /* Set trip voltage level. */ + SPC_SetIOVDDLowVoltageLevel(base, config->level); + + reg = base->VD_IO_CFG; + reg &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_HVDRE_MASK | SPC_VD_IO_CFG_HVDIE_MASK); + + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_IO_CFG_HVDIE(1U) : SPC_VD_IO_CFG_HVDIE(0U); + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_IO_CFG_LVDIE(1U) : SPC_VD_IO_CFG_LVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_IO_CFG_HVDRE(1U) : SPC_VD_IO_CFG_HVDRE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_IO_CFG_LVDRE(1U) : SPC_VD_IO_CFG_LVDRE(0U); + + base->VD_IO_CFG = reg; +} + +/*! + * brief Enables the IO VDD High Voltage Detector in Active mode. + * + * note If the IO high voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength + * of each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in active mode. + * false - Disable IO High voltage detector in active mode. + * + * retval kStatus_Success Enable IO High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO VDD Low Voltage Detector in Active mode. + * + * note If the IO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength + * of each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in active mode. + * false - Disable IO Low voltage detector in active mode. + * + * retval kStatus_Success Enable IO Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO VDD High Voltage Detector in Low Power mode. + * + * note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in low power mode. + * false - Disable IO High voltage detector in low power mode. + * + * retval kStatus_Success Enable IO High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_IO_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_IO_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO VDD Low Voltage Detector in Low Power mode. + * + * note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO Low voltage detector in low power mode. + * false - Disable IO Low voltage detector in low power mode. + * + * retval kStatus_Success Enable IO Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_IO_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_IO_LVDE_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * brief Configs external voltage domains + * + * This function configs external voltage domains isolation. + * + * param base SPC peripheral base address. + * param lowPowerIsoMask The mask of external domains isolate enable during low power mode. + * param IsoMask The mask of external domains isolate. + */ +void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask) +{ + uint32_t reg = 0UL; + + reg |= SPC_EVD_CFG_REG_EVDISO(IsoMask) | SPC_EVD_CFG_REG_EVDLPISO(lowPowerIsoMask); + base->EVD_CFG = reg; +} + +/*! + * brief Configs Core LDO Regulator in Active mode. + * + * @note The bandgap must be enabled before invoking this function. + * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_Core_LDO_option_t structure. + * + * retval kStatus_Success Config Core LDO regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength, + * all LVDs/HVDs must be disabled before invoking this function. + */ +status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option) +{ + assert(option != NULL); + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + return kStatus_SPC_Busy; + } + + /* Check input parameters. */ + /* 1. Bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* 2. To set to low drive strength, all LVDs/HVDs must be disabled previously. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) && + (option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + + if ((uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base) != (uint8_t)(option->CoreLDOVoltage)) + { +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, kSPC_CoreLDO_NormalDriveStrength); +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + } + +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + + return kStatus_Success; +} + +/*! + * brief Set Core LDO VDD Regulator Voltage level in Active mode. + * + * @note In active mode, the Core LDO voltage level should only be changed when the + * Core LDO is in normal drive strength. + * + * @note Update Core LDO voltage level will set Busy flag, + * this function return only when busy flag is cleared by hardware + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval kStatus_SPC_CORELDOVoltageSetFail Core LDO voltage level should only be + * changed when the CORE_LDO is in normal drive strength. + * retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + if ((uint8_t)voltageLevel != (uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base)) + { +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + if (SPC_GetActiveModeCoreLDODriveStrength(base) != kSPC_CoreLDO_NormalDriveStrength) + { + return kStatus_SPC_CORELDOVoltageSetFail; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(voltageLevel)); + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + } + return kStatus_Success; +} + +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. + */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_CoreLDO_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +/*! + * brief Configs CORE LDO Regulator in low power mode + * + * This function configs CORE LDO Regulator in Low Power mode. + * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage + * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap + * must be programmed to select bandgap enabled. + * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE + * LDO Drive Strength is set as Normal. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_lowpower_mode_Core_LDO_option_t structure. + * retval kStatus_Success Config Core LDO regulator in power mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore HVDs/LVDs are not disabled before invoking this function. + * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option) +{ + status_t status = kStatus_Success; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); + if (status == kStatus_Success) + { + (void)SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + } + + return status; +} + +/*! + * brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If Core LDO's drive strengths are same in active and low power mode, the Core LDO's voltage must be set to the + * same value in active and low power mode. Application should take care of this limitation. + * + * @note Some devices require Core LDO and DCDC have the same voltage level even if Core LDO is off. Application should + * take care of this limitation. + * + * param base SPC peripheral base address. + * param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval #kStatus_SPC_Busy The SPC instance is busy to execute other operation. + * retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_LVL_MASK) | SPC_LP_CFG_CORELDO_VDD_LVL(voltageLevel)); + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return kStatus_Success; +} + +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Low Power mode, then CORE_LDO's drive strength must not set to + * low. + */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + else + { + /* To specify normal drive strength, the bandgap must be enabled in low power mode. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_DS_MASK) | SPC_LP_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * brief Configs System LDO VDD Regulator in Active mode. + * + * This function configs System LDO VDD Regulator in Active mode. + * If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed + * to a value that enable the bandgap. + * If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will + * be ignored. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD + * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be disabled. + * Otherwise it will be fail to regulator to Over Drive Voltage. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_Sys_LDO_option_t structure. + * retval kStatus_Success Config System LDO regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. + * retval kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive voltage. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be + * ignored. + */ +status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option) +{ + assert(option != NULL); + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + /* Check input parameters before setting registers. */ + /* 1. To set to low DS, all LVDs/HVDs must be disabled previously. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) && + (option->SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + /* 2. If specify normal drive strength, bandgap must not be disabled. */ + if ((SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) && + (option->SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* 3. Must disable system LDO high voltage detector before specifying overdrive voltage. */ + if ((option->SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage) && + ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL)) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } + + (void)SPC_SetActiveModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + (void)SPC_SetActiveModeSystemLDORegulatorVoltageLevel(base, option->SysLDOVoltage); + + return kStatus_Success; +} + +/*! + * brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifying + * overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel) +{ + if (voltageLevel == kSPC_SysLDO_OverDriveVoltage) + { + /* Must disable system LDO high voltage detector before specifying overdrive voltage. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } + } + + base->ACTIVE_CFG = + (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(voltageLevel); + + return kStatus_Success; +} + +/*! + * brief Set System LDO Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) + { + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_SysLDO_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = + (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Configs System LDO regulator in low power modes. + * + * This function configs System LDO regulator in low power modes. + * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power + * mode must be programmed to a value that enables the Bandgap. + * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration + * to set System LDO Regulator drive strength as Low will be ignored. + * + * param base SPC peripheral base address. + * param option Pointer to spc_lowpower_mode_Sys_LDO_option_t structure. + * + * retval kStatus_Success Config System LDO regulator in Low Power Mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power Mode is wrong. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option) +{ + status_t status; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + + return status; +} + +/*! + * brief Set System LDO Regulator drive strength in Low Power Mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) + { + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + } + else + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = (base->LP_CFG & ~SPC_LP_CFG_SYSLDO_VDD_DS_MASK) | SPC_LP_CFG_SYSLDO_VDD_DS(driveStrength); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * brief Configs DCDC VDD Regulator in Active mode. + * + * note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_DCDC_option_t structure. + * + * retval kStatus_Success Config DCDC regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + */ +status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option) +{ + assert(option != NULL); + status_t status = kStatus_Success; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetActiveModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + + if (status == kStatus_Success) + { + SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set DCDC VDD Regulator drive strength in Active mode. + * + * note To set DCDC drive strength as Normal, the bandgap must be enabled. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Configs DCDC VDD Regulator in Low power modes. + * + * If DCDC VDD Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed + * to a value that enables the Bandgap. + * In Deep Power Down mode, DCDC regulator is always turned off. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_lowpower_mode_DCDC_option_t structure. + * + * retval kStatus_Success Config DCDC regulator in low power mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap should be enabled before invoking this function. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option) +{ + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + /* Check input parameter before setting registers. */ + if ((option->DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) && + (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled)) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* + 1. Configure to desired voltage level. + 2. Change to low drive strength. + 3. Configure same voltage level in active mode. + */ + SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); + + /* Change to desired drive strength. */ + if (option->DCDCDriveStrength != kSPC_DCDC_LowDriveStrength) + { + (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return kStatus_Success; +} + +/*! + * brief Set DCDC VDD Regulator drive strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Low power mode successfully. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_DCDC_VDD_DS_MASK)) | SPC_LP_CFG_DCDC_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Config DCDC Burst options + * + * param base SPC peripheral base address. + * param config Pointer to spc_DCDC_burst_config_t structure. + */ +void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config) +{ + assert(config != NULL); + uint32_t reg; + reg = base->DCDC_CFG; + reg &= ~(SPC_DCDC_CFG_FREQ_CNTRL_MASK | SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK); + reg |= SPC_DCDC_CFG_FREQ_CNTRL(config->freq); + reg |= config->stabilizeBurstFreq ? SPC_DCDC_CFG_FREQ_CNTRL_ON(1U) : SPC_DCDC_CFG_FREQ_CNTRL_ON(0U); + base->DCDC_CFG = reg; + + /* Blocking until previous DCDC burst completed. */ + while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL) + { + } + + if ((config->sofwareBurstRequest) || (config->externalBurstRequest)) + { + /* Clear DCDC burst acknowledge flag. */ + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; + } + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_EXT_BURST_EN(config->externalBurstRequest); + + if (config->sofwareBurstRequest) + { + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK; + } +} + +/*! + * brief Set the count value of the reference clock. + * + * This function set the count value of the reference clock to control the frequency + * of dcdc refresh when dcdc is configured in Pulse Refresh mode. + * + * param base SPC peripheral base address. + * param count The count value, 16 bit width. + */ +void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count) +{ + uint32_t reg; + + reg = base->DCDC_BURST_CFG; + reg &= ~SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK; + reg |= SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(count); + + base->DCDC_BURST_CFG = reg; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * brief Configs all settings of regulators in Active mode at a time. + * + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in active mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unknown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other low-level functions. + * + * param base SPC peripheral base address. + * param config Pointer to spc_active_mode_regulators_config_t structure. + * retval kStatus_Success Config regulators in Active power mode successful. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * retval kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored. + * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config) +{ + assert(config != NULL); + + uint32_t activeModeVDValue = SPC_GetActiveModeVoltageDetectStatus(base); + + /* Check input parameters */ + /* 1. Bandgap should not be disabled if any of regulator in normal drive strength or + if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */ + if ((config->bandgapMode == kSPC_BandgapDisabled) && + ((activeModeVDValue != 0UL) +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + || (SPC_CheckActiveModeVddCoreGlitchDetectEnabled(base) == true) +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + )) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 2. Must disable system LDO high voltage detector before specifying SysLDO to overdrive voltage */ + if (((activeModeVDValue & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) && + (config->SysLDOOption.SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage)) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 3. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((activeModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + /* 4. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((activeModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + /* 5. Core LDO and DCDC should have same voltage level. */ + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + return kStatus_SPC_Busy; + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG) & ~(SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + SPC_EnableActiveModeCMPBandgapBuffer(base, config->lpBuff); +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + (void)SPC_SetActiveModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + (void)SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + (void)SPC_SetActiveModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + + return kStatus_Success; +} + +/*! + * brief Configs regulators in Low Power mode. + * + * This function provides the method to config all on-chip regulators in Low Power mode. + * + * param base SPC peripheral base address. + * param config Pointer to spc_lowpower_mode_regulators_config_t structure. + * retval #kStatus_Success Config regulators in Low power mode successful. + * retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings. + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. + */ +status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config) +{ + assert(config != NULL); + uint32_t lpModeVDValue = SPC_GetLowPowerModeVoltageDetectStatus(base); + + /* Check input parameters */ + /* 1. Bandgap should not be disabled if any of regulator in normal drive strength or + if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */ + if ((config->bandgapMode == kSPC_BandgapDisabled) && + ((lpModeVDValue != 0UL) +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + || (SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(base) == true) +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + )) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 2. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((lpModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + /* 3. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((lpModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + /* 5. Core LDO and DCDC should have same voltage level. */ + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + base->LP_CFG = ((base->LP_CFG) & ~(SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + SPC_EnableLowPowerModeCMPBandgapBuffer(base, config->lpBuff); +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(base, config->CoreIVS); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + SPC_EnableLowPowerModeLowPowerIREF(base, config->lpIREF); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + (void)SPC_SetLowPowerModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + (void)SPC_SetLowPowerModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + (void)SPC_SetLowPowerModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + + return kStatus_Success; +} diff --git a/hw/bsp/mcx/drivers/spc/fsl_spc.h b/hw/bsp/mcx/drivers/spc/fsl_spc.h new file mode 100644 index 000000000..69a001098 --- /dev/null +++ b/hw/bsp/mcx/drivers/spc/fsl_spc.h @@ -0,0 +1,2433 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SPC_H_ +#define FSL_SPC_H_ +#include "fsl_common.h" + +/*! + * @addtogroup mcx_spc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief SPC driver version 2.4.2. */ +#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) +/*! @} */ + +#define SPC_EVD_CFG_REG_EVDISO_SHIFT 0UL +#define SPC_EVD_CFG_REG_EVDLPISO_SHIFT 8UL +#define SPC_EVD_CFG_REG_EVDSTAT_SHIFT 16UL + +#define SPC_EVD_CFG_REG_EVDISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDISO_SHIFT) +#define SPC_EVD_CFG_REG_EVDLPISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDLPISO_SHIFT) +#define SPC_EVD_CFG_REG_EVDSTAT(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDSTAT_SHIFT) + +#if (defined(SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK)) +#define VDD_CORE_GLITCH_DETECT_SC GLITCH_DETECT_SC +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG +#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK SPC_GLITCH_DETECT_SC_LOCK_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT SPC_GLITCH_DETECT_SC_CNT_SELECT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK SPC_GLITCH_DETECT_SC_RE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE SPC_GLITCH_DETECT_SC_RE +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK SPC_GLITCH_DETECT_SC_TIMEOUT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT SPC_GLITCH_DETECT_SC_TIMEOUT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK SPC_GLITCH_DETECT_SC_IE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE SPC_GLITCH_DETECT_SC_IE +#endif + +/*! + * @brief SPC status enumeration. + * + * @note Some device(such as MCXA family) do not equip DCDC or System LDO, please refer to the reference manual + * to check. + */ +enum +{ + kStatus_SPC_Busy = MAKE_STATUS(kStatusGroup_SPC, 0U), /*!< The SPC instance is busy executing any + type of power mode transition. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + kStatus_SPC_DCDCLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 1U), /*!< DCDC Low drive strength setting be + ignored for LVD/HVD enabled. */ + kStatus_SPC_DCDCPulseRefreshModeIgnore = MAKE_STATUS(kStatusGroup_SPC, 2U), /*!< DCDC Pulse Refresh Mode drive + strength setting be ignored for LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + kStatus_SPC_SYSLDOOverDriveVoltageFail = MAKE_STATUS(kStatusGroup_SPC, 3U), /*!< SYS LDO regulate to Over drive + voltage failed for SYS LDO HVD must be disabled. */ + kStatus_SPC_SYSLDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 4U), /*!< SYS LDO Low driver strength + setting be ignored for LDO LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + kStatus_SPC_CORELDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 5U), /*!< CORE LDO Low driver strength + setting be ignored for LDO LVD/HVD enabled. */ + kStatus_SPC_CORELDOVoltageWrong = MAKE_STATUS(kStatusGroup_SPC, 7U), /*!< Core LDO voltage is wrong. */ + kStatus_SPC_CORELDOVoltageSetFail = MAKE_STATUS(kStatusGroup_SPC, 8U), /*!< Core LDO voltage set fail. */ + kStatus_SPC_BandgapModeWrong = MAKE_STATUS(kStatusGroup_SPC, 6U), /*!< Selected Bandgap Mode wrong. */ +}; + +/*! + * @brief Voltage Detect Status Flags. + */ +enum _spc_voltage_detect_flags +{ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + kSPC_IOVDDHighVoltageDetectFlag = SPC_VD_STAT_IOVDD_HVDF_MASK, /*!< IO VDD High-Voltage detect flag. */ + kSPC_IOVDDLowVoltageDetectFlag = SPC_VD_STAT_IOVDD_LVDF_MASK, /*!< IO VDD Low-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + kSPC_SystemVDDHighVoltageDetectFlag = SPC_VD_STAT_SYSVDD_HVDF_MASK, /*!< System VDD High-Voltage detect flag. */ + kSPC_SystemVDDLowVoltageDetectFlag = SPC_VD_STAT_SYSVDD_LVDF_MASK, /*!< System VDD Low-Voltage detect flag. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + kSPC_CoreVDDHighVoltageDetectFlag = SPC_VD_STAT_COREVDD_HVDF_MASK, /*!< Core VDD High-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + kSPC_CoreVDDLowVoltageDetectFlag = SPC_VD_STAT_COREVDD_LVDF_MASK, /*!< Core VDD Low-Voltage detect flag. */ +}; + +/*! + * @brief SPC power domain isolation status. + * @note Some devices(such as MCXA family) do not contain WAKE Power Domain, please refer to the reference manual to + * check. + */ +enum _spc_power_domains +{ + kSPC_MAINPowerDomainRetain = 1UL << 16U, /*!< Peripherals and IO pads retain in MAIN Power Domain. */ + kSPC_WAKEPowerDomainRetain = 1UL << 17U, /*!< Peripherals and IO pads retain in WAKE Power Domain. */ +}; + +/*! + * @brief The enumeration of all analog module that can be controlled by SPC in active or low-power modes. + * @anchor spc_analog_module_control + */ +enum _spc_analog_module_control +{ + kSPC_controlVref = 1UL << 0UL, /*!< Enable/disable VREF in active or low-power modes. */ + kSPC_controlUsb3vDet = 1UL << 1UL, /*!< Enable/disable USB3V_Det in active or low-power modes. */ + kSPC_controlDac0 = 1UL << 4UL, /*!< Enable/disable DAC0 in active or low-power modes. */ + kSPC_controlDac1 = 1UL << 5UL, /*!< Enable/disable DAC1 in active or low-power modes. */ + kSPC_controlDac2 = 1UL << 6UL, /*!< Enable/disable DAC2 in active or low-power modes. */ + kSPC_controlOpamp0 = 1UL << 8UL, /*!< Enable/disable OPAMP0 in active or low-power modes. */ + kSPC_controlOpamp1 = 1UL << 9UL, /*!< Enable/disable OPAMP1 in active or low-power modes. */ + kSPC_controlOpamp2 = 1UL << 10UL, /*!< Enable/disable OPAMP2 in active or low-power modes. */ + kSPC_controlCmp0 = 1UL << 16UL, /*!< Enable/disable CMP0 in active or low-power modes. */ + kSPC_controlCmp1 = 1UL << 17UL, /*!< Enable/disable CMP1 in active or low-power modes. */ + kSPC_controlCmp2 = 1UL << 18UL, /*!< Enable/disable CMP2 in active or low-power modes. */ + kSPC_controlCmp0Dac = 1UL << 20UL, /*!< Enable/disable CMP0_DAC in active or low-power modes. */ + kSPC_controlCmp1Dac = 1UL << 21UL, /*!< Enable/disable CMP1_DAC in active or low-power modes. */ + kSPC_controlCmp2Dac = 1UL << 22UL, /*!< Enable/disable CMP2_DAC in active or low-power modes. */ + kSPC_controlAllModules = 0x770773UL, /*!< Enable/disable all modules in active or low-power modes. */ +}; + +/*! + * @brief The enumeration of spc power domain, the connected power domain is chip specific, please refer to chip's RM + * for details. + */ +typedef enum _spc_power_domain_id +{ + kSPC_PowerDomain0 = 0U, /*!< Power domain0, the connected power domain is chip specific. */ + kSPC_PowerDomain1 = 1U, /*!< Power domain1, the connected power domain is chip specific. */ +} spc_power_domain_id_t; + +/*! + * @brief The enumeration of Power domain's low power mode. + */ +typedef enum _spc_power_domain_low_power_mode +{ + kSPC_SleepWithSYSClockRunning = 0U, /*!< Power domain request SLEEP mode with SYS clock running. */ + kSPC_DeepSleepWithSysClockOff = 1U, /*!< Power domain request deep sleep mode with system clock off. */ + kSPC_PowerDownWithSysClockOff = 2U, /*!< Power domain request power down mode with system clock off. */ + kSPC_DeepPowerDownWithSysClockOff = 4U, /*!< Power domain request deep power down mode with system clock off. */ +} spc_power_domain_low_power_mode_t; + +/*! + * @brief SPC low power request output pin polarity. + */ +typedef enum _spc_lowPower_request_pin_polarity +{ + kSPC_HighTruePolarity = 0x0U, /*!< Control the High Polarity of the Low Power Request Pin. */ + kSPC_LowTruePolarity = 0x1U, /*!< Control the Low Polarity of the Low Power Request Pin. */ +} spc_lowpower_request_pin_polarity_t; + +/*! + * @brief SPC low power request output override. + */ +typedef enum _spc_lowPower_request_output_override +{ + kSPC_LowPowerRequestNotForced = 0x0U, /*!< Not Forced. */ + kSPC_LowPowerRequestReserved = 0x1U, /*!< Reserved. */ + kSPC_LowPowerRequestForcedLow = 0x2U, /*!< Forced Low (Ignore LowPower request output polarity setting.) */ + kSPC_LowPowerRequestForcedHigh = 0x3U, /*!< Forced High (Ignore LowPower request output polarity setting.) */ +} spc_lowpower_request_output_override_t; + +/*! + * @brief SPC Bandgap mode enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_bandgap_mode +{ + kSPC_BandgapDisabled = 0x0U, /*!< Bandgap disabled. */ + kSPC_BandgapEnabledBufferDisabled = 0x1U, /*!< Bandgap enabled with Buffer disabled. */ + kSPC_BandgapEnabledBufferEnabled = 0x2U, /*!< Bandgap enabled with Buffer enabled. */ + kSPC_BandgapReserved = 0x3U, /*!< Reserved. */ +} spc_bandgap_mode_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator voltage level enumeration in Active mode or Low Power Mode. + * + * @note #kSPC_DCDC_RetentionVoltage not supported for all power modes. + */ +typedef enum _spc_dcdc_voltage_level +{ + kSPC_DCDC_RetentionVoltage = 0x0U, /*!< DCDC_CORE Regulator regulate to retention + Voltage(Only supportedin low power modes) */ + kSPC_DCDC_MidVoltage = 0x1U, /*!< DCDC_CORE Regulator regulate to Mid Voltage(1.0V). */ + kSPC_DCDC_NormalVoltage = 0x2U, /*!< DCDC_CORE Regulator regulate to Normal Voltage(1.1V). */ + kSPC_DCDC_OverdriveVoltage = 0x3U, /*!< DCDC_CORE Regulator regulate to Safe-Mode Voltage(1.2V). */ +} spc_dcdc_voltage_level_t; + +/*! + * @brief DCDC regulator Drive Strength enumeration in Active mode or Low Power Mode. + * + * @note Different drive strength differ in these DCDC characteristics: + * Maximum load current + * Quiescent current + * Transient response. + */ +typedef enum _spc_dcdc_drive_strength +{ + kSPC_DCDC_PulseRefreshMode = 0x0U, /*!< DCDC_CORE Regulator Drive Strength set to Pulse Refresh Mode, + * This enum member is only useful for Low Power Mode config, please + * note that pulse refresh mode is invalid in SLEEP mode. + */ + kSPC_DCDC_LowDriveStrength = 0x1U, /*!< DCDC_CORE regulator Drive Strength set to low. */ + kSPC_DCDC_NormalDriveStrength = 0x2U, /*!< DCDC_CORE regulator Drive Strength set to Normal. */ +} spc_dcdc_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief SYS LDO regulator voltage level enumeration in Active mode. + */ +typedef enum _spc_sys_ldo_voltage_level +{ + kSPC_SysLDO_NormalVoltage = 0x0U, /*!< SYS LDO VDD Regulator regulate to Normal Voltage(1.8V). */ + kSPC_SysLDO_OverDriveVoltage = 0x1U, /*!< SYS LDO VDD Regulator regulate to Over Drive Voltage(2.5V). */ +} spc_sys_ldo_voltage_level_t; + +/*! + * @brief SYS LDO regulator Drive Strength enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_sys_ldo_drive_strength +{ + kSPC_SysLDO_LowDriveStrength = 0x0U, /*!< SYS LDO VDD regulator Drive Strength set to low. */ + kSPC_SysLDO_NormalDriveStrength = 0x1U, /*!< SYS LDO VDD regulator Drive Strength set to Normal. */ +} spc_sys_ldo_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +/*! + * @brief Core LDO regulator voltage level enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_core_ldo_voltage_level +{ + kSPC_CoreLDO_UnderDriveVoltage = 0x0U, /*!< @deprecated, to align with description of latest RM, please use + #kSPC_Core_LDO_RetentionVoltage as instead. */ + kSPC_Core_LDO_RetentionVoltage = 0x0U, /*!< Core LDO VDD regulator regulate to retention voltage, please note that + only useful in low power modes and not all devices support this options + please refer to devices' RM for details. */ + kSPC_CoreLDO_MidDriveVoltage = 0x1U, /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. */ + kSPC_CoreLDO_NormalVoltage = 0x2U, /*!< Core LDO VDD regulator regulate to Normal Voltage. */ + kSPC_CoreLDO_OverDriveVoltage = 0x3U, /*!< Core LDO VDD regulator regulate to overdrive Voltage. */ +} spc_core_ldo_voltage_level_t; + +/*! + * @brief CORE LDO VDD regulator Drive Strength enumeration in Low Power mode. + */ +typedef enum _spc_core_ldo_drive_strength +{ + kSPC_CoreLDO_LowDriveStrength = 0x0U, /*!< Core LDO VDD regulator Drive Strength set to low. */ + kSPC_CoreLDO_NormalDriveStrength = 0x1U, /*!< Core LDO VDD regulator Drive Strength set to Normal. */ +} spc_core_ldo_drive_strength_t; + +/*! + * @brief IO VDD Low-Voltage Level Select. + */ +typedef enum _spc_low_voltage_level_select +{ + kSPC_LowVoltageNormalLevel = 0x0U, /*!< @deprecated, please use kSPC_LowVoltageHighRange as instead. */ + kSPC_LowVoltageSafeLevel = 0x1U, /*!< @deprecated, please use kSPC_LowVoltageLowRange as instead. */ + + kSPC_LowVoltageHighRange = 0x0U, /*!< High range LVD threshold. */ + kSPC_LowVoltageLowRange = 0x1U, /*!< Low range LVD threshold. */ +} spc_low_voltage_level_select_t; + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief Used to select output of 4-bit ripple counter is used to monitor a glitch on VDD core. + */ +typedef enum _spc_vdd_core_glitch_ripple_counter_select +{ + kSPC_selectBit0Of4bitRippleCounter = 0x0U, /*!< Select bit-0 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit1Of4bitRippleCounter = 0x1U, /*!< Select bit-1 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit2Of4bitRippleCounter = 0x2U, /*!< Select bit-2 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit3Of4bitRippleCounter = 0x3U, /*!< Select bit-3 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ +} spc_vdd_core_glitch_ripple_counter_select_t; +#endif + +/*! + * @brief The list of the operating voltage for the SRAM's read/write timing margin. + */ +typedef enum _spc_sram_operate_voltage +{ + kSPC_sramOperateAt1P0V = 0x1U, /*!< SRAM configured for 1.0V operation. */ + kSPC_sramOperateAt1P1V = 0x2U, /*!< SRAM configured for 1.1V operation. */ + kSPC_sramOperateAt1P2V = 0x3U, /*!< SRAM configured for 1.2V operation. */ +} spc_sram_operate_voltage_t; + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief The configuration of VDD Core glitch detector. + */ +typedef struct _spc_vdd_core_glitch_detector_config +{ + spc_vdd_core_glitch_ripple_counter_select_t rippleCounterSelect; /*!< Used to set ripple counter. */ + uint8_t resetTimeoutValue; /*!< The timeout value used to reset glitch detect/compare logic after an initial + glitch is detected. */ + bool enableReset; /*!< Used to enable/disable POR/LVD reset that caused by CORE VDD glitch detect error. */ + bool enableInterrupt; /*!< Used to enable/disable hardware interrupt if CORE VDD glitch detect error. */ +} spc_vdd_core_glitch_detector_config_t; +#endif + +typedef struct _spc_sram_voltage_config +{ + spc_sram_operate_voltage_t operateVoltage; /*!< Specifies the operating voltage for the SRAM's + read/write timing margin. */ + bool requestVoltageUpdate; /*!< Used to control whether request an SRAM trim value change. */ +} spc_sram_voltage_config_t; + +/*! + * @brief Low Power Request output pin configuration. + */ +typedef struct _spc_lowpower_request_config +{ + bool enable; /*!< Low Power Request Output enable. */ + spc_lowpower_request_pin_polarity_t polarity; /*!< Low Power Request Output pin polarity select. */ + spc_lowpower_request_output_override_t override; /*!< Low Power Request Output Override. */ +} spc_lowpower_request_config_t; + +/*! + * @brief Core LDO regulator options in Active mode. + */ +typedef struct _spc_active_mode_core_ldo_option +{ + spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Active mode. */ +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength + selection in Active mode */ +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ +} spc_active_mode_core_ldo_option_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief System LDO regulator options in Active mode. + */ +typedef struct _spc_active_mode_sys_ldo_option +{ + spc_sys_ldo_voltage_level_t SysLDOVoltage; /*!< System LDO Regulator Voltage Level selection in Active mode. */ + spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength + selection in Active mode. */ +} spc_active_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator options in Active mode. + */ +typedef struct _spc_active_mode_dcdc_option +{ + spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Active mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Active mode. */ +} spc_active_mode_dcdc_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * @brief Core LDO regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_core_ldo_option +{ + spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Low Power mode. */ + spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength + selection in Low Power mode */ +} spc_lowpower_mode_core_ldo_option_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief System LDO regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_sys_ldo_option +{ + spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength + selection in Low Power mode. */ +} spc_lowpower_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_dcdc_option +{ + spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Low Power mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Low Power mode. */ +} spc_lowpower_mode_dcdc_option_t; + +/*! + * @brief DCDC Burst configuration. + * @deprecated Do not recommend to use this structure. + */ +typedef struct _spc_dcdc_burst_config +{ + bool sofwareBurstRequest; /*!< Enable/Disable DCDC Software Burst Request. */ + bool externalBurstRequest; /*!< Enable/Disable DCDC External Burst Request. */ + bool stabilizeBurstFreq; /*!< Enable/Disable DCDC frequency stabilization. */ + uint8_t freq; /*!< The frequency of the current burst. */ +} spc_dcdc_burst_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * @brief CORE/SYS/IO VDD Voltage Detect options. + */ +typedef struct _spc_voltage_detect_option +{ + bool HVDInterruptEnable; /*!< CORE/SYS/IO VDD High Voltage Detect interrupt enable. */ + bool HVDResetEnable; /*!< CORE/SYS/IO VDD High Voltage Detect reset enable. */ + bool LVDInterruptEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect interrupt enable. */ + bool LVDResetEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect reset enable. */ +} spc_voltage_detect_option_t; + +/*! + * @brief Core Voltage Detect configuration. + */ +typedef struct _spc_core_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< Core VDD Voltage Detect option. */ +} spc_core_voltage_detect_config_t; + +/*! + * @brief System Voltage Detect Configuration. + */ +typedef struct _spc_system_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< System VDD Voltage Detect option. */ + spc_low_voltage_level_select_t level; /*!< @deprecated, reserved for all devices, will removed in next release. */ +} spc_system_voltage_detect_config_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * @brief IO Voltage Detect Configuration. + */ +typedef struct _spc_io_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< IO VDD Voltage Detect option. */ + spc_low_voltage_level_select_t level; /*!< IO VDD Low-voltage level selection. */ +} spc_io_voltage_detect_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * @brief Active mode configuration. + */ +typedef struct _spc_active_mode_regulators_config +{ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in active mode. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_active_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + spc_active_mode_sys_ldo_option_t SysLDOOption; /*!< Specify System LDO configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + spc_active_mode_core_ldo_option_t CoreLDOOption; /*!< Specify Core LDO configurations in active mode. */ +} spc_active_mode_regulators_config_t; + +/*! + * @brief Low Power Mode configuration. + */ +typedef struct _spc_lowpower_mode_regulators_config +{ + bool lpIREF; /*!< Enable/disable low power IREF in low power modes. */ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in low power modes. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + bool CoreIVS; /*!< Enable/disable CORE VDD internal voltage scaling. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_lowpower_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + spc_lowpower_mode_sys_ldo_option_t SysLDOOption; /*!< Specify system LDO configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + spc_lowpower_mode_core_ldo_option_t CoreLDOOption; /*!< Specify core LDO configurations in low power modes. */ +} spc_lowpower_mode_regulators_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name SPC Status + * @{ + */ +/*! + * @brief Gets Isolation status for each power domains. + * + * This function gets the status which indicates whether certain + * peripheral and the IO pads are in a latched state as a result + * of having been in POWERDOWN mode. + * + * @param base SPC peripheral base address. + * @return Current isolation status for each power domains. See @ref _spc_power_domains for details. + */ +uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base); + +/*! + * @brief Clears peripherals and I/O pads isolation flags for each power domains. + * + * This function clears peripherals and I/O pads isolation flags for each power domains. + * After recovering from the POWERDOWN mode, user must invoke this function to release the + * I/O pads and certain peripherals to their normal run mode state. Before invoking this + * function, user must restore chip configuration in particular pin configuration for enabled + * WUU wakeup pins. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_ClearPeriphIOIsolationFlag(SPC_Type *base) +{ + base->SC |= SPC_SC_ISO_CLR_MASK; +} + +/*! + * @brief Gets SPC busy status flag. + * + * This function gets SPC busy status flag. When SPC executing any type of power mode + * transition in ACTIVE mode or any of the SOC low power mode, the SPC busy status flag is set + * and this function returns true. When changing CORE LDO voltage level and DCDC voltage level + * in ACTIVE mode, the SPC busy status flag is set and this function return true. + * + * @param base SPC peripheral base address. + * @return Ack busy flag. + * true - SPC is busy. + * false - SPC is not busy. + */ +static inline bool SPC_GetBusyStatusFlag(SPC_Type *base) +{ + return ((base->SC & SPC_SC_BUSY_MASK) != 0UL); +} + +/*! + * @brief Checks system low power request. + * + * @note Only when all power domains request low power mode entry, the result of this function is true. That means when + * all power domains request low power mode entry, the SPC regulators will be controlled by LP_CFG register. + * + * @param base SPC peripheral base address. + * @return The system low power request check result. + * - \b true All power domains have requested low power mode and SPC has entered a low power state and power mode + * configuration are based on the LP_CFG configuration register. + * - \b false SPC in active mode and ACTIVE_CFG register control system power supply. + */ +static inline bool SPC_CheckLowPowerReqest(SPC_Type *base) +{ + return ((base->SC & SPC_SC_SPC_LP_REQ_MASK) == SPC_SC_SPC_LP_REQ_MASK); +} + +/*! + * @brief Clears system low power request, set SPC in active mode. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_ClearLowPowerRequest(SPC_Type *base) +{ + base->SC |= SPC_SC_SPC_LP_REQ_MASK; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) && FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) +/*! + * @brief Checks whether the power switch is on. + * + * @param base SPC peripheral base address. + * + * @retval true The power switch is on. + * @retval false The power switch is off. + */ +static inline bool SPC_CheckSwitchState(SPC_Type *base) +{ + return ((base->SC & SPC_SC_SWITCH_STATE_MASK) != 0UL); +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT */ + +/*! + * @brief Gets selected power domain's requested low power mode. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + * + * @return The selected power domain's requested low power mode, please refer to @ref spc_power_domain_low_power_mode_t. + */ +spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId); + +/*! + * @brief Checks power domain's low power request. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + * @return The result of power domain's low power request. + * - \b true The selected power domain requests low power mode entry. + * - \b false The selected power domain does not request low power mode entry. + */ +static inline bool SPC_CheckPowerDomainLowPowerRequest(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + return ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) == + SPC_PD_STATUS_PWR_REQ_STATUS_MASK); +} + +/*! + * @brief Clears selected power domain's low power request flag. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + */ +static inline void SPC_ClearPowerDomainLowPowerRequestFlag(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + base->PD_STATUS[(uint8_t)powerDomainId] |= SPC_PD_STATUS_PD_LP_REQ_MASK; +} + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) && FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) +/*! + * @name SRAM Retention LDO Control APIs + * @{ + */ + +/*! + * @brief Trims SRAM retention regulator reference voltage, trim step is 12 mV, range is around 0.48V to 0.85V. + * + * @param base SPC peripheral base address. + * @param trimValue Reference voltage trim value. + */ +static inline void SPC_TrimSRAMLdoRefVoltage(SPC_Type *base, uint8_t trimValue) +{ + base->SRAMRETLDO_REFTRIM = + ((base->SRAMRETLDO_REFTRIM & ~SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK) | SPC_SRAMRETLDO_REFTRIM_REFTRIM(trimValue)); +} + +/*! + * @brief Enables/disables SRAM retention LDO. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable SRAM LDO : + * - \b true Enable SRAM LDO; + * - \b false Disable SRAM LDO. + */ +static inline void SPC_EnableSRAMLdo(SPC_Type *base, bool enable) +{ + if (enable) + { + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } + else + { + base->SRAMRETLDO_CNTRL &= ~SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } +} + +/*! + * @brief + * + * @todo Need to check. + * + * @param base SPC peripheral base address. + * @param mask The OR'ed value of SRAM Array. + */ +static inline void SPC_RetainSRAMArray(SPC_Type *base, uint8_t mask) +{ + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(mask); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG */ + +/*! + * @name Low Power Request configuration + * @{ + */ +/*! + * @brief Configs Low power request output pin. + * + * This function config the low power request output pin + * + * @param base SPC peripheral base address. + * @param config Pointer the @ref spc_lowpower_request_config_t structure. + */ +void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config); + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CFG_REG) && FSL_FEATURE_MCX_SPC_HAS_CFG_REG) +/*! + * @name Integrated Power Switch Control APIs + * @{ + */ + +/*! + * @brief Enables/disables the integrated power switch manually. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable the integrated power switch: + * - \b true Enable the integrated power switch; + * - \b false Disable the integrated power switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchManually(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= (SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } + else + { + base->CFG &= ~(SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } +} + +/*! + * @brief Enables/disables the integrated power switch automatically. + * + * To gate the integrated power switch when chip enter low power modes, and ungate the switch after wake-up from low + * power modes: + * @code + * SPC_EnableIntegratedPowerSwitchAutomatically(SPC, true, true); + * @endcode + * + * @param base SPC peripheral base address. + * @param sleepGate Enable the integrated power switch when chip enter low power modes: + * - \b true SPC asserts an output pin at low-power entry to power-gate the switch; + * - \b false SPC does not assert an output pin at low-power entry to power-gate the switch. + * @param wakeupUngate Enables the switch after wake-up from low power modes: + * - \b true SPC asserts an output pin at low-power exit to power-ungate the switch; + * - \b false SPC does not assert an output pin at low-power exit to power-ungate the switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchAutomatically(SPC_Type *base, bool sleepGate, bool wakeupUngate) +{ + uint32_t tmp32 = ((base->CFG) & ~(SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK)); + + tmp32 |= SPC_CFG_INTG_PWSWTCH_SLEEP_EN(sleepGate) | SPC_CFG_INTG_PWSWTCH_WKUP_EN(wakeupUngate); + + base->CFG = tmp32; +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_CFG_REG */ + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @name VDD Core Glitch Detector Control APIs + * @{ + */ + +/*! + * @brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * @param base SPC peripheral base address. + * @param config Pointer to the structure in type of @ref spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config); + +/*! + * @brief Checks selected 4-bit glitch ripple counter's output. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + * + * @retval true The selected ripple counter output is 1, will generate interrupt or reset based on settings. + * @retval false The selected ripple counter output is 0. + */ + +static inline bool SPC_CheckGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) == + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter))); +} + +/*! + * @brief Clears output of selected glitch ripple counter. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + */ +static inline void SPC_ClearGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter)); +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are allowed. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC &= ~SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief Checks if SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * + * @param base SPC peripheral base address. + * + * @retval true SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * @retval false SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is not writable. + */ +static inline bool SPC_CheckVddCoreVoltageGlitchResetControlState(SPC_Type *base) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif + +/*! + * @name SRAM Control APIs + * @{ + */ + +/*! + * @brief Set SRAM operate voltage. + * + * @param base SPC peripheral base address. + * @param config The pointer to @ref spc_sram_voltage_config_t, specifies the configuration of sram voltage. + */ +void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config); + +/*! @} */ + +/*! + * @name Active Mode configuration + * @{ + */ + +/*! + * @brief Gets the Bandgap mode in Active mode. + * + * @param base SPC peripheral base address. + * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration. + */ +static inline spc_bandgap_mode_t SPC_GetActiveModeBandgapMode(SPC_Type *base) +{ + return (spc_bandgap_mode_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_BGMODE_MASK) >> + SPC_ACTIVE_CFG_BGMODE_SHIFT); +} + +/*! + * @brief Gets all voltage detectors status in Active mode. + * + * @param base SPC peripheral base address. + * @return All voltage detectors status in Active mode. + */ +static inline uint32_t SPC_GetActiveModeVoltageDetectStatus(SPC_Type *base) +{ + uint32_t state; + state = base->ACTIVE_CFG & + ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_ACTIVE_CFG_IO_HVDE_MASK | SPC_ACTIVE_CFG_IO_LVDE_MASK | + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_ACTIVE_CFG_SYS_HVDE_MASK | SPC_ACTIVE_CFG_SYS_LVDE_MASK | SPC_ACTIVE_CFG_CORE_LVDE_MASK + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_ACTIVE_CFG_CORE_HVDE_MASK + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); + return state; +} + +/*! + * @brief Configs Bandgap mode in Active mode. + * + * @note To disable bandgap in Active mode: + * 1. Disable all LVD's and HVD's in active mode; + * 2. Disable Glitch detect; + * 3. Configure LDO's and DCDC to low drive strength in active mode; + * 4. Invoke this function to disable bandgap in active mode; + * otherwise the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * @param base SPC peripheral base address. + * @param mode The Bandgap mode be selected. + * + * @retval #kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode. + * @retval #kStatus_Success Config Bandgap mode in Active power mode successful. + */ +status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) +/*! + * @brief Enables/Disable the CMP Bandgap Buffer in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference voltage to CMP. + * false - Disable Buffer Stored Reference voltage to CMP. + */ +static inline void SPC_EnableActiveModeCMPBandgapBuffer(SPC_Type *base, bool enable) +{ + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_LPBUFF_EN_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_LPBUFF_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +/*! + * @brief Sets the delay when the regulators change voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @param delay The number of SPC timer clock cycles. + */ +static inline void SPC_SetActiveModeVoltageTrimDelay(SPC_Type *base, uint16_t delay) +{ + base->ACTIVE_VDELAY = SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(delay); +} + +/*! + * @brief Configs all settings of regulators in Active mode at a time. + * + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in active mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unknown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_active_mode_regulators_config_t structure. + * + * @retval #kStatus_Success Config regulators in Active power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong Based on input setting, bandgap can not be disabled. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage due to + * System VDD HVD is not disabled. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function. + * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. + */ +status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config); + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief Disables/Enables VDD Core Glitch Detect in Active mode. + * + * @note State of glitch detect disable feature will be ignored if bandgap is disabled and + * glitch detect hardware will be forced to OFF state. + * + * @param base SPC peripheral base address. + * @param disable Used to disable/enable VDD Core Glitch detect feature. + * - \b true Disable VDD Core Low Voltage detect; + * - \b false Enable VDD Core Low Voltage detect. + */ +static inline void SPC_DisableActiveModeVddCoreGlitchDetect(SPC_Type *base, bool disable) +{ + if (disable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + } +} + +/*! + * @brief Check if Glitch detect hardware is enabled in active mode. + * + * @param base SPC peripheral base address. + * @return Indicate if Glitch detector is enabled. + */ +static inline bool SPC_CheckActiveModeVddCoreGlitchDetectEnabled(SPC_Type *base) +{ + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return true; + } + else + { + return false; + } +} + +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ + +/*! + * @brief Enables analog modules in active mode. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to enable in active mode, should be the OR'ed value + * of @ref spc_analog_module_control. + */ +static inline void SPC_EnableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->ACTIVE_CFG1 |= SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Disables analog modules in active mode. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to disable in active mode, should be the OR'ed value + * of @ref spc_analog_module_control. + */ +static inline void SPC_DisableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->ACTIVE_CFG1 &= ~SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Gets enabled analog modules that enabled in active mode. + * + * @param base SPC peripheral base address. + * + * @return The mask of enabled analog modules that enabled in active mode. + */ +static inline uint32_t SPC_GetActiveModeEnabledAnalogModules(SPC_Type *base) +{ + return base->ACTIVE_CFG1; +} + +/*! @} */ + +/*! + * @name Low Power mode configuration + * @{ + */ + +/*! + * @brief Gets the Bandgap mode in Low Power mode. + * + * @param base SPC peripheral base address. + * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration. + */ +static inline spc_bandgap_mode_t SPC_GetLowPowerModeBandgapMode(SPC_Type *base) +{ + return (spc_bandgap_mode_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_BGMODE_MASK) >> SPC_LP_CFG_BGMODE_SHIFT); +} + +/*! + * @brief Gets the status of all voltage detectors in Low Power mode. + * + * @param base SPC peripheral base address. + * @return The status of all voltage detectors in low power mode. + */ +static inline uint32_t SPC_GetLowPowerModeVoltageDetectStatus(SPC_Type *base) +{ + uint32_t state; + state = base->LP_CFG & ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_LP_CFG_IO_HVDE_MASK | SPC_LP_CFG_IO_LVDE_MASK | + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_LP_CFG_SYS_HVDE_MASK | SPC_LP_CFG_SYS_LVDE_MASK | SPC_LP_CFG_CORE_LVDE_MASK + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_LP_CFG_CORE_HVDE_MASK + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); + return state; +} + +/*! + * @brief Enables/Disables Low Power IREF in low power modes. + * + * This function enables/disables Low Power IREF. Low Power IREF can only get + * disabled in Deep power down mode. In other low power modes, the Low Power IREF + * is always enabled. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Low Power IREF. + * true - Enable Low Power IREF for Low Power modes. + * false - Disable Low Power IREF for Deep Power Down mode. + */ +static inline void SPC_EnableLowPowerModeLowPowerIREF(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LP_IREFEN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LP_IREFEN_MASK; + } +} + +/*! + * @brief Configs Bandgap mode in Low Power mode. + * + * @note To disable Bandgap in Low-power mode: + * 1. Disable all LVD's ad HVD's in low power mode; + * 2. Disable Glitch detect in low power mode; + * 3. Configure LDO's and DCDC to low drive strength in low power mode; + * 4. Disable bandgap in low power mode; + * Otherwise, the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * @param base SPC peripheral base address. + * @param mode The Bandgap mode be selected. + * + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * @retval #kStatus_Success Config Bandgap mode in Low Power power mode successful. + */ +status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) && FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) +/*! + * @brief Enables/disables SRAM_LDO deep power low power IREF. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable low power IREF : + * - \b true: Low Power IREF is enabled ; + * - \b false: Low Power IREF is disabled for power saving. + */ +static inline void SPC_EnableSRAMLdOLowPowerModeIREF(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) +/*! + * @brief Enables/Disables CMP Bandgap Buffer. + * + * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off + * in Deep Power Down mode. + * + * @deprecated No longer used, please use SPC_EnableLowPowerModeCMPBandgapBuffer as instead. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference Voltage to CMP. + * false - Disable Buffer Stored Reference Voltage to CMP. + */ +static inline void SPC_EnableLowPowerModeCMPBandgapBufferMode(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK; + } +} + +/*! + * @brief Enables/Disables CMP Bandgap Buffer. + * + * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off + * in Deep Power Down mode. + * + * @deprecated No longer used. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference Voltage to CMP. + * false - Disable Buffer Stored Reference Voltage to CMP. + */ +static inline void SPC_EnableLowPowerModeCMPBandgapBuffer(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) +/*! + * @brief Enables/Disables CORE VDD IVS(Internal Voltage Scaling) in power down modes. + * + * This function gates CORE VDD IVS. When enabled, the IVS regulator will scale the + * external input CORE VDD to a lower voltage level to reduce internal leakage. + * IVS is invalid in Sleep or Deep power down mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IVS. + * true - enable CORE VDD IVS in Power Down mode. + * false - disable CORE VDD IVS in Power Down mode. + */ +static inline void SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_COREVDD_IVS_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_COREVDD_IVS_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + +/*! + * @brief Sets the delay when exit the low power modes. + * + * @param base SPC peripheral base address. + * @param delay The number of SPC timer clock cycles that the SPC waits on exit from low power modes. + */ +static inline void SPC_SetLowPowerWakeUpDelay(SPC_Type *base, uint16_t delay) +{ + base->LPWKUP_DELAY = SPC_LPWKUP_DELAY_LPWKUP_DELAY(delay); +} + +/*! + * @brief Configs all settings of regulators in Low power mode at a time. + * + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in low power mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unknown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_lowpower_mode_regulators_config_t structure. + * @retval #kStatus_Success Config regulators in Low power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. + */ +status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config); + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief Disable/Enable VDD Core Glitch Detect in low power mode. + * + * @note State of glitch detect disable feature will be ignored if bandgap is disabled and + * glitch detect hardware will be forced to OFF state. + * + * @param base SPC peripheral base address. + * @param disable Used to disable/enable VDD Core Glitch detect feature. + * - \b true Disable VDD Core Low Voltage detect; + * - \b false Enable VDD Core Low Voltage detect. + */ +static inline void SPC_DisableLowPowerModeVddCoreGlitchDetect(SPC_Type *base, bool disable) +{ + if (disable) + { + base->LP_CFG |= SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK; + } +} + +/*! + * @brief Check if Glitch detect hardware is enabled in low power mode. + * + * @param base SPC peripheral base address. + * @return Indicate if Glitch detector is enabled. + */ +static inline bool SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(SPC_Type *base) +{ + if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return true; + } + else + { + return false; + } +} +#endif + +/*! + * @brief Enables analog modules in low power modes. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to enable in low power modes, should be OR'ed value + of @ref spc_analog_module_control. + */ +static inline void SPC_EnableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->LP_CFG1 |= SPC_LP_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Disables analog modules in low power modes. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to disable in low power modes, should be OR'ed value + of @ref spc_analog_module_control. + */ +static inline void SPC_DisableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->LP_CFG1 &= ~SPC_LP_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Gets enabled analog modules that enabled in low power modes. + * + * @param base SPC peripheral base address. + * + * @return The mask of enabled analog modules that enabled in low power modes. + */ +static inline uint32_t SPC_GetLowPowerModeEnabledAnalogModules(SPC_Type *base) +{ + return base->LP_CFG1; +} + +/*! @} */ + +/*! + * @name Voltage Detect Status + * @{ + */ +/*! + * @brief Get Voltage Detect Status Flags. + * + * @param base SPC peripheral base address. + * @return Voltage Detect Status Flags. See @ref _spc_voltage_detect_flags for details. + */ +static inline uint8_t SPC_GetVoltageDetectStatusFlag(SPC_Type *base) +{ + return (uint8_t)(base->VD_STAT); +} + +/*! + * @brief Clear Voltage Detect Status Flags. + * + * @param base SPC peripheral base address. + * @param mask The mask of the voltage detect status flags. See @ref _spc_voltage_detect_flags for details. + */ +static inline void SPC_ClearVoltageDetectStatusFlag(SPC_Type *base, uint8_t mask) +{ + base->VD_STAT |= mask; +} + +/*! @} */ + +/*! + * @name Voltage Detect configuration for Core voltage domain. + * @{ + */ + +/*! + * @brief Configs CORE voltage detect options. + * + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_core_voltage_detect_config_t structure. + */ +void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config); + +/*! + * @brief Locks Core voltage detect reset setting. + * + * This function locks core voltage detect reset setting. After invoking this function + * any configuration of Core voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockCoreVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_CORE_CFG |= SPC_VD_CORE_CFG_LOCK_MASK; +} + +/*! + * @brief Unlocks Core voltage detect reset setting. + * + * This function unlocks core voltage detect reset setting. If locks the Core + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockCoreVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_CORE_CFG &= ~SPC_VD_CORE_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the Core Low Voltage Detector in Active mode. + * + * @note If the CORE_LDO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core LVD. + * true - Enable Core Low voltage detector in active mode. + * false - Disable Core Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the Core Low Voltage Detector in Low Power mode. + * + * This function enables/disables the Core Low Voltage Detector. + * If enabled the Core Low Voltage detector. The Bandgap mode in + * low power mode must be programmed so that Bandgap is enabled. + * + * @note If the CORE_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core Low voltage detector in low power mode. + * false - Disable Core Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) +/*! + * @brief Enables/Disables the Core High Voltage Detector in Active mode. + * + * @note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in active mode. + * false - Disable Core High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the Core High Voltage Detector in Low Power mode. + * + * This function enables/disables the Core High Voltage Detector. + * If enabled the Core High Voltage detector. The Bandgap mode in + * low power mode must be programmed so that Bandgap is enabled. + * + * @note If the CORE_LDO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in low power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in low power mode. + * false - Disable Core High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/*! @} */ + +/*! + * @name Voltage detect configuration for System Voltage domain + * @{ + */ +/*! + * @brief Set system VDD Low-voltage level selection. + * + * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level + * must be done after disabling the System VDD low voltage reset and interrupt. + * + * @deprecated In latest RM, reserved for all devices, will removed in next release. + * + * @param base SPC peripheral base address. + * @param level System VDD Low-Voltage level selection. + */ +void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level); + +/*! + * @brief Configs SYS voltage detect options. + * + * This function config SYS voltage detect options. + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_system_voltage_detect_config_t structure. + */ +void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config); + +/*! + * @brief Lock System voltage detect reset setting. + * + * This function locks system voltage detect reset setting. After invoking this function + * any configuration of System Voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockSystemVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_SYS_CFG |= SPC_VD_SYS_CFG_LOCK_MASK; +} + +/*! + * @brief Unlock System voltage detect reset setting. + * + * This function unlocks system voltage detect reset setting. If locks the System + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockSystemVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_SYS_CFG &= ~SPC_VD_SYS_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the System High Voltage Detector in Active mode. + * + * @note If the System_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in active mode. + * false - Disable System High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable System High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disable the System Low Voltage Detector in Active mode. + * + * @note If the System_LDO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System LVD. + * true - Enable System Low voltage detector in active mode. + * false - Disable System Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable the System Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the System High Voltage Detector in Low Power mode. + * + * @note If the System_LDO high voltage detect is enabled in Low Power mode, please note + * that the bandgap must be enabled and the drive strength of each regulator must + * not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in low power mode. + * false - Disable System High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable System High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the System Low Voltage Detector in Low Power mode. + * + * @note If the System_LDO low voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System Low voltage detector in low power mode. + * false - Disable System Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enables System Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable); + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * @name Voltage detect configuration for IO voltage domain + * @{ + */ +/*! + * @brief Set IO VDD Low-Voltage level selection. + * + * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level + * must be done after disabling the IO VDD low voltage reset and interrupt. + * + * @param base SPC peripheral base address. + * @param level IO VDD Low-voltage level selection. + */ +void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level); + +/*! + * @brief Configs IO voltage detect options. + * + * This function config IO voltage detect options. + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_voltage_detect_config_t structure. + */ +void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config); + +/*! + * @brief Lock IO Voltage detect reset setting. + * + * This function locks IO voltage detect reset setting. After invoking this function + * any configuration of system voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockIOVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_IO_CFG |= SPC_VD_IO_CFG_LOCK_MASK; +} + +/*! + * @brief Unlock IO voltage detect reset setting. + * + * This function unlocks IO voltage detect reset setting. If locks the IO + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockIOVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_IO_CFG &= ~SPC_VD_IO_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the IO High Voltage Detector in Active mode. + * + * @note If the IO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in active mode. + * false - Disable IO High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable IO High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO Low Voltage Detector in Active mode. + * + * @note If the IO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in active mode. + * false - Disable IO Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable IO Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO High Voltage Detector in Low Power mode. + * + * @note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in low power mode. + * false - Disable IO High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable IO High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO Low Voltage Detector in Low Power mode. + * + * @note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in low power mode. + * false - Disable IO Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable IO Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable); + +/*! @} */ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * @name External Voltage domains configuration + * @{ + */ +/*! + * @brief Configs external voltage domains + * + * This function configs external voltage domains isolation. + * + * @param base SPC peripheral base address. + * @param lowPowerIsoMask The mask of external domains isolate enable during low power mode. Please read the Reference + * Manual for the Bitmap. + * @param IsoMask The mask of external domains isolate. Please read the Reference Manual for the Bitmap. + */ +void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask); + +/*! + * @brief Gets External Domains status. + * + * @param base SPC peripheral base address. + * @return The status of each external domain. + */ +static inline uint8_t SPC_GetExternalDomainsStatus(SPC_Type *base) +{ + return (uint8_t)(base->EVD_CFG >> SPC_EVD_CFG_REG_EVDSTAT_SHIFT); +} + +/*! @} */ + +/*! + * @name Low Level APIs To Set CORE LDO Regulator + * @{ + */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) && FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) +/*! + * @brief Enable/Disable Core LDO regulator. + * + * @note The CORE LDO enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CORE LDO Regulator. + * true - Enable CORE LDO Regulator. + * false - Disable CORE LDO Regulator. + */ +static inline void SPC_EnableCoreLDORegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_CORELDO_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If CORE_LDO is disabled, all RAMs data will powered off. + */ + base->CNTRL &= ~SPC_CNTRL_CORELDO_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) && \ + FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) +/*! + * @brief Enable/Disable the CORE LDO Regulator pull down in Deep Power Down. + * + * @note This function only useful when enabled the CORE LDO Regulator. + * + * @param base SPC peripheral base address. + * @param pulldown Enable/Disable CORE LDO pulldown in Deep Power Down mode. + * true - CORE LDO Regulator will discharge in Deep Power Down mode. + * false - CORE LDO Regulator will not discharge in Deep Power Down mode. + */ +static inline void SPC_PullDownCoreLDORegulator(SPC_Type *base, bool pulldown) +{ + if (pulldown) + { + base->CORELDO_CFG &= ~SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK; + } + else + { + base->CORELDO_CFG |= SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT */ + +/*! + * @brief Configs Core LDO Regulator in Active mode. + * + * @note The bandgap must be enabled before invoking this function. + * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_core_ldo_option_t structure. + * + * @retval kStatus_Success Config Core LDO regulator in Active power mode successful. + * @retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function. + * @retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength, + * all LVDs/HVDs must be disabled before invoking this function. + */ +status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option); + +/*! + * @brief Set Core LDO Regulator Voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @note In active mode, the Core LDO voltage level should only be changed when the + * Core LDO is in normal drive strength. + * + * @note Update Core LDO voltage level will set Busy flag, + * this function return only when busy flag is cleared by hardware + * + * @retval kStatus_SPC_CORELDOVoltageSetFail The drive strength of Core LDO is not normal. + * @retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets CORE LDO Regulator Voltage level. + * + * This function returns the voltage level of CORE LDO Regulator in Active mode. + * + * @param base SPC peripheral base address. + * @return Voltage level of CORE LDO in type of @ref spc_core_ldo_voltage_level_t enumeration. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetActiveModeCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return (spc_core_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT); +} + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * @retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * @retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return Drive Strength of CORE LDO regulator in Active mode, please refer to @ref spc_core_ldo_drive_strength_t. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetActiveModeCoreLDODriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT); +} +#endif /* defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +/*! + * @brief Configs CORE LDO Regulator in low power mode + * + * This function configs CORE LDO Regulator in Low Power mode. + * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage + * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap + * must be programmed to select bandgap enabled. + * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE + * LDO Drive Strength set as Normal. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_lowpower_mode_core_ldo_option_t structure. + * + * @retval #kStatus_Success Config Core LDO regulator in power mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option); + +/*! + * @brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If CORE LDO's drive strength is set to Normal, the CORE LDO VDD regulator voltage in active mode and low power + * mode must be same. + * @note Voltage level for the CORE LDO in low power mode can only be changed when the CORE LDO Drive Strength set as + * Normal. + * + * @param base SPC peripheral base address. + * @param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @retval #kStatus_SPC_CORELDOVoltageWrong Voltage level in active mode and low power mode is not same. + * @retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + * @retval #kStatus_SPC_CORELDOVoltageSetFail Fail to update voltage level because drive strength is incorrect. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets the CORE LDO VDD Regulator Voltage Level for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO VDD Regulator's voltage level. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetLowPowerCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return ((spc_core_ldo_voltage_level_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)); +} + +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * @retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Drive Strength for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO's VDD Drive Strength. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetLowPowerCoreLDOVDDDriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) >> + SPC_LP_CFG_CORELDO_VDD_DS_SHIFT); +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @name Low Level APIs To Set System LDO Regulator + * @{ + */ + +/*! + * @brief Enable/Disable System LDO regulator. + * + * @note The SYSTEM LDO enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System LDO Regulator. + * true - Enable System LDO Regulator. + * false - Disable System LDO Regulator. + */ +static inline void SPC_EnableSystemLDORegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_SYSLDO_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If SYSTEM_LDO is disabled, may cause some unexpected issues. + */ + base->CNTRL &= ~SPC_CNTRL_SYSLDO_EN_MASK; + } +} + +/*! + * @brief Enable/Disable current sink feature of System LDO Regulator. + * + * @param base SPC peripheral base address. + * @param sink Enable/Disable current sink feature. + * true - Enable current sink feature of System LDO Regulator. + * false - Disable current sink feature of System LDO Regulator. + */ +static inline void SPC_EnableSystemLDOSinkFeature(SPC_Type *base, bool sink) +{ + if (sink) + { + base->SYSLDO_CFG |= SPC_SYSLDO_CFG_ISINKEN_MASK; + } + else + { + base->SYSLDO_CFG &= ~SPC_SYSLDO_CFG_ISINKEN_MASK; + } +} + +/*! + * @brief Configs System LDO VDD Regulator in Active mode. + * + * @note If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed + * to a value that enables the bandgap. + * @note If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will + * be ignored. + * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD + * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal. + * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be + * disabled. Otherwise it will be fail to regulator to Over Drive Voltage. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_sys_ldo_option_t structure. + * + * @retval #kStatus_Success Config System LDO regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive + * voltage. + * @retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be + * ignored. + */ +status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option); + +/*! + * @brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifying + * overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Get System LDO Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO Regulator voltage level in Active mode, please refer to @ref spc_sys_ldo_voltage_level_t. + */ +static inline spc_sys_ldo_voltage_level_t SPC_GetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_sys_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT); +} + +/*! + * @brief Set System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); + +/*! + * @brief Get System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Active mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT); +} + +/*! + * @brief Configs System LDO regulator in low power modes. + * + * This function configs System LDO regulator in low power modes. + * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power + * mode must be programmed to a value that enables the Bandgap. + * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration + * to set System LDO Regulator drive strength as Low will be ignored. + * + * @param base SPC peripheral base address. + * @param option Pointer to spc_lowpower_mode_sys_ldo_option_t structure. + * + * @retval #kStatus_Success Config System LDO regulator in Low Power Mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option); + +/*! + * @brief Set System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); + +/*! + * @brief Get System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Low Power Mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) >> + SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT); +} +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @name Low Level APIs To Set DCDC Regulator + * @{ + */ + +/*! + * @brief Enable/Disable DCDC Regulator. + * + * @note The DCDC enable bit is write-once, settings only reset after a POR, LVD, or HVD event. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable DCDC Regulator. + * true - Enable DCDC Regulator. + * false - Disable DCDC Regulator. + */ +static inline void SPC_EnableDCDCRegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_DCDC_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If DCDC is disabled, all RAMs data will powered off. + */ + base->CNTRL &= ~SPC_CNTRL_DCDC_EN_MASK; + } +} + +/*! + * @brief Config DCDC Burst options + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_dcdc_burst_config_t structure. + */ +void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config); + +/*! + * @brief Trigger a software burst request to DCDC. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_TriggerDCDCBurstRequest(SPC_Type *base) +{ + /* Blocking until previous DCDC burst completed. */ + while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL) + { + } + + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK; +} + +/*! + * @brief Check if burst acknowledge flag is asserted. + * + * @param base SPC peripheral base address. + * + * @retval false DCDC burst not complete. + * @retval true DCDC burst complete. + */ +static inline bool SPC_CheckDCDCBurstAck(SPC_Type *base) +{ + return ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) != 0UL); +} + +/*! + * @brief Clear DCDC busrt acknowledge flag. + * + * @param base SPC periphral base address. + */ +static inline void SPC_ClearDCDCBurstAckFlag(SPC_Type *base) +{ + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; +} + +/*! + * @brief Set the count value of the reference clock to configure the period of DCDC not active. + * + * @note This function is only useful when DCDC's drive strength is set as pulse refresh. + * @note The pulse duration(time between on and off) is: reference clock period * (count + 2). + * + * @param base SPC peripheral base address. + * @param count The count value, 16 bit width. + */ +void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN) && FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN) +/*! + * @brief Enable a bleed resistor to discharge DCDC output when DCDC is disabled. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable bleed resistor. + */ +static inline void SPC_EnableDCDCBleedResistor(SPC_Type *base, bool enable) +{ + if (enable) + { + base->DCDC_CFG |= SPC_DCDC_CFG_BLEED_EN_MASK; + } + else + { + base->DCDC_CFG &= ~SPC_DCDC_CFG_BLEED_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN */ + +/*! + * @brief Configs DCDC_CORE Regulator in Active mode. + * + * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_dcdc_option_t structure. + * + * @retval #kStatus_Success Config DCDC regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option); + +/*! + * @brief Set DCDC_CORE Regulator voltage level in Active mode. + * + * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->ACTIVE_CFG = + (base->ACTIVE_CFG & (~SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_LVL(voltageLevel); +} + +/*! + * @brief Get DCDC_CORE Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)); +} + +/*! + * @brief Set DCDC_CORE Regulator drive strength in Active mode. + * + * @note To set DCDC drive strength as Normal, the bandgap must be enabled. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC_CORE regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC_CORE Regulator drive strength in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT)); +} + +/*! + * @brief Configs DCDC_CORE Regulator in Low power modes. + * + * @note If DCDC_CORE Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed + * to a value that enables the Bandgap. + * @note In Deep Power Down mode, DCDC regulator is always turned off. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_lowpower_mode_dcdc_option_t structure. + * + * @retval #kStatus_Success Config DCDC regulator in low power mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option); + +/*! + * @brief Set DCDC_CORE Regulator drive strength in Low power mode. + * + * @note To set drive strength as normal, the bandgap must be enabled. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Low power mode successfully. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC_CORE Regulator drive strength in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) >> + SPC_LP_CFG_DCDC_VDD_DS_SHIFT)); +} + +/*! + * @brief Set DCDC_CORE Regulator voltage level in Low power mode. + * + * @note To change DCDC level in Low-Power mode: + * 1. Configure LP_CFG[DCDC_VDD_LVL] to desired level; + * 2. Configure LP_CFG[DCDC_VDD_DS] to low driver strength; + * 3. Configure ACTIVE_CFG[DCDC_VDD_LVL] to same level programmed in #1. + * + * @note After invoking this function, the voltage level in active mode(wakeup from low power modes) also changed, + * if it is necessary, please invoke SPC_SetActiveModeDCDCRegulatorVoltageLevel() to change to desried voltage level. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->LP_CFG = (base->LP_CFG & (~SPC_LP_CFG_DCDC_VDD_LVL_MASK)) | SPC_LP_CFG_DCDC_VDD_LVL(voltageLevel); + (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, kSPC_DCDC_LowDriveStrength); + SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, voltageLevel); +} + +/*! + * @brief Get DCDC_CORE Regulator voltage level in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_LVL_MASK) >> + SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* FSL_SPC_H_ */ diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c index ce54097fe..2dfefeb92 100644 --- a/hw/bsp/mcx/family.c +++ b/hw/bsp/mcx/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "bsp/board_api.h" #include "fsl_device_registers.h" #include "fsl_gpio.h" @@ -56,9 +60,14 @@ void USB0_IRQHandler(void) { void board_init(void) { + BOARD_InitPins(); + BOARD_InitBootClocks(); + + #ifdef XTAL0_CLK_HZ CLOCK_SetupExtClocking(XTAL0_CLK_HZ); + #endif #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer @@ -80,15 +89,7 @@ void board_init(void) { board_led_write(0); #ifdef NEOPIXEL_PIN - // Neopixel - static uint32_t pixelData[NEOPIXEL_NUMBER]; - IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN); - - sctpix_init(NEOPIXEL_TYPE); - sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER); - sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010); - sctpix_show(); + // No neo pixel support yet #endif // Button @@ -99,9 +100,6 @@ void board_init(void) { #endif #ifdef UART_DEV - // UART -// IOCON_PinMuxSet(IOCON, UART_RX_PINMUX); -// IOCON_PinMuxSet(IOCON, UART_TX_PINMUX); // Enable UART when debug log is on board_uart_init_clock(); @@ -111,6 +109,7 @@ void board_init(void) { uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; uart_config.enableTx = true; uart_config.enableRx = true; + LPUART_Init(UART_DEV, &uart_config, 12000000u); #endif @@ -192,17 +191,6 @@ void board_init(void) { void board_led_write(bool state) { GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); - -#ifdef NEOPIXEL_PIN - if (state) { - sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010); - } else { - sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010); - } - sctpix_show(); -#endif } uint32_t board_button_read(void) { diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index 223afb9ec..f857ed31a 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -8,10 +8,13 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up if (MCU_VARIANT STREQUAL "MCXA153") - set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor") + set(CMAKE_SYSTEM_CPU cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor") set(FAMILY_MCUS MCXA15 CACHE INTERNAL "") +elseif (MCU_VARIANT STREQUAL "MCXA156") + set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") + set(FAMILY_MCUS MCXA15 CACHE INTERNAL "") elseif (MCU_VARIANT STREQUAL "MCXN947") - set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") + set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(FAMILY_MCUS MCXN9 CACHE INTERNAL "") else() message(FATAL_ERROR "MCU_VARIANT not supported") @@ -38,12 +41,14 @@ function(add_board_target BOARD_TARGET) endif() set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + add_library(${BOARD_TARGET} STATIC ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} # driver - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c + ${SDK_DIR}/drivers/gpio/fsl_gpio.c + ${SDK_DIR}/drivers/common/fsl_common_arm.c + ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc/fsl_spc.c # mcu ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c @@ -51,18 +56,27 @@ function(add_board_target BOARD_TARGET) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMSIS_DIR}/CMSIS/Core/Include + ${SDK_DIR}/drivers/gpio/ + ${SDK_DIR}/drivers/lpuart + ${SDK_DIR}/drivers/common + ${SDK_DIR}/drivers/port + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc ${SDK_DIR}/devices/${MCU_VARIANT} ${SDK_DIR}/devices/${MCU_VARIANT}/drivers ) if (${FAMILY_MCUS} STREQUAL "MCXN9") + target_sources(${BOARD_TARGET} PRIVATE - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c + ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c + ) + + target_include_directories(${BOARD_TARGET} PUBLIC + ${SDK_DIR}/drivers/lpflexcomm ) elseif(${FAMILY_MCUS} STREQUAL "MCXA15") - target_sources(${BOARD_TARGET} PRIVATE - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_spc.c - ) + + endif() update_board(${BOARD_TARGET}) @@ -110,21 +124,21 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source if (${FAMILY_MCUS} STREQUAL "MCXN9") - family_add_tinyusb(${TARGET} OPT_MCU_MCXN9 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MCXN9) elseif(${FAMILY_MCUS} STREQUAL "MCXA15") - family_add_tinyusb(${TARGET} OPT_MCU_MCXA15 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MCXA15) endif() - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS ${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c> ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk index 58149fb8d..a16f4b6c0 100644 --- a/hw/bsp/mcx/family.mk +++ b/hw/bsp/mcx/family.mk @@ -1,8 +1,6 @@ UF2_FAMILY_ID = 0x2abc77ec SDK_DIR = hw/mcu/nxp/mcux-sdk -DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5 - include $(TOP)/$(BOARD_PATH)/board.mk # Default to Highspeed PORT1 @@ -35,18 +33,19 @@ SRC_C += \ $(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \ + ${SDK_DIR}/drivers/gpio/fsl_gpio.c \ + ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c \ + ${SDK_DIR}/drivers/common/fsl_common_arm.c\ + hw/bsp/mcx/drivers/spc/fsl_spc.c # fsl_lpflexcomm for MCXN9 ifeq ($(MCU_VARIANT), MCXN947) - SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c + SRC_C += ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c endif # fsl_spc for MCXNA15 ifeq ($(MCU_VARIANT), MCXA153) - SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c + endif INC += \ @@ -54,5 +53,15 @@ INC += \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \ $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \ + $(TOP)/$(SDK_DIR)/drivers/ \ + $(TOP)/$(SDK_DIR)/drivers/lpuart \ + $(TOP)/$(SDK_DIR)/drivers/lpflexcomm \ + $(TOP)/$(SDK_DIR)/drivers/common\ + $(TOP)/$(SDK_DIR)/drivers/gpio\ + $(TOP)/$(SDK_DIR)/drivers/port\ + $(TOP)/hw/bsp/mcx/drivers/spc + + + SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.h b/hw/bsp/mm32/boards/mm32f327x_mb39/board.h index 3ac048cf1..ee0800030 100644 --- a/hw/bsp/mm32/boards/mm32f327x_mb39/board.h +++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: MM32F3273G9P MB-039 + url: https://www.mindmotion.com.cn/support/development_tools/evaluation_boards/evboard/mm32f3273g9p/ +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h index 2b3f54a60..522d494a8 100644 --- a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h +++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: DshanMCU Pitaya Lite with MM32F3273G8P + url: https://gitee.com/weidongshan/DshanMCU-Pitaya-c +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/mm32/family.c b/hw/bsp/mm32/family.c index f0fd6d334..979efb6ca 100644 --- a/hw/bsp/mm32/family.c +++ b/hw/bsp/mm32/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: MindMotion +*/ + #include "hal_conf.h" #include "mm32_device.h" diff --git a/hw/bsp/mm32/family.cmake b/hw/bsp/mm32/family.cmake index bf315acaa..0561a63a0 100644 --- a/hw/bsp/mm32/family.cmake +++ b/hw/bsp/mm32/family.cmake @@ -7,7 +7,7 @@ set(SDK_DIR ${TOP}/hw/mcu/mindmotion/mm32sdk/${MCU_VARIANT_UPPER}) set(CMSIS_5 ${TOP}/lib/CMSIS_5) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS MM32F327X CACHE INTERNAL "") @@ -87,15 +87,15 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MM32F327X ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_MM32F327X) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h b/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h index ccfe321c2..8fbe5cc49 100644 --- a/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h +++ b/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MSP430F5529 LaunchPad + url: https://www.ti.com/tool/MSP-EXP430F5529LP +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/msp430/family.c b/hw/bsp/msp430/family.c index 5bb3d3866..a45bd5f93 100644 --- a/hw/bsp/msp430/family.c +++ b/hw/bsp/msp430/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Texas Instruments +*/ + #include "bsp/board_api.h" #include "board.h" #include "msp430.h" diff --git a/hw/bsp/msp430/family.cmake b/hw/bsp/msp430/family.cmake index e0b4ed28a..d9b4bf770 100644 --- a/hw/bsp/msp430/family.cmake +++ b/hw/bsp/msp430/family.cmake @@ -6,41 +6,42 @@ set(SDK_DIR ${TOP}/hw/mcu/ti/msp430/msp430-gcc-support-files/include) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR msp430 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU msp430 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/msp430_${TOOLCHAIN}.cmake) set(FAMILY_MCUS MSP430x5xx CACHE INTERNAL "") - #------------------------------------ # BOARD_TARGET #------------------------------------ # only need to be built ONCE for all examples function(add_board_target BOARD_TARGET) - if (NOT TARGET ${BOARD_TARGET}) - add_library(${BOARD_TARGET} INTERFACE) - target_compile_definitions(${BOARD_TARGET} INTERFACE - CFG_TUD_ENDPOINT0_SIZE=8 - CFG_EXAMPLE_VIDEO_READONLY - CFG_EXAMPLE_MSC_READONLY - ) - target_include_directories(${BOARD_TARGET} INTERFACE - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${SDK_DIR} - ) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + add_library(${BOARD_TARGET} INTERFACE) + target_compile_definitions(${BOARD_TARGET} INTERFACE + CFG_TUD_ENDPOINT0_SIZE=8 + CFG_EXAMPLE_VIDEO_READONLY + CFG_EXAMPLE_MSC_READONLY + ) + target_include_directories(${BOARD_TARGET} INTERFACE + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${SDK_DIR} + ) - update_board(${BOARD_TARGET}) + update_board(${BOARD_TARGET}) - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} INTERFACE - "LINKER:--script=${LD_FILE_GNU}" - -L${SDK_DIR} - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${BOARD_TARGET} INTERFACE - "LINKER:--config=${LD_FILE_IAR}" - ) - endif () + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} INTERFACE + "LINKER:--script=${LD_FILE_GNU}" + -L${SDK_DIR} + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} INTERFACE + "LINKER:--config=${LD_FILE_IAR}" + ) endif () endfunction() @@ -69,14 +70,11 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MSP430x5xx ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_MSP430x5xx) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/msp430/family.mk b/hw/bsp/msp430/family.mk index 06508ab2c..c973d9dcd 100644 --- a/hw/bsp/msp430/family.mk +++ b/hw/bsp/msp430/family.mk @@ -1,5 +1,4 @@ CROSS_COMPILE = msp430-elf- -DEPS_SUBMODULES += hw/mcu/ti SKIP_NANOLIB = 1 SDK_DIR = hw/mcu/ti/msp430/msp430-gcc-support-files/include diff --git a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h index 3130d663b..6206bb247 100644 --- a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h +++ b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MSP432E401Y LaunchPad + url: https://www.ti.com/tool/MSP-EXP432E401Y +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c index d5ef7f930..9a3b48b66 100644 --- a/hw/bsp/msp432e4/family.c +++ b/hw/bsp/msp432e4/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Texas Instruments +*/ + #include "bsp/board_api.h" #include "board.h" #include "msp.h" diff --git a/hw/bsp/msp432e4/family.cmake b/hw/bsp/msp432e4/family.cmake index f06e0d4c9..f6939ecfe 100644 --- a/hw/bsp/msp432e4/family.cmake +++ b/hw/bsp/msp432e4/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS MSP432E4 CACHE INTERNAL "") @@ -85,15 +85,14 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MSP432E4 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_MSP432E4) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ${TOP}/src/portable/mentor/musb/hcd_musb.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/nrf/boards/adafruit_clue/board.h b/hw/bsp/nrf/boards/adafruit_clue/board.h index 8d6df786e..a5d90f608 100644 --- a/hw/bsp/nrf/boards/adafruit_clue/board.h +++ b/hw/bsp/nrf/boards/adafruit_clue/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit CLUE + url: https://www.adafruit.com/product/4500 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h index 00fa8d8ea..6e6a079ab 100644 --- a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h +++ b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Arduino Nano 33 BLE + url: https://store.arduino.cc/arduino-nano-33-ble +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h index 3dd354efa..4cdac5f9f 100644 --- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h +++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Circuit Playground Bluefruit + url: https://www.adafruit.com/product/4333 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h index 3d59516d8..bfbb98677 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h +++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather nRF52840 Express + url: https://www.adafruit.com/product/4062 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h index 605deea24..288a1b52e 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h +++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather nRF52840 Sense + url: https://www.adafruit.com/product/4516 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h index 33c370f53..5f065eec0 100644 --- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h +++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit ItsyBitsy nRF52840 Express + url: https://www.adafruit.com/product/4481 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake index cc370aac8..85314f3bc 100644 --- a/hw/bsp/nrf/boards/pca10056/board.cmake +++ b/hw/bsp/nrf/boards/pca10056/board.cmake @@ -2,3 +2,9 @@ set(MCU_VARIANT nrf52840) function(update_board TARGET) endfunction() + +#board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") +#include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +#include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +#include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +#include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h index 24d3faa65..ec632e769 100644 --- a/hw/bsp/nrf/boards/pca10056/board.h +++ b/hw/bsp/nrf/boards/pca10056/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Nordic nRF52840DK + url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/pca10059/board.h b/hw/bsp/nrf/boards/pca10059/board.h index ea3f4030d..3b95481ad 100644 --- a/hw/bsp/nrf/boards/pca10059/board.h +++ b/hw/bsp/nrf/boards/pca10059/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Nordic nRF52840 Dongle + url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake index 95dd30969..6d183dde6 100644 --- a/hw/bsp/nrf/boards/pca10095/board.cmake +++ b/hw/bsp/nrf/boards/pca10095/board.cmake @@ -2,6 +2,6 @@ set(MCU_VARIANT nrf5340_application) function(update_board TARGET) target_sources(${TARGET} PRIVATE - ${NRFX_DIR}/drivers/src/nrfx_usbreg.c + ${NRFX_PATH}/drivers/src/nrfx_usbreg.c ) endfunction() diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h index 846c2ee5b..1c7981049 100644 --- a/hw/bsp/nrf/boards/pca10095/board.h +++ b/hw/bsp/nrf/boards/pca10095/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Nordic nRF5340 DK + url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF5340-DK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/pca10100/board.h b/hw/bsp/nrf/boards/pca10100/board.h index 2b2579732..8aca6dce9 100644 --- a/hw/bsp/nrf/boards/pca10100/board.h +++ b/hw/bsp/nrf/boards/pca10100/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Nordic nRF52833 DK + url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 885910f9a..298ca2302 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Nordic Semiconductor +*/ + #include "bsp/board_api.h" #include "board.h" @@ -40,10 +44,10 @@ #include "nrfx.h" #include "hal/nrf_gpio.h" -#include "drivers/include/nrfx_gpiote.h" -#include "drivers/include/nrfx_power.h" -#include "drivers/include/nrfx_uarte.h" -#include "drivers/include/nrfx_spim.h" +#include "nrfx_gpiote.h" +#include "nrfx_power.h" +#include "nrfx_uarte.h" +#include "nrfx_spim.h" #ifdef SOFTDEVICE_PRESENT #include "nrf_sdm.h" @@ -133,8 +137,20 @@ void board_init(void) { // Button nrf_gpio_cfg_input(BUTTON_PIN, NRF_GPIO_PIN_PULLUP); +#if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_ZEPHYR + #ifdef CONFIG_HAS_HW_NRF_USBREG + // IRQ_CONNECT(USBREGULATOR_IRQn, DT_IRQ(DT_INST(0, nordic_nrf_clock), priority), nrfx_isr, nrfx_usbreg_irq_handler, 0); + // irq_enable(USBREGULATOR_IRQn); + #endif + + /* USB device controller access from devicetree */ + #define DT_DRV_COMPAT nordic_nrf_usbd + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), nrfx_isr, USBD_IRQHandler, 0); + irq_enable(DT_INST_IRQN(0)); +#endif // UART #if NRFX_VER <= 2 @@ -167,7 +183,7 @@ void board_init(void) { }; #endif - nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //uart_handler); + nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //------------- USB -------------// #if CFG_TUD_ENABLED @@ -211,8 +227,12 @@ void board_init(void) { #endif } - if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED); - if ( usb_reg & OUTPUTRDY_Msk ) tusb_hal_nrf_power_event(USB_EVT_READY); + if ( usb_reg & VBUSDETECT_Msk ) { + tusb_hal_nrf_power_event(USB_EVT_DETECTED); + } + if ( usb_reg & OUTPUTRDY_Msk ) { + tusb_hal_nrf_power_event(USB_EVT_READY); + } #endif #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 @@ -224,7 +244,6 @@ void board_init(void) { //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ - void board_led_write(bool state) { nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); } diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 9e86374dc..7d0a9f6de 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -1,17 +1,20 @@ include_guard() -set(NRFX_DIR ${TOP}/hw/mcu/nordic/nrfx) +set(NRFX_PATH ${TOP}/hw/mcu/nordic/nrfx) set(CMSIS_DIR ${TOP}/lib/CMSIS_5) -# include board specific -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) +# include board specific, for zephyr BOARD_ALIAS may be used instead +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake OPTIONAL RESULT_VARIABLE board_cmake_included) +if (NOT board_cmake_included) + include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD_ALIAS}/board.cmake) +endif () # toolchain set up if (MCU_VARIANT STREQUAL "nrf5340_application") - set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") + set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(JLINK_DEVICE nrf5340_xxaa_app) else () - set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") + set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(JLINK_DEVICE ${MCU_VARIANT}_xxaa) endif () @@ -19,7 +22,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS NRF5X CACHE INTERNAL "") - #------------------------------------ # BOARD_TARGET #------------------------------------ @@ -40,18 +42,18 @@ function(add_board_target BOARD_TARGET) endif () if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID}) - set(STARTUP_FILE_GNU ${NRFX_DIR}/mdk/gcc_startup_${MCU_VARIANT}.S) + set(STARTUP_FILE_GNU ${NRFX_PATH}/mdk/gcc_startup_${MCU_VARIANT}.S) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) endif () add_library(${BOARD_TARGET} STATIC - ${NRFX_DIR}/helpers/nrfx_flag32_allocator.c - ${NRFX_DIR}/drivers/src/nrfx_gpiote.c - ${NRFX_DIR}/drivers/src/nrfx_power.c - ${NRFX_DIR}/drivers/src/nrfx_spim.c - ${NRFX_DIR}/drivers/src/nrfx_uarte.c - ${NRFX_DIR}/mdk/system_${MCU_VARIANT}.c - ${NRFX_DIR}/soc/nrfx_atomic.c + ${NRFX_PATH}/helpers/nrfx_flag32_allocator.c + ${NRFX_PATH}/drivers/src/nrfx_gpiote.c + ${NRFX_PATH}/drivers/src/nrfx_power.c + ${NRFX_PATH}/drivers/src/nrfx_spim.c + ${NRFX_PATH}/drivers/src/nrfx_uarte.c + ${NRFX_PATH}/mdk/system_${MCU_VARIANT}.c + ${NRFX_PATH}/soc/nrfx_atomic.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ) string(TOUPPER "${MCU_VARIANT_XXAA}" MCU_VARIANT_XXAA_UPPER) @@ -67,12 +69,10 @@ function(add_board_target BOARD_TARGET) endif () target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${NRFX_DIR} - ${NRFX_DIR}/mdk - ${NRFX_DIR}/hal - ${NRFX_DIR}/drivers/include - ${NRFX_DIR}/drivers/src + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/nrfx_config + ${NRFX_PATH} + ${NRFX_PATH}/mdk + ${NRFX_PATH}/drivers/include ${CMSIS_DIR}/CMSIS/Core/Include ) @@ -81,14 +81,14 @@ function(add_board_target BOARD_TARGET) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" - -L${NRFX_DIR}/mdk + -L${NRFX_PATH}/mdk --specs=nosys.specs --specs=nano.specs -nostartfiles ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" - -L${NRFX_DIR}/mdk + -L${NRFX_PATH}/mdk ) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${BOARD_TARGET} PUBLIC @@ -111,14 +111,17 @@ endfunction() function(family_configure_example TARGET RTOS) - family_configure_common(${TARGET} ${RTOS}) - # Board target - add_board_target(board_${BOARD}) + if (NOT RTOS STREQUAL zephyr) + add_board_target(board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + endif () + + family_configure_common(${TARGET} ${RTOS}) #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h - target_sources(${TARGET} PUBLIC + target_sources(${TARGET} PRIVATE # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c @@ -129,18 +132,18 @@ function(family_configure_example TARGET RTOS) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) + if (RTOS STREQUAL zephyr AND DEFINED BOARD_ALIAS AND NOT BOARD STREQUAL BOARD_ALIAS) + target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD_ALIAS}) + endif () # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_NRF5X) + target_sources(${TARGET} PRIVATE ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing +# family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) # family_flash_adafruit_nrfutil(${TARGET}) endfunction() diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk index b3c05e6db..a8acb1624 100644 --- a/hw/bsp/nrf/family.mk +++ b/hw/bsp/nrf/family.mk @@ -1,6 +1,6 @@ UF2_FAMILY_ID = 0xADA52840 -NRFX_DIR = hw/mcu/nordic/nrfx +NRFX_PATH = hw/mcu/nordic/nrfx include $(TOP)/$(BOARD_PATH)/board.mk @@ -28,31 +28,32 @@ CFLAGS_GCC += \ LDFLAGS_GCC += \ -nostartfiles \ --specs=nosys.specs --specs=nano.specs \ - -L$(TOP)/${NRFX_DIR}/mdk + -L$(TOP)/${NRFX_PATH}/mdk LDFLAGS_CLANG += \ - -L$(TOP)/${NRFX_DIR}/mdk \ + -L$(TOP)/${NRFX_PATH}/mdk \ SRC_C += \ src/portable/nordic/nrf5x/dcd_nrf5x.c \ - ${NRFX_DIR}/helpers/nrfx_flag32_allocator.c \ - ${NRFX_DIR}/drivers/src/nrfx_gpiote.c \ - ${NRFX_DIR}/drivers/src/nrfx_power.c \ - ${NRFX_DIR}/drivers/src/nrfx_spim.c \ - ${NRFX_DIR}/drivers/src/nrfx_uarte.c \ - ${NRFX_DIR}/mdk/system_$(MCU_VARIANT).c \ - ${NRFX_DIR}/soc/nrfx_atomic.c + ${NRFX_PATH}/helpers/nrfx_flag32_allocator.c \ + ${NRFX_PATH}/drivers/src/nrfx_gpiote.c \ + ${NRFX_PATH}/drivers/src/nrfx_power.c \ + ${NRFX_PATH}/drivers/src/nrfx_spim.c \ + ${NRFX_PATH}/drivers/src/nrfx_uarte.c \ + ${NRFX_PATH}/mdk/system_$(MCU_VARIANT).c \ + ${NRFX_PATH}/soc/nrfx_atomic.c INC += \ $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(FAMILY_PATH)/nrfx_config \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/${NRFX_DIR} \ - $(TOP)/${NRFX_DIR}/mdk \ - $(TOP)/${NRFX_DIR}/hal \ - $(TOP)/${NRFX_DIR}/drivers/include \ - $(TOP)/${NRFX_DIR}/drivers/src \ + $(TOP)/${NRFX_PATH} \ + $(TOP)/${NRFX_PATH}/mdk \ + $(TOP)/${NRFX_PATH}/hal \ + $(TOP)/${NRFX_PATH}/drivers/include \ + $(TOP)/${NRFX_PATH}/drivers/src \ -SRC_S += ${NRFX_DIR}/mdk/gcc_startup_$(MCU_VARIANT).S +SRC_S += ${NRFX_PATH}/mdk/gcc_startup_$(MCU_VARIANT).S ASFLAGS += -D__HEAP_SIZE=0 diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config/nrfx_config.h index fbec4192b..fbec4192b 100644 --- a/hw/bsp/nrf/nrfx_config.h +++ b/hw/bsp/nrf/nrfx_config/nrfx_config.h diff --git a/hw/bsp/nrf/nrfx_glue.h b/hw/bsp/nrf/nrfx_config/nrfx_glue.h index ef756c670..bc3b3689b 100644 --- a/hw/bsp/nrf/nrfx_glue.h +++ b/hw/bsp/nrf/nrfx_config/nrfx_glue.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2024, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -60,14 +62,14 @@ extern "C" { /** * @brief Macro for placing a runtime assertion. * - * @param expression Expression to evaluate. + * @param expression Expression to be evaluated. */ #define NRFX_ASSERT(expression) /** * @brief Macro for placing a compile time assertion. * - * @param expression Expression to evaluate. + * @param expression Expression to be evaluated. */ #define NRFX_STATIC_ASSERT(expression) @@ -76,8 +78,8 @@ extern "C" { /** * @brief Macro for setting the priority of a specific IRQ. * - * @param irq_number IRQ number. - * @param priority Priority to set. + * @param irq_number IRQ number. + * @param priority Priority to be set. */ #define NRFX_IRQ_PRIORITY_SET(irq_number, priority) _NRFX_IRQ_PRIORITY_SET(irq_number, priority) static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, @@ -158,14 +160,10 @@ static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) return (NVIC_GetPendingIRQ(irq_number) == 1); } -/** - * @brief Macro for entering into a critical section. - */ +/** @brief Macro for entering into a critical section. */ #define NRFX_CRITICAL_SECTION_ENTER() -/** - * @brief Macro for exiting from a critical section. - */ +/** @brief Macro for exiting from a critical section. */ #define NRFX_CRITICAL_SECTION_EXIT() //------------------------------------------------------------------------------ diff --git a/hw/bsp/nrf/nrfx_log.h b/hw/bsp/nrf/nrfx_config/nrfx_log.h index 3bc1b424e..3bc1b424e 100644 --- a/hw/bsp/nrf/nrfx_log.h +++ b/hw/bsp/nrf/nrfx_config/nrfx_log.h diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk index 161ff9041..06c47d544 100644 --- a/hw/bsp/nutiny_nuc121s/board.mk +++ b/hw/bsp/nutiny_nuc121s/board.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/nuvoton - CFLAGS += \ -flto \ -mthumb \ diff --git a/hw/bsp/nutiny_nuc125s/board.mk b/hw/bsp/nutiny_nuc125s/board.mk index 081764fd3..50b9d866a 100644 --- a/hw/bsp/nutiny_nuc125s/board.mk +++ b/hw/bsp/nutiny_nuc125s/board.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/nuvoton - CFLAGS += \ -flto \ -mthumb \ diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk index 2466b3a31..e87d1aad0 100644 --- a/hw/bsp/nutiny_nuc126v/board.mk +++ b/hw/bsp/nutiny_nuc126v/board.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/nuvoton - CFLAGS += \ -flto \ -mthumb \ diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk index b54895b58..d982bdc06 100644 --- a/hw/bsp/nutiny_sdk_nuc120/board.mk +++ b/hw/bsp/nutiny_sdk_nuc120/board.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/nuvoton - CFLAGS += \ -flto \ -mthumb \ diff --git a/hw/bsp/nutiny_sdk_nuc505/board.mk b/hw/bsp/nutiny_sdk_nuc505/board.mk index f3b389354..1dc8b244e 100644 --- a/hw/bsp/nutiny_sdk_nuc505/board.mk +++ b/hw/bsp/nutiny_sdk_nuc505/board.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/nuvoton - CFLAGS += \ -flto \ -mthumb \ diff --git a/hw/bsp/pic32mz/boards/olimex_emz64/board.h b/hw/bsp/pic32mz/boards/olimex_emz64/board.h new file mode 100644 index 000000000..7f42e024f --- /dev/null +++ b/hw/bsp/pic32mz/boards/olimex_emz64/board.h @@ -0,0 +1,43 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Olimex PIC32-EMZ64 + url: https://www.olimex.com/Products/PIC/Development/PIC32-EMZ64/open-source-hardware +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/pic32mz/boards/olimex_hmz144/board.h b/hw/bsp/pic32mz/boards/olimex_hmz144/board.h new file mode 100644 index 000000000..c9c07bf77 --- /dev/null +++ b/hw/bsp/pic32mz/boards/olimex_hmz144/board.h @@ -0,0 +1,43 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Olimex PIC32-HMZ144 + url: https://www.olimex.com/Products/PIC/Development/PIC32-HMZ144/open-source-hardware +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/pic32mz/family.c b/hw/bsp/pic32mz/family.c index 895e23899..da97f67a9 100644 --- a/hw/bsp/pic32mz/family.c +++ b/hw/bsp/pic32mz/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Microchip +*/ + #include <stdint.h> #include <stdbool.h> #include <xc.h> diff --git a/hw/bsp/ra/board_cfg.h b/hw/bsp/ra/board_cfg.h index baed46b5f..825f8cd32 100644 --- a/hw/bsp/ra/board_cfg.h +++ b/hw/bsp/ra/board_cfg.h @@ -1,45 +1,13 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2023 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - */ - -#ifndef _BOARD_CFG_H -#define _BOARD_CFG_H - +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ #ifdef __cplusplus -extern "C" { -#endif - -#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) - #define BOARD_HAS_USB_HIGHSPEED -#endif + extern "C" { + #endif -// for SystemInit() -void bsp_init(void * p_args); - - -#ifdef __cplusplus -} -#endif + void bsp_init(void * p_args); -#endif + #ifdef __cplusplus + } + #endif +#endif /* BOARD_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/board.cmake b/hw/bsp/ra/boards/portenta_c33/board.cmake index 1837d8450..a1545f070 100644 --- a/hw/bsp/ra/boards/portenta_c33/board.cmake +++ b/hw/bsp/ra/boards/portenta_c33/board.cmake @@ -1,25 +1,16 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) set(DFU_UTIL_VID_PID 2341:0368) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld) - -# Device port default to PORT1 Highspeed -if (NOT DEFINED PORT) -set(PORT 1) +# device default to PORT 1 High Speed +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) endif() - -# Host port will be the other port -set(HOST_PORT $<NOT:${PORT}>) function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - BOARD_TUD_RHPORT=${PORT} - BOARD_TUH_RHPORT=${HOST_PORT} - # port 0 is fullspeed, port 1 is highspeed - BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED> - BOARD_TUH_MAX_SPEED=$<IF:${HOST_PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED> - ) endfunction() diff --git a/hw/bsp/ra/boards/portenta_c33/board.h b/hw/bsp/ra/boards/portenta_c33/board.h index 7841ec8b8..7853c2dbd 100644 --- a/hw/bsp/ra/boards/portenta_c33/board.h +++ b/hw/bsp/ra/boards/portenta_c33/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Arduino Portenta C33 + url: https://www.arduino.cc/pro/hardware-product-portenta-c33/ +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ @@ -31,36 +36,9 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_01_PIN_07 // Red LED #define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_04_PIN_08 // D12 #define BUTTON_STATE_ACTIVE 0 -static const ioport_pin_cfg_t board_pin_cfg[] = { - { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW }, - { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, - - // USB FS - { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH }, - { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - - // USB HS - { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS }, - { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, - { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, - - // ETM Trace - #ifdef TRACE_ETM - { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - #endif -}; - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/portenta_c33/board.mk b/hw/bsp/ra/boards/portenta_c33/board.mk index 6a5c2ffce..ab814cda6 100644 --- a/hw/bsp/ra/boards/portenta_c33/board.mk +++ b/hw/bsp/ra/boards/portenta_c33/board.mk @@ -1,10 +1,9 @@ CPU_CORE = cortex-m33 MCU_VARIANT = ra6m5 -LD_FILE = ${BOARD_PATH}/${BOARD}.ld - # Port 1 is highspeed -PORT ?= 1 +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 JLINK_DEVICE = R7FA6M5BH DFU_UTIL_OPTION = -d 2341:0368 -a 0 diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 33d381850..000000000 --- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,63 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (2) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) -#else - #define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x1000) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 6845183db..000000000 --- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA6M5BH3CFC -#define BSP_MCU_FEATURE_SET ('B') -#define BSP_ROM_SIZE_BYTES (2097152) -#define BSP_RAM_SIZE_BYTES (524288) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (176) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld deleted file mode 100644 index ba15588e6..000000000 --- a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld +++ /dev/null @@ -1,25 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x80000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x200000; -DATA_FLASH_START = 0x08000000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x0100A100; -OPTION_SETTING_LENGTH = 0x100; -OPTION_SETTING_S_START = 0x0100A200; -OPTION_SETTING_S_LENGTH = 0x100; -ID_CODE_START = 0x00000000; -ID_CODE_LENGTH = 0x0; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x68000000; -OSPI_DEVICE_0_LENGTH = 0x8000000; -OSPI_DEVICE_1_START = 0x70000000; -OSPI_DEVICE_1_LENGTH = 0x10000000; - -/* Board has bootloader */ -FLASH_IMAGE_START = 0x10000; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..90afbdef3 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x1000) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h index bd6a901c3..bd6a901c3 100644 --- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..e532478f8 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M5BH3CFC + #define BSP_MCU_FEATURE_SET ('B') + #define BSP_ROM_SIZE_BYTES (2097152) + #define BSP_RAM_SIZE_BYTES (524288) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (176) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index d5428540f..c01219377 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -5,80 +5,80 @@ extern "C" { #endif -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA6M5 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA6M5 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif -#define BSP_CFG_FLL_ENABLE (0) + #define BSP_CFG_FLL_ENABLE (0) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) -#if defined(_RA_TZ_SECURE) + #if defined(_RA_TZ_SECURE) #define BSP_TZ_SECURE_BUILD (1) #define BSP_TZ_NONSECURE_BUILD (0) #elif defined(_RA_TZ_NONSECURE) #define BSP_TZ_SECURE_BUILD (0) #define BSP_TZ_NONSECURE_BUILD (1) #else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) -#endif + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif -/* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) -/* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) #ifndef SCB_NSACR_CP10_11_VAL -#define SCB_NSACR_CP10_11_VAL (3U) + #define SCB_NSACR_CP10_11_VAL (3U) #endif #ifndef FPU_FPCCR_TS_VAL -#define FPU_FPCCR_TS_VAL (1U) + #define FPU_FPCCR_TS_VAL (1U) #endif -#define FPU_FPCCR_CLRONRETS_VAL (1) + #define FPU_FPCCR_CLRONRETS_VAL (1) #ifndef FPU_FPCCR_CLRONRET_VAL -#define FPU_FPCCR_CLRONRET_VAL (1) + #define FPU_FPCCR_CLRONRET_VAL (1) #endif -/* The C-Cache line size that is configured during startup. */ + /* The C-Cache line size that is configured during startup. */ #ifndef BSP_CFG_C_CACHE_LINE_SIZE -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) + #define BSP_CFG_C_CACHE_LINE_SIZE (1U) #endif -/* Type 1 Peripheral Security Attribution */ + /* Type 1 Peripheral Security Attribution */ -/* Peripheral Security Attribution Register (PSAR) Settings */ + /* Peripheral Security Attribution Register (PSAR) Settings */ #ifndef BSP_TZ_CFG_PSARB #define BSP_TZ_CFG_PSARB (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ @@ -146,19 +146,19 @@ extern "C" { 0xfffffffc) /* Unused */ #endif -/* Type 2 Peripheral Security Attribution */ + /* Type 2 Peripheral Security Attribution */ -/* Security attribution for Cache registers. */ + /* Security attribution for Cache registers. */ #ifndef BSP_TZ_CFG_CSAR #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) #endif -/* Security attribution for RSTSRn registers. */ + /* Security attribution for RSTSRn registers. */ #ifndef BSP_TZ_CFG_RSTSAR #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) #endif -/* Security attribution for registers of LVD channels. */ + /* Security attribution for registers of LVD channels. */ #ifndef BSP_TZ_CFG_LVDSAR #define BSP_TZ_CFG_LVDSAR (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ @@ -166,16 +166,16 @@ extern "C" { 0xFFFFFFFCU) #endif -/* Security attribution for LPM registers. */ + /* Security attribution for LPM registers. */ #ifndef BSP_TZ_CFG_LPMSAR #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) #endif -/* Deep Standby Interrupt Factor Security Attribution Register. */ + /* Deep Standby Interrupt Factor Security Attribution Register. */ #ifndef BSP_TZ_CFG_DPFSAR #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) #endif -/* Security attribution for CGC registers. */ + /* Security attribution for CGC registers. */ #ifndef BSP_TZ_CFG_CGFSAR #if BSP_CFG_CLOCKS_SECURE /* Protect all CGC registers from Non-secure write access. */ @@ -186,12 +186,12 @@ extern "C" { #endif #endif -/* Security attribution for Battery Backup registers. */ + /* Security attribution for Battery Backup registers. */ #ifndef BSP_TZ_CFG_BBFSAR #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) #endif -/* Security attribution for registers for IRQ channels. */ + /* Security attribution for registers for IRQ channels. */ #ifndef BSP_TZ_CFG_ICUSARA #define BSP_TZ_CFG_ICUSARA (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ @@ -213,12 +213,12 @@ extern "C" { 0xFFFF0000U) #endif -/* Security attribution for NMI registers. */ + /* Security attribution for NMI registers. */ #ifndef BSP_TZ_CFG_ICUSARB #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ #endif -/* Security attribution for registers for DMAC channels */ + /* Security attribution for registers for DMAC channels */ #ifndef BSP_TZ_CFG_ICUSARC #define BSP_TZ_CFG_ICUSARC (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ @@ -232,29 +232,29 @@ extern "C" { 0xFFFFFF00U) #endif -/* Security attribution registers for SELSR0. */ + /* Security attribution registers for SELSR0. */ #ifndef BSP_TZ_CFG_ICUSARD #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN0. */ + /* Security attribution registers for WUPEN0. */ #ifndef BSP_TZ_CFG_ICUSARE #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN1. */ + /* Security attribution registers for WUPEN1. */ #ifndef BSP_TZ_CFG_ICUSARF #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) #endif -/* Set DTCSTSAR if the Secure program uses the DTC. */ + /* Set DTCSTSAR if the Secure program uses the DTC. */ #if RA_NOT_DEFINED == RA_NOT_DEFINED -#define BSP_TZ_CFG_DTC_USED (0U) + #define BSP_TZ_CFG_DTC_USED (0U) #else #define BSP_TZ_CFG_DTC_USED (1U) #endif -/* Security attribution of FLWT and FCKMHZ registers. */ + /* Security attribution of FLWT and FCKMHZ registers. */ #ifndef BSP_TZ_CFG_FSAR /* If the CGC registers are only accessible in Secure mode, than there is no * reason for nonsecure applications to access FLWT and FCKMHZ. */ @@ -267,118 +267,123 @@ extern "C" { #endif #endif -/* Security attribution for SRAM registers. */ + /* Security attribution for SRAM registers. */ #ifndef BSP_TZ_CFG_SRAMSAR /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (\ + #define BSP_TZ_CFG_SRAMSAR (\ 1 | \ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ 4 | \ 0xFFFFFFF8U) #endif -/* Security attribution for Standby RAM registers. */ + /* Security attribution for Standby RAM registers. */ #ifndef BSP_TZ_CFG_STBRAMSAR -#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) + #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) #endif -/* Security attribution for the DMAC Bus Master MPU settings. */ + /* Security attribution for the DMAC Bus Master MPU settings. */ #ifndef BSP_TZ_CFG_MMPUSARA -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ -#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) #endif -/* Security Attribution Register A for BUS Control registers. */ + /* Security Attribution Register A for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARA -#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) #endif -/* Security Attribution Register B for BUS Control registers. */ + /* Security Attribution Register B for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARB -#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) #endif -/* Enable Uninitialized Non-Secure Application Fallback. */ + /* Enable Uninitialized Non-Secure Application Fallback. */ #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK -#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) #endif -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -/* Option Function Select Register 1 Security Attribution */ + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + + /* Option Function Select Register 1 Security Attribution */ #ifndef BSP_CFG_ROM_REG_OFS1_SEL #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) #else -#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) #endif #endif -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -/* Dual Mode Select Register */ + /* Dual Mode Select Register */ #ifndef BSP_CFG_ROM_REG_DUALSEL -#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) + #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) #endif -/* Block Protection Register 0 */ + /* Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_BPS0 -#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) #endif -/* Block Protection Register 1 */ + /* Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_BPS1 -#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) #endif -/* Block Protection Register 2 */ + /* Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_BPS2 -#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) #endif -/* Block Protection Register 3 */ + /* Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_BPS3 -#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) #endif -/* Permanent Block Protection Register 0 */ + /* Permanent Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_PBPS0 -#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) #endif -/* Permanent Block Protection Register 1 */ + /* Permanent Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_PBPS1 -#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) #endif -/* Permanent Block Protection Register 2 */ + /* Permanent Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_PBPS2 -#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) #endif -/* Permanent Block Protection Register 3 */ + /* Permanent Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_PBPS3 -#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) #endif -/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL0 -#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) + #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) #endif -/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL1 -#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) + #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) #endif -/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL2 -#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) + #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) #endif -/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL3 -#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) + #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif + /* Security Attribution for Bank Select Register */ +#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL + #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) #endif #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) #endif #ifdef __cplusplus diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..c411386c1 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define LED1 (BSP_IO_PORT_01_PIN_07) +#define SW1 (BSP_IO_PORT_04_PIN_08) +extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BH3CFC.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/r_ioport_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h index cb7c07932..d2688bf5b 100644 --- a/hw/bsp/ra/r_ioport_cfg.h +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -1,7 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef R_IOPORT_CFG_H_ #define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif #define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifdef __cplusplus +} +#endif #endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..91b9de11e --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,35 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ +#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c b/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c new file mode 100644 index 000000000..fad79741a --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c @@ -0,0 +1,71 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_01_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_11_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/linker/gcc/fsp.ld b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld index 453d46f24..605eef7d2 100644 --- a/hw/bsp/ra/linker/gcc/fsp.ld +++ b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld @@ -1,3 +1,9 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + /* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ /* XIP_SECONDARY_SLOT_IMAGE = 1; @@ -14,8 +20,6 @@ ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -NS_OFFSET_START = DEFINED(NS_OFFSET_START) ? NS_OFFSET_START : 0; -NS_IMAGE_OFFSET = DEFINED(PROJECT_NONSECURE) ? NS_OFFSET_START : 0; RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; @@ -32,20 +36,21 @@ PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE) USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); __bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; __bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; __bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; __bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; __bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; __bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; __bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START - FLASH_APPLICATION_NSC_LENGTH; + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; __bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; @@ -55,7 +60,7 @@ __bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : __bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); __bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; @@ -67,30 +72,34 @@ FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; /* Define memory regions. */ MEMORY { - ITCM (rx) : ORIGIN = ITCM_START + NS_IMAGE_OFFSET, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START + NS_IMAGE_OFFSET, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN + NS_IMAGE_OFFSET, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START + NS_IMAGE_OFFSET, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START + NS_IMAGE_OFFSET, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET + 0x34, LENGTH = OPTION_SETTING_LENGTH - 0x34 - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH } /* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) +GROUP(libgcc.a libc.a libm.a) /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. @@ -144,27 +153,6 @@ ENTRY(Reset_Handler) SECTIONS { - /* Initialized ITCM data. */ - .itcm_data : - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start__ = .; - - KEEP(*(.itcm_data*)) - - /* All ITCM data end */ - __itcm_data_end__ = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end__, 8192); - } > ITCM - .text : { __tz_FLASH_S = ABSOLUTE(FLASH_START); @@ -177,6 +165,10 @@ SECTIONS KEEP(*(.application_vectors*)) __Vectors_End = .; + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; KEEP(*(.rom_registers*)) @@ -187,7 +179,6 @@ SECTIONS /* Allocate flash write-boundary-aligned * space for sce9 wrapped public keys for mcuboot if the module is used. */ - . = ALIGN(128); KEEP(*(.mcuboot_sce9_key*)) *(.text*) @@ -233,16 +224,54 @@ SECTIONS __Vectors_Size = __Vectors_End - __Vectors; - .ARM.extab : + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; __exidx_start = .; - .ARM.exidx : + /DISCARD/ : { + *(.ARM.extab* .gnu.linkonce.armextab.*) *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH + } __exidx_end = .; /* To copy multiple ROM to RAM sections, @@ -337,50 +366,76 @@ SECTIONS } > RAM AT > FLASH - /* Start address of the initial values for .dtcm_data. */ - __dtcm_data_init_start = __etext + __data_end__ - __data_start__; + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); /* Initialized DTCM data. */ - .dtcm_data : + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) { /* Start of DTCM Secure Trustzone region. */ __tz_DTCM_S = ABSOLUTE(DTCM_START); /* Initialized DTCM data start */ - __dtcm_data_start__ = .; + __dtcm_data_start = .; KEEP(*(.dtcm_data*)) + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + /* Initialized DTCM data end */ - __dtcm_data_end__ = .; - } > DTCM AT > FLASH + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + . = __dtcm_data_end; /* Uninitialized DTCM data. */ - .dtcm_noinit (NOLOAD): + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : { /* Uninitialized DTCM data start */ - __dtcm_noinit_start = .; + __dtcm_bss_start = .; - KEEP(*(.dtcm_noinit*)) + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); /* Uninitialized DTCM data end */ - __dtcm_noinit_end = .; + __dtcm_bss_end = .; /* * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_noinit_end, 8192); + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); } > DTCM - /* TrustZone Secure Gateway Stubs Section. */ + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - /* Some arithmetic is needed to eliminate unnecessary FILL for secure projects. */ - /* 1. Get the address to the next block after the .data section in FLASH. */ - DATA_END = LOADADDR(.data) + SIZEOF(.data); - /* 2. Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block after .data */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(DATA_END, 1024); - /* 3. Manually specify the start location for .gnu.sgstubs */ + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) { __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); @@ -407,8 +462,8 @@ SECTIONS __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__); - .qspi_non_retentive : AT (__qspi_flash_code_addr__) + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) { __qspi_non_retentive_start__ = .; KEEP(*(.qspi_non_retentive*)) @@ -456,8 +511,8 @@ SECTIONS __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__); - .ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__) + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) { __ospi_device_0_non_retentive_start__ = .; KEEP(*(.ospi_device_0_non_retentive*)) @@ -486,8 +541,8 @@ SECTIONS __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__); - .ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__) + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) { __ospi_device_1_non_retentive_start__ = .; KEEP(*(.ospi_device_1_non_retentive*)) @@ -527,7 +582,6 @@ SECTIONS { . = ALIGN(8); __HeapBase = .; - PROVIDE(end = .); /* Place the STD heap here. */ KEEP(*(.heap)) __HeapLimit = .; @@ -615,7 +669,6 @@ SECTIONS __ID_Code_End = .; } > ID_CODE - /* Symbol required for RA Configuration tool. */ __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); diff --git a/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld b/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld new file mode 100644 index 000000000..74c648329 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld @@ -0,0 +1,25 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x80000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x0100A100; + OPTION_SETTING_LENGTH = 0x100; + OPTION_SETTING_S_START = 0x0100A200; + OPTION_SETTING_S_LENGTH = 0x100; + ID_CODE_START = 0x00000000; + ID_CODE_LENGTH = 0x0; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x4000000; + OSPI_DEVICE_0_START = 0x68000000; + OSPI_DEVICE_0_LENGTH = 0x8000000; + OSPI_DEVICE_1_START = 0x70000000; + OSPI_DEVICE_1_LENGTH = 0x10000000; + +/* Board has bootloader */ +FLASH_IMAGE_START = 0x10000; diff --git a/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml b/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml new file mode 100644 index 000000000..fcc9d711d --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml @@ -0,0 +1,240 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<raConfiguration version="9"> + <generalSettings> + <option key="#Board#" value="board.custom"/> + <option key="CPU" value="RA6M5"/> + <option key="Core" value="CM33"/> + <option key="#TargetName#" value="R7FA6M5BH3CFC"/> + <option key="#TargetARCHITECTURE#" value="cortex-m33"/> + <option key="#DeviceCommand#" value="R7FA6M5BH"/> + <option key="#RTOS#" value="_none"/> + <option key="#pinconfiguration#" value="R7FA6M5BH3CFC.pincfg"/> + <option key="#FSPVersion#" value="5.6.0"/> + <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/> + </generalSettings> + <raBspConfiguration> + <config id="config.bsp.ra6m5.R7FA6M5BH3CFC"> + <property id="config.bsp.part_number" value="config.bsp.part_number.value"/> + <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/> + <property id="config.bsp.rom_size_bytes_hidden" value="2097152"/> + <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/> + <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/> + <property id="config.bsp.package_style" value="config.bsp.package_style.value"/> + <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/> + <property id="config.bsp.irq_count_hidden" value="96"/> + </config> + <config id="config.bsp.ra6m5"> + <property id="config.bsp.series" value="config.bsp.series.value"/> + </config> + <config id="config.bsp.ra6m5.fsp"> + <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/> + <property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/> + <property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/> + <property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/> + <property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/> + <property id="config.bsp.fsp.tz.csar" value="config.bsp.fsp.tz.csar.both"/> + <property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/> + <property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/> + <property id="config.bsp.fsp.tz.sramsar.sramprcr" value="config.bsp.fsp.tz.sramsar.sramprcr.both"/> + <property id="config.bsp.fsp.tz.sramsar.sramecc" value="config.bsp.fsp.tz.sramsar.sramecc.both"/> + <property id="config.bsp.fsp.tz.stbramsar" value="config.bsp.fsp.tz.stbramsar.both"/> + <property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/> + <property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/> + <property id="config.bsp.fsp.tz.banksel_sel" value="config.bsp.fsp.tz.banksel_sel.both"/> + <property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/> + <property id="config.bsp.fsp.cache_line_size" value="config.bsp.fsp.cache_line_size.32"/> + <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/> + <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/> + <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/> + <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0_level" value="config.bsp.fsp.OFS1_SEL.voltage_detection0_level.secure"/> + <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.start" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.start.secure"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/> + <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/> + <property id="config.bsp.fsp.BPS.BPS0" value=""/> + <property id="config.bsp.fsp.BPS.BPS1" value=""/> + <property id="config.bsp.fsp.BPS.BPS2" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS0" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS1" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS2" value=""/> + <property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/> + <property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/> + <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/> + <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="50000000"/> + <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="16666666"/> + <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/> + <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/> + <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="25000000"/> + <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/> + <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/> + <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x3"/> + <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/> + <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x3"/> + <property id="config.bsp.fsp.mcu.canfd.num_channels" value="2"/> + <property id="config.bsp.fsp.mcu.canfd.rx_fifos" value="8"/> + <property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="4864"/> + <property id="config.bsp.fsp.mcu.canfd.afl_rules" value="128"/> + <property id="config.bsp.fsp.mcu.canfd.afl_rules_each_chnl" value="64"/> + <property id="config.bsp.fsp.mcu.canfd.max_data_rate_hz" value="5"/> + <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x03F9"/> + <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/> + <property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="65535"/> + </config> + <config id="config.bsp.ra"> + <property id="config.bsp.common.main" value="0x1000"/> + <property id="config.bsp.common.heap" value="0x1000"/> + <property id="config.bsp.common.vcc" value="3300"/> + <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/> + <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/> + <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/> + <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/> + <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/> + <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/> + <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/> + <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/> + <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/> + <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/> + <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/> + <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/> + </config> + </raBspConfiguration> + <raClockConfiguration> + <node id="board.clock.xtal.freq" mul="24000000" option="_edit"/> + <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/> + <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/> + <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/> + <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/> + <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/> + <node id="board.clock.pll.div" option="board.clock.pll.div.3"/> + <node id="board.clock.pll.mul" option="board.clock.pll.mul.250"/> + <node id="board.clock.pll.display" option="board.clock.pll.display.value"/> + <node id="board.clock.pll2.source" option="board.clock.pll2.source.xtal"/> + <node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/> + <node id="board.clock.pll2.mul" option="board.clock.pll2.mul.200"/> + <node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/> + <node id="board.clock.clock.source" option="board.clock.clock.source.pll"/> + <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/> + <node id="board.clock.uclk.source" option="board.clock.uclk.source.pll2"/> + <node id="board.clock.u60ck.source" option="board.clock.u60ck.source.pll2"/> + <node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/> + <node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/> + <node id="board.clock.cecclk.source" option="board.clock.cecclk.source.disabled"/> + <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/> + <node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/> + <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/> + <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/> + <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/> + <node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/> + <node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/> + <node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/> + <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/> + <node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/> + <node id="board.clock.u60ck.div" option="board.clock.u60ck.div.4"/> + <node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.1"/> + <node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.1"/> + <node id="board.clock.cecclk.div" option="board.clock.cecclk.div.1"/> + <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/> + <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/> + <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/> + <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/> + <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/> + <node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/> + <node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/> + <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/> + <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/> + <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/> + <node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/> + <node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/> + <node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/> + <node id="board.clock.cecclk.display" option="board.clock.cecclk.display.value"/> + </raClockConfiguration> + <raComponentSelection> + <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0"> + <description>Board Support Package Common Files</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0"> + <description>I/O Port</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0"> + <description>Arm CMSIS Version 6 - Core (M)</description> + <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="5.6.0"> + <description>Custom Board Support Files</description> + <originalPack>Renesas.RA_board_custom.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="R7FA6M5BH3CFC" vendor="Renesas" version="5.6.0"> + <description>Board support package for R7FA6M5BH3CFC</description> + <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA6M5</description> + <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA6M5 - FSP Data</description> + <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="events" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA6M5 - Events</description> + <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack> + </component> + </raComponentSelection> + <raElcConfiguration/> + <raIcuConfiguration/> + <raModuleConfiguration> + <module id="module.driver.ioport_on_ioport.0"> + <property id="module.driver.ioport.name" value="g_ioport"/> + <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/> + <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/> + </module> + <context id="_hal.0"> + <stack module="module.driver.ioport_on_ioport.0"/> + </context> + <config id="config.driver.ioport"> + <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/> + </config> + </raModuleConfiguration> + <raPinConfiguration> + <symbolicName propertyId="p107.symbolic_name" value="LED1"/> + <symbolicName propertyId="p408.symbolic_name" value="SW1"/> + <pincfg active="true" name="R7FA6M5BH3CFC.pincfg" selected="true" symbol="g_bsp_pin_cfg"> + <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/> + <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/> + <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/> + <configSetting altId="p107.output.low" configurationId="p107"/> + <configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/> + <configSetting altId="p108.debug0.swdio" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p300.debug0.swclk" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/> + <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/> + <configSetting altId="p408.input" configurationId="p408"/> + <configSetting altId="p408.gpio_mode.gpio_mode_in" configurationId="p408.gpio_mode"/> + <configSetting altId="p408.gpio_pupd.gpio_pupd_ip_up" configurationId="p408.gpio_pupd"/> + <configSetting altId="pb01.usbhs0.vbus" configurationId="pb01"/> + <configSetting altId="pb01.gpio_mode.gpio_mode_peripheral" configurationId="pb01.gpio_mode"/> + <configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/> + <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/> + <configSetting altId="usbhs0.mode.device" configurationId="usbhs0.mode"/> + <configSetting altId="usbhs0.vbus.pb01" configurationId="usbhs0.vbus"/> + </pincfg> + </raPinConfiguration> +</raConfiguration> diff --git a/hw/bsp/ra/boards/ra2a1_ek/board.cmake b/hw/bsp/ra/boards/ra2a1_ek/board.cmake index 4d083ca98..9c679c4b5 100644 --- a/hw/bsp/ra/boards/ra2a1_ek/board.cmake +++ b/hw/bsp/ra/boards/ra2a1_ek/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m23 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m23 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra2a1) set(JLINK_DEVICE R7FA2A1AB) diff --git a/hw/bsp/ra/boards/ra2a1_ek/board.h b/hw/bsp/ra/boards/ra2a1_ek/board.h index 1c2b666d2..d925fc551 100644 --- a/hw/bsp/ra/boards/ra2a1_ek/board.h +++ b/hw/bsp/ra/boards/ra2a1_ek/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: RA2A1 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra2a1-evaluation-kit-ra2a1-mcu-group +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ @@ -31,21 +36,9 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_02_PIN_05 -#define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_02_PIN_06 +#define LED_STATE_ON 1 #define BUTTON_STATE_ACTIVE 0 -static const ioport_pin_cfg_t board_pin_cfg[] = { - {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, - {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, - // USB FS D+, D-, VBus - {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, -}; - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 30637c17b..000000000 --- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,62 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (2) - #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) - #else -#define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) - #endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -#define BSP_CFG_HEAP_BYTES (0x400) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus - } - #endif -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 710e85b28..000000000 --- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA2A1AB3CFM -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (262144) -#define BSP_RAM_SIZE_BYTES (32768) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (64) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h deleted file mode 100644 index 6caef62cc..000000000 --- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,84 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" -#define BSP_MCU_GROUP_RA2A1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (24000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (32000000) - #elif BSP_CFG_HOCO_FREQUENCY == 4 - #define BSP_HOCO_HZ (48000000) - #elif BSP_CFG_HOCO_FREQUENCY == 5 - #define BSP_HOCO_HZ (64000000) - #else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" - #endif - -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) - #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) - #else -/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ -#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif - -#ifdef __cplusplus - } - #endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..bf1fe0cc6 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x400) + #define BSP_CFG_HEAP_BYTES (0x400) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h index eb82f4697..eb82f4697 100644 --- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..6970e4c33 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA2A1AB3CFM + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (262144) + #define BSP_RAM_SIZE_BYTES (32768) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (64) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..24e3efaa2 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,89 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA2A1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (24000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) + #elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (0) + + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) + #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC) + #define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF) + #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC) + #define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #endif + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + + /* + ID Code + Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings. + WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled. + */ + #if defined(BSP_ID_CODE_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else + /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ + #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) + #endif + + #if (0) + #define BSP_SECTION_FLASH_GAP BSP_PLACE_IN_SECTION(".flash_gap") + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..fc48a5809 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define LED1 (BSP_IO_PORT_02_PIN_05) +#define SW1 (BSP_IO_PORT_02_PIN_06) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA2A1-EK.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h index cd9d135f7..6b41669d3 100644 --- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h @@ -8,7 +8,7 @@ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ #define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ #define BSP_CFG_SDADC_CLOCK_SOURCE (0) /* SDADCCLK Src: HOCO */ #define BSP_CFG_SDADCCLK_DIV (7) /* SDADCCLK Div /12 */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..7fed32687 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c @@ -0,0 +1,115 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_00_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_02_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_03_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_04_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_09_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld new file mode 100644 index 000000000..605eef7d2 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld @@ -0,0 +1,769 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld new file mode 100644 index 000000000..2d6992fed --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld @@ -0,0 +1,22 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x8000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x40000; + DATA_FLASH_START = 0x40100000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x00000000; + OPTION_SETTING_LENGTH = 0x0; + OPTION_SETTING_S_START = 0x80000000; + OPTION_SETTING_S_LENGTH = 0x0; + ID_CODE_START = 0x01010018; + ID_CODE_LENGTH = 0x20; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x0; + OSPI_DEVICE_0_START = 0x80020000; + OSPI_DEVICE_0_LENGTH = 0x0; + OSPI_DEVICE_1_START = 0x80030000; + OSPI_DEVICE_1_LENGTH = 0x0; diff --git a/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..beeeb67f2 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml @@ -0,0 +1,258 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<raConfiguration version="9"> + <generalSettings> + <option key="#Board#" value="board.ra2a1_ek"/> + <option key="CPU" value="RA2A1"/> + <option key="Core" value="CM23"/> + <option key="#TargetName#" value="R7FA2A1AB3CFM"/> + <option key="#TargetARCHITECTURE#" value="cortex-m23"/> + <option key="#DeviceCommand#" value="R7FA2A1AB"/> + <option key="#RTOS#" value="_none"/> + <option key="#pinconfiguration#" value="R7FA2A1AB3CFM.pincfg"/> + <option key="#FSPVersion#" value="5.6.0"/> + <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra2a1_ek##"/> + <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/> + </generalSettings> + <raBspConfiguration> + <config id="config.bsp.ra2a1.R7FA2A1AB3CFM"> + <property id="config.bsp.part_number" value="config.bsp.part_number.value"/> + <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/> + <property id="config.bsp.rom_size_bytes_hidden" value="262144"/> + <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/> + <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/> + <property id="config.bsp.package_style" value="config.bsp.package_style.value"/> + <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/> + <property id="config.bsp.irq_count_hidden" value="32"/> + </config> + <config id="config.bsp.ra2a1"> + <property id="config.bsp.series" value="config.bsp.series.value"/> + </config> + <config id="config.bsp.ra2a1.fsp"> + <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.disabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/> + <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/> + <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/> + <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.190"/> + <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.enabled"/> + <property id="config.bsp.low_voltage_mode" value="config.bsp.low_voltage_mode.disabled"/> + <property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/> + <property id="config.bsp.fsp.mpu_pc0_start" value="0x000FFFFC"/> + <property id="config.bsp.fsp.mpu_pc0_end" value="0x000FFFFF"/> + <property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/> + <property id="config.bsp.fsp.mpu_pc1_start" value="0x000FFFFC"/> + <property id="config.bsp.fsp.mpu_pc1_end" value="0x000FFFFF"/> + <property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg0_start" value="0x000FFFFC"/> + <property id="config.bsp.fsp.mpu_reg0_end" value="0x000FFFFF"/> + <property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/> + <property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/> + <property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/> + <property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/> + <property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/> + <property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/> + <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/> + <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="32000000"/> + <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="3333333"/> + <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/> + <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="1"/> + <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="8000000"/> + <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="16000000"/> + <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="0"/> + <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0"/> + <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="0"/> + <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x0"/> + <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/> + <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/> + <property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/> + <property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/> + <property id="config.bsp.common.id1" value=""/> + <property id="config.bsp.common.id2" value=""/> + <property id="config.bsp.common.id3" value=""/> + <property id="config.bsp.common.id4" value=""/> + <property id="config.bsp.common.id_fixed" value=""/> + <property id="config.bsp.common.fill_flash_gap" value="config.bsp.common.fill_flash_gap.disabled"/> + </config> + <config id="config.bsp.ra"> + <property id="config.bsp.common.main" value="0x400"/> + <property id="config.bsp.common.heap" value="0x400"/> + <property id="config.bsp.common.vcc" value="3300"/> + <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/> + <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/> + <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/> + <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/> + <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/> + <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/> + <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/> + <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/> + <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/> + <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/> + <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/> + <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/> + </config> + </raBspConfiguration> + <raClockConfiguration> + <node id="board.clock.xtal.freq" mul="12000000" option="_edit"/> + <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/> + <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/> + <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/> + <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/> + <node id="board.clock.clock.source" option="board.clock.clock.source.hoco"/> + <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/> + <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/> + <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/> + <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/> + <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/> + <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/> + <node id="board.clock.fclk.div" option="board.clock.fclk.div.2"/> + <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/> + <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/> + <node id="board.clock.sdadcclk.source" option="board.clock.sdadcclk.source.hoco"/> + <node id="board.clock.sdadcclk.div" option="board.clock.sdadcclk.div.12"/> + <node id="board.clock.sdadcclk.display" option="board.clock.sdadcclk.display.value"/> + <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/> + <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/> + <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/> + </raClockConfiguration> + <raComponentSelection> + <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0"> + <description>Simple application that blinks an LED. No RTOS included.</description> + <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0"> + <description>Board Support Package Common Files</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0"> + <description>I/O Port</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0"> + <description>Arm CMSIS Version 6 - Core (M)</description> + <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra2a1_ek" variant="" vendor="Renesas" version="5.6.0"> + <description>RA2A1-EK Board Support Files</description> + <originalPack>Renesas.RA_board_ra2a1_ek.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="device" variant="R7FA2A1AB3CFM" vendor="Renesas" version="5.6.0"> + <description>Board support package for R7FA2A1AB3CFM</description> + <originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="device" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA2A1</description> + <originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA2A1 - FSP Data</description> + <originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="events" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA2A1 - Events</description> + <originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack> + </component> + </raComponentSelection> + <raElcConfiguration/> + <raIcuConfiguration/> + <raModuleConfiguration> + <module id="module.driver.ioport_on_ioport.0"> + <property id="module.driver.ioport.name" value="g_ioport"/> + <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/> + <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/> + </module> + <context id="_hal.0"> + <stack module="module.driver.ioport_on_ioport.0"/> + </context> + <config id="config.driver.ioport"> + <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/> + </config> + </raModuleConfiguration> + <raPinConfiguration> + <symbolicName propertyId="p205.symbolic_name" value="LED1"/> + <symbolicName propertyId="p206.symbolic_name" value="SW1"/> + <pincfg active="true" name="RA2A1-EK.pincfg" selected="true" symbol="g_bsp_pin_cfg"> + <configSetting altId="adc0.an06.p003" configurationId="adc0.an06"/> + <configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/> + <configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/> + <configSetting altId="ctsu0.ts15.p001" configurationId="ctsu0.ts15"/> + <configSetting altId="ctsu0.tscap.p409" configurationId="ctsu0.tscap"/> + <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/> + <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/> + <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/> + <configSetting altId="p001.ctsu0.ts15" configurationId="p001"/> + <configSetting altId="p001.gpio_mode.gpio_mode_peripheral" configurationId="p001.gpio_mode"/> + <configSetting altId="p003.adc0.an06" configurationId="p003"/> + <configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/> + <configSetting altId="p108.debug0.swdio" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p111.spi0.rspck" configurationId="p111"/> + <configSetting altId="p111.gpio_mode.gpio_mode_peripheral" configurationId="p111.gpio_mode"/> + <configSetting altId="p112.spi0.ssl0" configurationId="p112"/> + <configSetting altId="p112.gpio_mode.gpio_mode_peripheral" configurationId="p112.gpio_mode"/> + <configSetting altId="p201.input" configurationId="p201"/> + <configSetting altId="p201.gpio_mode.gpio_mode_in" configurationId="p201.gpio_mode"/> + <configSetting altId="p204.sci0.rxd" configurationId="p204"/> + <configSetting altId="p204.gpio_mode.gpio_mode_peripheral" configurationId="p204.gpio_mode"/> + <configSetting altId="p205.output.low" configurationId="p205"/> + <configSetting altId="p205.gpio_mode.gpio_mode_out.low" configurationId="p205.gpio_mode"/> + <configSetting altId="p206.input" configurationId="p206"/> + <configSetting altId="p206.gpio_mode.gpio_mode_in" configurationId="p206.gpio_mode"/> + <configSetting altId="p206.gpio_pupd.gpio_pupd_ip_up" configurationId="p206.gpio_pupd"/> + <configSetting altId="p300.debug0.swclk" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + <configSetting altId="p303.spi0.mosi" configurationId="p303"/> + <configSetting altId="p303.gpio_mode.gpio_mode_peripheral" configurationId="p303.gpio_mode"/> + <configSetting altId="p304.spi0.miso" configurationId="p304"/> + <configSetting altId="p304.gpio_mode.gpio_mode_peripheral" configurationId="p304.gpio_mode"/> + <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/> + <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/> + <configSetting altId="p409.ctsu0.tscap" configurationId="p409"/> + <configSetting altId="p409.gpio_mode.gpio_mode_peripheral" configurationId="p409.gpio_mode"/> + <configSetting altId="p411.sci0.txd" configurationId="p411"/> + <configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/> + <configSetting altId="p914.usbfs0.dp" configurationId="p914"/> + <configSetting altId="p914.gpio_mode.gpio_mode_peripheral" configurationId="p914.gpio_mode"/> + <configSetting altId="p915.usbfs0.dm" configurationId="p915"/> + <configSetting altId="p915.gpio_mode.gpio_mode_peripheral" configurationId="p915.gpio_mode"/> + <configSetting altId="sci0.mode.asynchronous.free" configurationId="sci0.mode"/> + <configSetting altId="sci0.rxd.p204" configurationId="sci0.rxd"/> + <configSetting altId="sci0.txd.p411" configurationId="sci0.txd"/> + <configSetting altId="spi0.miso.p304" configurationId="spi0.miso"/> + <configSetting altId="spi0.mode.enabled.b" configurationId="spi0.mode"/> + <configSetting altId="spi0.mosi.p303" configurationId="spi0.mosi"/> + <configSetting altId="spi0.pairing.b" configurationId="spi0.pairing"/> + <configSetting altId="spi0.rspck.p111" configurationId="spi0.rspck"/> + <configSetting altId="spi0.ssl0.p112" configurationId="spi0.ssl0"/> + <configSetting altId="usbfs0.dm.p915" configurationId="usbfs0.dm"/> + <configSetting altId="usbfs0.dp.p914" configurationId="usbfs0.dp"/> + <configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/> + <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/> + </pincfg> + <pincfg active="false" name="R7FA2A1AB3CFM.pincfg" selected="false" symbol=""> + <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/> + <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/> + <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/> + <configSetting altId="p108.debug0.swdio" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p300.debug0.swclk" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + </pincfg> + </raPinConfiguration> +</raConfiguration> diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.cmake b/hw/bsp/ra/boards/ra4m1_ek/board.cmake index 7bb48bf44..247dea619 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/board.cmake +++ b/hw/bsp/ra/boards/ra4m1_ek/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra4m1) set(JLINK_DEVICE R7FA4M1AB) diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h index c132387bc..e146261be 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/board.h +++ b/hw/bsp/ra/boards/ra4m1_ek/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: RA4M1 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m1-evaluation-kit-ra4m1-mcu-group +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ @@ -31,21 +36,9 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_01_PIN_06 -#define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_01_PIN_05 +#define LED_STATE_ON 1 #define BUTTON_STATE_ACTIVE 0 -static const ioport_pin_cfg_t board_pin_cfg[] = { - {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, - {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, - // USB FS D+, D-, VBus - {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, -}; - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 11d5795df..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,35 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#undef RA_NOT_DEFINED -#define BSP_CFG_RTOS (0) -#if defined(_RA_BOOT_IMAGE) -#define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x800) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) - -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index d810dabb2..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA4M1AB3CFP -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (262144) -#define BSP_RAM_SIZE_BYTES (32768) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (100) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h deleted file mode 100644 index 72cdb89e6..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,78 +0,0 @@ -/* generated configuration header file through renesas e2 studio */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA4M1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 - #define BSP_HOCO_HZ (24000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (32000000) -#elif BSP_CFG_HOCO_FREQUENCY == 4 - #define BSP_HOCO_HZ (48000000) -#elif BSP_CFG_HOCO_FREQUENCY == 5 - #define BSP_HOCO_HZ (64000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) -#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) - #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) - #else -/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ -#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif - -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..43b0f5b65 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x800) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h index 444d32e56..444d32e56 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..243fad9b6 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M1AB3CFP + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (262144) + #define BSP_RAM_SIZE_BYTES (32768) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (100) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..3d482b2b6 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,84 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA4M1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (24000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) + #elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) + + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) + #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) + #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #endif + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + + /* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ + #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else + /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ + #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..f77a5bcec --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define SW1 (BSP_IO_PORT_01_PIN_05) +#define LED1 (BSP_IO_PORT_01_PIN_06) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M1-EK.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h index 554126523..81ac5dc11 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h @@ -7,7 +7,7 @@ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(8u,0u)) /* PLL Mul x8 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(8U,0U) /* PLL Mul x8 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..baa713443 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c @@ -0,0 +1,119 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_04_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_04_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_04_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld new file mode 100644 index 000000000..605eef7d2 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld @@ -0,0 +1,769 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld new file mode 100644 index 000000000..2d6992fed --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld @@ -0,0 +1,22 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x8000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x40000; + DATA_FLASH_START = 0x40100000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x00000000; + OPTION_SETTING_LENGTH = 0x0; + OPTION_SETTING_S_START = 0x80000000; + OPTION_SETTING_S_LENGTH = 0x0; + ID_CODE_START = 0x01010018; + ID_CODE_LENGTH = 0x20; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x0; + OSPI_DEVICE_0_START = 0x80020000; + OSPI_DEVICE_0_LENGTH = 0x0; + OSPI_DEVICE_1_START = 0x80030000; + OSPI_DEVICE_1_LENGTH = 0x0; diff --git a/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..2ca7fe595 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml @@ -0,0 +1,271 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<raConfiguration version="9"> + <generalSettings> + <option key="#Board#" value="board.ra4m1ek"/> + <option key="CPU" value="RA4M1"/> + <option key="Core" value="CM4"/> + <option key="#TargetName#" value="R7FA4M1AB3CFP"/> + <option key="#TargetARCHITECTURE#" value="cortex-m4"/> + <option key="#DeviceCommand#" value="R7FA4M1AB"/> + <option key="#RTOS#" value="_none"/> + <option key="#pinconfiguration#" value="R7FA4M1AB3CFP.pincfg"/> + <option key="#FSPVersion#" value="5.6.0"/> + <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra4m1_ek##"/> + <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/> + </generalSettings> + <raBspConfiguration> + <config id="config.bsp.ra4m1.R7FA4M1AB3CFP"> + <property id="config.bsp.part_number" value="config.bsp.part_number.value"/> + <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/> + <property id="config.bsp.rom_size_bytes_hidden" value="262144"/> + <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/> + <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/> + <property id="config.bsp.package_style" value="config.bsp.package_style.value"/> + <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/> + <property id="config.bsp.irq_count_hidden" value="32"/> + </config> + <config id="config.bsp.ra4m1"> + <property id="config.bsp.series" value="config.bsp.series.value"/> + </config> + <config id="config.bsp.ra4m1.fsp"> + <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/> + <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/> + <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/> + <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.190"/> + <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.enabled"/> + <property id="config.bsp.low_voltage_mode" value="config.bsp.low_voltage_mode.disabled"/> + <property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/> + <property id="config.bsp.fsp.mpu_pc0_start" value="0x00FFFFFC"/> + <property id="config.bsp.fsp.mpu_pc0_end" value="0x00FFFFFF"/> + <property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/> + <property id="config.bsp.fsp.mpu_pc1_start" value="0x00FFFFFC"/> + <property id="config.bsp.fsp.mpu_pc1_end" value="0x00FFFFFF"/> + <property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg0_start" value="0x00FFFFFC"/> + <property id="config.bsp.fsp.mpu_reg0_end" value="0x00FFFFFF"/> + <property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/> + <property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/> + <property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/> + <property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/> + <property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/> + <property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/> + <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/> + <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="64000000"/> + <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="6666666"/> + <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/> + <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="1"/> + <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="12000000"/> + <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="24000000"/> + <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="0"/> + <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0"/> + <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="0"/> + <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x0"/> + <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/> + <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/> + <property id="config.bsp.fsp.mcu.slcdc.1_4_bias_method" value="1"/> + <property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/> + <property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/> + <property id="config.bsp.common.id1" value=""/> + <property id="config.bsp.common.id2" value=""/> + <property id="config.bsp.common.id3" value=""/> + <property id="config.bsp.common.id4" value=""/> + <property id="config.bsp.common.id_fixed" value=""/> + </config> + <config id="config.bsp.ra"> + <property id="config.bsp.common.main" value="0x800"/> + <property id="config.bsp.common.heap" value="0x1000"/> + <property id="config.bsp.common.vcc" value="3300"/> + <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/> + <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/> + <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/> + <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/> + <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/> + <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/> + <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/> + <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/> + <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/> + <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/> + <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/> + <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/> + </config> + </raBspConfiguration> + <raClockConfiguration> + <node id="board.clock.xtal.freq" mul="12000000" option="_edit"/> + <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/> + <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.24m"/> + <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/> + <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/> + <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/> + <node id="board.clock.pll.div" option="board.clock.pll.div.2"/> + <node id="board.clock.pll.mul" option="board.clock.pll.mul.8"/> + <node id="board.clock.pll.display" option="board.clock.pll.display.value"/> + <node id="board.clock.clock.source" option="board.clock.clock.source.pll"/> + <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/> + <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/> + <node id="board.clock.pclka.div" option="board.clock.pclka.div.1"/> + <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/> + <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/> + <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/> + <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.1"/> + <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/> + <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/> + <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/> + <node id="board.clock.fclk.div" option="board.clock.fclk.div.2"/> + <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/> + <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/> + <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/> + <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/> + <node id="board.clock.uclk.source" option="board.clock.uclk.source.pll"/> + <node id="board.clock.uclk.display" option="board.clock.clkout.display.value"/> + </raClockConfiguration> + <raComponentSelection> + <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0"> + <description>Simple application that blinks an LED. No RTOS included.</description> + <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0"> + <description>Board Support Package Common Files</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0"> + <description>I/O Port</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0"> + <description>Arm CMSIS Version 6 - Core (M)</description> + <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra4m1_ek" variant="" vendor="Renesas" version="5.6.0"> + <description>RA4M1-EK Board Support Files</description> + <originalPack>Renesas.RA_board_ra4m1_ek.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="device" variant="R7FA4M1AB3CFP" vendor="Renesas" version="5.6.0"> + <description>Board support package for R7FA4M1AB3CFP</description> + <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="device" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA4M1</description> + <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA4M1 - FSP Data</description> + <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="events" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA4M1 - Events</description> + <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack> + </component> + </raComponentSelection> + <raElcConfiguration/> + <raIcuConfiguration/> + <raModuleConfiguration> + <module id="module.driver.ioport_on_ioport.0"> + <property id="module.driver.ioport.name" value="g_ioport"/> + <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/> + <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/> + </module> + <context id="_hal.0"> + <stack module="module.driver.ioport_on_ioport.0"/> + </context> + <config id="config.driver.ioport"> + <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/> + </config> + </raModuleConfiguration> + <raPinConfiguration> + <symbolicName propertyId="p105.symbolic_name" value="SW1"/> + <symbolicName propertyId="p106.symbolic_name" value="LED1"/> + <pincfg active="true" name="RA4M1-EK.pincfg" selected="true" symbol="g_bsp_pin_cfg"> + <configSetting altId="adc0.an04.p004" configurationId="adc0.an04"/> + <configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/> + <configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/> + <configSetting altId="ctsu0.ts35.p115" configurationId="ctsu0.ts35"/> + <configSetting altId="ctsu0.tscap.p205" configurationId="ctsu0.tscap"/> + <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/> + <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/> + <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/> + <configSetting altId="p004.adc0.an04" configurationId="p004"/> + <configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/> + <configSetting altId="p100.spi0.miso" configurationId="p100"/> + <configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/> + <configSetting altId="p101.spi0.mosi" configurationId="p101"/> + <configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/> + <configSetting altId="p102.spi0.rspck" configurationId="p102"/> + <configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/> + <configSetting altId="p103.spi0.ssl0" configurationId="p103"/> + <configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/> + <configSetting altId="p105.input" configurationId="p105"/> + <configSetting altId="p105.gpio_mode.gpio_mode_in" configurationId="p105.gpio_mode"/> + <configSetting altId="p105.gpio_pupd.gpio_pupd_ip_up" configurationId="p105.gpio_pupd"/> + <configSetting altId="p106.output.low" configurationId="p106"/> + <configSetting altId="p106.gpio_mode.gpio_mode_out.low" configurationId="p106.gpio_mode"/> + <configSetting altId="p108.debug0.swdio" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p115.ctsu0.ts35" configurationId="p115"/> + <configSetting altId="p115.gpio_mode.gpio_mode_peripheral" configurationId="p115.gpio_mode"/> + <configSetting altId="p205.ctsu0.tscap" configurationId="p205"/> + <configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/> + <configSetting altId="p300.debug0.swclk" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + <configSetting altId="p400.output.low" configurationId="p400"/> + <configSetting altId="p400.gpio_mode.gpio_mode_out.low" configurationId="p400.gpio_mode"/> + <configSetting altId="p401.sci1.txd" configurationId="p401"/> + <configSetting altId="p401.gpio_mode.gpio_mode_peripheral" configurationId="p401.gpio_mode"/> + <configSetting altId="p402.sci1.rxd" configurationId="p402"/> + <configSetting altId="p402.gpio_mode.gpio_mode_peripheral" configurationId="p402.gpio_mode"/> + <configSetting altId="p403.output.low" configurationId="p403"/> + <configSetting altId="p403.gpio_mode.gpio_mode_out.low" configurationId="p403.gpio_mode"/> + <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/> + <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/> + <configSetting altId="p914.usbfs0.usbdp" configurationId="p914"/> + <configSetting altId="p914.gpio_mode.gpio_mode_peripheral" configurationId="p914.gpio_mode"/> + <configSetting altId="p915.usbfs0.usbdm" configurationId="p915"/> + <configSetting altId="p915.gpio_mode.gpio_mode_peripheral" configurationId="p915.gpio_mode"/> + <configSetting altId="sci1.mode.asynchronous.free" configurationId="sci1.mode"/> + <configSetting altId="sci1.rxd.p402" configurationId="sci1.rxd"/> + <configSetting altId="sci1.txd.p401" configurationId="sci1.txd"/> + <configSetting altId="spi0.miso.p100" configurationId="spi0.miso"/> + <configSetting altId="spi0.mode.enabled.a" configurationId="spi0.mode"/> + <configSetting altId="spi0.mosi.p101" configurationId="spi0.mosi"/> + <configSetting altId="spi0.rspck.p102" configurationId="spi0.rspck"/> + <configSetting altId="spi0.ssl0.p103" configurationId="spi0.ssl0"/> + <configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/> + <configSetting altId="usbfs0.usbdm.p915" configurationId="usbfs0.usbdm"/> + <configSetting altId="usbfs0.usbdp.p914" configurationId="usbfs0.usbdp"/> + <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/> + </pincfg> + <pincfg active="false" name="R7FA4M1AB3CFP.pincfg" selected="false" symbol=""> + <configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/> + <configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/> + <configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/> + <configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/> + <configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/> + <configSetting altId="p108.debug0.tms" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p109.debug0.tdo" configurationId="p109"/> + <configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/> + <configSetting altId="p110.debug0.tdi" configurationId="p110"/> + <configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/> + <configSetting altId="p300.debug0.tck" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + </pincfg> + </raPinConfiguration> +</raConfiguration> diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.cmake b/hw/bsp/ra/boards/ra4m3_ek/board.cmake index dfd5fc95a..b413abc36 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/board.cmake +++ b/hw/bsp/ra/boards/ra4m3_ek/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra4m3) set(JLINK_DEVICE R7FA4M3AF) diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.h b/hw/bsp/ra/boards/ra4m3_ek/board.h index 9dd2545a0..8b277f6f0 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/board.h +++ b/hw/bsp/ra/boards/ra4m3_ek/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: RA4M3 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m3-evaluation-kit-ra4m3-mcu-group +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 862ec25b7..000000000 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,63 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) -#define BSP_CFG_RTOS (1) -#else -#define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) -#define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x800) -#define BSP_CFG_HEAP_BYTES (0x800) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 1a0bc02e2..000000000 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA4M3AF3CFB -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (1048576) -#define BSP_RAM_SIZE_BYTES (131072) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (144) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..96087fa0d --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x800) + #define BSP_CFG_HEAP_BYTES (0x800) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h index 444d32e56..444d32e56 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..1aaa4be0a --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M3AF3CFB + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (1048576) + #define BSP_RAM_SIZE_BYTES (131072) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (144) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index d5428540f..cb9429057 100644 --- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -5,80 +5,80 @@ extern "C" { #endif -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA6M5 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA4M3 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif -#define BSP_CFG_FLL_ENABLE (0) + #define BSP_CFG_FLL_ENABLE (0) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) -#if defined(_RA_TZ_SECURE) + #if defined(_RA_TZ_SECURE) #define BSP_TZ_SECURE_BUILD (1) #define BSP_TZ_NONSECURE_BUILD (0) #elif defined(_RA_TZ_NONSECURE) #define BSP_TZ_SECURE_BUILD (0) #define BSP_TZ_NONSECURE_BUILD (1) #else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) -#endif + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif -/* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) -/* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) #ifndef SCB_NSACR_CP10_11_VAL -#define SCB_NSACR_CP10_11_VAL (3U) + #define SCB_NSACR_CP10_11_VAL (3U) #endif #ifndef FPU_FPCCR_TS_VAL -#define FPU_FPCCR_TS_VAL (1U) + #define FPU_FPCCR_TS_VAL (1U) #endif -#define FPU_FPCCR_CLRONRETS_VAL (1) + #define FPU_FPCCR_CLRONRETS_VAL (1) #ifndef FPU_FPCCR_CLRONRET_VAL -#define FPU_FPCCR_CLRONRET_VAL (1) + #define FPU_FPCCR_CLRONRET_VAL (1) #endif -/* The C-Cache line size that is configured during startup. */ + /* The C-Cache line size that is configured during startup. */ #ifndef BSP_CFG_C_CACHE_LINE_SIZE -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) + #define BSP_CFG_C_CACHE_LINE_SIZE (1U) #endif -/* Type 1 Peripheral Security Attribution */ + /* Type 1 Peripheral Security Attribution */ -/* Peripheral Security Attribution Register (PSAR) Settings */ + /* Peripheral Security Attribution Register (PSAR) Settings */ #ifndef BSP_TZ_CFG_PSARB #define BSP_TZ_CFG_PSARB (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ @@ -146,19 +146,19 @@ extern "C" { 0xfffffffc) /* Unused */ #endif -/* Type 2 Peripheral Security Attribution */ + /* Type 2 Peripheral Security Attribution */ -/* Security attribution for Cache registers. */ + /* Security attribution for Cache registers. */ #ifndef BSP_TZ_CFG_CSAR #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) #endif -/* Security attribution for RSTSRn registers. */ + /* Security attribution for RSTSRn registers. */ #ifndef BSP_TZ_CFG_RSTSAR #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) #endif -/* Security attribution for registers of LVD channels. */ + /* Security attribution for registers of LVD channels. */ #ifndef BSP_TZ_CFG_LVDSAR #define BSP_TZ_CFG_LVDSAR (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ @@ -166,16 +166,16 @@ extern "C" { 0xFFFFFFFCU) #endif -/* Security attribution for LPM registers. */ + /* Security attribution for LPM registers. */ #ifndef BSP_TZ_CFG_LPMSAR #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) #endif -/* Deep Standby Interrupt Factor Security Attribution Register. */ + /* Deep Standby Interrupt Factor Security Attribution Register. */ #ifndef BSP_TZ_CFG_DPFSAR #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) #endif -/* Security attribution for CGC registers. */ + /* Security attribution for CGC registers. */ #ifndef BSP_TZ_CFG_CGFSAR #if BSP_CFG_CLOCKS_SECURE /* Protect all CGC registers from Non-secure write access. */ @@ -186,12 +186,12 @@ extern "C" { #endif #endif -/* Security attribution for Battery Backup registers. */ + /* Security attribution for Battery Backup registers. */ #ifndef BSP_TZ_CFG_BBFSAR #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) #endif -/* Security attribution for registers for IRQ channels. */ + /* Security attribution for registers for IRQ channels. */ #ifndef BSP_TZ_CFG_ICUSARA #define BSP_TZ_CFG_ICUSARA (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ @@ -213,12 +213,12 @@ extern "C" { 0xFFFF0000U) #endif -/* Security attribution for NMI registers. */ + /* Security attribution for NMI registers. */ #ifndef BSP_TZ_CFG_ICUSARB #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ #endif -/* Security attribution for registers for DMAC channels */ + /* Security attribution for registers for DMAC channels */ #ifndef BSP_TZ_CFG_ICUSARC #define BSP_TZ_CFG_ICUSARC (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ @@ -232,29 +232,29 @@ extern "C" { 0xFFFFFF00U) #endif -/* Security attribution registers for SELSR0. */ + /* Security attribution registers for SELSR0. */ #ifndef BSP_TZ_CFG_ICUSARD #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN0. */ + /* Security attribution registers for WUPEN0. */ #ifndef BSP_TZ_CFG_ICUSARE #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN1. */ + /* Security attribution registers for WUPEN1. */ #ifndef BSP_TZ_CFG_ICUSARF #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) #endif -/* Set DTCSTSAR if the Secure program uses the DTC. */ + /* Set DTCSTSAR if the Secure program uses the DTC. */ #if RA_NOT_DEFINED == RA_NOT_DEFINED -#define BSP_TZ_CFG_DTC_USED (0U) + #define BSP_TZ_CFG_DTC_USED (0U) #else #define BSP_TZ_CFG_DTC_USED (1U) #endif -/* Security attribution of FLWT and FCKMHZ registers. */ + /* Security attribution of FLWT and FCKMHZ registers. */ #ifndef BSP_TZ_CFG_FSAR /* If the CGC registers are only accessible in Secure mode, than there is no * reason for nonsecure applications to access FLWT and FCKMHZ. */ @@ -267,118 +267,119 @@ extern "C" { #endif #endif -/* Security attribution for SRAM registers. */ + /* Security attribution for SRAM registers. */ #ifndef BSP_TZ_CFG_SRAMSAR /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (\ + #define BSP_TZ_CFG_SRAMSAR (\ 1 | \ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ 4 | \ 0xFFFFFFF8U) #endif -/* Security attribution for Standby RAM registers. */ + /* Security attribution for Standby RAM registers. */ #ifndef BSP_TZ_CFG_STBRAMSAR -#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) + #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) #endif -/* Security attribution for the DMAC Bus Master MPU settings. */ + /* Security attribution for the DMAC Bus Master MPU settings. */ #ifndef BSP_TZ_CFG_MMPUSARA -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ -#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) #endif -/* Security Attribution Register A for BUS Control registers. */ + /* Security Attribution Register A for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARA -#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) #endif -/* Security Attribution Register B for BUS Control registers. */ + /* Security Attribution Register B for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARB -#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) #endif -/* Enable Uninitialized Non-Secure Application Fallback. */ + /* Enable Uninitialized Non-Secure Application Fallback. */ #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK -#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) #endif -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -/* Option Function Select Register 1 Security Attribution */ + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + + /* Option Function Select Register 1 Security Attribution */ #ifndef BSP_CFG_ROM_REG_OFS1_SEL #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) #else -#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) #endif #endif -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -/* Dual Mode Select Register */ + /* Dual Mode Select Register */ #ifndef BSP_CFG_ROM_REG_DUALSEL -#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) + #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU) #endif -/* Block Protection Register 0 */ + /* Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_BPS0 -#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) #endif -/* Block Protection Register 1 */ + /* Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_BPS1 -#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) #endif -/* Block Protection Register 2 */ + /* Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_BPS2 -#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) #endif -/* Block Protection Register 3 */ + /* Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_BPS3 -#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) #endif -/* Permanent Block Protection Register 0 */ + /* Permanent Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_PBPS0 -#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) #endif -/* Permanent Block Protection Register 1 */ + /* Permanent Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_PBPS1 -#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) #endif -/* Permanent Block Protection Register 2 */ + /* Permanent Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_PBPS2 -#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) #endif -/* Permanent Block Protection Register 3 */ + /* Permanent Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_PBPS3 -#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) #endif -/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL0 -#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) + #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) #endif -/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL1 -#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) + #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) #endif -/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL2 -#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) + #define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU) #endif -/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL3 -#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) + #define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU) #endif #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) #endif #ifdef __cplusplus diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..8ed58a11b --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,67 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define ARDUINO_A0_MIKROBUS_AN (BSP_IO_PORT_00_PIN_00) +#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_01) +#define ARDUINO_A2 (BSP_IO_PORT_00_PIN_03) +#define SW1 (BSP_IO_PORT_00_PIN_05) +#define SW2 (BSP_IO_PORT_00_PIN_06) +#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_07) +#define PMOD1_INT (BSP_IO_PORT_00_PIN_08) +#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14) +#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15) +#define ARDUINO_RX_MIKROBUS_RX (BSP_IO_PORT_01_PIN_00) +#define ARDUINO_TX_MIKROBUS_TX (BSP_IO_PORT_01_PIN_01) +#define ARDUINO_D2 (BSP_IO_PORT_01_PIN_05) +#define ARDUINO_D3 (BSP_IO_PORT_01_PIN_11) +#define MIKROBUS_RST (BSP_IO_PORT_01_PIN_15) +#define ARDUINO_MISO_MIKROBUS_MISO_PMOD1_MISO (BSP_IO_PORT_02_PIN_02) +#define ARDUINO_MOSI_MIKROBUS_MOSI_PMOD1_MOSI (BSP_IO_PORT_02_PIN_03) +#define ARDUINO_CLK_MIKROBUS_CLK_PMOD1_CLK (BSP_IO_PORT_02_PIN_04) +#define ARDUINO_SS_MIKCRBUS_SS (BSP_IO_PORT_02_PIN_05) +#define PMOD1_SS1 (BSP_IO_PORT_02_PIN_06) +#define PMOD1_SS2 (BSP_IO_PORT_02_PIN_07) +#define PMOD1_SS3 (BSP_IO_PORT_03_PIN_02) +#define ARDUINO_D9 (BSP_IO_PORT_03_PIN_03) +#define ARDUINO_D7 (BSP_IO_PORT_03_PIN_04) +#define QSPI_CLK (BSP_IO_PORT_03_PIN_05) +#define QSPI_SSL (BSP_IO_PORT_03_PIN_06) +#define QSPI_IO0 (BSP_IO_PORT_03_PIN_07) +#define QSPI_IO1 (BSP_IO_PORT_03_PIN_08) +#define QSPI_IO2 (BSP_IO_PORT_03_PIN_09) +#define QSPI_IO3 (BSP_IO_PORT_03_PIN_10) +#define PMOD1_RST (BSP_IO_PORT_03_PIN_11) +#define LED3 (BSP_IO_PORT_04_PIN_00) +#define LED2 (BSP_IO_PORT_04_PIN_04) +#define USB_VBUS (BSP_IO_PORT_04_PIN_07) +#define ARDUINO_D6_MIKROBUS_PWM (BSP_IO_PORT_04_PIN_08) +#define MIKROBUS_INT (BSP_IO_PORT_04_PIN_09) +#define PMOD2_INT (BSP_IO_PORT_04_PIN_14) +#define LED1 (BSP_IO_PORT_04_PIN_15) +#define USB_VBUS_EN (BSP_IO_PORT_05_PIN_00) +#define USB_VBUS_OC (BSP_IO_PORT_05_PIN_01) +#define GROVE2_AN1 (BSP_IO_PORT_05_PIN_05) +#define GROVE2_AN2 (BSP_IO_PORT_05_PIN_06) +#define GROVE1_SDA_QWIIC_SDA (BSP_IO_PORT_05_PIN_11) +#define GROVE1_SCL_QWIIC_SCL (BSP_IO_PORT_05_PIN_12) +#define ARDUINO_SCL_MIKROBUS_SCL (BSP_IO_PORT_06_PIN_01) +#define ARDUINO_SDA_MIKROBUS_SDA (BSP_IO_PORT_06_PIN_02) +#define ARDUINO_D8 (BSP_IO_PORT_06_PIN_11) +#define ARDUINO_RST (BSP_IO_PORT_06_PIN_12) +#define PMOD2_RST (BSP_IO_PORT_07_PIN_08) +#define PMOD2_SS2 (BSP_IO_PORT_07_PIN_09) +#define PMOD2_SS3 (BSP_IO_PORT_07_PIN_10) +#define ARDUINO_D5 (BSP_IO_PORT_07_PIN_12) +#define ARDUINO_D4 (BSP_IO_PORT_07_PIN_13) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M3 EK */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h index 80641945d..3eac2985e 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h @@ -7,10 +7,10 @@ #define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL Mul x24.0 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */ #define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */ -#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL2 Mul x24.0 */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ #define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ @@ -21,5 +21,5 @@ #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ #define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ #define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ #endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..bf30782cf --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c @@ -0,0 +1,263 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_03_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_03_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_03_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_GPT1) + }, + { + .pin = BSP_IO_PORT_04_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_04_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_04_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_05_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_05_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_05_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_05_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_06_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_06_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_06_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_06_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_07_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_07_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_07_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_07_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_07_PIN_13, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld b/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld new file mode 100644 index 000000000..605eef7d2 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld @@ -0,0 +1,769 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld new file mode 100644 index 000000000..04d7de497 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld @@ -0,0 +1,22 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x20000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x0100A100; + OPTION_SETTING_LENGTH = 0x100; + OPTION_SETTING_S_START = 0x0100A200; + OPTION_SETTING_S_LENGTH = 0x100; + ID_CODE_START = 0x00000000; + ID_CODE_LENGTH = 0x0; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x4000000; + OSPI_DEVICE_0_START = 0x80020000; + OSPI_DEVICE_0_LENGTH = 0x0; + OSPI_DEVICE_1_START = 0x80030000; + OSPI_DEVICE_1_LENGTH = 0x0; diff --git a/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..1d75f1b72 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml @@ -0,0 +1,432 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<raConfiguration version="9"> + <generalSettings> + <option key="#Board#" value="board.ra4m3ek"/> + <option key="CPU" value="RA4M3"/> + <option key="Core" value="CM33"/> + <option key="#TargetName#" value="R7FA4M3AF3CFB"/> + <option key="#TargetARCHITECTURE#" value="cortex-m33"/> + <option key="#DeviceCommand#" value="R7FA4M3AF"/> + <option key="#RTOS#" value="_none"/> + <option key="#pinconfiguration#" value="R7FA4M3AF3CFB.pincfg"/> + <option key="#FSPVersion#" value="5.6.0"/> + <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra4m3_ek##"/> + <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/> + </generalSettings> + <raBspConfiguration> + <config id="config.bsp.ra4m3.R7FA4M3AF3CFB"> + <property id="config.bsp.part_number" value="config.bsp.part_number.value"/> + <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/> + <property id="config.bsp.rom_size_bytes_hidden" value="1048576"/> + <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/> + <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/> + <property id="config.bsp.package_style" value="config.bsp.package_style.value"/> + <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/> + <property id="config.bsp.irq_count_hidden" value="96"/> + </config> + <config id="config.bsp.ra4m3"> + <property id="config.bsp.series" value="config.bsp.series.value"/> + </config> + <config id="config.bsp.ra4m3.fsp"> + <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/> + <property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/> + <property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/> + <property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/> + <property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/> + <property id="config.bsp.fsp.tz.csar" value="config.bsp.fsp.tz.csar.both"/> + <property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/> + <property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/> + <property id="config.bsp.fsp.tz.sramsar.sramprcr" value="config.bsp.fsp.tz.sramsar.sramprcr.both"/> + <property id="config.bsp.fsp.tz.sramsar.sramecc" value="config.bsp.fsp.tz.sramsar.sramecc.both"/> + <property id="config.bsp.fsp.tz.stbramsar" value="config.bsp.fsp.tz.stbramsar.both"/> + <property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/> + <property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/> + <property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/> + <property id="config.bsp.fsp.cache_line_size" value="config.bsp.fsp.cache_line_size.32"/> + <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/> + <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/> + <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/> + <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0_level" value="config.bsp.fsp.OFS1_SEL.voltage_detection0_level.secure"/> + <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.start" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.start.secure"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/> + <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/> + <property id="config.bsp.fsp.BPS.BPS0" value=""/> + <property id="config.bsp.fsp.BPS.BPS1" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS0" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS1" value=""/> + <property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/> + <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/> + <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="50000000"/> + <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="16666666"/> + <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/> + <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="25000000"/> + <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/> + <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/> + <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x1"/> + <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/> + <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x1"/> + <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0219"/> + <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/> + <property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="32767"/> + </config> + <config id="config.bsp.ra"> + <property id="config.bsp.common.main" value="0x800"/> + <property id="config.bsp.common.heap" value="0x800"/> + <property id="config.bsp.common.vcc" value="3300"/> + <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/> + <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/> + <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/> + <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/> + <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/> + <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/> + <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/> + <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/> + <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/> + <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/> + <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/> + <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/> + </config> + </raBspConfiguration> + <raClockConfiguration> + <node id="board.clock.xtal.freq" mul="24000000" option="_edit"/> + <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/> + <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/> + <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/> + <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/> + <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/> + <node id="board.clock.pll.div" option="board.clock.pll.div.3"/> + <node id="board.clock.pll.mul" option="board.clock.pll.mul.250"/> + <node id="board.clock.pll.display" option="board.clock.pll.display.value"/> + <node id="board.clock.pll2.source" option="board.clock.pll2.source.xtal"/> + <node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/> + <node id="board.clock.pll2.mul" option="board.clock.pll2.mul.200"/> + <node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/> + <node id="board.clock.clock.source" option="board.clock.clock.source.pll"/> + <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/> + <node id="board.clock.uclk.source" option="board.clock.uclk.source.pll2"/> + <node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/> + <node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/> + <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/> + <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/> + <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/> + <node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/> + <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/> + <node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/> + <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/> + <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/> + <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/> + <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/> + <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/> + <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/> + <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/> + <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/> + </raClockConfiguration> + <raComponentSelection> + <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0"> + <description>Simple application that blinks an LED. No RTOS included.</description> + <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0"> + <description>Board Support Package Common Files</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0"> + <description>I/O Port</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0"> + <description>Arm CMSIS Version 6 - Core (M)</description> + <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m3" subgroup="device" variant="R7FA4M3AF3CFB" vendor="Renesas" version="5.6.0"> + <description>Board support package for R7FA4M3AF3CFB</description> + <originalPack>Renesas.RA_mcu_ra4m3.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m3" subgroup="device" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA4M3</description> + <originalPack>Renesas.RA_mcu_ra4m3.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m3" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA4M3 - FSP Data</description> + <originalPack>Renesas.RA_mcu_ra4m3.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m3" subgroup="events" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA4M3 - Events</description> + <originalPack>Renesas.RA_mcu_ra4m3.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra4m3_ek" variant="" vendor="Renesas" version="5.6.0"> + <description>RA4M3-EK Board Support Files</description> + <originalPack>Renesas.RA_board_ra4m3_ek.5.6.0.pack</originalPack> + </component> + </raComponentSelection> + <raElcConfiguration/> + <raIcuConfiguration/> + <raModuleConfiguration> + <module id="module.driver.ioport_on_ioport.0"> + <property id="module.driver.ioport.name" value="g_ioport"/> + <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/> + <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/> + </module> + <context id="_hal.0"> + <stack module="module.driver.ioport_on_ioport.0"/> + </context> + <config id="config.driver.ioport"> + <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/> + </config> + </raModuleConfiguration> + <raPinConfiguration> + <symbolicName propertyId="p000.symbolic_name" value="ARDUINO_A0_MIKROBUS_AN"/> + <symbolicName propertyId="p001.symbolic_name" value="ARDUINO_A1"/> + <symbolicName propertyId="p003.symbolic_name" value="ARDUINO_A2"/> + <symbolicName propertyId="p005.symbolic_name" value="SW1"/> + <symbolicName propertyId="p006.symbolic_name" value="SW2"/> + <symbolicName propertyId="p007.symbolic_name" value="ARDUINO_A3"/> + <symbolicName propertyId="p008.symbolic_name" value="PMOD1_INT"/> + <symbolicName propertyId="p014.symbolic_name" value="ARDUINO_A4"/> + <symbolicName propertyId="p015.symbolic_name" value="ARDUINO_A5"/> + <symbolicName propertyId="p100.symbolic_name" value="ARDUINO_RX_MIKROBUS_RX"/> + <symbolicName propertyId="p101.symbolic_name" value="ARDUINO_TX_MIKROBUS_TX"/> + <symbolicName propertyId="p105.symbolic_name" value="ARDUINO_D2"/> + <symbolicName propertyId="p111.symbolic_name" value="ARDUINO_D3"/> + <symbolicName propertyId="p115.symbolic_name" value="MIKROBUS_RST"/> + <symbolicName propertyId="p202.symbolic_name" value="ARDUINO_MISO_MIKROBUS_MISO_PMOD1_MISO"/> + <symbolicName propertyId="p203.symbolic_name" value="ARDUINO_MOSI_MIKROBUS_MOSI_PMOD1_MOSI"/> + <symbolicName propertyId="p204.symbolic_name" value="ARDUINO_CLK_MIKROBUS_CLK_PMOD1_CLK"/> + <symbolicName propertyId="p205.symbolic_name" value="ARDUINO_SS_MIKCRBUS_SS"/> + <symbolicName propertyId="p206.symbolic_name" value="PMOD1_SS1"/> + <symbolicName propertyId="p207.symbolic_name" value="PMOD1_SS2"/> + <symbolicName propertyId="p302.symbolic_name" value="PMOD1_SS3"/> + <symbolicName propertyId="p303.symbolic_name" value="ARDUINO_D9"/> + <symbolicName propertyId="p304.symbolic_name" value="ARDUINO_D7"/> + <symbolicName propertyId="p305.symbolic_name" value="QSPI_CLK"/> + <symbolicName propertyId="p306.symbolic_name" value="QSPI_SSL"/> + <symbolicName propertyId="p307.symbolic_name" value="QSPI_IO0"/> + <symbolicName propertyId="p308.symbolic_name" value="QSPI_IO1"/> + <symbolicName propertyId="p309.symbolic_name" value="QSPI_IO2"/> + <symbolicName propertyId="p310.symbolic_name" value="QSPI_IO3"/> + <symbolicName propertyId="p311.symbolic_name" value="PMOD1_RST"/> + <symbolicName propertyId="p400.symbolic_name" value="LED3"/> + <symbolicName propertyId="p404.symbolic_name" value="LED2"/> + <symbolicName propertyId="p407.symbolic_name" value="USB_VBUS"/> + <symbolicName propertyId="p408.symbolic_name" value="ARDUINO_D6_MIKROBUS_PWM"/> + <symbolicName propertyId="p409.symbolic_name" value="MIKROBUS_INT"/> + <symbolicName propertyId="p414.symbolic_name" value="PMOD2_INT"/> + <symbolicName propertyId="p415.symbolic_name" value="LED1"/> + <symbolicName propertyId="p500.symbolic_name" value="USB_VBUS_EN"/> + <symbolicName propertyId="p501.symbolic_name" value="USB_VBUS_OC"/> + <symbolicName propertyId="p505.symbolic_name" value="GROVE2_AN1"/> + <symbolicName propertyId="p506.symbolic_name" value="GROVE2_AN2"/> + <symbolicName propertyId="p511.symbolic_name" value="GROVE1_SDA_QWIIC_SDA"/> + <symbolicName propertyId="p512.symbolic_name" value="GROVE1_SCL_QWIIC_SCL"/> + <symbolicName propertyId="p601.symbolic_name" value="ARDUINO_SCL_MIKROBUS_SCL"/> + <symbolicName propertyId="p602.symbolic_name" value="ARDUINO_SDA_MIKROBUS_SDA"/> + <symbolicName propertyId="p611.symbolic_name" value="ARDUINO_D8"/> + <symbolicName propertyId="p612.symbolic_name" value="ARDUINO_RST"/> + <symbolicName propertyId="p708.symbolic_name" value="PMOD2_RST"/> + <symbolicName propertyId="p709.symbolic_name" value="PMOD2_SS2"/> + <symbolicName propertyId="p710.symbolic_name" value="PMOD2_SS3"/> + <symbolicName propertyId="p712.symbolic_name" value="ARDUINO_D5"/> + <symbolicName propertyId="p713.symbolic_name" value="ARDUINO_D4"/> + <pincfg active="true" name="RA4M3 EK" selected="true" symbol="g_bsp_pin_cfg"> + <configSetting altId="adc0.an00.p000" configurationId="adc0.an00"/> + <configSetting altId="adc0.an01.p001" configurationId="adc0.an01"/> + <configSetting altId="adc0.an03.p003" configurationId="adc0.an03"/> + <configSetting altId="adc0.an07.p007" configurationId="adc0.an07"/> + <configSetting altId="adc0.an12.p014" configurationId="adc0.an12"/> + <configSetting altId="adc0.an13.p015" configurationId="adc0.an13"/> + <configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/> + <configSetting altId="adc1.an21.p505" configurationId="adc1.an21"/> + <configSetting altId="adc1.an22.p506" configurationId="adc1.an22"/> + <configSetting altId="adc1.mode.custom" configurationId="adc1.mode"/> + <configSetting altId="cgc0.extal.p212" configurationId="cgc0.extal"/> + <configSetting altId="cgc0.mode.mainsub" configurationId="cgc0.mode"/> + <configSetting altId="cgc0.xtal.p213" configurationId="cgc0.xtal"/> + <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/> + <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/> + <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/> + <configSetting altId="gpt6.gtiocb.p408" configurationId="gpt6.gtiocb"/> + <configSetting altId="gpt6.mode.gtiocaorgtiocb.free" configurationId="gpt6.mode"/> + <configSetting altId="iic1.mode.enabled.a" configurationId="iic1.mode"/> + <configSetting altId="iic1.scl.p512" configurationId="iic1.scl"/> + <configSetting altId="iic1.sda.p511" configurationId="iic1.sda"/> + <configSetting altId="p000.asel" configurationId="p000"/> + <configSetting altId="p000.gpio_mode.gpio_mode_an" configurationId="p000.gpio_mode"/> + <configSetting altId="p001.asel" configurationId="p001"/> + <configSetting altId="p001.gpio_mode.gpio_mode_an" configurationId="p001.gpio_mode"/> + <configSetting altId="p003.asel" configurationId="p003"/> + <configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/> + <configSetting altId="p005.input" configurationId="p005"/> + <configSetting altId="p005.gpio_mode.gpio_mode_in" configurationId="p005.gpio_mode"/> + <configSetting altId="p006.input" configurationId="p006"/> + <configSetting altId="p006.gpio_irq.gpio_irq_enabled" configurationId="p006.gpio_irq"/> + <configSetting altId="p006.gpio_mode.gpio_mode_in" configurationId="p006.gpio_mode"/> + <configSetting altId="p007.asel" configurationId="p007"/> + <configSetting altId="p007.gpio_mode.gpio_mode_an" configurationId="p007.gpio_mode"/> + <configSetting altId="p008.input" configurationId="p008"/> + <configSetting altId="p008.gpio_irq.gpio_irq_enabled" configurationId="p008.gpio_irq"/> + <configSetting altId="p008.gpio_mode.gpio_mode_in" configurationId="p008.gpio_mode"/> + <configSetting altId="p008.gpio_pupd.gpio_pupd_ip_up" configurationId="p008.gpio_pupd"/> + <configSetting altId="p014.asel" configurationId="p014"/> + <configSetting altId="p014.gpio_mode.gpio_mode_an" configurationId="p014.gpio_mode"/> + <configSetting altId="p015.asel" configurationId="p015"/> + <configSetting altId="p015.gpio_mode.gpio_mode_an" configurationId="p015.gpio_mode"/> + <configSetting altId="p100.sci0.rxd" configurationId="p100"/> + <configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/> + <configSetting altId="p101.sci0.txd" configurationId="p101"/> + <configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/> + <configSetting altId="p105.output.low" configurationId="p105"/> + <configSetting altId="p105.gpio_mode.gpio_mode_out.low" configurationId="p105.gpio_mode"/> + <configSetting altId="p108.debug0.swdio" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p111.output.low" configurationId="p111"/> + <configSetting altId="p111.gpio_mode.gpio_mode_out.low" configurationId="p111.gpio_mode"/> + <configSetting altId="p115.output.low" configurationId="p115"/> + <configSetting altId="p115.gpio_mode.gpio_mode_out.low" configurationId="p115.gpio_mode"/> + <configSetting altId="p202.spi0.miso" configurationId="p202"/> + <configSetting altId="p202.gpio_mode.gpio_mode_peripheral" configurationId="p202.gpio_mode"/> + <configSetting altId="p203.spi0.mosi" configurationId="p203"/> + <configSetting altId="p203.gpio_mode.gpio_mode_peripheral" configurationId="p203.gpio_mode"/> + <configSetting altId="p204.spi0.rspck" configurationId="p204"/> + <configSetting altId="p204.gpio_mode.gpio_mode_peripheral" configurationId="p204.gpio_mode"/> + <configSetting altId="p205.spi0.ssl0" configurationId="p205"/> + <configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/> + <configSetting altId="p206.spi0.ssl1" configurationId="p206"/> + <configSetting altId="p206.gpio_mode.gpio_mode_peripheral" configurationId="p206.gpio_mode"/> + <configSetting altId="p207.spi0.ssl2" configurationId="p207"/> + <configSetting altId="p207.gpio_mode.gpio_mode_peripheral" configurationId="p207.gpio_mode"/> + <configSetting altId="p212.cgc0.extal" configurationId="p212"/> + <configSetting altId="p212.gpio_mode.gpio_mode_peripheral" configurationId="p212.gpio_mode"/> + <configSetting altId="p213.cgc0.xtal" configurationId="p213"/> + <configSetting altId="p213.gpio_mode.gpio_mode_peripheral" configurationId="p213.gpio_mode"/> + <configSetting altId="p300.debug0.swclk" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + <configSetting altId="p302.spi0.ssl3" configurationId="p302"/> + <configSetting altId="p302.gpio_mode.gpio_mode_peripheral" configurationId="p302.gpio_mode"/> + <configSetting altId="p303.output.low" configurationId="p303"/> + <configSetting altId="p303.gpio_mode.gpio_mode_out.low" configurationId="p303.gpio_mode"/> + <configSetting altId="p304.output.low" configurationId="p304"/> + <configSetting altId="p304.gpio_mode.gpio_mode_out.low" configurationId="p304.gpio_mode"/> + <configSetting altId="p305.qspi0.qspclk" configurationId="p305"/> + <configSetting altId="p305.gpio_mode.gpio_mode_peripheral" configurationId="p305.gpio_mode"/> + <configSetting altId="p306.qspi0.qssl" configurationId="p306"/> + <configSetting altId="p306.gpio_mode.gpio_mode_peripheral" configurationId="p306.gpio_mode"/> + <configSetting altId="p307.qspi0.qio0" configurationId="p307"/> + <configSetting altId="p307.gpio_mode.gpio_mode_peripheral" configurationId="p307.gpio_mode"/> + <configSetting altId="p308.qspi0.qio1" configurationId="p308"/> + <configSetting altId="p308.gpio_mode.gpio_mode_peripheral" configurationId="p308.gpio_mode"/> + <configSetting altId="p309.qspi0.qio2" configurationId="p309"/> + <configSetting altId="p309.gpio_mode.gpio_mode_peripheral" configurationId="p309.gpio_mode"/> + <configSetting altId="p310.qspi0.qio3" configurationId="p310"/> + <configSetting altId="p310.gpio_mode.gpio_mode_peripheral" configurationId="p310.gpio_mode"/> + <configSetting altId="p311.output.low" configurationId="p311"/> + <configSetting altId="p311.gpio_mode.gpio_mode_out.low" configurationId="p311.gpio_mode"/> + <configSetting altId="p400.output.low" configurationId="p400"/> + <configSetting altId="p400.gpio_mode.gpio_mode_out.low" configurationId="p400.gpio_mode"/> + <configSetting altId="p404.output.low" configurationId="p404"/> + <configSetting altId="p404.gpio_mode.gpio_mode_out.low" configurationId="p404.gpio_mode"/> + <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/> + <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/> + <configSetting altId="p408.gpt6.gtiocb" configurationId="p408"/> + <configSetting altId="p408.gpio_mode.gpio_mode_peripheral" configurationId="p408.gpio_mode"/> + <configSetting altId="p409.input" configurationId="p409"/> + <configSetting altId="p409.gpio_irq.gpio_irq_enabled" configurationId="p409.gpio_irq"/> + <configSetting altId="p409.gpio_mode.gpio_mode_in" configurationId="p409.gpio_mode"/> + <configSetting altId="p409.gpio_pupd.gpio_pupd_ip_up" configurationId="p409.gpio_pupd"/> + <configSetting altId="p414.input" configurationId="p414"/> + <configSetting altId="p414.gpio_irq.gpio_irq_enabled" configurationId="p414.gpio_irq"/> + <configSetting altId="p414.gpio_mode.gpio_mode_in" configurationId="p414.gpio_mode"/> + <configSetting altId="p414.gpio_pupd.gpio_pupd_ip_up" configurationId="p414.gpio_pupd"/> + <configSetting altId="p415.output.low" configurationId="p415"/> + <configSetting altId="p415.gpio_mode.gpio_mode_out.low" configurationId="p415.gpio_mode"/> + <configSetting altId="p500.usbfs0.vbusen" configurationId="p500"/> + <configSetting altId="p500.gpio_mode.gpio_mode_peripheral" configurationId="p500.gpio_mode"/> + <configSetting altId="p501.usbfs0.ovrcura" configurationId="p501"/> + <configSetting altId="p501.gpio_mode.gpio_mode_peripheral" configurationId="p501.gpio_mode"/> + <configSetting altId="p505.asel" configurationId="p505"/> + <configSetting altId="p505.gpio_mode.gpio_mode_an" configurationId="p505.gpio_mode"/> + <configSetting altId="p506.asel" configurationId="p506"/> + <configSetting altId="p506.gpio_mode.gpio_mode_an" configurationId="p506.gpio_mode"/> + <configSetting altId="p511.iic1.sda" configurationId="p511"/> + <configSetting altId="p511.gpio_mode.gpio_mode_peripheral" configurationId="p511.gpio_mode"/> + <configSetting altId="p512.iic1.scl" configurationId="p512"/> + <configSetting altId="p512.gpio_mode.gpio_mode_peripheral" configurationId="p512.gpio_mode"/> + <configSetting altId="p601.sci9.scl" configurationId="p601"/> + <configSetting altId="p601.gpio_mode.gpio_mode_peripheral" configurationId="p601.gpio_mode"/> + <configSetting altId="p601.gpio_otype.gpio_otype_n_ch_od" configurationId="p601.gpio_otype"/> + <configSetting altId="p602.sci9.sda" configurationId="p602"/> + <configSetting altId="p602.gpio_mode.gpio_mode_peripheral" configurationId="p602.gpio_mode"/> + <configSetting altId="p602.gpio_otype.gpio_otype_n_ch_od" configurationId="p602.gpio_otype"/> + <configSetting altId="p611.output.low" configurationId="p611"/> + <configSetting altId="p611.gpio_mode.gpio_mode_out.low" configurationId="p611.gpio_mode"/> + <configSetting altId="p612.output.low" configurationId="p612"/> + <configSetting altId="p612.gpio_mode.gpio_mode_out.low" configurationId="p612.gpio_mode"/> + <configSetting altId="p708.output.low" configurationId="p708"/> + <configSetting altId="p708.gpio_mode.gpio_mode_out.low" configurationId="p708.gpio_mode"/> + <configSetting altId="p709.output.low" configurationId="p709"/> + <configSetting altId="p709.gpio_mode.gpio_mode_out.low" configurationId="p709.gpio_mode"/> + <configSetting altId="p710.output.low" configurationId="p710"/> + <configSetting altId="p710.gpio_mode.gpio_mode_out.low" configurationId="p710.gpio_mode"/> + <configSetting altId="p712.output.low" configurationId="p712"/> + <configSetting altId="p712.gpio_mode.gpio_mode_out.low" configurationId="p712.gpio_mode"/> + <configSetting altId="p713.output.low" configurationId="p713"/> + <configSetting altId="p713.gpio_mode.gpio_mode_out.low" configurationId="p713.gpio_mode"/> + <configSetting altId="qspi0.mode.quad.b" configurationId="qspi0.mode"/> + <configSetting altId="qspi0.pairing.b" configurationId="qspi0.pairing"/> + <configSetting altId="qspi0.qio0.p307" configurationId="qspi0.qio0"/> + <configSetting altId="qspi0.qio1.p308" configurationId="qspi0.qio1"/> + <configSetting altId="qspi0.qio2.p309" configurationId="qspi0.qio2"/> + <configSetting altId="qspi0.qio3.p310" configurationId="qspi0.qio3"/> + <configSetting altId="qspi0.qspclk.p305" configurationId="qspi0.qspclk"/> + <configSetting altId="qspi0.qssl.p306" configurationId="qspi0.qssl"/> + <configSetting altId="sci0.mode.asynchronous.free" configurationId="sci0.mode"/> + <configSetting altId="sci0.rxd.p100" configurationId="sci0.rxd"/> + <configSetting altId="sci0.txd.p101" configurationId="sci0.txd"/> + <configSetting altId="sci9.mode.iic.free" configurationId="sci9.mode"/> + <configSetting altId="sci9.scl.p601" configurationId="sci9.scl"/> + <configSetting altId="sci9.sda.p602" configurationId="sci9.sda"/> + <configSetting altId="spi0.miso.p202" configurationId="spi0.miso"/> + <configSetting altId="spi0.mode.enabled.free" configurationId="spi0.mode"/> + <configSetting altId="spi0.mosi.p203" configurationId="spi0.mosi"/> + <configSetting altId="spi0.pairing.free" configurationId="spi0.pairing"/> + <configSetting altId="spi0.rspck.p204" configurationId="spi0.rspck"/> + <configSetting altId="spi0.ssl0.p205" configurationId="spi0.ssl0"/> + <configSetting altId="spi0.ssl1.p206" configurationId="spi0.ssl1"/> + <configSetting altId="spi0.ssl2.p207" configurationId="spi0.ssl2"/> + <configSetting altId="spi0.ssl3.p302" configurationId="spi0.ssl3"/> + <configSetting altId="usbfs0.mode.custom" configurationId="usbfs0.mode"/> + <configSetting altId="usbfs0.ovrcura.p501" configurationId="usbfs0.ovrcura"/> + <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/> + <configSetting altId="usbfs0.vbusen.p500" configurationId="usbfs0.vbusen"/> + </pincfg> + <pincfg active="false" name="R7FA4M3AF3CFB.pincfg" selected="false" symbol=""> + <configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/> + <configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/> + <configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/> + <configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/> + <configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/> + <configSetting altId="p108.debug0.tms" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p109.debug0.tdo" configurationId="p109"/> + <configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/> + <configSetting altId="p110.debug0.tdi" configurationId="p110"/> + <configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/> + <configSetting altId="p300.debug0.tck" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + </pincfg> + </raPinConfiguration> +</raConfiguration> diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.cmake b/hw/bsp/ra/boards/ra6m1_ek/board.cmake index b2f41a354..957e8394d 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m1_ek/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra6m1) set(JLINK_DEVICE R7FA6M1AD) diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h index f73a08fc0..2024a0335 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/board.h +++ b/hw/bsp/ra/boards/ra6m1_ek/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: RA6M1 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m1-evaluation-kit-ra6m1-mcu-group +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ @@ -31,19 +36,9 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_01_PIN_12 -#define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_04_PIN_15 +#define LED_STATE_ON 1 #define BUTTON_STATE_ACTIVE 0 -static const ioport_pin_cfg_t board_pin_cfg[] = { - { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT }, - { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, - // USB FS - { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS }, -}; - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 772e5e5b1..000000000 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (2) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) -#else - #define BSP_CFG_RTOS (0) -#endif -#endif - -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif - -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) -#endif - -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x1000) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 40bb3a3bf..000000000 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA6M1AD3CFP -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (524288) -#define BSP_RAM_SIZE_BYTES (262144) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (100) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h deleted file mode 100644 index 5fedd754f..000000000 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,84 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA6M1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif - -#define BSP_CFG_FLL_ENABLE (0) - -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) - #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) -#else - /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ - #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) - #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) - #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) - #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..90afbdef3 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x1000) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h index bd6a901c3..bd6a901c3 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..5e7841442 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M1AD3CFP + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (524288) + #define BSP_RAM_SIZE_BYTES (262144) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (100) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..16349b5ff --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,84 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA6M1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + + #define BSP_CFG_FLL_ENABLE (0) + + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) + + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) + #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #endif + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + + /* + ID Code + Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings. + WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled. + */ + #if defined(BSP_ID_CODE_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else + /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ + #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..8ba9aafba --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define LED1 (BSP_IO_PORT_01_PIN_12) +#define SW1 (BSP_IO_PORT_04_PIN_15) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M1-EK.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h index 945a6010b..945a6010b 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..80774b0a5 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c @@ -0,0 +1,115 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_02_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld new file mode 100644 index 000000000..605eef7d2 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld @@ -0,0 +1,769 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld new file mode 100644 index 000000000..9d973c737 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld @@ -0,0 +1,22 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x1FFE0000; + RAM_LENGTH = 0x40000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x80000; + DATA_FLASH_START = 0x40100000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x00000000; + OPTION_SETTING_LENGTH = 0x0; + OPTION_SETTING_S_START = 0x80000000; + OPTION_SETTING_S_LENGTH = 0x0; + ID_CODE_START = 0x0100A150; + ID_CODE_LENGTH = 0x10; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x4000000; + OSPI_DEVICE_0_START = 0x80020000; + OSPI_DEVICE_0_LENGTH = 0x0; + OSPI_DEVICE_1_START = 0x80030000; + OSPI_DEVICE_1_LENGTH = 0x0; diff --git a/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..4c5d77ed0 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml @@ -0,0 +1,270 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<raConfiguration version="9"> + <generalSettings> + <option key="#Board#" value="board.ra6m1ek"/> + <option key="CPU" value="RA6M1"/> + <option key="Core" value="CM4"/> + <option key="#TargetName#" value="R7FA6M1AD3CFP"/> + <option key="#TargetARCHITECTURE#" value="cortex-m4"/> + <option key="#DeviceCommand#" value="R7FA6M1AD"/> + <option key="#RTOS#" value="_none"/> + <option key="#pinconfiguration#" value="R7FA6M1AD3CFP.pincfg"/> + <option key="#FSPVersion#" value="5.6.0"/> + <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra6m1_ek##"/> + <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/> + </generalSettings> + <raBspConfiguration> + <config id="config.bsp.ra6m1.R7FA6M1AD3CFP"> + <property id="config.bsp.part_number" value="config.bsp.part_number.value"/> + <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/> + <property id="config.bsp.rom_size_bytes_hidden" value="524288"/> + <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/> + <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/> + <property id="config.bsp.package_style" value="config.bsp.package_style.value"/> + <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/> + <property id="config.bsp.irq_count_hidden" value="96"/> + </config> + <config id="config.bsp.ra6m1"> + <property id="config.bsp.series" value="config.bsp.series.value"/> + </config> + <config id="config.bsp.ra6m1.fsp"> + <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/> + <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/> + <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/> + <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/> + <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/> + <property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/> + <property id="config.bsp.fsp.mpu_pc0_start" value="0xFFFFFFFC"/> + <property id="config.bsp.fsp.mpu_pc0_end" value="0xFFFFFFFF"/> + <property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/> + <property id="config.bsp.fsp.mpu_pc1_start" value="0xFFFFFFFC"/> + <property id="config.bsp.fsp.mpu_pc1_end" value="0xFFFFFFFF"/> + <property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg0_start" value="0x00FFFFFC"/> + <property id="config.bsp.fsp.mpu_reg0_end" value="0x00FFFFFF"/> + <property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/> + <property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/> + <property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/> + <property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/> + <property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/> + <property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/> + <property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/> + <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/> + <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="60000000"/> + <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="20000000"/> + <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="1"/> + <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/> + <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="30000000"/> + <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="30000000"/> + <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/> + <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x1"/> + <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/> + <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x1"/> + <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/> + <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/> + <property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/> + <property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/> + <property id="config.bsp.common.id1" value=""/> + <property id="config.bsp.common.id2" value=""/> + <property id="config.bsp.common.id3" value=""/> + <property id="config.bsp.common.id4" value=""/> + <property id="config.bsp.common.id_fixed" value=""/> + </config> + <config id="config.bsp.ra"> + <property id="config.bsp.common.main" value="0x1000"/> + <property id="config.bsp.common.heap" value="0x1000"/> + <property id="config.bsp.common.vcc" value="3300"/> + <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/> + <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/> + <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/> + <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/> + <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/> + <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/> + <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/> + <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/> + <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/> + <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/> + <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/> + <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/> + </config> + </raBspConfiguration> + <raClockConfiguration> + <node id="board.clock.xtal.freq" mul="12000000" option="_edit"/> + <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/> + <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/> + <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/> + <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/> + <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/> + <node id="board.clock.pll.div" option="board.clock.pll.div.1"/> + <node id="board.clock.pll.mul" option="board.clock.pll.mul.200"/> + <node id="board.clock.pll.display" option="board.clock.pll.display.value"/> + <node id="board.clock.clock.source" option="board.clock.clock.source.pll"/> + <node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/> + <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/> + <node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/> + <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/> + <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/> + <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/> + <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/> + <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/> + <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/> + <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/> + <node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/> + <node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/> + <node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/> + <node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/> + <node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/> + <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/> + <node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/> + <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/> + <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/> + <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/> + <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/> + </raClockConfiguration> + <raComponentSelection> + <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0"> + <description>Simple application that blinks an LED. No RTOS included.</description> + <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0"> + <description>Board Support Package Common Files</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0"> + <description>I/O Port</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0"> + <description>Arm CMSIS Version 6 - Core (M)</description> + <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra6m1_ek" variant="" vendor="Renesas" version="5.6.0"> + <description>RA6M1-EK Board Support Files</description> + <originalPack>Renesas.RA_board_ra6m1_ek.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m1" subgroup="device" variant="R7FA6M1AD3CFP" vendor="Renesas" version="5.6.0"> + <description>Board support package for R7FA6M1AD3CFP</description> + <originalPack>Renesas.RA_mcu_ra6m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m1" subgroup="device" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA6M1</description> + <originalPack>Renesas.RA_mcu_ra6m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA6M1 - FSP Data</description> + <originalPack>Renesas.RA_mcu_ra6m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m1" subgroup="events" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA6M1 - Events</description> + <originalPack>Renesas.RA_mcu_ra6m1.5.6.0.pack</originalPack> + </component> + </raComponentSelection> + <raElcConfiguration/> + <raIcuConfiguration/> + <raModuleConfiguration> + <module id="module.driver.ioport_on_ioport.0"> + <property id="module.driver.ioport.name" value="g_ioport"/> + <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/> + <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/> + </module> + <context id="_hal.0"> + <stack module="module.driver.ioport_on_ioport.0"/> + </context> + <config id="config.driver.ioport"> + <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/> + </config> + </raModuleConfiguration> + <raPinConfiguration> + <symbolicName propertyId="p112.symbolic_name" value="LED1"/> + <symbolicName propertyId="p415.symbolic_name" value="SW1"/> + <pincfg active="true" name="RA6M1-EK.pincfg" selected="true" symbol="g_bsp_pin_cfg"> + <configSetting altId="adc1.an00.p004" configurationId="adc1.an00"/> + <configSetting altId="adc1.mode.custom" configurationId="adc1.mode"/> + <configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/> + <configSetting altId="ctsu0.ts02.p207" configurationId="ctsu0.ts02"/> + <configSetting altId="ctsu0.tscap.p205" configurationId="ctsu0.tscap"/> + <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/> + <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/> + <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/> + <configSetting altId="p004.asel" configurationId="p004"/> + <configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/> + <configSetting altId="p100.spi0.miso" configurationId="p100"/> + <configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/> + <configSetting altId="p101.spi0.mosi" configurationId="p101"/> + <configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/> + <configSetting altId="p102.spi0.rspck" configurationId="p102"/> + <configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/> + <configSetting altId="p103.spi0.ssl0" configurationId="p103"/> + <configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/> + <configSetting altId="p104.sci8.rxd" configurationId="p104"/> + <configSetting altId="p104.gpio_mode.gpio_mode_peripheral" configurationId="p104.gpio_mode"/> + <configSetting altId="p105.sci8.txd" configurationId="p105"/> + <configSetting altId="p105.gpio_mode.gpio_mode_peripheral" configurationId="p105.gpio_mode"/> + <configSetting altId="p106.output.low" configurationId="p106"/> + <configSetting altId="p106.gpio_mode.gpio_mode_out.low" configurationId="p106.gpio_mode"/> + <configSetting altId="p107.output.low" configurationId="p107"/> + <configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/> + <configSetting altId="p108.debug0.swdio" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p112.output.low" configurationId="p112"/> + <configSetting altId="p112.gpio_mode.gpio_mode_out.low" configurationId="p112.gpio_mode"/> + <configSetting altId="p201.input" configurationId="p201"/> + <configSetting altId="p201.gpio_mode.gpio_mode_in" configurationId="p201.gpio_mode"/> + <configSetting altId="p205.ctsu0.tscap" configurationId="p205"/> + <configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/> + <configSetting altId="p207.ctsu0.ts02" configurationId="p207"/> + <configSetting altId="p207.gpio_mode.gpio_mode_peripheral" configurationId="p207.gpio_mode"/> + <configSetting altId="p300.debug0.swclk" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/> + <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/> + <configSetting altId="p415.input" configurationId="p415"/> + <configSetting altId="p415.gpio_mode.gpio_mode_in" configurationId="p415.gpio_mode"/> + <configSetting altId="p415.gpio_pupd.gpio_pupd_ip_up" configurationId="p415.gpio_pupd"/> + <configSetting altId="sci8.mode.asynchronous.free" configurationId="sci8.mode"/> + <configSetting altId="sci8.rxd.p104" configurationId="sci8.rxd"/> + <configSetting altId="sci8.txd.p105" configurationId="sci8.txd"/> + <configSetting altId="spi0.miso.p100" configurationId="spi0.miso"/> + <configSetting altId="spi0.mode.enabled.a" configurationId="spi0.mode"/> + <configSetting altId="spi0.mosi.p101" configurationId="spi0.mosi"/> + <configSetting altId="spi0.rspck.p102" configurationId="spi0.rspck"/> + <configSetting altId="spi0.ssl0.p103" configurationId="spi0.ssl0"/> + <configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/> + <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/> + </pincfg> + <pincfg active="false" name="R7FA6M1AD3CFP.pincfg" selected="false" symbol=""> + <configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/> + <configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/> + <configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/> + <configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/> + <configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/> + <configSetting altId="p108.debug0.tms" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p109.debug0.tdo" configurationId="p109"/> + <configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/> + <configSetting altId="p110.debug0.tdi" configurationId="p110"/> + <configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/> + <configSetting altId="p300.debug0.tck" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + </pincfg> + </raPinConfiguration> +</raConfiguration> diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake index c91d48a32..bc99845a1 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake @@ -1,22 +1,16 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) +set(JLINK_OPTION "-USB 000831915224") -# Device port default to PORT1 Highspeed -if (NOT DEFINED PORT) -set(PORT 1) +# device default to PORT 1 High Speed +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) endif() - -# Host port will be the other port -set(HOST_PORT $<NOT:${PORT}>) function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - BOARD_TUD_RHPORT=${PORT} - BOARD_TUH_RHPORT=${HOST_PORT} - # port 0 is fullspeed, port 1 is highspeed - BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED> - BOARD_TUH_MAX_SPEED=$<IF:${HOST_PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED> - ) endfunction() diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h index 779f71810..32ede3a97 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.h +++ b/hw/bsp/ra/boards/ra6m5_ek/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: RA6M5 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m5-evaluation-kit-ra6m5-mcu-group +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ @@ -31,35 +36,9 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_00_PIN_08 #define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_00_PIN_05 #define BUTTON_STATE_ACTIVE 0 -static const ioport_pin_cfg_t board_pin_cfg[] = { - { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW }, - { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, - - // USB FS - { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH }, - { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - - // USB HS - { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS }, - { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, - { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, - - // ETM Trace - #ifdef TRACE_ETM - { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - #endif -}; #ifdef __cplusplus } diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.mk b/hw/bsp/ra/boards/ra6m5_ek/board.mk index a5c933764..5fcc1d0f1 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.mk +++ b/hw/bsp/ra/boards/ra6m5_ek/board.mk @@ -5,6 +5,7 @@ MCU_VARIANT = ra6m5 JLINK_DEVICE = R7FA6M5BH # Port 1 is highspeed -PORT ?= 1 +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 flash: flash-jlink diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 33d381850..000000000 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,63 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (2) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) -#else - #define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x1000) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 6845183db..000000000 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA6M5BH3CFC -#define BSP_MCU_FEATURE_SET ('B') -#define BSP_ROM_SIZE_BYTES (2097152) -#define BSP_RAM_SIZE_BYTES (524288) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (176) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h deleted file mode 100644 index 0eb5e0516..000000000 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h +++ /dev/null @@ -1,37 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CLOCK_CFG_H_ -#define BSP_CLOCK_CFG_H_ - -#define BSP_CFG_CLOCKS_SECURE (0) -#define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ -#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ -#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ -#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ -#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ -#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ -#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ -#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ -#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ -#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ -#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ -#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ -#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ - -#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug index 7b8ee9c95..ca18fed7c 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug +++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug @@ -20,9 +20,7 @@ void OnProjectLoad (void) { Project.SetTraceSource ("Trace Pins"); Project.SetTracePortWidth (4); - //File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf"); - //File.Open ("../../../../../../examples/dual/cmake-build-ra6m5/host_hid_to_device_cdc/host_hid_to_device_cdc.elf"); - File.Open ("../../../../../../examples/cmake-build-ra6m5/host/cdc_msc_hid/cdc_msc_hid.elf"); + File.Open ("../../../../../../examples/cmake-build-ra6m5_ek/device/cdc_msc/cdc_msc.elf"); } /********************************************************************* * diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..90afbdef3 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x1000) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h index bd6a901c3..bd6a901c3 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..e532478f8 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M5BH3CFC + #define BSP_MCU_FEATURE_SET ('B') + #define BSP_ROM_SIZE_BYTES (2097152) + #define BSP_RAM_SIZE_BYTES (524288) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (176) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 26e184a94..c01219377 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -5,17 +5,17 @@ extern "C" { #endif -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" -#define BSP_MCU_GROUP_RA4M3 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA6M5 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 #define BSP_HOCO_HZ (18000000) #elif BSP_CFG_HOCO_FREQUENCY == 2 #define BSP_HOCO_HZ (20000000) @@ -23,61 +23,62 @@ extern "C" { #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" #endif -#define BSP_CFG_FLL_ENABLE (0) + #define BSP_CFG_FLL_ENABLE (0) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) -#if defined(_RA_TZ_SECURE) + #if defined(_RA_TZ_SECURE) #define BSP_TZ_SECURE_BUILD (1) #define BSP_TZ_NONSECURE_BUILD (0) #elif defined(_RA_TZ_NONSECURE) #define BSP_TZ_SECURE_BUILD (0) #define BSP_TZ_NONSECURE_BUILD (1) #else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) -#endif + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif -/* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) -/* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) #ifndef SCB_NSACR_CP10_11_VAL -#define SCB_NSACR_CP10_11_VAL (3U) + #define SCB_NSACR_CP10_11_VAL (3U) #endif #ifndef FPU_FPCCR_TS_VAL -#define FPU_FPCCR_TS_VAL (1U) + #define FPU_FPCCR_TS_VAL (1U) #endif -#define FPU_FPCCR_CLRONRETS_VAL (1) + #define FPU_FPCCR_CLRONRETS_VAL (1) #ifndef FPU_FPCCR_CLRONRET_VAL -#define FPU_FPCCR_CLRONRET_VAL (1) + #define FPU_FPCCR_CLRONRET_VAL (1) #endif -/* The C-Cache line size that is configured during startup. */ + /* The C-Cache line size that is configured during startup. */ #ifndef BSP_CFG_C_CACHE_LINE_SIZE -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) + #define BSP_CFG_C_CACHE_LINE_SIZE (1U) #endif -/* Type 1 Peripheral Security Attribution */ + /* Type 1 Peripheral Security Attribution */ -/* Peripheral Security Attribution Register (PSAR) Settings */ + /* Peripheral Security Attribution Register (PSAR) Settings */ #ifndef BSP_TZ_CFG_PSARB #define BSP_TZ_CFG_PSARB (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ @@ -114,7 +115,7 @@ extern "C" { (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ - (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ 0xffae07f0) /* Unused */ @@ -129,13 +130,13 @@ extern "C" { (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ - (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ - (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ 0x3f3ff8) /* Unused */ #endif #ifndef BSP_TZ_CFG_MSSAR @@ -145,19 +146,19 @@ extern "C" { 0xfffffffc) /* Unused */ #endif -/* Type 2 Peripheral Security Attribution */ + /* Type 2 Peripheral Security Attribution */ -/* Security attribution for Cache registers. */ + /* Security attribution for Cache registers. */ #ifndef BSP_TZ_CFG_CSAR #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) #endif -/* Security attribution for RSTSRn registers. */ + /* Security attribution for RSTSRn registers. */ #ifndef BSP_TZ_CFG_RSTSAR #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) #endif -/* Security attribution for registers of LVD channels. */ + /* Security attribution for registers of LVD channels. */ #ifndef BSP_TZ_CFG_LVDSAR #define BSP_TZ_CFG_LVDSAR (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ @@ -165,16 +166,16 @@ extern "C" { 0xFFFFFFFCU) #endif -/* Security attribution for LPM registers. */ + /* Security attribution for LPM registers. */ #ifndef BSP_TZ_CFG_LPMSAR #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) #endif -/* Deep Standby Interrupt Factor Security Attribution Register. */ + /* Deep Standby Interrupt Factor Security Attribution Register. */ #ifndef BSP_TZ_CFG_DPFSAR #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) #endif -/* Security attribution for CGC registers. */ + /* Security attribution for CGC registers. */ #ifndef BSP_TZ_CFG_CGFSAR #if BSP_CFG_CLOCKS_SECURE /* Protect all CGC registers from Non-secure write access. */ @@ -185,12 +186,12 @@ extern "C" { #endif #endif -/* Security attribution for Battery Backup registers. */ + /* Security attribution for Battery Backup registers. */ #ifndef BSP_TZ_CFG_BBFSAR #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) #endif -/* Security attribution for registers for IRQ channels. */ + /* Security attribution for registers for IRQ channels. */ #ifndef BSP_TZ_CFG_ICUSARA #define BSP_TZ_CFG_ICUSARA (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ @@ -203,8 +204,8 @@ extern "C" { (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ - (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ @@ -212,12 +213,12 @@ extern "C" { 0xFFFF0000U) #endif -/* Security attribution for NMI registers. */ + /* Security attribution for NMI registers. */ #ifndef BSP_TZ_CFG_ICUSARB #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ #endif -/* Security attribution for registers for DMAC channels */ + /* Security attribution for registers for DMAC channels */ #ifndef BSP_TZ_CFG_ICUSARC #define BSP_TZ_CFG_ICUSARC (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ @@ -231,29 +232,29 @@ extern "C" { 0xFFFFFF00U) #endif -/* Security attribution registers for SELSR0. */ + /* Security attribution registers for SELSR0. */ #ifndef BSP_TZ_CFG_ICUSARD #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN0. */ + /* Security attribution registers for WUPEN0. */ #ifndef BSP_TZ_CFG_ICUSARE #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN1. */ + /* Security attribution registers for WUPEN1. */ #ifndef BSP_TZ_CFG_ICUSARF #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) #endif -/* Set DTCSTSAR if the Secure program uses the DTC. */ + /* Set DTCSTSAR if the Secure program uses the DTC. */ #if RA_NOT_DEFINED == RA_NOT_DEFINED -#define BSP_TZ_CFG_DTC_USED (0U) + #define BSP_TZ_CFG_DTC_USED (0U) #else #define BSP_TZ_CFG_DTC_USED (1U) #endif -/* Security attribution of FLWT and FCKMHZ registers. */ + /* Security attribution of FLWT and FCKMHZ registers. */ #ifndef BSP_TZ_CFG_FSAR /* If the CGC registers are only accessible in Secure mode, than there is no * reason for nonsecure applications to access FLWT and FCKMHZ. */ @@ -266,118 +267,123 @@ extern "C" { #endif #endif -/* Security attribution for SRAM registers. */ + /* Security attribution for SRAM registers. */ #ifndef BSP_TZ_CFG_SRAMSAR /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (\ + #define BSP_TZ_CFG_SRAMSAR (\ 1 | \ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ 4 | \ 0xFFFFFFF8U) #endif -/* Security attribution for Standby RAM registers. */ + /* Security attribution for Standby RAM registers. */ #ifndef BSP_TZ_CFG_STBRAMSAR -#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) + #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) #endif -/* Security attribution for the DMAC Bus Master MPU settings. */ + /* Security attribution for the DMAC Bus Master MPU settings. */ #ifndef BSP_TZ_CFG_MMPUSARA -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ -#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) #endif -/* Security Attribution Register A for BUS Control registers. */ + /* Security Attribution Register A for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARA -#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) #endif -/* Security Attribution Register B for BUS Control registers. */ + /* Security Attribution Register B for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARB -#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) #endif -/* Enable Uninitialized Non-Secure Application Fallback. */ + /* Enable Uninitialized Non-Secure Application Fallback. */ #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK -#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) #endif -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -/* Option Function Select Register 1 Security Attribution */ + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + + /* Option Function Select Register 1 Security Attribution */ #ifndef BSP_CFG_ROM_REG_OFS1_SEL #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) #else -#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) #endif #endif -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -/* Dual Mode Select Register */ + /* Dual Mode Select Register */ #ifndef BSP_CFG_ROM_REG_DUALSEL -#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) #endif -/* Block Protection Register 0 */ + /* Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_BPS0 -#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) #endif -/* Block Protection Register 1 */ + /* Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_BPS1 -#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) #endif -/* Block Protection Register 2 */ + /* Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_BPS2 -#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) #endif -/* Block Protection Register 3 */ + /* Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_BPS3 -#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) #endif -/* Permanent Block Protection Register 0 */ + /* Permanent Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_PBPS0 -#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) #endif -/* Permanent Block Protection Register 1 */ + /* Permanent Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_PBPS1 -#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) #endif -/* Permanent Block Protection Register 2 */ + /* Permanent Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_PBPS2 -#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) #endif -/* Permanent Block Protection Register 3 */ + /* Permanent Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_PBPS3 -#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) #endif -/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL0 -#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) + #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) #endif -/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL1 -#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) + #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) #endif -/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL2 -#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) #endif -/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL3 -#define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif + /* Security Attribution for Bank Select Register */ +#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL + #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) #endif #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) #endif #ifdef __cplusplus diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..d2eec08ae --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,99 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define MIKROBUS_AN_ARDUINO_A0 (BSP_IO_PORT_00_PIN_00) +#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_01) +#define ARDUINO_A2 (BSP_IO_PORT_00_PIN_02) +#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_03) +#define SW2 (BSP_IO_PORT_00_PIN_04) +#define SW1 (BSP_IO_PORT_00_PIN_05) +#define LED1 (BSP_IO_PORT_00_PIN_06) +#define LED2 (BSP_IO_PORT_00_PIN_07) +#define LED3 (BSP_IO_PORT_00_PIN_08) +#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14) +#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15) +#define OSPI_CLK (BSP_IO_PORT_01_PIN_00) +#define OSPI_SIO7 (BSP_IO_PORT_01_PIN_01) +#define OSPI_SIO1 (BSP_IO_PORT_01_PIN_02) +#define OSPI_SIO6 (BSP_IO_PORT_01_PIN_03) +#define OSPI_DQS (BSP_IO_PORT_01_PIN_04) +#define OSPI_SIO5 (BSP_IO_PORT_01_PIN_05) +#define OSPI_SIO0 (BSP_IO_PORT_01_PIN_06) +#define OSPI_SIO3 (BSP_IO_PORT_01_PIN_07) +#define MIKROBUS_PWM_ARDUINO_D3_PWM (BSP_IO_PORT_01_PIN_11) +#define ARDUINO_D4 (BSP_IO_PORT_01_PIN_12) +#define ARDUINO_D5 (BSP_IO_PORT_01_PIN_13) +#define ARDUINO_D6 (BSP_IO_PORT_01_PIN_14) +#define ARDUINO_D9 (BSP_IO_PORT_01_PIN_15) +#define MIKROBUS_MISO_ARDUINO_MISO_PMOD1_MISO (BSP_IO_PORT_02_PIN_02) +#define MIKROBUS_MOSI_ARDUINO_MOSI_PMOD1_MOSI (BSP_IO_PORT_02_PIN_03) +#define MIKROBUS_SCK_ARDUINO_SCK_PMOD1_SCK (BSP_IO_PORT_02_PIN_04) +#define MIKROBUS_SS_ARDUINO_SS (BSP_IO_PORT_02_PIN_05) +#define PMOD1_SS (BSP_IO_PORT_02_PIN_06) +#define ARDUINO_D8 (BSP_IO_PORT_02_PIN_07) +#define PMOD1_SS2 (BSP_IO_PORT_03_PIN_01) +#define PMOD1_SS3 (BSP_IO_PORT_03_PIN_02) +#define MIKROBUS_RESET_ARDUINO_RESET (BSP_IO_PORT_03_PIN_03) +#define QSPI_CLK (BSP_IO_PORT_03_PIN_05) +#define QSPI_CS (BSP_IO_PORT_03_PIN_06) +#define QSPI_IO0 (BSP_IO_PORT_03_PIN_07) +#define QSPI_IO1 (BSP_IO_PORT_03_PIN_08) +#define QSPI_IO2 (BSP_IO_PORT_03_PIN_09) +#define QSPI_IO3 (BSP_IO_PORT_03_PIN_10) +#define PMOD1_RST (BSP_IO_PORT_03_PIN_11) +#define PMOD2_INT (BSP_IO_PORT_04_PIN_00) +#define ETH_MDC (BSP_IO_PORT_04_PIN_01) +#define ETH_MDIO (BSP_IO_PORT_04_PIN_02) +#define ETH_RST (BSP_IO_PORT_04_PIN_03) +#define PMOD2_RST (BSP_IO_PORT_04_PIN_04) +#define ETH_TXEN (BSP_IO_PORT_04_PIN_05) +#define ETH_TXD1 (BSP_IO_PORT_04_PIN_06) +#define USBFS_VBUS (BSP_IO_PORT_04_PIN_07) +#define PMOD2_SS2 (BSP_IO_PORT_04_PIN_08) +#define MIKROBUS_INT_ARDUINO_INT0 (BSP_IO_PORT_04_PIN_09) +#define PMOD2_MISO (BSP_IO_PORT_04_PIN_10) +#define PMOD2_MOSI (BSP_IO_PORT_04_PIN_11) +#define PMOD2_SCK (BSP_IO_PORT_04_PIN_12) +#define PMOS2_SS (BSP_IO_PORT_04_PIN_13) +#define GROVE1_SDA_QWIIC_SDA (BSP_IO_PORT_04_PIN_14) +#define GROVE1_SCL_QWIIC_SCL (BSP_IO_PORT_04_PIN_15) +#define USBFS_VBUS_EN (BSP_IO_PORT_05_PIN_00) +#define USBFS_OVERCURA (BSP_IO_PORT_05_PIN_01) +#define GROVE2_SCL (BSP_IO_PORT_05_PIN_05) +#define GROVE2_SDA (BSP_IO_PORT_05_PIN_06) +#define MIKROBUS_SDA_ARDUINO_SDA (BSP_IO_PORT_05_PIN_11) +#define MIKROBUS_SCL_ARDUINO_SCL (BSP_IO_PORT_05_PIN_12) +#define OSPI_SIO4 (BSP_IO_PORT_06_PIN_00) +#define OSPI_SIO2 (BSP_IO_PORT_06_PIN_01) +#define OSPI_CS1 (BSP_IO_PORT_06_PIN_02) +#define ARDUINO_D7 (BSP_IO_PORT_06_PIN_08) +#define CAN_TXD (BSP_IO_PORT_06_PIN_09) +#define CAN_RDX (BSP_IO_PORT_06_PIN_10) +#define CAN_STBY (BSP_IO_PORT_06_PIN_11) +#define MIKROBUS_TX_ARDUINO_TX (BSP_IO_PORT_06_PIN_13) +#define MIKROBUS_RX_ARDUINO_RX (BSP_IO_PORT_06_PIN_14) +#define OSPI_RST (BSP_IO_PORT_06_PIN_15) +#define ETH_TXD0 (BSP_IO_PORT_07_PIN_00) +#define ETH_50REF (BSP_IO_PORT_07_PIN_01) +#define ETH_RXD0 (BSP_IO_PORT_07_PIN_02) +#define ETH_RXD1 (BSP_IO_PORT_07_PIN_03) +#define ETH_RXERR (BSP_IO_PORT_07_PIN_04) +#define ETH_CRSDV (BSP_IO_PORT_07_PIN_05) +#define ETH_INT (BSP_IO_PORT_07_PIN_06) +#define USBHS_OVERCURA (BSP_IO_PORT_07_PIN_07) +#define PMOD2_SS3 (BSP_IO_PORT_07_PIN_08) +#define PMOD1_INT (BSP_IO_PORT_09_PIN_05) +#define USBHS_VBUS_EN (BSP_IO_PORT_11_PIN_00) +#define USBHS_VBUS (BSP_IO_PORT_11_PIN_01) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M5 EK */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h index 0eb5e0516..0eb5e0516 100644 --- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..6b814d74a --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c @@ -0,0 +1,411 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_00_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_00_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_00_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_GPT1) + }, + { + .pin = BSP_IO_PORT_01_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_13, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_02_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_02_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_02_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_02_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_03_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_03_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_04_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_04_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_04_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH) + }, + { + .pin = BSP_IO_PORT_04_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_04_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_04_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_13, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_04_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_05_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_05_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_05_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_05_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_06_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_06_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_06_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_06_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_06_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CAN) + }, + { + .pin = BSP_IO_PORT_06_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CAN) + }, + { + .pin = BSP_IO_PORT_06_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_06_PIN_13, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_06_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_06_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH) + }, + { + .pin = BSP_IO_PORT_07_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_07_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, + { + .pin = BSP_IO_PORT_07_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_09_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_11_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, + { + .pin = BSP_IO_PORT_11_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld b/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld new file mode 100644 index 000000000..605eef7d2 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld @@ -0,0 +1,769 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld new file mode 100644 index 000000000..19864683f --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld @@ -0,0 +1,22 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x80000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x0100A100; + OPTION_SETTING_LENGTH = 0x100; + OPTION_SETTING_S_START = 0x0100A200; + OPTION_SETTING_S_LENGTH = 0x100; + ID_CODE_START = 0x00000000; + ID_CODE_LENGTH = 0x0; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x4000000; + OSPI_DEVICE_0_START = 0x68000000; + OSPI_DEVICE_0_LENGTH = 0x8000000; + OSPI_DEVICE_1_START = 0x70000000; + OSPI_DEVICE_1_LENGTH = 0x10000000; diff --git a/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..4544d0f2a --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml @@ -0,0 +1,670 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<raConfiguration version="9"> + <generalSettings> + <option key="#Board#" value="board.ra6m5ek"/> + <option key="CPU" value="RA6M5"/> + <option key="Core" value="CM33"/> + <option key="#TargetName#" value="R7FA6M5BH3CFC"/> + <option key="#TargetARCHITECTURE#" value="cortex-m33"/> + <option key="#DeviceCommand#" value="R7FA6M5BH"/> + <option key="#RTOS#" value="_none"/> + <option key="#pinconfiguration#" value="R7FA6M5BH3CFC.pincfg"/> + <option key="#FSPVersion#" value="5.6.0"/> + <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra6m5_ek##"/> + <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/> + </generalSettings> + <raBspConfiguration> + <config id="config.bsp.ra6m5.R7FA6M5BH3CFC"> + <property id="config.bsp.part_number" value="config.bsp.part_number.value"/> + <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/> + <property id="config.bsp.rom_size_bytes_hidden" value="2097152"/> + <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/> + <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/> + <property id="config.bsp.package_style" value="config.bsp.package_style.value"/> + <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/> + <property id="config.bsp.irq_count_hidden" value="96"/> + </config> + <config id="config.bsp.ra6m5"> + <property id="config.bsp.series" value="config.bsp.series.value"/> + </config> + <config id="config.bsp.ra6m5.fsp"> + <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/> + <property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/> + <property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/> + <property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/> + <property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/> + <property id="config.bsp.fsp.tz.csar" value="config.bsp.fsp.tz.csar.both"/> + <property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/> + <property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/> + <property id="config.bsp.fsp.tz.sramsar.sramprcr" value="config.bsp.fsp.tz.sramsar.sramprcr.both"/> + <property id="config.bsp.fsp.tz.sramsar.sramecc" value="config.bsp.fsp.tz.sramsar.sramecc.both"/> + <property id="config.bsp.fsp.tz.stbramsar" value="config.bsp.fsp.tz.stbramsar.both"/> + <property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/> + <property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/> + <property id="config.bsp.fsp.tz.banksel_sel" value="config.bsp.fsp.tz.banksel_sel.both"/> + <property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/> + <property id="config.bsp.fsp.cache_line_size" value="config.bsp.fsp.cache_line_size.32"/> + <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/> + <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/> + <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/> + <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0_level" value="config.bsp.fsp.OFS1_SEL.voltage_detection0_level.secure"/> + <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.start" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.start.secure"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/> + <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/> + <property id="config.bsp.fsp.BPS.BPS0" value=""/> + <property id="config.bsp.fsp.BPS.BPS1" value=""/> + <property id="config.bsp.fsp.BPS.BPS2" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS0" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS1" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS2" value=""/> + <property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/> + <property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/> + <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/> + <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="50000000"/> + <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="16666666"/> + <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/> + <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/> + <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="25000000"/> + <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/> + <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/> + <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x3"/> + <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/> + <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x3"/> + <property id="config.bsp.fsp.mcu.canfd.num_channels" value="2"/> + <property id="config.bsp.fsp.mcu.canfd.rx_fifos" value="8"/> + <property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="4864"/> + <property id="config.bsp.fsp.mcu.canfd.afl_rules" value="128"/> + <property id="config.bsp.fsp.mcu.canfd.afl_rules_each_chnl" value="64"/> + <property id="config.bsp.fsp.mcu.canfd.max_data_rate_hz" value="5"/> + <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x03F9"/> + <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/> + <property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="65535"/> + </config> + <config id="config.bsp.ra"> + <property id="config.bsp.common.main" value="0x1000"/> + <property id="config.bsp.common.heap" value="0x1000"/> + <property id="config.bsp.common.vcc" value="3300"/> + <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/> + <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/> + <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/> + <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/> + <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/> + <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/> + <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/> + <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/> + <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/> + <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/> + <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/> + <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/> + </config> + </raBspConfiguration> + <raClockConfiguration> + <node id="board.clock.xtal.freq" mul="24000000" option="_edit"/> + <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/> + <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/> + <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/> + <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/> + <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/> + <node id="board.clock.pll.div" option="board.clock.pll.div.3"/> + <node id="board.clock.pll.mul" option="board.clock.pll.mul.250"/> + <node id="board.clock.pll.display" option="board.clock.pll.display.value"/> + <node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/> + <node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/> + <node id="board.clock.pll2.mul" option="board.clock.pll2.mul.200"/> + <node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/> + <node id="board.clock.clock.source" option="board.clock.clock.source.pll"/> + <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/> + <node id="board.clock.uclk.source" option="board.clock.uclk.source.disabled"/> + <node id="board.clock.u60ck.source" option="board.clock.u60ck.source.disabled"/> + <node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/> + <node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/> + <node id="board.clock.cecclk.source" option="board.clock.cecclk.source.disabled"/> + <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/> + <node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/> + <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/> + <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/> + <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/> + <node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/> + <node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/> + <node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/> + <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/> + <node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/> + <node id="board.clock.u60ck.div" option="board.clock.u60ck.div.1"/> + <node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.1"/> + <node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.6"/> + <node id="board.clock.cecclk.div" option="board.clock.cecclk.div.1"/> + <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/> + <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/> + <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/> + <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/> + <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/> + <node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/> + <node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/> + <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/> + <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/> + <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/> + <node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/> + <node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/> + <node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/> + <node id="board.clock.cecclk.display" option="board.clock.cecclk.display.value"/> + </raClockConfiguration> + <raComponentSelection> + <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0"> + <description>Simple application that blinks an LED. No RTOS included.</description> + <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0"> + <description>Board Support Package Common Files</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0"> + <description>I/O Port</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0"> + <description>Arm CMSIS Version 6 - Core (M)</description> + <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra6m5_ek" variant="" vendor="Renesas" version="5.6.0"> + <description>RA6M5-EK Board Support Files</description> + <originalPack>Renesas.RA_board_ra6m5_ek.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="R7FA6M5BH3CFC" vendor="Renesas" version="5.6.0"> + <description>Board support package for R7FA6M5BH3CFC</description> + <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA6M5</description> + <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA6M5 - FSP Data</description> + <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="events" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA6M5 - Events</description> + <originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack> + </component> + </raComponentSelection> + <raElcConfiguration/> + <raIcuConfiguration/> + <raModuleConfiguration> + <module id="module.driver.ioport_on_ioport.0"> + <property id="module.driver.ioport.name" value="g_ioport"/> + <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/> + <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/> + </module> + <context id="_hal.0"> + <stack module="module.driver.ioport_on_ioport.0"/> + </context> + <config id="config.driver.ioport"> + <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/> + </config> + </raModuleConfiguration> + <raPinConfiguration> + <symbolicName propertyId="p000.symbolic_name" value="MIKROBUS_AN_ARDUINO_A0"/> + <symbolicName propertyId="p001.symbolic_name" value="ARDUINO_A1"/> + <symbolicName propertyId="p002.symbolic_name" value="ARDUINO_A2"/> + <symbolicName propertyId="p003.symbolic_name" value="ARDUINO_A3"/> + <symbolicName propertyId="p004.symbolic_name" value="SW2"/> + <symbolicName propertyId="p005.symbolic_name" value="SW1"/> + <symbolicName propertyId="p006.symbolic_name" value="LED1"/> + <symbolicName propertyId="p007.symbolic_name" value="LED2"/> + <symbolicName propertyId="p008.symbolic_name" value="LED3"/> + <symbolicName propertyId="p014.symbolic_name" value="ARDUINO_A4"/> + <symbolicName propertyId="p015.symbolic_name" value="ARDUINO_A5"/> + <symbolicName propertyId="p100.symbolic_name" value="OSPI_CLK"/> + <symbolicName propertyId="p101.symbolic_name" value="OSPI_SIO7"/> + <symbolicName propertyId="p102.symbolic_name" value="OSPI_SIO1"/> + <symbolicName propertyId="p103.symbolic_name" value="OSPI_SIO6"/> + <symbolicName propertyId="p104.symbolic_name" value="OSPI_DQS"/> + <symbolicName propertyId="p105.symbolic_name" value="OSPI_SIO5"/> + <symbolicName propertyId="p106.symbolic_name" value="OSPI_SIO0"/> + <symbolicName propertyId="p107.symbolic_name" value="OSPI_SIO3"/> + <symbolicName propertyId="p111.symbolic_name" value="MIKROBUS_PWM_ARDUINO_D3_PWM"/> + <symbolicName propertyId="p112.symbolic_name" value="ARDUINO_D4"/> + <symbolicName propertyId="p113.symbolic_name" value="ARDUINO_D5"/> + <symbolicName propertyId="p114.symbolic_name" value="ARDUINO_D6"/> + <symbolicName propertyId="p115.symbolic_name" value="ARDUINO_D9"/> + <symbolicName propertyId="p202.symbolic_name" value="MIKROBUS_MISO_ARDUINO_MISO_PMOD1_MISO"/> + <symbolicName propertyId="p203.symbolic_name" value="MIKROBUS_MOSI_ARDUINO_MOSI_PMOD1_MOSI"/> + <symbolicName propertyId="p204.symbolic_name" value="MIKROBUS_SCK_ARDUINO_SCK_PMOD1_SCK"/> + <symbolicName propertyId="p205.symbolic_name" value="MIKROBUS_SS_ARDUINO_SS"/> + <symbolicName propertyId="p206.symbolic_name" value="PMOD1_SS"/> + <symbolicName propertyId="p207.symbolic_name" value="ARDUINO_D8"/> + <symbolicName propertyId="p301.symbolic_name" value="PMOD1_SS2"/> + <symbolicName propertyId="p302.symbolic_name" value="PMOD1_SS3"/> + <symbolicName propertyId="p303.symbolic_name" value="MIKROBUS_RESET_ARDUINO_RESET"/> + <symbolicName propertyId="p305.symbolic_name" value="QSPI_CLK"/> + <symbolicName propertyId="p306.symbolic_name" value="QSPI_CS"/> + <symbolicName propertyId="p307.symbolic_name" value="QSPI_IO0"/> + <symbolicName propertyId="p308.symbolic_name" value="QSPI_IO1"/> + <symbolicName propertyId="p309.symbolic_name" value="QSPI_IO2"/> + <symbolicName propertyId="p310.symbolic_name" value="QSPI_IO3"/> + <symbolicName propertyId="p311.symbolic_name" value="PMOD1_RST"/> + <symbolicName propertyId="p400.symbolic_name" value="PMOD2_INT"/> + <symbolicName propertyId="p401.symbolic_name" value="ETH_MDC"/> + <symbolicName propertyId="p402.symbolic_name" value="ETH_MDIO"/> + <symbolicName propertyId="p403.symbolic_name" value="ETH_RST"/> + <symbolicName propertyId="p404.symbolic_name" value="PMOD2_RST"/> + <symbolicName propertyId="p405.symbolic_name" value="ETH_TXEN"/> + <symbolicName propertyId="p406.symbolic_name" value="ETH_TXD1"/> + <symbolicName propertyId="p407.symbolic_name" value="USBFS_VBUS"/> + <symbolicName propertyId="p408.symbolic_name" value="PMOD2_SS2"/> + <symbolicName propertyId="p409.symbolic_name" value="MIKROBUS_INT_ARDUINO_INT0"/> + <symbolicName propertyId="p410.symbolic_name" value="PMOD2_MISO"/> + <symbolicName propertyId="p411.symbolic_name" value="PMOD2_MOSI"/> + <symbolicName propertyId="p412.symbolic_name" value="PMOD2_SCK"/> + <symbolicName propertyId="p413.symbolic_name" value="PMOS2_SS"/> + <symbolicName propertyId="p414.symbolic_name" value="GROVE1_SDA_QWIIC_SDA"/> + <symbolicName propertyId="p415.symbolic_name" value="GROVE1_SCL_QWIIC_SCL"/> + <symbolicName propertyId="p500.symbolic_name" value="USBFS_VBUS_EN"/> + <symbolicName propertyId="p501.symbolic_name" value="USBFS_OVERCURA"/> + <symbolicName propertyId="p505.symbolic_name" value="GROVE2_SCL"/> + <symbolicName propertyId="p506.symbolic_name" value="GROVE2_SDA"/> + <symbolicName propertyId="p511.symbolic_name" value="MIKROBUS_SDA_ARDUINO_SDA"/> + <symbolicName propertyId="p512.symbolic_name" value="MIKROBUS_SCL_ARDUINO_SCL"/> + <symbolicName propertyId="p600.symbolic_name" value="OSPI_SIO4"/> + <symbolicName propertyId="p601.symbolic_name" value="OSPI_SIO2"/> + <symbolicName propertyId="p602.symbolic_name" value="OSPI_CS1"/> + <symbolicName propertyId="p608.symbolic_name" value="ARDUINO_D7"/> + <symbolicName propertyId="p609.symbolic_name" value="CAN_TXD"/> + <symbolicName propertyId="p610.symbolic_name" value="CAN_RDX"/> + <symbolicName propertyId="p611.symbolic_name" value="CAN_STBY"/> + <symbolicName propertyId="p613.symbolic_name" value="MIKROBUS_TX_ARDUINO_TX"/> + <symbolicName propertyId="p614.symbolic_name" value="MIKROBUS_RX_ARDUINO_RX"/> + <symbolicName propertyId="p615.symbolic_name" value="OSPI_RST"/> + <symbolicName propertyId="p700.symbolic_name" value="ETH_TXD0"/> + <symbolicName propertyId="p701.symbolic_name" value="ETH_50REF"/> + <symbolicName propertyId="p702.symbolic_name" value="ETH_RXD0"/> + <symbolicName propertyId="p703.symbolic_name" value="ETH_RXD1"/> + <symbolicName propertyId="p704.symbolic_name" value="ETH_RXERR"/> + <symbolicName propertyId="p705.symbolic_name" value="ETH_CRSDV"/> + <symbolicName propertyId="p706.symbolic_name" value="ETH_INT"/> + <symbolicName propertyId="p707.symbolic_name" value="USBHS_OVERCURA"/> + <symbolicName propertyId="p708.symbolic_name" value="PMOD2_SS3"/> + <symbolicName propertyId="p905.symbolic_name" value="PMOD1_INT"/> + <symbolicName propertyId="pb00.symbolic_name" value="USBHS_VBUS_EN"/> + <symbolicName propertyId="pb01.symbolic_name" value="USBHS_VBUS"/> + <pincfg active="true" name="RA6M5 EK" selected="true" symbol="g_bsp_pin_cfg"> + <configSetting altId="adc0.an00.p000" configurationId="adc0.an00"/> + <configSetting altId="adc0.an01.p001" configurationId="adc0.an01"/> + <configSetting altId="adc0.an02.p002" configurationId="adc0.an02"/> + <configSetting altId="adc0.an03.p003" configurationId="adc0.an03"/> + <configSetting altId="adc0.an12.p014" configurationId="adc0.an12"/> + <configSetting altId="adc0.an13.p015" configurationId="adc0.an13"/> + <configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/> + <configSetting altId="can1.crx.p610" configurationId="can1.crx"/> + <configSetting altId="can1.ctx.p609" configurationId="can1.ctx"/> + <configSetting altId="can1.mode.enabled.free" configurationId="can1.mode"/> + <configSetting altId="cgc0.extal.p212" configurationId="cgc0.extal"/> + <configSetting altId="cgc0.mode.mainsub" configurationId="cgc0.mode"/> + <configSetting altId="cgc0.xtal.p213" configurationId="cgc0.xtal"/> + <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/> + <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/> + <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/> + <configSetting altId="etherc0.rmii.crs_dv.p705" configurationId="etherc0.rmii.crs_dv"/> + <configSetting altId="etherc0.rmii.mdc.p401" configurationId="etherc0.rmii.mdc"/> + <configSetting altId="etherc0.rmii.mdio.p402" configurationId="etherc0.rmii.mdio"/> + <configSetting altId="etherc0.rmii.mode.rmii.free" configurationId="etherc0.rmii.mode"/> + <configSetting altId="etherc0.rmii.pairing.free" configurationId="etherc0.rmii.pairing"/> + <configSetting altId="etherc0.rmii.ref50ck.p701" configurationId="etherc0.rmii.ref50ck"/> + <configSetting altId="etherc0.rmii.rx_er.p704" configurationId="etherc0.rmii.rx_er"/> + <configSetting altId="etherc0.rmii.rxd0.p702" configurationId="etherc0.rmii.rxd0"/> + <configSetting altId="etherc0.rmii.rxd1.p703" configurationId="etherc0.rmii.rxd1"/> + <configSetting altId="etherc0.rmii.txd0.p700" configurationId="etherc0.rmii.txd0"/> + <configSetting altId="etherc0.rmii.txd1.p406" configurationId="etherc0.rmii.txd1"/> + <configSetting altId="etherc0.rmii.txd_en.p405" configurationId="etherc0.rmii.txd_en"/> + <configSetting altId="gpt3.gtioca.p111" configurationId="gpt3.gtioca"/> + <configSetting altId="gpt3.mode.gtiocaorgtiocb.free" configurationId="gpt3.mode"/> + <configSetting altId="iic1.mode.enabled.a" configurationId="iic1.mode"/> + <configSetting altId="iic1.scl.p512" configurationId="iic1.scl"/> + <configSetting altId="iic1.sda.p511" configurationId="iic1.sda"/> + <configSetting altId="iic2.mode.enabled.free" configurationId="iic2.mode"/> + <configSetting altId="iic2.pairing.free" configurationId="iic2.pairing"/> + <configSetting altId="iic2.scl.p415" configurationId="iic2.scl"/> + <configSetting altId="iic2.sda.p414" configurationId="iic2.sda"/> + <configSetting altId="ospi0.mode.custom.free" configurationId="ospi0.mode"/> + <configSetting altId="ospi0.omcs1.p602" configurationId="ospi0.omcs1"/> + <configSetting altId="ospi0.omdqs.p104" configurationId="ospi0.omdqs"/> + <configSetting altId="ospi0.omsclk.p100" configurationId="ospi0.omsclk"/> + <configSetting altId="ospi0.omsio0.p106" configurationId="ospi0.omsio0"/> + <configSetting altId="ospi0.omsio1.p102" configurationId="ospi0.omsio1"/> + <configSetting altId="ospi0.omsio2.p601" configurationId="ospi0.omsio2"/> + <configSetting altId="ospi0.omsio3.p107" configurationId="ospi0.omsio3"/> + <configSetting altId="ospi0.omsio4.p600" configurationId="ospi0.omsio4"/> + <configSetting altId="ospi0.omsio5.p105" configurationId="ospi0.omsio5"/> + <configSetting altId="ospi0.omsio6.p103" configurationId="ospi0.omsio6"/> + <configSetting altId="ospi0.omsio7.p101" configurationId="ospi0.omsio7"/> + <configSetting altId="ospi0.pairing.free" configurationId="ospi0.pairing"/> + <configSetting altId="p000.asel" configurationId="p000"/> + <configSetting altId="p000.gpio_mode.gpio_mode_an" configurationId="p000.gpio_mode"/> + <configSetting altId="p001.asel" configurationId="p001"/> + <configSetting altId="p001.gpio_mode.gpio_mode_an" configurationId="p001.gpio_mode"/> + <configSetting altId="p002.asel" configurationId="p002"/> + <configSetting altId="p002.gpio_mode.gpio_mode_an" configurationId="p002.gpio_mode"/> + <configSetting altId="p003.asel" configurationId="p003"/> + <configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/> + <configSetting altId="p004.input" configurationId="p004"/> + <configSetting altId="p004.gpio_irq.gpio_irq_enabled" configurationId="p004.gpio_irq"/> + <configSetting altId="p004.gpio_mode.gpio_mode_in" configurationId="p004.gpio_mode"/> + <configSetting altId="p005.input" configurationId="p005"/> + <configSetting altId="p005.gpio_irq.gpio_irq_enabled" configurationId="p005.gpio_irq"/> + <configSetting altId="p005.gpio_mode.gpio_mode_in" configurationId="p005.gpio_mode"/> + <configSetting altId="p006.output.low" configurationId="p006"/> + <configSetting altId="p006.gpio_mode.gpio_mode_out.low" configurationId="p006.gpio_mode"/> + <configSetting altId="p007.output.low" configurationId="p007"/> + <configSetting altId="p007.gpio_mode.gpio_mode_out.low" configurationId="p007.gpio_mode"/> + <configSetting altId="p008.output.low" configurationId="p008"/> + <configSetting altId="p008.gpio_mode.gpio_mode_out.low" configurationId="p008.gpio_mode"/> + <configSetting altId="p014.asel" configurationId="p014"/> + <configSetting altId="p014.gpio_mode.gpio_mode_an" configurationId="p014.gpio_mode"/> + <configSetting altId="p015.asel" configurationId="p015"/> + <configSetting altId="p015.gpio_mode.gpio_mode_an" configurationId="p015.gpio_mode"/> + <configSetting altId="p100.ospi0.omsclk" configurationId="p100"/> + <configSetting altId="p100.gpio_speed.gpio_speed_highspeedhigh" configurationId="p100.gpio_drivecapacity"/> + <configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/> + <configSetting altId="p101.ospi0.omsio7" configurationId="p101"/> + <configSetting altId="p101.gpio_speed.gpio_speed_highspeedhigh" configurationId="p101.gpio_drivecapacity"/> + <configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/> + <configSetting altId="p102.ospi0.omsio1" configurationId="p102"/> + <configSetting altId="p102.gpio_speed.gpio_speed_highspeedhigh" configurationId="p102.gpio_drivecapacity"/> + <configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/> + <configSetting altId="p103.ospi0.omsio6" configurationId="p103"/> + <configSetting altId="p103.gpio_speed.gpio_speed_highspeedhigh" configurationId="p103.gpio_drivecapacity"/> + <configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/> + <configSetting altId="p104.ospi0.omdqs" configurationId="p104"/> + <configSetting altId="p104.gpio_speed.gpio_speed_highspeedhigh" configurationId="p104.gpio_drivecapacity"/> + <configSetting altId="p104.gpio_mode.gpio_mode_peripheral" configurationId="p104.gpio_mode"/> + <configSetting altId="p105.ospi0.omsio5" configurationId="p105"/> + <configSetting altId="p105.gpio_speed.gpio_speed_highspeedhigh" configurationId="p105.gpio_drivecapacity"/> + <configSetting altId="p105.gpio_mode.gpio_mode_peripheral" configurationId="p105.gpio_mode"/> + <configSetting altId="p106.ospi0.omsio0" configurationId="p106"/> + <configSetting altId="p106.gpio_speed.gpio_speed_highspeedhigh" configurationId="p106.gpio_drivecapacity"/> + <configSetting altId="p106.gpio_mode.gpio_mode_peripheral" configurationId="p106.gpio_mode"/> + <configSetting altId="p107.ospi0.omsio3" configurationId="p107"/> + <configSetting altId="p107.gpio_speed.gpio_speed_highspeedhigh" configurationId="p107.gpio_drivecapacity"/> + <configSetting altId="p107.gpio_mode.gpio_mode_peripheral" configurationId="p107.gpio_mode"/> + <configSetting altId="p108.debug0.swdio" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p111.gpt3.gtioca" configurationId="p111"/> + <configSetting altId="p111.gpio_speed.gpio_speed_high" configurationId="p111.gpio_drivecapacity"/> + <configSetting altId="p111.gpio_mode.gpio_mode_peripheral" configurationId="p111.gpio_mode"/> + <configSetting altId="p112.output.low" configurationId="p112"/> + <configSetting altId="p112.gpio_speed.gpio_speed_high" configurationId="p112.gpio_drivecapacity"/> + <configSetting altId="p112.gpio_mode.gpio_mode_out.low" configurationId="p112.gpio_mode"/> + <configSetting altId="p113.output.low" configurationId="p113"/> + <configSetting altId="p113.gpio_speed.gpio_speed_high" configurationId="p113.gpio_drivecapacity"/> + <configSetting altId="p113.gpio_mode.gpio_mode_out.low" configurationId="p113.gpio_mode"/> + <configSetting altId="p114.output.low" configurationId="p114"/> + <configSetting altId="p114.gpio_speed.gpio_speed_high" configurationId="p114.gpio_drivecapacity"/> + <configSetting altId="p114.gpio_mode.gpio_mode_out.low" configurationId="p114.gpio_mode"/> + <configSetting altId="p115.output.low" configurationId="p115"/> + <configSetting altId="p115.gpio_speed.gpio_speed_high" configurationId="p115.gpio_drivecapacity"/> + <configSetting altId="p115.gpio_mode.gpio_mode_out.low" configurationId="p115.gpio_mode"/> + <configSetting altId="p202.spi0.miso" configurationId="p202"/> + <configSetting altId="p202.gpio_speed.gpio_speed_high" configurationId="p202.gpio_drivecapacity"/> + <configSetting altId="p202.gpio_mode.gpio_mode_peripheral" configurationId="p202.gpio_mode"/> + <configSetting altId="p203.spi0.mosi" configurationId="p203"/> + <configSetting altId="p203.gpio_speed.gpio_speed_high" configurationId="p203.gpio_drivecapacity"/> + <configSetting altId="p203.gpio_mode.gpio_mode_peripheral" configurationId="p203.gpio_mode"/> + <configSetting altId="p204.spi0.rspck" configurationId="p204"/> + <configSetting altId="p204.gpio_speed.gpio_speed_high" configurationId="p204.gpio_drivecapacity"/> + <configSetting altId="p204.gpio_mode.gpio_mode_peripheral" configurationId="p204.gpio_mode"/> + <configSetting altId="p205.spi0.ssl0" configurationId="p205"/> + <configSetting altId="p205.gpio_speed.gpio_speed_high" configurationId="p205.gpio_drivecapacity"/> + <configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/> + <configSetting altId="p206.spi0.ssl1" configurationId="p206"/> + <configSetting altId="p206.gpio_speed.gpio_speed_high" configurationId="p206.gpio_drivecapacity"/> + <configSetting altId="p206.gpio_mode.gpio_mode_peripheral" configurationId="p206.gpio_mode"/> + <configSetting altId="p207.output.low" configurationId="p207"/> + <configSetting altId="p207.gpio_speed.gpio_speed_high" configurationId="p207.gpio_drivecapacity"/> + <configSetting altId="p207.gpio_mode.gpio_mode_out.low" configurationId="p207.gpio_mode"/> + <configSetting altId="p208.trace0.tdata3" configurationId="p208"/> + <configSetting altId="p208.gpio_mode.gpio_mode_peripheral" configurationId="p208.gpio_mode"/> + <configSetting altId="p209.trace0.tdata2" configurationId="p209"/> + <configSetting altId="p209.gpio_mode.gpio_mode_peripheral" configurationId="p209.gpio_mode"/> + <configSetting altId="p210.trace0.tdata1" configurationId="p210"/> + <configSetting altId="p210.gpio_mode.gpio_mode_peripheral" configurationId="p210.gpio_mode"/> + <configSetting altId="p211.trace0.tdata0" configurationId="p211"/> + <configSetting altId="p211.gpio_mode.gpio_mode_peripheral" configurationId="p211.gpio_mode"/> + <configSetting altId="p212.cgc0.extal" configurationId="p212"/> + <configSetting altId="p212.gpio_mode.gpio_mode_peripheral" configurationId="p212.gpio_mode"/> + <configSetting altId="p213.cgc0.xtal" configurationId="p213"/> + <configSetting altId="p213.gpio_mode.gpio_mode_peripheral" configurationId="p213.gpio_mode"/> + <configSetting altId="p214.trace0.tclk" configurationId="p214"/> + <configSetting altId="p214.gpio_mode.gpio_mode_peripheral" configurationId="p214.gpio_mode"/> + <configSetting altId="p300.debug0.swclk" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + <configSetting altId="p301.spi0.ssl2" configurationId="p301"/> + <configSetting altId="p301.gpio_speed.gpio_speed_high" configurationId="p301.gpio_drivecapacity"/> + <configSetting altId="p301.gpio_mode.gpio_mode_peripheral" configurationId="p301.gpio_mode"/> + <configSetting altId="p302.spi0.ssl3" configurationId="p302"/> + <configSetting altId="p302.gpio_speed.gpio_speed_high" configurationId="p302.gpio_drivecapacity"/> + <configSetting altId="p302.gpio_mode.gpio_mode_peripheral" configurationId="p302.gpio_mode"/> + <configSetting altId="p303.output.low" configurationId="p303"/> + <configSetting altId="p303.gpio_speed.gpio_speed_high" configurationId="p303.gpio_drivecapacity"/> + <configSetting altId="p303.gpio_mode.gpio_mode_out.low" configurationId="p303.gpio_mode"/> + <configSetting altId="p305.qspi0.qspclk" configurationId="p305"/> + <configSetting altId="p305.gpio_speed.gpio_speed_high" configurationId="p305.gpio_drivecapacity"/> + <configSetting altId="p305.gpio_mode.gpio_mode_peripheral" configurationId="p305.gpio_mode"/> + <configSetting altId="p306.qspi0.qssl" configurationId="p306"/> + <configSetting altId="p306.gpio_speed.gpio_speed_high" configurationId="p306.gpio_drivecapacity"/> + <configSetting altId="p306.gpio_mode.gpio_mode_peripheral" configurationId="p306.gpio_mode"/> + <configSetting altId="p307.qspi0.qio0" configurationId="p307"/> + <configSetting altId="p307.gpio_speed.gpio_speed_high" configurationId="p307.gpio_drivecapacity"/> + <configSetting altId="p307.gpio_mode.gpio_mode_peripheral" configurationId="p307.gpio_mode"/> + <configSetting altId="p308.qspi0.qio1" configurationId="p308"/> + <configSetting altId="p308.gpio_speed.gpio_speed_high" configurationId="p308.gpio_drivecapacity"/> + <configSetting altId="p308.gpio_mode.gpio_mode_peripheral" configurationId="p308.gpio_mode"/> + <configSetting altId="p309.qspi0.qio2" configurationId="p309"/> + <configSetting altId="p309.gpio_speed.gpio_speed_high" configurationId="p309.gpio_drivecapacity"/> + <configSetting altId="p309.gpio_mode.gpio_mode_peripheral" configurationId="p309.gpio_mode"/> + <configSetting altId="p310.qspi0.qio3" configurationId="p310"/> + <configSetting altId="p310.gpio_speed.gpio_speed_high" configurationId="p310.gpio_drivecapacity"/> + <configSetting altId="p310.gpio_mode.gpio_mode_peripheral" configurationId="p310.gpio_mode"/> + <configSetting altId="p311.output.low" configurationId="p311"/> + <configSetting altId="p311.gpio_speed.gpio_speed_high" configurationId="p311.gpio_drivecapacity"/> + <configSetting altId="p311.gpio_mode.gpio_mode_out.low" configurationId="p311.gpio_mode"/> + <configSetting altId="p400.input" configurationId="p400"/> + <configSetting altId="p400.gpio_irq.gpio_irq_enabled" configurationId="p400.gpio_irq"/> + <configSetting altId="p400.gpio_mode.gpio_mode_in" configurationId="p400.gpio_mode"/> + <configSetting altId="p400.gpio_pupd.gpio_pupd_ip_up" configurationId="p400.gpio_pupd"/> + <configSetting altId="p401.etherc0.rmii.mdc" configurationId="p401"/> + <configSetting altId="p401.gpio_speed.gpio_speed_high" configurationId="p401.gpio_drivecapacity"/> + <configSetting altId="p401.gpio_mode.gpio_mode_peripheral" configurationId="p401.gpio_mode"/> + <configSetting altId="p402.etherc0.rmii.mdio" configurationId="p402"/> + <configSetting altId="p402.gpio_speed.gpio_speed_high" configurationId="p402.gpio_drivecapacity"/> + <configSetting altId="p402.gpio_mode.gpio_mode_peripheral" configurationId="p402.gpio_mode"/> + <configSetting altId="p403.output.high" configurationId="p403"/> + <configSetting altId="p403.gpio_speed.gpio_speed_high" configurationId="p403.gpio_drivecapacity"/> + <configSetting altId="p403.gpio_mode.gpio_mode_out.high" configurationId="p403.gpio_mode"/> + <configSetting altId="p404.output.low" configurationId="p404"/> + <configSetting altId="p404.gpio_speed.gpio_speed_high" configurationId="p404.gpio_drivecapacity"/> + <configSetting altId="p404.gpio_mode.gpio_mode_out.low" configurationId="p404.gpio_mode"/> + <configSetting altId="p405.etherc0.rmii.txd_en" configurationId="p405"/> + <configSetting altId="p405.gpio_speed.gpio_speed_high" configurationId="p405.gpio_drivecapacity"/> + <configSetting altId="p405.gpio_mode.gpio_mode_peripheral" configurationId="p405.gpio_mode"/> + <configSetting altId="p406.etherc0.rmii.txd1" configurationId="p406"/> + <configSetting altId="p406.gpio_speed.gpio_speed_high" configurationId="p406.gpio_drivecapacity"/> + <configSetting altId="p406.gpio_mode.gpio_mode_peripheral" configurationId="p406.gpio_mode"/> + <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/> + <configSetting altId="p407.gpio_speed.gpio_speed_high" configurationId="p407.gpio_drivecapacity"/> + <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/> + <configSetting altId="p408.output.low" configurationId="p408"/> + <configSetting altId="p408.gpio_speed.gpio_speed_high" configurationId="p408.gpio_drivecapacity"/> + <configSetting altId="p408.gpio_mode.gpio_mode_out.low" configurationId="p408.gpio_mode"/> + <configSetting altId="p409.input" configurationId="p409"/> + <configSetting altId="p409.gpio_irq.gpio_irq_enabled" configurationId="p409.gpio_irq"/> + <configSetting altId="p409.gpio_mode.gpio_mode_in" configurationId="p409.gpio_mode"/> + <configSetting altId="p409.gpio_pupd.gpio_pupd_ip_up" configurationId="p409.gpio_pupd"/> + <configSetting altId="p410.spi1.miso" configurationId="p410"/> + <configSetting altId="p410.gpio_speed.gpio_speed_high" configurationId="p410.gpio_drivecapacity"/> + <configSetting altId="p410.gpio_mode.gpio_mode_peripheral" configurationId="p410.gpio_mode"/> + <configSetting altId="p411.spi1.mosi" configurationId="p411"/> + <configSetting altId="p411.gpio_speed.gpio_speed_high" configurationId="p411.gpio_drivecapacity"/> + <configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/> + <configSetting altId="p412.spi1.rspck" configurationId="p412"/> + <configSetting altId="p412.gpio_speed.gpio_speed_high" configurationId="p412.gpio_drivecapacity"/> + <configSetting altId="p412.gpio_mode.gpio_mode_peripheral" configurationId="p412.gpio_mode"/> + <configSetting altId="p413.spi1.ssl0" configurationId="p413"/> + <configSetting altId="p413.gpio_speed.gpio_speed_high" configurationId="p413.gpio_drivecapacity"/> + <configSetting altId="p413.gpio_mode.gpio_mode_peripheral" configurationId="p413.gpio_mode"/> + <configSetting altId="p414.iic2.sda" configurationId="p414"/> + <configSetting altId="p414.gpio_speed.gpio_speed_high" configurationId="p414.gpio_drivecapacity"/> + <configSetting altId="p414.gpio_mode.gpio_mode_peripheral" configurationId="p414.gpio_mode"/> + <configSetting altId="p415.iic2.scl" configurationId="p415"/> + <configSetting altId="p415.gpio_speed.gpio_speed_high" configurationId="p415.gpio_drivecapacity"/> + <configSetting altId="p415.gpio_mode.gpio_mode_peripheral" configurationId="p415.gpio_mode"/> + <configSetting altId="p500.usbfs0.vbusen" configurationId="p500"/> + <configSetting altId="p500.gpio_speed.gpio_speed_high" configurationId="p500.gpio_drivecapacity"/> + <configSetting altId="p500.gpio_mode.gpio_mode_peripheral" configurationId="p500.gpio_mode"/> + <configSetting altId="p501.usbfs0.ovrcura" configurationId="p501"/> + <configSetting altId="p501.gpio_speed.gpio_speed_high" configurationId="p501.gpio_drivecapacity"/> + <configSetting altId="p501.gpio_mode.gpio_mode_peripheral" configurationId="p501.gpio_mode"/> + <configSetting altId="p505.sci6.scl" configurationId="p505"/> + <configSetting altId="p505.gpio_speed.gpio_speed_high" configurationId="p505.gpio_drivecapacity"/> + <configSetting altId="p505.gpio_mode.gpio_mode_peripheral" configurationId="p505.gpio_mode"/> + <configSetting altId="p505.gpio_otype.gpio_otype_n_ch_od" configurationId="p505.gpio_otype"/> + <configSetting altId="p506.sci6.sda" configurationId="p506"/> + <configSetting altId="p506.gpio_speed.gpio_speed_high" configurationId="p506.gpio_drivecapacity"/> + <configSetting altId="p506.gpio_mode.gpio_mode_peripheral" configurationId="p506.gpio_mode"/> + <configSetting altId="p506.gpio_otype.gpio_otype_n_ch_od" configurationId="p506.gpio_otype"/> + <configSetting altId="p511.iic1.sda" configurationId="p511"/> + <configSetting altId="p511.gpio_speed.gpio_speed_high" configurationId="p511.gpio_drivecapacity"/> + <configSetting altId="p511.gpio_mode.gpio_mode_peripheral" configurationId="p511.gpio_mode"/> + <configSetting altId="p512.iic1.scl" configurationId="p512"/> + <configSetting altId="p512.gpio_speed.gpio_speed_high" configurationId="p512.gpio_drivecapacity"/> + <configSetting altId="p512.gpio_mode.gpio_mode_peripheral" configurationId="p512.gpio_mode"/> + <configSetting altId="p600.ospi0.omsio4" configurationId="p600"/> + <configSetting altId="p600.gpio_speed.gpio_speed_highspeedhigh" configurationId="p600.gpio_drivecapacity"/> + <configSetting altId="p600.gpio_mode.gpio_mode_peripheral" configurationId="p600.gpio_mode"/> + <configSetting altId="p601.ospi0.omsio2" configurationId="p601"/> + <configSetting altId="p601.gpio_speed.gpio_speed_highspeedhigh" configurationId="p601.gpio_drivecapacity"/> + <configSetting altId="p601.gpio_mode.gpio_mode_peripheral" configurationId="p601.gpio_mode"/> + <configSetting altId="p602.ospi0.omcs1" configurationId="p602"/> + <configSetting altId="p602.gpio_mode.gpio_mode_peripheral" configurationId="p602.gpio_mode"/> + <configSetting altId="p608.output.low" configurationId="p608"/> + <configSetting altId="p608.gpio_speed.gpio_speed_high" configurationId="p608.gpio_drivecapacity"/> + <configSetting altId="p608.gpio_mode.gpio_mode_out.low" configurationId="p608.gpio_mode"/> + <configSetting altId="p609.can1.ctx" configurationId="p609"/> + <configSetting altId="p609.gpio_mode.gpio_mode_peripheral" configurationId="p609.gpio_mode"/> + <configSetting altId="p610.can1.crx" configurationId="p610"/> + <configSetting altId="p610.gpio_mode.gpio_mode_peripheral" configurationId="p610.gpio_mode"/> + <configSetting altId="p611.output.low" configurationId="p611"/> + <configSetting altId="p611.gpio_speed.gpio_speed_high" configurationId="p611.gpio_drivecapacity"/> + <configSetting altId="p611.gpio_mode.gpio_mode_out.low" configurationId="p611.gpio_mode"/> + <configSetting altId="p613.sci7.txd" configurationId="p613"/> + <configSetting altId="p613.gpio_mode.gpio_mode_peripheral" configurationId="p613.gpio_mode"/> + <configSetting altId="p614.sci7.rxd" configurationId="p614"/> + <configSetting altId="p614.gpio_mode.gpio_mode_peripheral" configurationId="p614.gpio_mode"/> + <configSetting altId="p615.output.high" configurationId="p615"/> + <configSetting altId="p615.gpio_speed.gpio_speed_medium" configurationId="p615.gpio_drivecapacity"/> + <configSetting altId="p615.gpio_mode.gpio_mode_out.high" configurationId="p615.gpio_mode"/> + <configSetting altId="p700.etherc0.rmii.txd0" configurationId="p700"/> + <configSetting altId="p700.gpio_speed.gpio_speed_high" configurationId="p700.gpio_drivecapacity"/> + <configSetting altId="p700.gpio_mode.gpio_mode_peripheral" configurationId="p700.gpio_mode"/> + <configSetting altId="p701.etherc0.rmii.ref50ck" configurationId="p701"/> + <configSetting altId="p701.gpio_speed.gpio_speed_high" configurationId="p701.gpio_drivecapacity"/> + <configSetting altId="p701.gpio_mode.gpio_mode_peripheral" configurationId="p701.gpio_mode"/> + <configSetting altId="p702.etherc0.rmii.rxd0" configurationId="p702"/> + <configSetting altId="p702.gpio_speed.gpio_speed_high" configurationId="p702.gpio_drivecapacity"/> + <configSetting altId="p702.gpio_mode.gpio_mode_peripheral" configurationId="p702.gpio_mode"/> + <configSetting altId="p703.etherc0.rmii.rxd1" configurationId="p703"/> + <configSetting altId="p703.gpio_speed.gpio_speed_high" configurationId="p703.gpio_drivecapacity"/> + <configSetting altId="p703.gpio_mode.gpio_mode_peripheral" configurationId="p703.gpio_mode"/> + <configSetting altId="p704.etherc0.rmii.rx_er" configurationId="p704"/> + <configSetting altId="p704.gpio_speed.gpio_speed_high" configurationId="p704.gpio_drivecapacity"/> + <configSetting altId="p704.gpio_mode.gpio_mode_peripheral" configurationId="p704.gpio_mode"/> + <configSetting altId="p705.etherc0.rmii.crs_dv" configurationId="p705"/> + <configSetting altId="p705.gpio_speed.gpio_speed_high" configurationId="p705.gpio_drivecapacity"/> + <configSetting altId="p705.gpio_mode.gpio_mode_peripheral" configurationId="p705.gpio_mode"/> + <configSetting altId="p706.input" configurationId="p706"/> + <configSetting altId="p706.gpio_irq.gpio_irq_enabled" configurationId="p706.gpio_irq"/> + <configSetting altId="p706.gpio_mode.gpio_mode_in" configurationId="p706.gpio_mode"/> + <configSetting altId="p707.usbhs0.ovrcura" configurationId="p707"/> + <configSetting altId="p707.gpio_mode.gpio_mode_peripheral" configurationId="p707.gpio_mode"/> + <configSetting altId="p708.spi1.ssl3" configurationId="p708"/> + <configSetting altId="p708.gpio_speed.gpio_speed_high" configurationId="p708.gpio_drivecapacity"/> + <configSetting altId="p708.gpio_mode.gpio_mode_peripheral" configurationId="p708.gpio_mode"/> + <configSetting altId="p905.input" configurationId="p905"/> + <configSetting altId="p905.gpio_irq.gpio_irq_enabled" configurationId="p905.gpio_irq"/> + <configSetting altId="p905.gpio_mode.gpio_mode_in" configurationId="p905.gpio_mode"/> + <configSetting altId="p905.gpio_pupd.gpio_pupd_ip_up" configurationId="p905.gpio_pupd"/> + <configSetting altId="pb00.usbhs0.vbusen" configurationId="pb00"/> + <configSetting altId="pb00.gpio_speed.gpio_speed_high" configurationId="pb00.gpio_drivecapacity"/> + <configSetting altId="pb00.gpio_mode.gpio_mode_peripheral" configurationId="pb00.gpio_mode"/> + <configSetting altId="pb01.usbhs0.vbus" configurationId="pb01"/> + <configSetting altId="pb01.gpio_speed.gpio_speed_high" configurationId="pb01.gpio_drivecapacity"/> + <configSetting altId="pb01.gpio_mode.gpio_mode_peripheral" configurationId="pb01.gpio_mode"/> + <configSetting altId="qspi0.mode.quad.free" configurationId="qspi0.mode"/> + <configSetting altId="qspi0.pairing.free" configurationId="qspi0.pairing"/> + <configSetting altId="qspi0.qio0.p307" configurationId="qspi0.qio0"/> + <configSetting altId="qspi0.qio1.p308" configurationId="qspi0.qio1"/> + <configSetting altId="qspi0.qio2.p309" configurationId="qspi0.qio2"/> + <configSetting altId="qspi0.qio3.p310" configurationId="qspi0.qio3"/> + <configSetting altId="qspi0.qspclk.p305" configurationId="qspi0.qspclk"/> + <configSetting altId="qspi0.qssl.p306" configurationId="qspi0.qssl"/> + <configSetting altId="sci6.mode.iic.free" configurationId="sci6.mode"/> + <configSetting altId="sci6.scl.p505" configurationId="sci6.scl"/> + <configSetting altId="sci6.sda.p506" configurationId="sci6.sda"/> + <configSetting altId="sci7.mode.asynchronous.free" configurationId="sci7.mode"/> + <configSetting altId="sci7.rxd.p614" configurationId="sci7.rxd"/> + <configSetting altId="sci7.txd.p613" configurationId="sci7.txd"/> + <configSetting altId="spi0.miso.p202" configurationId="spi0.miso"/> + <configSetting altId="spi0.mode.custom.free" configurationId="spi0.mode"/> + <configSetting altId="spi0.mosi.p203" configurationId="spi0.mosi"/> + <configSetting altId="spi0.pairing.free" configurationId="spi0.pairing"/> + <configSetting altId="spi0.rspck.p204" configurationId="spi0.rspck"/> + <configSetting altId="spi0.ssl0.p205" configurationId="spi0.ssl0"/> + <configSetting altId="spi0.ssl1.p206" configurationId="spi0.ssl1"/> + <configSetting altId="spi0.ssl2.p301" configurationId="spi0.ssl2"/> + <configSetting altId="spi0.ssl3.p302" configurationId="spi0.ssl3"/> + <configSetting altId="spi1.miso.p410" configurationId="spi1.miso"/> + <configSetting altId="spi1.mode.enabled.free" configurationId="spi1.mode"/> + <configSetting altId="spi1.mosi.p411" configurationId="spi1.mosi"/> + <configSetting altId="spi1.pairing.free" configurationId="spi1.pairing"/> + <configSetting altId="spi1.rspck.p412" configurationId="spi1.rspck"/> + <configSetting altId="spi1.ssl0.p413" configurationId="spi1.ssl0"/> + <configSetting altId="spi1.ssl3.p708" configurationId="spi1.ssl3"/> + <configSetting altId="trace0.mode.trace4bit" configurationId="trace0.mode"/> + <configSetting altId="trace0.tclk.p214" configurationId="trace0.tclk"/> + <configSetting altId="trace0.tdata0.p211" configurationId="trace0.tdata0"/> + <configSetting altId="trace0.tdata1.p210" configurationId="trace0.tdata1"/> + <configSetting altId="trace0.tdata2.p209" configurationId="trace0.tdata2"/> + <configSetting altId="trace0.tdata3.p208" configurationId="trace0.tdata3"/> + <configSetting altId="usbfs0.mode.custom" configurationId="usbfs0.mode"/> + <configSetting altId="usbfs0.ovrcura.p501" configurationId="usbfs0.ovrcura"/> + <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/> + <configSetting altId="usbfs0.vbusen.p500" configurationId="usbfs0.vbusen"/> + <configSetting altId="usbhs0.mode.custom" configurationId="usbhs0.mode"/> + <configSetting altId="usbhs0.ovrcura.p707" configurationId="usbhs0.ovrcura"/> + <configSetting altId="usbhs0.vbus.pb01" configurationId="usbhs0.vbus"/> + <configSetting altId="usbhs0.vbusen.pb00" configurationId="usbhs0.vbusen"/> + </pincfg> + <pincfg active="false" name="R7FA6M5BH3CFC.pincfg" selected="false" symbol=""> + <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/> + <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/> + <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/> + <configSetting altId="p108.debug0.swdio" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p300.debug0.swclk" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + </pincfg> + </raPinConfiguration> +</raConfiguration> diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.cmake b/hw/bsp/ra/boards/ra8m1_ek/board.cmake new file mode 100644 index 000000000..c61166f38 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/board.cmake @@ -0,0 +1,16 @@ +set(CMAKE_SYSTEM_CPU cortex-m85 CACHE INTERNAL "System Processor") +set(MCU_VARIANT ra8m1) + +set(JLINK_DEVICE R7FA8M1AH) +#set(JLINK_OPTION "-USB 001083115236") + +# device default to PORT 1 High Speed +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif() + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.h b/hw/bsp/ra/boards/ra8m1_ek/board.h new file mode 100644 index 000000000..54672452f --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/board.h @@ -0,0 +1,47 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: RA8M1 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8m1-evaluation-kit-ra8m1-mcu-group +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define LED_STATE_ON 1 +#define BUTTON_STATE_ACTIVE 0 + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.mk b/hw/bsp/ra/boards/ra8m1_ek/board.mk new file mode 100644 index 000000000..2e56b3781 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/board.mk @@ -0,0 +1,11 @@ +CPU_CORE = cortex-m85 +MCU_VARIANT = ra8m1 + +# For flash-jlink target +JLINK_DEVICE = R7FA8M1AH + +# Port 1 is highspeed +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 + +flash: flash-jlink diff --git a/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex b/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex Binary files differnew file mode 100644 index 000000000..70dd323ec --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex diff --git a/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug b/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug new file mode 100644 index 000000000..242a15db9 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug @@ -0,0 +1,231 @@ + +/********************************************************************* +* +* OnProjectLoad +* +* Function description +* Project load routine. Required. +* +********************************************************************** +*/ +void OnProjectLoad (void) { + Project.SetTraceSource ("Trace Pins"); + Project.SetDevice ("R7FA8M1AH"); + Project.SetHostIF ("USB", ""); + Project.SetTargetIF ("SWD"); + Project.SetTIFSpeed ("50 MHz"); + + Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M85F.svd"); + Project.AddSvdFile ("../../../../../../../cmsis-svd-data/data/Renesas/R7FA6M5BH.svd"); + + File.Open ("../../../../../../examples/cmake-build-ra8m1_ek/device/cdc_msc/cdc_msc.elf"); +} +/********************************************************************* +* +* BeforeTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +void BeforeTargetConnect (void) { + // Trace pin init is done by J-Link script file as J-Link script files are IDE independent + //Project.SetJLinkScript("../../../debug.jlinkscript"); + Project.SetJLinkScript ("$(ProjectDir)/Renesas_RA8_TracePins.pex"); +} + +/********************************************************************* +* +* AfterTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetConnect (void) { +//} + +/********************************************************************* +* +* TargetDownload +* +* Function description +* Replaces the default program download routine. Optional. +* +********************************************************************** +*/ +//void TargetDownload (void) { +//} + +/********************************************************************* +* +* BeforeTargetDownload +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDownload (void) { +//} + +/********************************************************************* +* +* AfterTargetDownload +* +* Function description +* Event handler routine. Optional. +* The default implementation initializes SP and PC to reset values. +* +********************************************************************** +*/ +void AfterTargetDownload (void) { + _SetupTarget(); +} + +/********************************************************************* +* +* BeforeTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetHalt +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetHalt (void) { +//} + +/********************************************************************* +* +* BeforeTargetResume +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetResume (void) { +//} + +/********************************************************************* +* +* OnSnapshotLoad +* +* Function description +* Called upon loading a snapshot. Optional. +* +* Additional information +* This function is used to restore the target state in cases +* where values cannot simply be written to the target. +* Typical use: GPIO clock needs to be enabled, before +* GPIO is configured. +* +********************************************************************** +*/ +//void OnSnapshotLoad (void) { +//} + +/********************************************************************* +* +* OnSnapshotSave +* +* Function description +* Called upon saving a snapshot. Optional. +* +* Additional information +* This function is usually used to save values of the target +* state which can either not be trivially read, +* or need to be restored in a specific way or order. +* Typically use: Memory Mapped Registers, +* such as PLL and GPIO configuration. +* +********************************************************************** +*/ +//void OnSnapshotSave (void) { +//} + +/********************************************************************* +* +* OnError +* +* Function description +* Called when an error occurred. Optional. +* +********************************************************************** +*/ +//void OnError (void) { +//} + +/********************************************************************* +* +* AfterProjectLoad +* +* Function description +* After Project load routine. Optional. +* +********************************************************************** +*/ +//void AfterProjectLoad (void) { +//} + +/********************************************************************* +* +* _SetupTarget +* +* Function description +* Setup the target. +* Called by AfterTargetReset() and AfterTargetDownload(). +* +* Auto-generated function. May be overridden by Ozone. +* +********************************************************************** +*/ +void _SetupTarget(void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + // + // Set up initial stack pointer + // + SP = Target.ReadU32(VectorTableAddr); + if (SP != 0xFFFFFFFF) { + Target.SetReg("SP", SP); + } + // + // Set up entry point PC + // + PC = Elf.GetEntryPointPC(); + if (PC != 0xFFFFFFFF) { + Target.SetReg("PC", PC); + } else { + Util.Error("Project script error: failed to set up entry point PC", 1); + } +} diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..90afbdef3 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x1000) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..92e7ddcdb --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (8) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..a22da075d --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA8M1AHECBD + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (2064384) + #define BSP_RAM_SIZE_BYTES (917504) + #define BSP_DATA_FLASH_SIZE_BYTES (12288) + #define BSP_PACKAGE_BGA + #define BSP_PACKAGE_PINS (224) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..94f09c61f --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,526 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h" + #include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA8M1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (0) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 7 + #define BSP_HOCO_HZ (48000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + + #define BSP_CFG_FLL_ENABLE (0) + + #define BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE (1) + #define BSP_CFG_SLEEP_MODE_DELAY_ENABLE (1) + #define BSP_CFG_MSTP_CHANGE_DELAY_ENABLE (1) + #define BSP_CFG_RTOS_IDLE_SLEEP (0) + #define BSP_CFG_CLOCK_SETTLING_DELAY_US (150) + + #if defined(BSP_PACKAGE_LQFP) && (BSP_PACKAGE_PINS == 100) + #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (180000000U) + #elif defined(BSP_PACKAGE_LQFP) + #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (200000000U) + #else + #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (240000000U) + #endif + + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) + + #if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif + + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL + #define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL + #define FPU_FPCCR_TS_VAL (1U) +#endif + #define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL + #define FPU_FPCCR_CLRONRET_VAL (1) +#endif + + /* Type 1 Peripheral Security Attribution */ + + /* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* USBHS */ | \ + (1 << 15) /* ETHERC/EDMAC */ | \ + (1 << 16) /* OSPI */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */) +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7) /* SSIE1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* SDHI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* CEU */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* CANFD1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* RSIP-E51A */) +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* AGT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC121 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC120 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC120 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* ACMPHS1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ACMPHS0 */) +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* ULPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* ULPT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* GPT13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* GPT12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* GPT11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21) /* GPT10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */) +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* DTC_DMAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* ELC */) +#endif + + /* Type 2 Peripheral Security Attribution */ + + /* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0x00000007U) +#endif + + /* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR + /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ +#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) +#define BSP_TZ_CFG_LVDSAR (0U) +#else +#define BSP_TZ_CFG_LVDSAR (3U) +#endif +#endif + + /* Security attribution for LPM registers. + * - OPCCR based on clock security. + * - Set remaining registers based on LPM security. + */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 : (\ + 0x002E0106U | \ + (BSP_CFG_CLOCKS_SECURE == 0))) +#endif + /* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0U : 0xAF1FFFFFU) +#endif + /* RAM Standby Control Security Attribution Register. */ +#ifndef BSP_TZ_CFG_RSCSAR +#define BSP_TZ_CFG_RSCSAR ((RA_NOT_DEFINED > 0) ? 0U : 0x00037FFFU) +#endif + + /* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0x047F3BFDU) +#endif +#endif + + /* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#if 0 +#define BSP_TZ_CFG_BBFSAR (0U) +#else +#define BSP_TZ_CFG_BBFSAR (0x1FU) +#endif +#endif + + /* Security attribution for Battery Backup registers (VBTBKRn). */ +#ifndef BSP_TZ_CFG_VBRSABAR +#if 0 +#define BSP_TZ_CFG_VBRSABAR (0xFFE0) +#else +#define BSP_TZ_CFG_VBRSABAR (0xED00) +#endif +#endif + + /* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */) +#endif + + /* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0U) /* Should match AIRCR.BFHFNMINS. */ +#endif + + /* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_DMACCHSAR +#define BSP_TZ_CFG_DMACCHSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */) +#endif + + /* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0U : 0xFF1D0000U) +#endif + + /* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0U : 0x00007F08U) +#endif + + /* Trusted Event Route Control Register for IELSR, DMAC.DELSR and ELC.ELSR. Note that currently Trusted Event Route Control is not supported. */ +#ifndef BSP_TZ_CFG_TEVTRCR +#define BSP_TZ_CFG_TEVTRCR (0) +#endif + + /* Security attribution register for ELCR, ELSEGR0, ELSEGR1 Security Attribution. */ +#ifndef BSP_TZ_CFG_ELCSARA + #define BSP_TZ_CFG_ELCSARA (0x00000007U) +#endif + + /* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED + #define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + + /* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#define BSP_TZ_CFG_FSAR (\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */\ + ((RA_NOT_DEFINED) > 0 ? 0U: (1U << 1)) | /* FCACHESA */\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \ + ((RA_NOT_DEFINED) > 0 ? 0U : (1U << 9U)) | /* FACICMISA */\ + ((RA_NOT_DEFINED) > 0 ? 0U: (1U << 10U)) /* FACICMRSA */) +#endif + + /* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ + #define BSP_TZ_CFG_SRAMSAR (\ + ((1U) << 0U) | /* SRAMSA0 */\ + ((1U) << 1U) | /* SRAMSA1 */\ + ((1U) << 7U) | /* STBRAMSA */\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */) +#endif + + /* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_DMACCHSAR) +#endif + + /* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA + #define BSP_TZ_CFG_BUSSARA (1U) +#endif + /* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB + #define BSP_TZ_CFG_BUSSARB (1U) +#endif + /* Security Attribution Register C for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARC + #define BSP_TZ_CFG_BUSSARC (1U) +#endif + + /* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + + + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + + #define BSP_CFG_ROM_REG_OFS2 ((1 << 0) | 0xFFFFFFFEU) + + /* Option Function Select Register 1 Security Attribution */ +#ifndef BSP_CFG_ROM_REG_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U) | ((0U << 24U)) | ((0U << 25U))) +#else + #define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U) +#endif +#endif + #define BSP_CFG_ROM_REG_OFS1_INITECCEN (0 << 25) + #define BSP_CFG_ROM_REG_OFS1 (0xFCFFFED0 | (1 << 3) | (7) | (1 << 5) | (1 << 8) | (1 << 24) | (BSP_CFG_ROM_REG_OFS1_INITECCEN)) + + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + + /* Dual Mode Select Register */ +#ifndef BSP_CFG_ROM_REG_DUALSEL + #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) +#endif + + /* Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_BPS0 + #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) +#endif + /* Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_BPS1 + #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) +#endif + /* Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_BPS2 + #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) +#endif + /* Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_BPS3 + #define BSP_CFG_ROM_REG_BPS3 (~( 0U)) +#endif + /* Permanent Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_PBPS0 + #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) +#endif + /* Permanent Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_PBPS1 + #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) +#endif + /* Permanent Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_PBPS2 + #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) +#endif + /* Permanent Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_PBPS3 + #define BSP_CFG_ROM_REG_PBPS3 (~( 0U)) +#endif + /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL0 + #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) +#endif + /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL1 + #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) +#endif + /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL2 + #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) +#endif + /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL3 + #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif + /* Security Attribution for Bank Select Register */ +#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL + #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + + /* FSBL Control Register 0 */ +#ifndef BSP_CFG_ROM_REG_FSBLCTRL0 +#define BSP_CFG_ROM_REG_FSBLCTRL0 ( \ + (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos) | \ + (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos) | \ + (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos) | \ + (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos) | \ + 0xFFFFF000) +#endif + + /* FSBL Control Register 1 */ +#ifndef BSP_CFG_ROM_REG_FSBLCTRL1 +#define BSP_CFG_ROM_REG_FSBLCTRL1 ( \ + (3 << R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos) | \ + 0xFFFFFFFC) +#endif + + /* FSBL Control Register 2 */ +#ifndef BSP_CFG_ROM_REG_FSBLCTRL2 +#define BSP_CFG_ROM_REG_FSBLCTRL2 ( \ + (15 << R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos) | \ + (0x1F << R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos) | \ + 0xFFFFFE00) +#endif + + /* Start Address of Code Certificate Register 0 */ +#ifndef BSP_CFG_ROM_REG_SACC0 +#define BSP_CFG_ROM_REG_SACC0 (0xFFFFFFFF) +#endif + + /* Start Address of Code Certificate Register 1 */ +#ifndef BSP_CFG_ROM_REG_SACC1 +#define BSP_CFG_ROM_REG_SACC1 (0xFFFFFFFF) +#endif + + /* Start Address of Measurement Report Register */ +#ifndef BSP_CFG_ROM_REG_SAMR +#define BSP_CFG_ROM_REG_SAMR (0xFFFFFFFF) +#endif + +#ifndef BSP_CFG_DCACHE_ENABLED +#define BSP_CFG_DCACHE_ENABLED (0) +#endif + + +#ifndef BSP_CFG_SDRAM_ENABLED + #define BSP_CFG_SDRAM_ENABLED (0) +#endif + +#ifndef BSP_CFG_SDRAM_TRAS + #define BSP_CFG_SDRAM_TRAS (6) +#endif + +#ifndef BSP_CFG_SDRAM_TRCD + #define BSP_CFG_SDRAM_TRCD (3) +#endif + +#ifndef BSP_CFG_SDRAM_TRP + #define BSP_CFG_SDRAM_TRP (3) +#endif + +#ifndef BSP_CFG_SDRAM_TWR + #define BSP_CFG_SDRAM_TWR (2) +#endif + +#ifndef BSP_CFG_SDRAM_TCL + #define BSP_CFG_SDRAM_TCL (3) +#endif + +#ifndef BSP_CFG_SDRAM_TRFC + #define BSP_CFG_SDRAM_TRFC (937) +#endif + +#ifndef BSP_CFG_SDRAM_TREFW + #define BSP_CFG_SDRAM_TREFW (8) +#endif + +#ifndef BSP_CFG_SDRAM_INIT_ARFI + #define BSP_CFG_SDRAM_INIT_ARFI (10) +#endif + +#ifndef BSP_CFG_SDRAM_INIT_ARFC + #define BSP_CFG_SDRAM_INIT_ARFC (8) +#endif + +#ifndef BSP_CFG_SDRAM_INIT_PRC + #define BSP_CFG_SDRAM_INIT_PRC (3) +#endif + +#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT + #define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (1) +#endif + +#ifndef BSP_CFG_SDRAM_ENDIAN_MODE + #define BSP_CFG_SDRAM_ENDIAN_MODE (0) +#endif + +#ifndef BSP_CFG_SDRAM_ACCESS_MODE + #define BSP_CFG_SDRAM_ACCESS_MODE (1) +#endif + +#ifndef BSP_CFG_SDRAM_BUS_WIDTH + #define BSP_CFG_SDRAM_BUS_WIDTH (0) +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..883363437 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,127 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define ENET_RMII_INT (BSP_IO_PORT_00_PIN_00) +#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_01) +#define GROVE2_AN102 (BSP_IO_PORT_00_PIN_02) +#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_03) +#define ARDUINO_A0_MIKROBUS_AN000 (BSP_IO_PORT_00_PIN_04) +#define GROVE2_AN001 (BSP_IO_PORT_00_PIN_05) +#define PMOD1_IRQ11 (BSP_IO_PORT_00_PIN_06) +#define ARDUINO_A004 (BSP_IO_PORT_00_PIN_07) +#define USER_S2 (BSP_IO_PORT_00_PIN_08) +#define SW1 (BSP_IO_PORT_00_PIN_09) +#define MIKROBUS_IRQ14 (BSP_IO_PORT_00_PIN_10) +#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14) +#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15) +#define OSPI_DQ0 (BSP_IO_PORT_01_PIN_00) +#define OSPI_DQ3 (BSP_IO_PORT_01_PIN_01) +#define OSPI_DQ4 (BSP_IO_PORT_01_PIN_02) +#define OSPI_DQ2 (BSP_IO_PORT_01_PIN_03) +#define OSPI_CS (BSP_IO_PORT_01_PIN_04) +#define OSPI_INT (BSP_IO_PORT_01_PIN_05) +#define OSPI_RESET (BSP_IO_PORT_01_PIN_06) +#define LED3 (BSP_IO_PORT_01_PIN_07) +#define ETH_A_RMII_RMII_RXDV (BSP_IO_PORT_01_PIN_12) +#define ETH_A_LINKSTA (BSP_IO_PORT_01_PIN_14) +#define MPLX_CTRL (BSP_IO_PORT_01_PIN_15) +#define NMI (BSP_IO_PORT_02_PIN_00) +#define MD (BSP_IO_PORT_02_PIN_01) +#define CAN_STB (BSP_IO_PORT_02_PIN_07) +#define TDI (BSP_IO_PORT_02_PIN_08) +#define TDO (BSP_IO_PORT_02_PIN_09) +#define SWDIO (BSP_IO_PORT_02_PIN_10) +#define SWCLK (BSP_IO_PORT_02_PIN_11) +#define EXTAL (BSP_IO_PORT_02_PIN_12) +#define XTAL (BSP_IO_PORT_02_PIN_13) +#define ETH_A_RXER (BSP_IO_PORT_03_PIN_00) +#define ETH_A_RXD1 (BSP_IO_PORT_03_PIN_01) +#define ETH_A_RXD0 (BSP_IO_PORT_03_PIN_02) +#define ETH_A_REFCLK (BSP_IO_PORT_03_PIN_03) +#define ETH_A_TXD0 (BSP_IO_PORT_03_PIN_04) +#define ETH_A_TXD1 (BSP_IO_PORT_03_PIN_05) +#define ETH_A_TXEN (BSP_IO_PORT_03_PIN_06) +#define ETH_A_MDIO (BSP_IO_PORT_03_PIN_07) +#define ETH_A_MDC (BSP_IO_PORT_03_PIN_08) +#define ARDUINO_D0_MIKROBUS_RXD3 (BSP_IO_PORT_03_PIN_09) +#define ARDUINO_D1_MIKROBUS_TXD3 (BSP_IO_PORT_03_PIN_10) +#define CAN_RXD (BSP_IO_PORT_03_PIN_11) +#define CAN_TXD (BSP_IO_PORT_03_PIN_12) +#define I3C_SCL0_ARDUINO_MIKROBUS_PMOD1_3_qwiic (BSP_IO_PORT_04_PIN_00) +#define I3C_SDA0_ARDUINO_MIKROBUS_PMOD1_4_qwiic (BSP_IO_PORT_04_PIN_01) +#define ETH_B_MDIO (BSP_IO_PORT_04_PIN_02) +#define ETH_B_LINKSTA (BSP_IO_PORT_04_PIN_03) +#define ETH_B_RST_N (BSP_IO_PORT_04_PIN_04) +#define ETH_B_TXEN (BSP_IO_PORT_04_PIN_05) +#define ETH_B_TXD1 (BSP_IO_PORT_04_PIN_06) +#define USBFS_VBUS (BSP_IO_PORT_04_PIN_07) +#define USBHS_VBUSEN (BSP_IO_PORT_04_PIN_08) +#define USBHS_OVRCURA (BSP_IO_PORT_04_PIN_09) +#define MISOB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_10) +#define MOSIB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_11) +#define RSPCKB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_12) +#define SSLB0_B_ARDUINO_D10_MIKROBUS (BSP_IO_PORT_04_PIN_13) +#define LED2 (BSP_IO_PORT_04_PIN_14) +#define USBFS_VBUS_EN (BSP_IO_PORT_05_PIN_00) +#define USBFS_OVERCURA (BSP_IO_PORT_05_PIN_01) +#define MIKROBUS_RESET (BSP_IO_PORT_05_PIN_02) +#define PMOD2_7_IRQ1 (BSP_IO_PORT_05_PIN_08) +#define GROVE2_IIC_SDA1 (BSP_IO_PORT_05_PIN_11) +#define GROVE2_IIC_SCL1 (BSP_IO_PORT_05_PIN_12) +#define LED1 (BSP_IO_PORT_06_PIN_00) +#define ARDUINO_D5 (BSP_IO_PORT_06_PIN_01) +#define ARDUINO_D6 (BSP_IO_PORT_06_PIN_02) +#define ARDUINO_D9 (BSP_IO_PORT_06_PIN_03) +#define PMOD1_3_MISO0_RXD0_SCL0 (BSP_IO_PORT_06_PIN_09) +#define PMOD1_2_MOSI0_TXD0 (BSP_IO_PORT_06_PIN_10) +#define PMOD1_4_SCK0 (BSP_IO_PORT_06_PIN_11) +#define PMOD1_1_SSL0_CTS_RTS (BSP_IO_PORT_06_PIN_12) +#define PMOD1_1_CTS0 (BSP_IO_PORT_06_PIN_13) +#define PMOD1_9_GPIO (BSP_IO_PORT_06_PIN_14) +#define PMOD1_10_GPIO (BSP_IO_PORT_06_PIN_15) +#define ETH_B_TXD0 (BSP_IO_PORT_07_PIN_00) +#define ETH_B_REFCLK (BSP_IO_PORT_07_PIN_01) +#define ETH_B_RXD0 (BSP_IO_PORT_07_PIN_02) +#define ETH_B_RXD1 (BSP_IO_PORT_07_PIN_03) +#define ETH_B_RXER (BSP_IO_PORT_07_PIN_04) +#define ETH_B_RMII_RXDV (BSP_IO_PORT_07_PIN_05) +#define I3C_SDA0_PULLUP (BSP_IO_PORT_07_PIN_11) +#define OSPI_DQ5 (BSP_IO_PORT_08_PIN_00) +#define OSPI_DS (BSP_IO_PORT_08_PIN_01) +#define OSPI_DQ6 (BSP_IO_PORT_08_PIN_02) +#define OSPI_DQ1 (BSP_IO_PORT_08_PIN_03) +#define OSPI_DQ7 (BSP_IO_PORT_08_PIN_04) +#define OSPI_CK (BSP_IO_PORT_08_PIN_08) +#define PMOD2_8_RESET (BSP_IO_PORT_08_PIN_09) +#define PMOD2_9_GPIO (BSP_IO_PORT_08_PIN_10) +#define PMOD2_10_GPIO (BSP_IO_PORT_08_PIN_11) +#define ARDUINO_RESET (BSP_IO_PORT_08_PIN_12) +#define USBFS_P (BSP_IO_PORT_08_PIN_14) +#define USBFS_N (BSP_IO_PORT_08_PIN_15) +#define ARDUINO_D4 (BSP_IO_PORT_09_PIN_05) +#define ARDUINO_D2 (BSP_IO_PORT_09_PIN_06) +#define ARDUINO_D3_MIKROBUS_GTIOC13A (BSP_IO_PORT_09_PIN_07) +#define ARDUINO_D7 (BSP_IO_PORT_09_PIN_08) +#define ARDUINO_D8 (BSP_IO_PORT_09_PIN_09) +#define PMOD2_3_MISO2_RXD2 (BSP_IO_PORT_10_PIN_02) +#define PMOD2_2_MOSI2_TXD2 (BSP_IO_PORT_10_PIN_03) +#define PMOD2_4_SCK2 (BSP_IO_PORT_10_PIN_04) +#define PMOD2_1_CTS_RTS_SSL2 (BSP_IO_PORT_10_PIN_05) +#define PMOD2_1_CTS2 (BSP_IO_PORT_10_PIN_06) +#define PMOD1_8_RESET (BSP_IO_PORT_10_PIN_08) +#define JLOB_COMS_TX (BSP_IO_PORT_10_PIN_14) +#define JLOB_COMS_RX (BSP_IO_PORT_10_PIN_15) +#define I3C_SCL0_PULLUP (BSP_IO_PORT_11_PIN_00) +#define USBHS_VBUS (BSP_IO_PORT_11_PIN_01) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA8M1 EK */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..f2f1ae0c9 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,56 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (7) /* HOCO 48MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL Mul x80-99|Mul x96|PLL Mul x96.00 */ +#define BSP_CFG_PLL_FREQUENCY_HZ (960000000) /* PLL 960000000Hz */ +#define BSP_CFG_PLODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL1P Div /2 */ +#define BSP_CFG_PLL1P_FREQUENCY_HZ (480000000) /* PLL1P 480000000Hz */ +#define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_4) /* PLL1Q Div /4 */ +#define BSP_CFG_PLL1Q_FREQUENCY_HZ (240000000) /* PLL1Q 240000000Hz */ +#define BSP_CFG_PLODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL1R Div /2 */ +#define BSP_CFG_PLL1R_FREQUENCY_HZ (480000000) /* PLL1R 480000000Hz */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL2 Mul x80-99|Mul x96|PLL2 Mul x96.00 */ +#define BSP_CFG_PLL2_FREQUENCY_HZ (0) /* PLL2 0Hz */ +#define BSP_CFG_PL2ODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL2P Div /2 */ +#define BSP_CFG_PLL2P_FREQUENCY_HZ (0) /* PLL2P 0Hz */ +#define BSP_CFG_PL2ODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL2Q Div /2 */ +#define BSP_CFG_PLL2Q_FREQUENCY_HZ (0) /* PLL2Q 0Hz */ +#define BSP_CFG_PL2ODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL2R Div /2 */ +#define BSP_CFG_PLL2R_FREQUENCY_HZ (0) /* PLL2R 0Hz */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* Clock Src: PLL1P */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_SCICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SCICLK Disabled */ +#define BSP_CFG_SPICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_I3CCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* I3CCLK Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1Q) /* UCK Src: PLL1Q */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* U60CK Src: PLL1P */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKA Div /4 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKB Div /8 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKC Div /8 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKD Div /4 */ +#define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKE Div /2 */ +#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLK Enabled */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* BCLK Div /4 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* FCLK Div /8 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_SCICLK_DIV (BSP_CLOCKS_SCI_CLOCK_DIV_4) /* SCICLK Div /4 */ +#define BSP_CFG_SPICLK_DIV (BSP_CLOCKS_SPI_CLOCK_DIV_4) /* SPICLK Div /4 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_8) /* CANFDCLK Div /8 */ +#define BSP_CFG_I3CCLK_DIV (BSP_CLOCKS_I3C_CLOCK_DIV_3) /* I3CCLK Div /3 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_8) /* U60CK Div /8 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_4) /* OCTASPICLK Div /4 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..b92421739 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c @@ -0,0 +1,275 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_02_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_02_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_03_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_03_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_03_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_03_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_03_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, + { + .pin = BSP_IO_PORT_04_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, + { + .pin = BSP_IO_PORT_04_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_13, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_05_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_05_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_06_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_08_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_08_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_08_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_10_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_10_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_10_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_10_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_10_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_10_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_10_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_11_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld new file mode 100644 index 000000000..d7f78a915 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld @@ -0,0 +1,823 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; +OPTION_SETTING_DATA_FLASH_S_START = DEFINED(OPTION_SETTING_DATA_FLASH_S_START) ? OPTION_SETTING_DATA_FLASH_S_START : 0; +OPTION_SETTING_DATA_FLASH_S_LENGTH = DEFINED(OPTION_SETTING_DATA_FLASH_S_LENGTH) ? OPTION_SETTING_DATA_FLASH_S_LENGTH : 0; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_DATA_FLASH = PROJECT_SECURE_OR_FLAT && (OPTION_SETTING_DATA_FLASH_S_LENGTH != 0); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + OPTION_SETTING_DATA_FLASH_S (r) : ORIGIN = OPTION_SETTING_DATA_FLASH_S_START, LENGTH = OPTION_SETTING_DATA_FLASH_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __FLASH_NSC_START = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + . = .; + __nocache_pre_location = .; + .nocache ALIGN(32) (NOLOAD): + { + __nocache_start = .; + + KEEP(*(.nocache)) + + . = ALIGN(32); + __nocache_end = .; + } > RAM + . = (SIZEOF(.nocache) > 0) ? __nocache_end : __nocache_pre_location; + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __RAM_NSC_START = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(FLASH_BOOTLOADER_LENGTH) ? (RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH) : DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_NSC_START, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + . = .; + __nocache_sdram_pre_location = .; + .nocache_sdram ALIGN(32) (NOLOAD): + { + __nocache_sdram_start = .; + + KEEP(*(.nocache_sdram)) + + . = ALIGN(32); + __nocache_sdram_end = .; + } > SDRAM + . = (SIZEOF(.nocache_sdram) > 0) ? __nocache_sdram_end : __nocache_sdram_pre_location; + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_DATA_FLASH_S_S = ORIGIN(OPTION_SETTING_DATA_FLASH_S); + + .option_setting_data_flash_s : + { + __OPTION_SETTING_DATA_FLASH_S_Start = .; + KEEP(*(.option_setting_data_flash_fsblctrl0)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x04 : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_fsblctrl1)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x08 : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_fsblctrl2)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x0C : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_sacc0)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x10 : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_sacc1)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x14 : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_samr)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x2E0 : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_hoemrtpk)) + __OPTION_SETTING_DATA_FLASH_S_End = .; + } > OPTION_SETTING_DATA_FLASH_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_DATA_FLASH_S_N = __OPTION_SETTING_DATA_FLASH_S_End; +} diff --git a/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld new file mode 100644 index 000000000..2bc162511 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld @@ -0,0 +1,30 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x22000000; + RAM_LENGTH = 0xE0000; + FLASH_START = 0x02000000; + FLASH_LENGTH = 0x1F8000; + DATA_FLASH_START = 0x27000000; + DATA_FLASH_LENGTH = 0x3000; + OPTION_SETTING_START = 0x0300A100; + OPTION_SETTING_LENGTH = 0x100; + OPTION_SETTING_S_START = 0x0300A200; + OPTION_SETTING_S_LENGTH = 0x100; + OPTION_SETTING_DATA_FLASH_S_START = 0x27030080; + OPTION_SETTING_DATA_FLASH_S_LENGTH = 0x800; + ID_CODE_START = 0x00000000; + ID_CODE_LENGTH = 0x0; + SDRAM_START = 0x68000000; + SDRAM_LENGTH = 0x8000000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x0; + OSPI_DEVICE_0_START = 0x80000000; + OSPI_DEVICE_0_LENGTH = 0x10000000; + OSPI_DEVICE_1_START = 0x90000000; + OSPI_DEVICE_1_LENGTH = 0x10000000; + ITCM_START = 0x00000000; + ITCM_LENGTH = 0x10000; + DTCM_START = 0x20000000; + DTCM_LENGTH = 0x10000; + NS_OFFSET_START = 0x10000000; + NS_OFFSET_LENGTH = 0x0; diff --git a/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..0f83b4a11 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml @@ -0,0 +1,680 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<raConfiguration version="9"> + <generalSettings> + <option key="#Board#" value="board.ra8m1ek"/> + <option key="CPU" value="RA8M1"/> + <option key="Core" value="CM85"/> + <option key="#TargetName#" value="R7FA8M1AHECBD"/> + <option key="#TargetARCHITECTURE#" value="cortex-m85"/> + <option key="#DeviceCommand#" value="R7FA8M1AH"/> + <option key="#RTOS#" value="_none"/> + <option key="#pinconfiguration#" value="R7FA8M1AHECBD.pincfg"/> + <option key="#FSPVersion#" value="5.6.0"/> + <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra8m1_ek##"/> + <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/> + </generalSettings> + <raBspConfiguration> + <config id="config.bsp.ra8m1.R7FA8M1AHECBD"> + <property id="config.bsp.part_number" value="config.bsp.part_number.value"/> + <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/> + <property id="config.bsp.rom_size_bytes_hidden" value="2064384"/> + <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/> + <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/> + <property id="config.bsp.package_style" value="config.bsp.package_style.value"/> + <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/> + <property id="config.bsp.irq_count_hidden" value="96"/> + </config> + <config id="config.bsp.ra8m1"> + <property id="config.bsp.series" value="config.bsp.series.value"/> + </config> + <config id="config.bsp.ra8m1.fsp"> + <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/> + <property id="config.bsp.fsp.sdram.enabled" value="config.bsp.fsp.sdram.enabled.disabled"/> + <property id="config.bsp.fsp.sdram.tras" value="config.bsp.fsp.sdram.tras.6"/> + <property id="config.bsp.fsp.sdram.trcd" value="config.bsp.fsp.sdram.trcd.3"/> + <property id="config.bsp.fsp.sdram.trp" value="config.bsp.fsp.sdram.trp.3"/> + <property id="config.bsp.fsp.sdram.twr" value="config.bsp.fsp.sdram.twr.2"/> + <property id="config.bsp.fsp.sdram.tcl" value="config.bsp.fsp.sdram.tcl.3"/> + <property id="config.bsp.fsp.sdram.trfc" value="937"/> + <property id="config.bsp.fsp.sdram.trefw" value="config.bsp.fsp.sdram.trefw.8"/> + <property id="config.bsp.fsp.sdram.arfi" value="config.bsp.fsp.sdram.arfi.10"/> + <property id="config.bsp.fsp.sdram.arfc" value="config.bsp.fsp.sdram.arfc.8"/> + <property id="config.bsp.fsp.sdram.prc" value="config.bsp.fsp.sdram.prc.3"/> + <property id="config.bsp.fsp.sdram.addr_shift" value="config.bsp.fsp.sdram.addr_shift.9"/> + <property id="config.bsp.fsp.sdram.endian_mode" value="config.bsp.fsp.sdram.endian_mode.little"/> + <property id="config.bsp.fsp.sdram.continuous_access_mode" value="config.bsp.fsp.sdram.continuous_access_mode.enabled"/> + <property id="config.bsp.fsp.sdram.bus_width" value="config.bsp.fsp.sdram.bus_width.16"/> + <property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/> + <property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/> + <property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/> + <property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/> + <property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/> + <property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/> + <property id="config.bsp.fsp.tz.sramsar.sramsa0" value="config.bsp.fsp.tz.sramsar.sramsa0.both"/> + <property id="config.bsp.fsp.tz.sramsar.sramsa1" value="config.bsp.fsp.tz.sramsar.sramsa1.both"/> + <property id="config.bsp.fsp.tz.sramsar.stbramsa" value="config.bsp.fsp.tz.sramsar.stbramsa.both"/> + <property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/> + <property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/> + <property id="config.bsp.fsp.tz.bussarc" value="config.bsp.fsp.tz.bussarc.both"/> + <property id="config.bsp.fsp.tz.banksel_sel" value="config.bsp.fsp.tz.banksel_sel.both"/> + <property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/> + <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/> + <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/> + <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0_level" value="config.bsp.fsp.OFS1_SEL.voltage_detection0_level.secure"/> + <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.start" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.start.secure"/> + <property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.low_power_consumption" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.low_power_consumption.secure"/> + <property id="config.bsp.fsp.OFS1_SEL.swdbg" value="config.bsp.fsp.OFS1_SEL.swdbg.secure"/> + <property id="config.bsp.fsp.OFS1_SEL.initeccen" value="config.bsp.fsp.OFS1_SEL.initeccen.secure"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.160"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0.low_power_consumption" value="config.bsp.fsp.OFS1.voltage_detection0.low_power_consumption.disabled"/> + <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/> + <property id="config.bsp.fsp.OFS1.swdbg" value="config.bsp.fsp.OFS1.swdbg.disabled"/> + <property id="config.bsp.fsp.OFS1.initeccen" value="config.bsp.fsp.OFS1.initeccen.disabled"/> + <property id="config.bsp.fsp.OFS2.dcdc" value="config.bsp.fsp.OFS2.dcdc.enabled"/> + <property id="config.bsp.fsp.BPS.BPS0" value=""/> + <property id="config.bsp.fsp.BPS.BPS1" value=""/> + <property id="config.bsp.fsp.BPS.BPS2" value=""/> + <property id="config.bsp.fsp.BPS.BPS3" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS0" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS1" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS2" value=""/> + <property id="config.bsp.fsp.PBPS.PBPS3" value=""/> + <property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/> + <property id="config.bsp.fsp.FSBLCTRL0.FSBLEN" value="config.bsp.fsp.FSBLCTRL0.FSBLEN.disabled"/> + <property id="config.bsp.fsp.FSBLCTRL0.FSBLSKIPSW" value="config.bsp.fsp.FSBLCTRL0.FSBLSKIPSW.disabled"/> + <property id="config.bsp.fsp.FSBLCTRL0.FSBLSKIPDS" value="config.bsp.fsp.FSBLCTRL0.FSBLSKIPDS.disabled"/> + <property id="config.bsp.fsp.FSBLCTRL0.FSBLCLK" value="config.bsp.fsp.FSBLCTRL0.FSBLCLK.240"/> + <property id="config.bsp.fsp.FSBLCTRL1.FSBLEXMD" value="config.bsp.fsp.FSBLCTRL1.FSBLEXMD.secure_report"/> + <property id="config.bsp.fsp.FSBLCTRL2.PORTPN" value="config.bsp.fsp.FSBLCTRL2.PORTPN.15"/> + <property id="config.bsp.fsp.FSBLCTRL2.PORTGN" value="config.bsp.fsp.FSBLCTRL2.PORTGN.reserved"/> + <property id="config.bsp.fsp.SACC0" value="0xFFFFFFFF"/> + <property id="config.bsp.fsp.SACC1" value="0xFFFFFFFF"/> + <property id="config.bsp.fsp.SAMR" value="0xFFFFFFFF"/> + <property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/> + <property id="config.bsp.fsp.clock_settling_delay" value="config.bsp.fsp.clock_settling_delay.enabled"/> + <property id="config.bsp.fsp.sleep_mode_delays" value="config.bsp.fsp.sleep_mode_delays.enabled"/> + <property id="config.bsp.fsp.rtos_idle_sleep" value="config.bsp.fsp.rtos_idle_sleep.disabled"/> + <property id="config.bsp.fsp.mstp_change_delays" value="config.bsp.fsp.mstp_change_delays.enabled"/> + <property id="config.bsp.fsp.settling_delay_us" value="150"/> + <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/> + <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="60000000"/> + <property id="config.bsp.fsp.mcu.sci_b_uart.max_baud" value="30000000"/> + <property id="config.bsp.fsp.mcu.sci_b_uart.ctspen_channels" value="0x021F"/> + <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="1"/> + <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/> + <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="30000000"/> + <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="60000000"/> + <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/> + <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x3"/> + <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/> + <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x3"/> + <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0x3FFF"/> + <property id="config.bsp.fsp.mcu.canfd.num_channels" value="2"/> + <property id="config.bsp.fsp.mcu.canfd.rx_fifos" value="2"/> + <property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="1216"/> + <property id="config.bsp.fsp.mcu.canfd.afl_rules" value="32"/> + <property id="config.bsp.fsp.mcu.canfd.afl_rules_each_chnl" value="16"/> + <property id="config.bsp.fsp.mcu.canfd.max_data_rate_hz" value="8"/> + <property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="32767"/> + <property id="config.bsp.fsp.mcu.sci_b_lin.max_baud" value="7500000"/> + <property id="config.bsp.fsp.dcache" value="config.bsp.fsp.dcache.disabled"/> + </config> + <config id="config.bsp.ra"> + <property id="config.bsp.common.main" value="0x1000"/> + <property id="config.bsp.common.heap" value="0x1000"/> + <property id="config.bsp.common.vcc" value="3300"/> + <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/> + <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/> + <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/> + <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/> + <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/> + <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/> + <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/> + <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/> + <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/> + <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/> + <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/> + <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/> + </config> + </raBspConfiguration> + <raClockConfiguration> + <node id="board.clock.xtal.freq" mul="20000000" option="_edit"/> + <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/> + <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/> + <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/> + <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/> + <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/> + <node id="board.clock.pll.div" option="board.clock.pll.div.2"/> + <node id="board.clock.pll.mul" option="board.clock.pll.mul.96_00"/> + <node id="board.clock.pll.display" option="board.clock.pll.display.value"/> + <node id="board.clock.pll1p.div" option="board.clock.pll1p.div.2"/> + <node id="board.clock.pll1p.display" option="board.clock.pll1p.display.value"/> + <node id="board.clock.pll1q.div" option="board.clock.pll1q.div.4"/> + <node id="board.clock.pll1q.display" option="board.clock.pll1q.display.value"/> + <node id="board.clock.pll1r.div" option="board.clock.pll1r.div.2"/> + <node id="board.clock.pll1r.display" option="board.clock.pll1r.display.value"/> + <node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/> + <node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/> + <node id="board.clock.pll2.mul" option="board.clock.pll2.mul.96_00"/> + <node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/> + <node id="board.clock.pll2p.div" option="board.clock.pll2p.div.2"/> + <node id="board.clock.pll2p.display" option="board.clock.pll2p.display.value"/> + <node id="board.clock.pll2q.div" option="board.clock.pll2q.div.2"/> + <node id="board.clock.pll2q.display" option="board.clock.pll2q.display.value"/> + <node id="board.clock.pll2r.div" option="board.clock.pll2r.div.2"/> + <node id="board.clock.pll2r.display" option="board.clock.pll2r.display.value"/> + <node id="board.clock.clock.source" option="board.clock.clock.source.pll1p"/> + <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/> + <node id="board.clock.sciclk.source" option="board.clock.sciclk.source.disabled"/> + <node id="board.clock.spiclk.source" option="board.clock.spiclk.source.disabled"/> + <node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/> + <node id="board.clock.i3cclk.source" option="board.clock.i3cclk.source.disabled"/> + <node id="board.clock.uck.source" option="board.clock.uck.source.pll1q"/> + <node id="board.clock.u60ck.source" option="board.clock.u60ck.source.pll1p"/> + <node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/> + <node id="board.clock.cpuclk.div" option="board.clock.cpuclk.div.1"/> + <node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/> + <node id="board.clock.pclka.div" option="board.clock.pclka.div.4"/> + <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.8"/> + <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.8"/> + <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.4"/> + <node id="board.clock.pclke.div" option="board.clock.pclke.div.2"/> + <node id="board.clock.sdclkout.enable" option="board.clock.sdclkout.enable.enabled"/> + <node id="board.clock.bclk.div" option="board.clock.bclk.div.4"/> + <node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/> + <node id="board.clock.fclk.div" option="board.clock.fclk.div.8"/> + <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/> + <node id="board.clock.sciclk.div" option="board.clock.sciclk.div.4"/> + <node id="board.clock.spiclk.div" option="board.clock.spiclk.div.4"/> + <node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.8"/> + <node id="board.clock.i3cclk.div" option="board.clock.i3cclk.div.3"/> + <node id="board.clock.uck.div" option="board.clock.uck.div.5"/> + <node id="board.clock.u60ck.div" option="board.clock.u60ck.div.8"/> + <node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.4"/> + <node id="board.clock.cpuclk.display" option="board.clock.cpuclk.display.value"/> + <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/> + <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/> + <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/> + <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/> + <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/> + <node id="board.clock.pclke.display" option="board.clock.pclke.display.value"/> + <node id="board.clock.sdclkout.display" option="board.clock.sdclkout.display.value"/> + <node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/> + <node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/> + <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/> + <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/> + <node id="board.clock.sciclk.display" option="board.clock.sciclk.display.value"/> + <node id="board.clock.spiclk.display" option="board.clock.spiclk.display.value"/> + <node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/> + <node id="board.clock.i3cclk.display" option="board.clock.i3cclk.display.value"/> + <node id="board.clock.uck.display" option="board.clock.uck.display.value"/> + <node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/> + <node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/> + </raClockConfiguration> + <raComponentSelection> + <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0"> + <description>Simple application that blinks an LED. No RTOS included.</description> + <originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0"> + <description>Board Support Package Common Files</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0"> + <description>I/O Port</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0"> + <description>Arm CMSIS Version 6 - Core (M)</description> + <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra8m1_ek" variant="" vendor="Renesas" version="5.6.0"> + <description>RA8M1-EK Board Support Files</description> + <originalPack>Renesas.RA_board_ra8m1_ek.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="device" variant="R7FA8M1AHECBD" vendor="Renesas" version="5.6.0"> + <description>Board support package for R7FA8M1AHECBD</description> + <originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="device" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA8M1</description> + <originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA8M1 - FSP Data</description> + <originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="events" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA8M1 - Events</description> + <originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_usb_basic" variant="" vendor="Renesas" version="5.6.0"> + <description>USB Basic</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_usb_pcdc" variant="" vendor="Renesas" version="5.6.0"> + <description>USB Peripheral Communications Device Class</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + </raComponentSelection> + <raElcConfiguration/> + <raIcuConfiguration/> + <raModuleConfiguration> + <module id="module.driver.ioport_on_ioport.0"> + <property id="module.driver.ioport.name" value="g_ioport"/> + <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/> + <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/> + </module> + <module id="module.driver.pcdc_on_usb.216998869"> + <property id="module.driver.pcdc.name" value="g_pcdc0"/> + </module> + <module id="module.driver.basic_on_usb.877233012"> + <property id="module.driver.basic.name" value="g_basic1"/> + <property id="module.driver.usb_basic.usb_mode" value="module.driver.usb_basic.usb_mode.host"/> + <property id="module.driver.usb_basic.usb_speed" value="module.driver.usb_basic.usb_speed.hs"/> + <property id="module.driver.usb_basic.usb_modulenumber" value="module.driver.usb_basic.usb_modulenumber.1"/> + <property id="module.driver.usb_basic.usb_classtype" value="module.driver.usb_basic.usb_classtype.pcdc"/> + <property id="module.driver.usb_basic.p_usb_reg" value="g_usb_descriptor"/> + <property id="module.driver.usb_basic.complience_cb" value="NULL"/> + <property id="module.driver.usb_basic.ipl" value="board.icu.common.irq.priority12"/> + <property id="module.driver.usb_basic.ipl_r" value="board.icu.common.irq.priority12"/> + <property id="module.driver.usb_basic.ipl_d0" value="board.icu.common.irq.priority12"/> + <property id="module.driver.usb_basic.ipl_d1" value="board.icu.common.irq.priority12"/> + <property id="module.driver.usb_basic.hsipl" value="board.icu.common.irq.priority12"/> + <property id="module.driver.usb_basic.hsipl_d0" value="board.icu.common.irq.priority12"/> + <property id="module.driver.usb_basic.hsipl_d1" value="board.icu.common.irq.priority12"/> + <property id="module.driver.usb_basic.rtos_callback" value="NULL"/> + <property id="module.driver.usb_basic.other_context" value="NULL"/> + </module> + <context id="_hal.0"> + <stack module="module.driver.ioport_on_ioport.0"/> + <stack module="module.driver.pcdc_on_usb.216998869"> + <stack module="module.driver.basic_on_usb.877233012" requires="module.driver.basic_on_usb.requires.basic"/> + </stack> + </context> + <config id="config.driver.usb_basic"> + <property id="config.driver.usb_basic.param_checking_enable" value="config.driver.usb_basic.param_checking_enable.bsp"/> + <property id="config.driver.usb_basic.pll_clock_frequency" value="config.driver.usb_basic.pll_clock_frequency.20mhz"/> + <property id="config.driver.usb_basic.buswait" value="config.driver.usb_basic.buswait.7"/> + <property id="config.driver.usb_basic.bc_function" value="config.driver.usb_basic.bc_function.enable"/> + <property id="config.driver.usb_basic.power_source" value="config.driver.usb_basic.power_source.high"/> + <property id="config.driver.usb_basic.dcp_function" value="config.driver.usb_basic.dcp_function.disable"/> + <property id="config.driver.usb_basic.request" value="config.driver.usb_basic.request.enable"/> + <property id="config.driver.usb_basic.dblb" value="config.driver.usb_basic.dblb.enable"/> + <property id="config.driver.usb_basic.cntmd" value="config.driver.usb_basic.cntmd.disable"/> + <property id="config.driver.usb_basic.ldo_regulator" value="config.driver.usb_basic.ldo_regulator.disable"/> + <property id="config.driver.usb_basic.type_c" value="config.driver.usb_basic.type_c.disable"/> + <property id="config.driver.usb_basic.dma" value="config.driver.usb_basic.dma.disable"/> + <property id="config.driver.usb_basic.source_address" value="config.driver.usb_basic.source_address.none"/> + <property id="config.driver.usb_basic.dest_address" value="config.driver.usb_basic.dest_address.none"/> + <property id="config.driver.usb_basic.compliance_mode" value="config.driver.usb_basic.compliance_mode.disable"/> + <property id="config.driver.usb_basic.tpl_table" value="NULL"/> + </config> + <config id="config.driver.usb_pcdc"> + <property id="config.driver.usb_pcdc.bulk_in" value="config.driver.usb_pcdc.bulk_in.pipe4"/> + <property id="config.driver.usb_pcdc.bulk_out" value="config.driver.usb_pcdc.bulk_out.pipe5"/> + <property id="config.driver.usb_pcdc.int_in" value="config.driver.usb_pcdc.int_in.pipe6"/> + </config> + <config id="config.driver.usb_pcdc_class"/> + <config id="config.driver.ioport"> + <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/> + </config> + </raModuleConfiguration> + <raPinConfiguration> + <symbolicName propertyId="p000.symbolic_name" value="ENET_RMII_INT"/> + <symbolicName propertyId="p001.symbolic_name" value="ARDUINO_A3"/> + <symbolicName propertyId="p002.symbolic_name" value="GROVE2_AN102"/> + <symbolicName propertyId="p003.symbolic_name" value="ARDUINO_A1"/> + <symbolicName propertyId="p004.symbolic_name" value="ARDUINO_A0_MIKROBUS_AN000"/> + <symbolicName propertyId="p005.symbolic_name" value="GROVE2_AN001"/> + <symbolicName propertyId="p006.symbolic_name" value="PMOD1_IRQ11"/> + <symbolicName propertyId="p007.symbolic_name" value="ARDUINO_A004"/> + <symbolicName propertyId="p008.symbolic_name" value="USER_S2"/> + <symbolicName propertyId="p009.symbolic_name" value="SW1"/> + <symbolicName propertyId="p010.symbolic_name" value="MIKROBUS_IRQ14"/> + <symbolicName propertyId="p014.symbolic_name" value="ARDUINO_A4"/> + <symbolicName propertyId="p015.symbolic_name" value="ARDUINO_A5"/> + <symbolicName propertyId="p100.symbolic_name" value="OSPI_DQ0"/> + <symbolicName propertyId="p101.symbolic_name" value="OSPI_DQ3"/> + <symbolicName propertyId="p102.symbolic_name" value="OSPI_DQ4"/> + <symbolicName propertyId="p103.symbolic_name" value="OSPI_DQ2"/> + <symbolicName propertyId="p104.symbolic_name" value="OSPI_CS"/> + <symbolicName propertyId="p105.symbolic_name" value="OSPI_INT"/> + <symbolicName propertyId="p106.symbolic_name" value="OSPI_RESET"/> + <symbolicName propertyId="p107.symbolic_name" value="LED3"/> + <symbolicName propertyId="p112.symbolic_name" value="ETH_A_RMII_RMII_RXDV"/> + <symbolicName propertyId="p114.symbolic_name" value="ETH_A_LINKSTA"/> + <symbolicName propertyId="p115.symbolic_name" value="MPLX_CTRL"/> + <symbolicName propertyId="p200.symbolic_name" value="NMI"/> + <symbolicName propertyId="p201.symbolic_name" value="MD"/> + <symbolicName propertyId="p207.symbolic_name" value="CAN_STB"/> + <symbolicName propertyId="p208.symbolic_name" value="TDI"/> + <symbolicName propertyId="p209.symbolic_name" value="TDO"/> + <symbolicName propertyId="p210.symbolic_name" value="SWDIO"/> + <symbolicName propertyId="p211.symbolic_name" value="SWCLK"/> + <symbolicName propertyId="p212.symbolic_name" value="EXTAL"/> + <symbolicName propertyId="p213.symbolic_name" value="XTAL"/> + <symbolicName propertyId="p300.symbolic_name" value="ETH_A_RXER"/> + <symbolicName propertyId="p301.symbolic_name" value="ETH_A_RXD1"/> + <symbolicName propertyId="p302.symbolic_name" value="ETH_A_RXD0"/> + <symbolicName propertyId="p303.symbolic_name" value="ETH_A_REFCLK"/> + <symbolicName propertyId="p304.symbolic_name" value="ETH_A_TXD0"/> + <symbolicName propertyId="p305.symbolic_name" value="ETH_A_TXD1"/> + <symbolicName propertyId="p306.symbolic_name" value="ETH_A_TXEN"/> + <symbolicName propertyId="p307.symbolic_name" value="ETH_A_MDIO"/> + <symbolicName propertyId="p308.symbolic_name" value="ETH_A_MDC"/> + <symbolicName propertyId="p309.symbolic_name" value="ARDUINO_D0_MIKROBUS_RXD3"/> + <symbolicName propertyId="p310.symbolic_name" value="ARDUINO_D1_MIKROBUS_TXD3"/> + <symbolicName propertyId="p311.symbolic_name" value="CAN_RXD"/> + <symbolicName propertyId="p312.symbolic_name" value="CAN_TXD"/> + <symbolicName propertyId="p400.symbolic_name" value="I3C_SCL0_ARDUINO_MIKROBUS_PMOD1_3_qwiic"/> + <symbolicName propertyId="p401.symbolic_name" value="I3C_SDA0_ARDUINO_MIKROBUS_PMOD1_4_qwiic"/> + <symbolicName propertyId="p402.symbolic_name" value="ETH_B_MDIO"/> + <symbolicName propertyId="p403.symbolic_name" value="ETH_B_LINKSTA"/> + <symbolicName propertyId="p404.symbolic_name" value="ETH_B_RST_N"/> + <symbolicName propertyId="p405.symbolic_name" value="ETH_B_TXEN"/> + <symbolicName propertyId="p406.symbolic_name" value="ETH_B_TXD1"/> + <symbolicName propertyId="p407.symbolic_name" value="USBFS_VBUS"/> + <symbolicName propertyId="p408.symbolic_name" value="USBHS_VBUSEN"/> + <symbolicName propertyId="p409.symbolic_name" value="USBHS_OVRCURA"/> + <symbolicName propertyId="p410.symbolic_name" value="MISOB_B_ARDUINO_MIKROBUS"/> + <symbolicName propertyId="p411.symbolic_name" value="MOSIB_B_ARDUINO_MIKROBUS"/> + <symbolicName propertyId="p412.symbolic_name" value="RSPCKB_B_ARDUINO_MIKROBUS"/> + <symbolicName propertyId="p413.symbolic_name" value="SSLB0_B_ARDUINO_D10_MIKROBUS"/> + <symbolicName propertyId="p414.symbolic_name" value="LED2"/> + <symbolicName propertyId="p500.symbolic_name" value="USBFS_VBUS_EN"/> + <symbolicName propertyId="p501.symbolic_name" value="USBFS_OVERCURA"/> + <symbolicName propertyId="p502.symbolic_name" value="MIKROBUS_RESET"/> + <symbolicName propertyId="p508.symbolic_name" value="PMOD2_7_IRQ1"/> + <symbolicName propertyId="p511.symbolic_name" value="GROVE2_IIC_SDA1"/> + <symbolicName propertyId="p512.symbolic_name" value="GROVE2_IIC_SCL1"/> + <symbolicName propertyId="p600.symbolic_name" value="LED1"/> + <symbolicName propertyId="p601.symbolic_name" value="ARDUINO_D5"/> + <symbolicName propertyId="p602.symbolic_name" value="ARDUINO_D6"/> + <symbolicName propertyId="p603.symbolic_name" value="ARDUINO_D9"/> + <symbolicName propertyId="p609.symbolic_name" value="PMOD1_3_MISO0_RXD0_SCL0"/> + <symbolicName propertyId="p610.symbolic_name" value="PMOD1_2_MOSI0_TXD0"/> + <symbolicName propertyId="p611.symbolic_name" value="PMOD1_4_SCK0"/> + <symbolicName propertyId="p612.symbolic_name" value="PMOD1_1_SSL0_CTS_RTS"/> + <symbolicName propertyId="p613.symbolic_name" value="PMOD1_1_CTS0"/> + <symbolicName propertyId="p614.symbolic_name" value="PMOD1_9_GPIO"/> + <symbolicName propertyId="p615.symbolic_name" value="PMOD1_10_GPIO"/> + <symbolicName propertyId="p700.symbolic_name" value="ETH_B_TXD0"/> + <symbolicName propertyId="p701.symbolic_name" value="ETH_B_REFCLK"/> + <symbolicName propertyId="p702.symbolic_name" value="ETH_B_RXD0"/> + <symbolicName propertyId="p703.symbolic_name" value="ETH_B_RXD1"/> + <symbolicName propertyId="p704.symbolic_name" value="ETH_B_RXER"/> + <symbolicName propertyId="p705.symbolic_name" value="ETH_B_RMII_RXDV"/> + <symbolicName propertyId="p711.symbolic_name" value="I3C_SDA0_PULLUP"/> + <symbolicName propertyId="p800.symbolic_name" value="OSPI_DQ5"/> + <symbolicName propertyId="p801.symbolic_name" value="OSPI_DS"/> + <symbolicName propertyId="p802.symbolic_name" value="OSPI_DQ6"/> + <symbolicName propertyId="p803.symbolic_name" value="OSPI_DQ1"/> + <symbolicName propertyId="p804.symbolic_name" value="OSPI_DQ7"/> + <symbolicName propertyId="p808.symbolic_name" value="OSPI_CK"/> + <symbolicName propertyId="p809.symbolic_name" value="PMOD2_8_RESET"/> + <symbolicName propertyId="p810.symbolic_name" value="PMOD2_9_GPIO"/> + <symbolicName propertyId="p811.symbolic_name" value="PMOD2_10_GPIO"/> + <symbolicName propertyId="p812.symbolic_name" value="ARDUINO_RESET"/> + <symbolicName propertyId="p814.symbolic_name" value="USBFS_P"/> + <symbolicName propertyId="p815.symbolic_name" value="USBFS_N"/> + <symbolicName propertyId="p905.symbolic_name" value="ARDUINO_D4"/> + <symbolicName propertyId="p906.symbolic_name" value="ARDUINO_D2"/> + <symbolicName propertyId="p907.symbolic_name" value="ARDUINO_D3_MIKROBUS_GTIOC13A"/> + <symbolicName propertyId="p908.symbolic_name" value="ARDUINO_D7"/> + <symbolicName propertyId="p909.symbolic_name" value="ARDUINO_D8"/> + <symbolicName propertyId="pa02.symbolic_name" value="PMOD2_3_MISO2_RXD2"/> + <symbolicName propertyId="pa03.symbolic_name" value="PMOD2_2_MOSI2_TXD2"/> + <symbolicName propertyId="pa04.symbolic_name" value="PMOD2_4_SCK2"/> + <symbolicName propertyId="pa05.symbolic_name" value="PMOD2_1_CTS_RTS_SSL2"/> + <symbolicName propertyId="pa06.symbolic_name" value="PMOD2_1_CTS2"/> + <symbolicName propertyId="pa08.symbolic_name" value="PMOD1_8_RESET"/> + <symbolicName propertyId="pa14.symbolic_name" value="JLOB_COMS_TX"/> + <symbolicName propertyId="pa15.symbolic_name" value="JLOB_COMS_RX"/> + <symbolicName propertyId="pb00.symbolic_name" value="I3C_SCL0_PULLUP"/> + <symbolicName propertyId="pb01.symbolic_name" value="USBHS_VBUS"/> + <pincfg active="true" name="RA8M1 EK" selected="true" symbol="g_bsp_pin_cfg"> + <configSetting altId="adc0.an000.p004" configurationId="adc0.an000"/> + <configSetting altId="adc0.an001.p005" configurationId="adc0.an001"/> + <configSetting altId="adc0.an004.p007" configurationId="adc0.an004"/> + <configSetting altId="adc0.an007.p014" configurationId="adc0.an007"/> + <configSetting altId="adc0.mode.custom.free" configurationId="adc0.mode"/> + <configSetting altId="adc1.an102.p002" configurationId="adc1.an102"/> + <configSetting altId="adc1.an104.p003" configurationId="adc1.an104"/> + <configSetting altId="adc1.an105.p015" configurationId="adc1.an105"/> + <configSetting altId="adc1.an106.p011" configurationId="adc1.an106"/> + <configSetting altId="adc1.mode.custom.free" configurationId="adc1.mode"/> + <configSetting altId="ether_rmii.pairing.a" configurationId="ether_rmii.pairing"/> + <configSetting altId="iic1.mode.enabled.a" configurationId="iic1.mode"/> + <configSetting altId="iic1.scl1.p512" configurationId="iic1.scl1"/> + <configSetting altId="iic1.sda1.p511" configurationId="iic1.sda1"/> + <configSetting altId="irq12.irq12_dash_ds.p008" configurationId="irq12.irq12_dash_ds"/> + <configSetting altId="irq12.mode.custom.free" configurationId="irq12.mode"/> + <configSetting altId="irq13.irq13_dash_ds.p009" configurationId="irq13.irq13_dash_ds"/> + <configSetting altId="irq13.mode.custom.free" configurationId="irq13.mode"/> + <configSetting altId="irq9.mode.custom.free" configurationId="irq9.mode"/> + <configSetting altId="jtag_fslash_swd.mode.swd.free" configurationId="jtag_fslash_swd.mode"/> + <configSetting altId="jtag_fslash_swd.swclk.p211" configurationId="jtag_fslash_swd.swclk"/> + <configSetting altId="jtag_fslash_swd.swdio.p210" configurationId="jtag_fslash_swd.swdio"/> + <configSetting altId="ospi.mode.custom.free" configurationId="ospi.mode"/> + <configSetting altId="ospi.om_cs1.p104" configurationId="ospi.om_cs1"/> + <configSetting altId="ospi.om_dqs.p801" configurationId="ospi.om_dqs"/> + <configSetting altId="ospi.om_ecsint1.p105" configurationId="ospi.om_ecsint1"/> + <configSetting altId="ospi.om_reset.p106" configurationId="ospi.om_reset"/> + <configSetting altId="ospi.om_sclk.p808" configurationId="ospi.om_sclk"/> + <configSetting altId="ospi.om_sio0.p100" configurationId="ospi.om_sio0"/> + <configSetting altId="ospi.om_sio1.p803" configurationId="ospi.om_sio1"/> + <configSetting altId="ospi.om_sio2.p103" configurationId="ospi.om_sio2"/> + <configSetting altId="ospi.om_sio3.p101" configurationId="ospi.om_sio3"/> + <configSetting altId="ospi.om_sio4.p102" configurationId="ospi.om_sio4"/> + <configSetting altId="ospi.om_sio5.p800" configurationId="ospi.om_sio5"/> + <configSetting altId="ospi.om_sio6.p802" configurationId="ospi.om_sio6"/> + <configSetting altId="ospi.om_sio7.p804" configurationId="ospi.om_sio7"/> + <configSetting altId="p000.input" configurationId="p000"/> + <configSetting altId="p000.gpio_mode.gpio_mode_in" configurationId="p000.gpio_mode"/> + <configSetting altId="p002.adc1.an102" configurationId="p002"/> + <configSetting altId="p002.gpio_mode.gpio_mode_an" configurationId="p002.gpio_mode"/> + <configSetting altId="p003.adc1.an104" configurationId="p003"/> + <configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/> + <configSetting altId="p004.adc0.an000" configurationId="p004"/> + <configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/> + <configSetting altId="p005.adc0.an001" configurationId="p005"/> + <configSetting altId="p005.gpio_mode.gpio_mode_an" configurationId="p005.gpio_mode"/> + <configSetting altId="p007.adc0.an004" configurationId="p007"/> + <configSetting altId="p007.gpio_mode.gpio_mode_an" configurationId="p007.gpio_mode"/> + <configSetting altId="p008.irq12.irq12_dash_ds" configurationId="p008"/> + <configSetting altId="p008.gpio_irq.gpio_irq_enabled" configurationId="p008.gpio_irq"/> + <configSetting altId="p008.gpio_mode.gpio_mode_irq" configurationId="p008.gpio_mode"/> + <configSetting altId="p009.irq13.irq13_dash_ds" configurationId="p009"/> + <configSetting altId="p009.gpio_irq.gpio_irq_enabled" configurationId="p009.gpio_irq"/> + <configSetting altId="p009.gpio_mode.gpio_mode_irq" configurationId="p009.gpio_mode"/> + <configSetting altId="p011.adc1.an106" configurationId="p011"/> + <configSetting altId="p011.gpio_mode.gpio_mode_an" configurationId="p011.gpio_mode"/> + <configSetting altId="p014.adc0.an007" configurationId="p014"/> + <configSetting altId="p014.gpio_mode.gpio_mode_an" configurationId="p014.gpio_mode"/> + <configSetting altId="p015.adc1.an105" configurationId="p015"/> + <configSetting altId="p015.gpio_mode.gpio_mode_an" configurationId="p015.gpio_mode"/> + <configSetting altId="p100.ospi.om_sio0" configurationId="p100"/> + <configSetting altId="p100.gpio_speed.gpio_speed_hh" configurationId="p100.gpio_drivecapacity"/> + <configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/> + <configSetting altId="p101.ospi.om_sio3" configurationId="p101"/> + <configSetting altId="p101.gpio_speed.gpio_speed_hh" configurationId="p101.gpio_drivecapacity"/> + <configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/> + <configSetting altId="p102.ospi.om_sio4" configurationId="p102"/> + <configSetting altId="p102.gpio_speed.gpio_speed_hh" configurationId="p102.gpio_drivecapacity"/> + <configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/> + <configSetting altId="p103.ospi.om_sio2" configurationId="p103"/> + <configSetting altId="p103.gpio_speed.gpio_speed_hh" configurationId="p103.gpio_drivecapacity"/> + <configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/> + <configSetting altId="p104.ospi.om_cs1" configurationId="p104"/> + <configSetting altId="p104.gpio_speed.gpio_speed_h" configurationId="p104.gpio_drivecapacity"/> + <configSetting altId="p104.gpio_mode.gpio_mode_peripheral" configurationId="p104.gpio_mode"/> + <configSetting altId="p105.ospi.om_ecsint1" configurationId="p105"/> + <configSetting altId="p105.gpio_mode.gpio_mode_peripheral" configurationId="p105.gpio_mode"/> + <configSetting altId="p106.ospi.om_reset" configurationId="p106"/> + <configSetting altId="p106.gpio_mode.gpio_mode_peripheral" configurationId="p106.gpio_mode"/> + <configSetting altId="p107.output.low" configurationId="p107"/> + <configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/> + <configSetting altId="p209.trace.traceswo" configurationId="p209"/> + <configSetting altId="p209.gpio_mode.gpio_mode_peripheral" configurationId="p209.gpio_mode"/> + <configSetting altId="p210.jtag_fslash_swd.swdio" configurationId="p210"/> + <configSetting altId="p210.gpio_mode.gpio_mode_peripheral" configurationId="p210.gpio_mode"/> + <configSetting altId="p211.jtag_fslash_swd.swclk" configurationId="p211"/> + <configSetting altId="p211.gpio_mode.gpio_mode_peripheral" configurationId="p211.gpio_mode"/> + <configSetting altId="p304.trace.tdata3" configurationId="p304"/> + <configSetting altId="p304.gpio_mode.gpio_mode_peripheral" configurationId="p304.gpio_mode"/> + <configSetting altId="p305.trace.tdata2" configurationId="p305"/> + <configSetting altId="p305.gpio_mode.gpio_mode_peripheral" configurationId="p305.gpio_mode"/> + <configSetting altId="p306.trace.tdata1" configurationId="p306"/> + <configSetting altId="p306.gpio_mode.gpio_mode_peripheral" configurationId="p306.gpio_mode"/> + <configSetting altId="p307.trace.tdata0" configurationId="p307"/> + <configSetting altId="p307.gpio_mode.gpio_mode_peripheral" configurationId="p307.gpio_mode"/> + <configSetting altId="p308.trace.tclk" configurationId="p308"/> + <configSetting altId="p308.gpio_mode.gpio_mode_peripheral" configurationId="p308.gpio_mode"/> + <configSetting altId="p407.usbfs.usb_vbus" configurationId="p407"/> + <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/> + <configSetting altId="p408.usbhs.usbhs_vbusen" configurationId="p408"/> + <configSetting altId="p408.gpio_mode.gpio_mode_peripheral" configurationId="p408.gpio_mode"/> + <configSetting altId="p409.usbhs.usbhs_ovrcura" configurationId="p409"/> + <configSetting altId="p409.gpio_mode.gpio_mode_peripheral" configurationId="p409.gpio_mode"/> + <configSetting altId="p410.spi1.miso1" configurationId="p410"/> + <configSetting altId="p410.gpio_speed.gpio_speed_h" configurationId="p410.gpio_drivecapacity"/> + <configSetting altId="p410.gpio_mode.gpio_mode_peripheral" configurationId="p410.gpio_mode"/> + <configSetting altId="p411.spi1.mosi1" configurationId="p411"/> + <configSetting altId="p411.gpio_speed.gpio_speed_h" configurationId="p411.gpio_drivecapacity"/> + <configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/> + <configSetting altId="p412.spi1.rspck1" configurationId="p412"/> + <configSetting altId="p412.gpio_speed.gpio_speed_h" configurationId="p412.gpio_drivecapacity"/> + <configSetting altId="p412.gpio_mode.gpio_mode_peripheral" configurationId="p412.gpio_mode"/> + <configSetting altId="p413.spi1.sslb0" configurationId="p413"/> + <configSetting altId="p413.gpio_speed.gpio_speed_h" configurationId="p413.gpio_drivecapacity"/> + <configSetting altId="p413.gpio_mode.gpio_mode_peripheral" configurationId="p413.gpio_mode"/> + <configSetting altId="p414.output.low" configurationId="p414"/> + <configSetting altId="p414.gpio_mode.gpio_mode_out.low" configurationId="p414.gpio_mode"/> + <configSetting altId="p500.usbfs.usb_vbusen" configurationId="p500"/> + <configSetting altId="p500.gpio_mode.gpio_mode_peripheral" configurationId="p500.gpio_mode"/> + <configSetting altId="p501.usbfs.usb_ovrcura" configurationId="p501"/> + <configSetting altId="p501.gpio_mode.gpio_mode_peripheral" configurationId="p501.gpio_mode"/> + <configSetting altId="p511.iic1.sda1" configurationId="p511"/> + <configSetting altId="p511.gpio_speed.gpio_speed_m" configurationId="p511.gpio_drivecapacity"/> + <configSetting altId="p511.gpio_mode.gpio_mode_peripheral" configurationId="p511.gpio_mode"/> + <configSetting altId="p512.iic1.scl1" configurationId="p512"/> + <configSetting altId="p512.gpio_speed.gpio_speed_m" configurationId="p512.gpio_drivecapacity"/> + <configSetting altId="p512.gpio_mode.gpio_mode_peripheral" configurationId="p512.gpio_mode"/> + <configSetting altId="p600.output.low" configurationId="p600"/> + <configSetting altId="p600.gpio_mode.gpio_mode_out.low" configurationId="p600.gpio_mode"/> + <configSetting altId="p800.ospi.om_sio5" configurationId="p800"/> + <configSetting altId="p800.gpio_speed.gpio_speed_hh" configurationId="p800.gpio_drivecapacity"/> + <configSetting altId="p800.gpio_mode.gpio_mode_peripheral" configurationId="p800.gpio_mode"/> + <configSetting altId="p801.ospi.om_dqs" configurationId="p801"/> + <configSetting altId="p801.gpio_speed.gpio_speed_hh" configurationId="p801.gpio_drivecapacity"/> + <configSetting altId="p801.gpio_mode.gpio_mode_peripheral" configurationId="p801.gpio_mode"/> + <configSetting altId="p802.ospi.om_sio6" configurationId="p802"/> + <configSetting altId="p802.gpio_speed.gpio_speed_hh" configurationId="p802.gpio_drivecapacity"/> + <configSetting altId="p802.gpio_mode.gpio_mode_peripheral" configurationId="p802.gpio_mode"/> + <configSetting altId="p803.ospi.om_sio1" configurationId="p803"/> + <configSetting altId="p803.gpio_speed.gpio_speed_hh" configurationId="p803.gpio_drivecapacity"/> + <configSetting altId="p803.gpio_mode.gpio_mode_peripheral" configurationId="p803.gpio_mode"/> + <configSetting altId="p804.ospi.om_sio7" configurationId="p804"/> + <configSetting altId="p804.gpio_speed.gpio_speed_hh" configurationId="p804.gpio_drivecapacity"/> + <configSetting altId="p804.gpio_mode.gpio_mode_peripheral" configurationId="p804.gpio_mode"/> + <configSetting altId="p808.ospi.om_sclk" configurationId="p808"/> + <configSetting altId="p808.gpio_speed.gpio_speed_hh" configurationId="p808.gpio_drivecapacity"/> + <configSetting altId="p808.gpio_mode.gpio_mode_peripheral" configurationId="p808.gpio_mode"/> + <configSetting altId="p809.output.low" configurationId="p809"/> + <configSetting altId="p809.gpio_mode.gpio_mode_out.low" configurationId="p809.gpio_mode"/> + <configSetting altId="p814.usbfs.usb_dp" configurationId="p814"/> + <configSetting altId="p814.gpio_mode.gpio_mode_peripheral" configurationId="p814.gpio_mode"/> + <configSetting altId="p815.usbfs.usb_dm" configurationId="p815"/> + <configSetting altId="p815.gpio_mode.gpio_mode_peripheral" configurationId="p815.gpio_mode"/> + <configSetting altId="pa02.sci2.rxd2" configurationId="pa02"/> + <configSetting altId="pa02.gpio_speed.gpio_speed_h" configurationId="pa02.gpio_drivecapacity"/> + <configSetting altId="pa02.gpio_mode.gpio_mode_peripheral" configurationId="pa02.gpio_mode"/> + <configSetting altId="pa03.sci2.txd2" configurationId="pa03"/> + <configSetting altId="pa03.gpio_speed.gpio_speed_h" configurationId="pa03.gpio_drivecapacity"/> + <configSetting altId="pa03.gpio_mode.gpio_mode_peripheral" configurationId="pa03.gpio_mode"/> + <configSetting altId="pa04.sci2.sck2" configurationId="pa04"/> + <configSetting altId="pa04.gpio_speed.gpio_speed_h" configurationId="pa04.gpio_drivecapacity"/> + <configSetting altId="pa04.gpio_mode.gpio_mode_peripheral" configurationId="pa04.gpio_mode"/> + <configSetting altId="pa05.sci2.cts_rts2" configurationId="pa05"/> + <configSetting altId="pa05.gpio_speed.gpio_speed_h" configurationId="pa05.gpio_drivecapacity"/> + <configSetting altId="pa05.gpio_mode.gpio_mode_peripheral" configurationId="pa05.gpio_mode"/> + <configSetting altId="pa06.input" configurationId="pa06"/> + <configSetting altId="pa06.gpio_mode.gpio_mode_in" configurationId="pa06.gpio_mode"/> + <configSetting altId="pa14.sci9.txd9" configurationId="pa14"/> + <configSetting altId="pa14.gpio_speed.gpio_speed_h" configurationId="pa14.gpio_drivecapacity"/> + <configSetting altId="pa14.gpio_mode.gpio_mode_peripheral" configurationId="pa14.gpio_mode"/> + <configSetting altId="pa15.sci9.rxd9" configurationId="pa15"/> + <configSetting altId="pa15.gpio_speed.gpio_speed_h" configurationId="pa15.gpio_drivecapacity"/> + <configSetting altId="pa15.gpio_mode.gpio_mode_peripheral" configurationId="pa15.gpio_mode"/> + <configSetting altId="pb01.usbhs.usbhs_vbus" configurationId="pb01"/> + <configSetting altId="pb01.gpio_speed.gpio_speed_h" configurationId="pb01.gpio_drivecapacity"/> + <configSetting altId="pb01.gpio_mode.gpio_mode_peripheral" configurationId="pb01.gpio_mode"/> + <configSetting altId="sci0.mode.custom.free" configurationId="sci0.mode"/> + <configSetting altId="sci1.mode.custom.free" configurationId="sci1.mode"/> + <configSetting altId="sci2.cts_rts2.pa05" configurationId="sci2.cts_rts2"/> + <configSetting altId="sci2.mode.custom.free" configurationId="sci2.mode"/> + <configSetting altId="sci2.rxd2.pa02" configurationId="sci2.rxd2"/> + <configSetting altId="sci2.sck2.pa04" configurationId="sci2.sck2"/> + <configSetting altId="sci2.txd2.pa03" configurationId="sci2.txd2"/> + <configSetting altId="sci4.mode.custom.free" configurationId="sci4.mode"/> + <configSetting altId="sci9.mode.custom.free" configurationId="sci9.mode"/> + <configSetting altId="sci9.rxd9.pa15" configurationId="sci9.rxd9"/> + <configSetting altId="sci9.txd9.pa14" configurationId="sci9.txd9"/> + <configSetting altId="spi1.miso1.p410" configurationId="spi1.miso1"/> + <configSetting altId="spi1.mode.custom.free" configurationId="spi1.mode"/> + <configSetting altId="spi1.mosi1.p411" configurationId="spi1.mosi1"/> + <configSetting altId="spi1.rspck1.p412" configurationId="spi1.rspck1"/> + <configSetting altId="spi1.sslb0.p413" configurationId="spi1.sslb0"/> + <configSetting altId="system.mode.custom.free" configurationId="system.mode"/> + <configSetting altId="trace.mode.custom.free" configurationId="trace.mode"/> + <configSetting altId="trace.tclk.p308" configurationId="trace.tclk"/> + <configSetting altId="trace.tdata0.p307" configurationId="trace.tdata0"/> + <configSetting altId="trace.tdata1.p306" configurationId="trace.tdata1"/> + <configSetting altId="trace.tdata2.p305" configurationId="trace.tdata2"/> + <configSetting altId="trace.tdata3.p304" configurationId="trace.tdata3"/> + <configSetting altId="trace.traceswo.p209" configurationId="trace.traceswo"/> + <configSetting altId="usbfs.mode.custom.free" configurationId="usbfs.mode"/> + <configSetting altId="usbfs.usb_dm.p815" configurationId="usbfs.usb_dm"/> + <configSetting altId="usbfs.usb_dp.p814" configurationId="usbfs.usb_dp"/> + <configSetting altId="usbfs.usb_ovrcura.p501" configurationId="usbfs.usb_ovrcura"/> + <configSetting altId="usbfs.usb_vbus.p407" configurationId="usbfs.usb_vbus"/> + <configSetting altId="usbfs.usb_vbusen.p500" configurationId="usbfs.usb_vbusen"/> + <configSetting altId="usbhs.mode.custom.free" configurationId="usbhs.mode"/> + <configSetting altId="usbhs.usbhs_ovrcura.p409" configurationId="usbhs.usbhs_ovrcura"/> + <configSetting altId="usbhs.usbhs_vbus.pb01" configurationId="usbhs.usbhs_vbus"/> + <configSetting altId="usbhs.usbhs_vbusen.p408" configurationId="usbhs.usbhs_vbusen"/> + </pincfg> + <pincfg active="false" name="R7FA8M1AHECBD.pincfg" selected="false" symbol=""> + <configSetting altId="jtag_fslash_swd.mode.jtag.free" configurationId="jtag_fslash_swd.mode"/> + <configSetting altId="jtag_fslash_swd.tck.p211" configurationId="jtag_fslash_swd.tck"/> + <configSetting altId="jtag_fslash_swd.tdi.p208" configurationId="jtag_fslash_swd.tdi"/> + <configSetting altId="jtag_fslash_swd.tdo.p209" configurationId="jtag_fslash_swd.tdo"/> + <configSetting altId="jtag_fslash_swd.tms.p210" configurationId="jtag_fslash_swd.tms"/> + <configSetting altId="p208.jtag_fslash_swd.tdi" configurationId="p208"/> + <configSetting altId="p208.gpio_mode.gpio_mode_peripheral" configurationId="p208.gpio_mode"/> + <configSetting altId="p209.jtag_fslash_swd.tdo" configurationId="p209"/> + <configSetting altId="p209.gpio_mode.gpio_mode_peripheral" configurationId="p209.gpio_mode"/> + <configSetting altId="p210.jtag_fslash_swd.tms" configurationId="p210"/> + <configSetting altId="p210.gpio_mode.gpio_mode_peripheral" configurationId="p210.gpio_mode"/> + <configSetting altId="p211.jtag_fslash_swd.tck" configurationId="p211"/> + <configSetting altId="p211.gpio_mode.gpio_mode_peripheral" configurationId="p211.gpio_mode"/> + </pincfg> + </raPinConfiguration> +</raConfiguration> diff --git a/hw/bsp/ra/boards/uno_r4/board.cmake b/hw/bsp/ra/boards/uno_r4/board.cmake index 9d59bc4f7..735a93035 100644 --- a/hw/bsp/ra/boards/uno_r4/board.cmake +++ b/hw/bsp/ra/boards/uno_r4/board.cmake @@ -1,13 +1,9 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra4m1) - set(JLINK_DEVICE R7FA4M1AB) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CFG_EXAMPLE_VIDEO_READONLY ) -# target_sources(${TARGET} PRIVATE) -# target_include_directories(${BOARD_TARGET} PUBLIC) endfunction() diff --git a/hw/bsp/ra/boards/uno_r4/board.h b/hw/bsp/ra/boards/uno_r4/board.h index 72abda27f..4e7ebb5ce 100644 --- a/hw/bsp/ra/boards/uno_r4/board.h +++ b/hw/bsp/ra/boards/uno_r4/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Arduino UNO R4 + url: https://store-usa.arduino.cc/pages/uno-r4 +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ @@ -31,20 +36,8 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_01_PIN_11 // D13 -#define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_01_PIN_10 // D12 -#define BUTTON_STATE_ACTIVE 0 - -static const ioport_pin_cfg_t board_pin_cfg[] = { - {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, - {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, - // USB FS D+, D-, VBus - {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, -}; +#define LED_STATE_ON 1 +#define BUTTON_STATE_ACTIVE 0 #ifdef __cplusplus } diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk index b7075eec0..f257c0000 100644 --- a/hw/bsp/ra/boards/uno_r4/board.mk +++ b/hw/bsp/ra/boards/uno_r4/board.mk @@ -1,8 +1,6 @@ CPU_CORE = cortex-m4 MCU_VARIANT = ra4m1 -LD_FILE = ${BOARD_PATH}/${BOARD}.ld - # For flash-jlink target JLINK_DEVICE = R7FA4M1AB diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index c1d1022cc..000000000 --- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,35 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#undef RA_NOT_DEFINED -#define BSP_CFG_RTOS (0) -#if defined(_RA_BOOT_IMAGE) -#define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x800) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) - -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0) -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 336918800..000000000 --- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA4M1AB3CNE -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (262144) -#define BSP_RAM_SIZE_BYTES (32768) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_QFN -#define BSP_PACKAGE_PINS (48) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h deleted file mode 100644 index fc604eb3b..000000000 --- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,87 +0,0 @@ -/* generated configuration header file through renesas e2 studio */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA4M1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 - #define BSP_HOCO_HZ (24000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (32000000) -#elif BSP_CFG_HOCO_FREQUENCY == 4 - #define BSP_HOCO_HZ (48000000) -#elif BSP_CFG_HOCO_FREQUENCY == 5 - #define BSP_HOCO_HZ (64000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) -#define BSP_MCU_VBATT_SUPPORT (1) - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) -#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) - #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) - #else -/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ -#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..4eef62a0e --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x800) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h index 444d32e56..444d32e56 100644 --- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..3f1d02b0d --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M1AB3CNE + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (262144) + #define BSP_RAM_SIZE_BYTES (32768) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_QFN + #define BSP_PACKAGE_PINS (48) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..3d482b2b6 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,84 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA4M1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (24000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) + #elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) + + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) + #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) + #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #endif + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + + /* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ + #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else + /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ + #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..5440b293b --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define SW1 (BSP_IO_PORT_01_PIN_10) /* active low */ +#define LED1 (BSP_IO_PORT_01_PIN_11) /* active high */ +extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA4M1AB3CNE.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h index 63618ec4b..559000a7a 100644 --- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h @@ -4,10 +4,10 @@ #define BSP_CFG_CLOCKS_SECURE (0) #define BSP_CFG_CLOCKS_OVERRIDE (0) #define BSP_CFG_XTAL_HZ (0) /* XTAL 0Hz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: Disabled */ #define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_4) /* PLL Div /4 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12, 0) /* PLL Mul x12 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12U,0U) /* PLL Mul x12 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ @@ -15,7 +15,7 @@ #define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ #define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Src: SUBCLK */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ #define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ #define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */ #endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c b/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c new file mode 100644 index 000000000..58262de8b --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c @@ -0,0 +1,75 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/uno_r4/script/fsp.ld b/hw/bsp/ra/boards/uno_r4/script/fsp.ld new file mode 100644 index 000000000..605eef7d2 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/script/fsp.ld @@ -0,0 +1,769 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld b/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld new file mode 100644 index 000000000..22775395c --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld @@ -0,0 +1,25 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x8000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x40000; + DATA_FLASH_START = 0x40100000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x00000000; + OPTION_SETTING_LENGTH = 0x0; + OPTION_SETTING_S_START = 0x80000000; + OPTION_SETTING_S_LENGTH = 0x0; + ID_CODE_START = 0x01010018; + ID_CODE_LENGTH = 0x20; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x0; + OSPI_DEVICE_0_START = 0x80020000; + OSPI_DEVICE_0_LENGTH = 0x0; + OSPI_DEVICE_1_START = 0x80030000; + OSPI_DEVICE_1_LENGTH = 0x0; + +/* Uno R4 has bootloader */ +FLASH_IMAGE_START = 0x4000; diff --git a/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml b/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml new file mode 100644 index 000000000..b716c8ec9 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml @@ -0,0 +1,218 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<raConfiguration version="9"> + <generalSettings> + <option key="#Board#" value="board.custom"/> + <option key="CPU" value="RA4M1"/> + <option key="Core" value="CM4"/> + <option key="#TargetName#" value="R7FA4M1AB3CNE"/> + <option key="#TargetARCHITECTURE#" value="cortex-m4"/> + <option key="#DeviceCommand#" value="R7FA4M1AB"/> + <option key="#RTOS#" value="_none"/> + <option key="#pinconfiguration#" value="R7FA4M1AB3CNE.pincfg"/> + <option key="#FSPVersion#" value="5.6.0"/> + <option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/> + </generalSettings> + <raBspConfiguration> + <config id="config.bsp.ra4m1.R7FA4M1AB3CNE"> + <property id="config.bsp.part_number" value="config.bsp.part_number.value"/> + <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/> + <property id="config.bsp.rom_size_bytes_hidden" value="262144"/> + <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/> + <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/> + <property id="config.bsp.package_style" value="config.bsp.package_style.value"/> + <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/> + <property id="config.bsp.irq_count_hidden" value="32"/> + </config> + <config id="config.bsp.ra4m1"> + <property id="config.bsp.series" value="config.bsp.series.value"/> + </config> + <config id="config.bsp.ra4m1.fsp"> + <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/> + <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/> + <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/> + <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/> + <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/> + <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/> + <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/> + <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/> + <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/> + <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.190"/> + <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.enabled"/> + <property id="config.bsp.low_voltage_mode" value="config.bsp.low_voltage_mode.disabled"/> + <property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/> + <property id="config.bsp.fsp.mpu_pc0_start" value="0x00FFFFFC"/> + <property id="config.bsp.fsp.mpu_pc0_end" value="0x00FFFFFF"/> + <property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/> + <property id="config.bsp.fsp.mpu_pc1_start" value="0x00FFFFFC"/> + <property id="config.bsp.fsp.mpu_pc1_end" value="0x00FFFFFF"/> + <property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg0_start" value="0x00FFFFFC"/> + <property id="config.bsp.fsp.mpu_reg0_end" value="0x00FFFFFF"/> + <property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/> + <property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/> + <property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/> + <property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/> + <property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/> + <property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/> + <property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/> + <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/> + <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="64000000"/> + <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="6666666"/> + <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/> + <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="1"/> + <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="12000000"/> + <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="24000000"/> + <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="0"/> + <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0"/> + <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="0"/> + <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x0"/> + <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/> + <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/> + <property id="config.bsp.fsp.mcu.slcdc.1_4_bias_method" value="1"/> + <property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/> + <property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/> + <property id="config.bsp.common.id1" value=""/> + <property id="config.bsp.common.id2" value=""/> + <property id="config.bsp.common.id3" value=""/> + <property id="config.bsp.common.id4" value=""/> + <property id="config.bsp.common.id_fixed" value=""/> + </config> + <config id="config.bsp.ra"> + <property id="config.bsp.common.main" value="0x800"/> + <property id="config.bsp.common.heap" value="0x1000"/> + <property id="config.bsp.common.vcc" value="3300"/> + <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/> + <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/> + <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/> + <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/> + <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.disabled"/> + <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/> + <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/> + <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/> + <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/> + <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.disabled"/> + <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/> + <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/> + </config> + </raBspConfiguration> + <raClockConfiguration> + <node id="board.clock.xtal.freq" mul="0" option="_edit"/> + <node id="board.clock.pll.source" option="board.clock.pll.source.disabled"/> + <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/> + <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/> + <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/> + <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/> + <node id="board.clock.pll.div" option="board.clock.pll.div.4"/> + <node id="board.clock.pll.mul" option="board.clock.pll.mul.12"/> + <node id="board.clock.pll.display" option="board.clock.pll.display.value"/> + <node id="board.clock.clock.source" option="board.clock.clock.source.hoco"/> + <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/> + <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/> + <node id="board.clock.pclka.div" option="board.clock.pclka.div.1"/> + <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/> + <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/> + <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/> + <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.1"/> + <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/> + <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/> + <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/> + <node id="board.clock.fclk.div" option="board.clock.fclk.div.2"/> + <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/> + <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/> + <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/> + <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/> + <node id="board.clock.uclk.source" option="board.clock.uclk.source.hoco"/> + <node id="board.clock.uclk.display" option="board.clock.clkout.display.value"/> + </raClockConfiguration> + <raComponentSelection> + <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0"> + <description>Board Support Package Common Files</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0"> + <description>I/O Port</description> + <originalPack>Renesas.RA.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0"> + <description>Arm CMSIS Version 6 - Core (M)</description> + <originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="5.6.0"> + <description>Custom Board Support Files</description> + <originalPack>Renesas.RA_board_custom.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="device" variant="R7FA4M1AB3CNE" vendor="Renesas" version="5.6.0"> + <description>Board support package for R7FA4M1AB3CNE</description> + <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="device" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA4M1</description> + <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA4M1 - FSP Data</description> + <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack> + </component> + <component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="events" variant="" vendor="Renesas" version="5.6.0"> + <description>Board support package for RA4M1 - Events</description> + <originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack> + </component> + </raComponentSelection> + <raElcConfiguration/> + <raIcuConfiguration/> + <raModuleConfiguration> + <module id="module.driver.ioport_on_ioport.0"> + <property id="module.driver.ioport.name" value="g_ioport"/> + <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/> + <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/> + <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/> + </module> + <context id="_hal.0"> + <stack module="module.driver.ioport_on_ioport.0"/> + </context> + <config id="config.driver.ioport"> + <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/> + </config> + </raModuleConfiguration> + <raPinConfiguration> + <symbolicName propertyId="p110.symbolic_name" value="SW1"/> + <symbolicName propertyId="p111.symbolic_name" value="LED1"/> + <comment propertyId="p110.comment" value="active low"/> + <comment propertyId="p111.comment" value="active high"/> + <pincfg active="true" name="R7FA4M1AB3CNE.pincfg" selected="true" symbol="g_bsp_pin_cfg"> + <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/> + <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/> + <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/> + <configSetting altId="p108.debug0.swdio" configurationId="p108"/> + <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/> + <configSetting altId="p110.input" configurationId="p110"/> + <configSetting altId="p110.gpio_mode.gpio_mode_in" configurationId="p110.gpio_mode"/> + <configSetting altId="p110.gpio_pupd.gpio_pupd_ip_up" configurationId="p110.gpio_pupd"/> + <configSetting altId="p111.output.low" configurationId="p111"/> + <configSetting altId="p111.gpio_mode.gpio_mode_out.low" configurationId="p111.gpio_mode"/> + <configSetting altId="p300.debug0.swclk" configurationId="p300"/> + <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/> + <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/> + <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/> + <configSetting altId="p914.usbfs0.usbdp" configurationId="p914"/> + <configSetting altId="p914.gpio_mode.gpio_mode_peripheral" configurationId="p914.gpio_mode"/> + <configSetting altId="p915.usbfs0.usbdm" configurationId="p915"/> + <configSetting altId="p915.gpio_mode.gpio_mode_peripheral" configurationId="p915.gpio_mode"/> + <configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/> + <configSetting altId="usbfs0.usbdm.p915" configurationId="usbfs0.usbdm"/> + <configSetting altId="usbfs0.usbdp.p914" configurationId="usbfs0.usbdp"/> + <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/> + </pincfg> + </raPinConfiguration> +</raConfiguration> diff --git a/hw/bsp/ra/boards/uno_r4/uno_r4.ld b/hw/bsp/ra/boards/uno_r4/uno_r4.ld deleted file mode 100644 index 45f11dfb1..000000000 --- a/hw/bsp/ra/boards/uno_r4/uno_r4.ld +++ /dev/null @@ -1,25 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x8000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x40000; -DATA_FLASH_START = 0x40100000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x00000000; -OPTION_SETTING_LENGTH = 0x0; -OPTION_SETTING_S_START = 0x80000000; -OPTION_SETTING_S_LENGTH = 0x0; -ID_CODE_START = 0x01010018; -ID_CODE_LENGTH = 0x20; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x0; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -/* Uno R4 has bootloader */ -FLASH_IMAGE_START = 0x4000; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 87f7b4a22..0fd24e493 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -24,20 +24,19 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Renesas +*/ + #include <stdio.h> #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstrict-prototypes" #pragma GCC diagnostic ignored "-Wundef" - -// extra push due to https://github.com/renesas/fsp/pull/278 -#pragma GCC diagnostic push #endif -#include "bsp_api.h" -#include "r_ioport.h" -#include "r_ioport_api.h" +#include "common_data.h" #include "renesas.h" #ifdef __GNUC__ @@ -50,12 +49,6 @@ /* Key code for writing PRCR register. */ #define BSP_PRV_PRCR_KEY (0xA500U) -static const ioport_cfg_t family_pin_cfg = { - .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t), - .p_pin_cfg_data = board_pin_cfg, -}; -static ioport_instance_ctrl_t port_ctrl; - //--------------------------------------------------------------------+ // Vector Data //--------------------------------------------------------------------+ @@ -103,7 +96,7 @@ void board_init(void) { __enable_irq(); /* Configure pins. */ - R_IOPORT_Open(&port_ctrl, &family_pin_cfg); + R_IOPORT_Open(&IOPORT_CFG_CTRL, &IOPORT_CFG_NAME); #ifdef TRACE_ETM // TRCKCR is protected by PRCR bit0 register @@ -138,12 +131,12 @@ void board_init_after_tusb(void) { } void board_led_write(bool state) { - R_IOPORT_PinWrite(&port_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON); + R_IOPORT_PinWrite(&IOPORT_CFG_CTRL, LED1, state ? LED_STATE_ON : !LED_STATE_ON); } uint32_t board_button_read(void) { bsp_io_level_t lvl = !BUTTON_STATE_ACTIVE; - R_IOPORT_PinRead(&port_ctrl, SW1, &lvl); + R_IOPORT_PinRead(&IOPORT_CFG_CTRL, SW1, &lvl); return lvl == BUTTON_STATE_ACTIVE; } @@ -211,7 +204,6 @@ void usbfs_d1fifo_handler(void) { //------------- USB1 HighSpeed -------------// #ifdef BOARD_HAS_USB_HIGHSPEED - void usbhs_interrupt_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); @@ -230,7 +222,6 @@ void usbhs_d1fifo_handler(void) { R_BSP_IrqStatusClear(irq); // TODO not used yet } - #endif //--------------------------------------------------------------------+ diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 426e1ca8f..42a32631c 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -4,7 +4,7 @@ if (NOT BOARD) message(FATAL_ERROR "BOARD not specified") endif () -set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +set(CMSIS_DIR ${TOP}/lib/CMSIS_6) set(FSP_RA ${TOP}/hw/mcu/renesas/fsp/ra/fsp) # include board specific @@ -15,6 +15,28 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS RAXXX ${MCU_VARIANT} CACHE INTERNAL "") +# ---------------------- +# Port & Speed Selection +# ---------------------- +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 0) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif () + +if (NOT DEFINED RHPORT_SPEED) + set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) +endif () +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () + +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) + #------------------------------------ # BOARD_TARGET #------------------------------------ @@ -32,10 +54,11 @@ function(add_board_target BOARD_TARGET) ${FSP_RA}/src/bsp/mcu/all/bsp_io.c ${FSP_RA}/src/bsp/mcu/all/bsp_irq.c ${FSP_RA}/src/bsp/mcu/all/bsp_register_protection.c - ${FSP_RA}/src/bsp/mcu/all/bsp_rom_registers.c ${FSP_RA}/src/bsp/mcu/all/bsp_sbrk.c ${FSP_RA}/src/bsp/mcu/all/bsp_security.c ${FSP_RA}/src/r_ioport/r_ioport.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/common_data.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/pin_data.c ) target_compile_options(${BOARD_TARGET} PUBLIC @@ -44,8 +67,9 @@ function(add_board_target BOARD_TARGET) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg/bsp + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_cfg/fsp_cfg + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_cfg/fsp_cfg/bsp + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen ${CMSIS_DIR}/CMSIS/Core/Include ${FSP_RA}/inc ${FSP_RA}/inc/api @@ -54,22 +78,27 @@ function(add_board_target BOARD_TARGET) ${FSP_RA}/src/bsp/mcu/all ${FSP_RA}/src/bsp/mcu/${MCU_VARIANT} ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + ) update_board(${BOARD_TARGET}) if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID}) - set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc/${MCU_VARIANT}.ld) + set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script/fsp.ld) endif () if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${BOARD_TARGET} PUBLIC # linker file "LINKER:--script=${LD_FILE_GNU}" - -L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc + -L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script + -Wl,--defsym=end=__bss_end__ -nostartfiles - # nanolib - --specs=nano.specs - --specs=nosys.specs + --specs=nano.specs --specs=nosys.specs ) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${BOARD_TARGET} PUBLIC @@ -95,12 +124,18 @@ function(family_configure_example TARGET RTOS) # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + # Explicitly added bsp_rom_registers here, otherwise MCU can be bricked if g_bsp_rom_registers is dropped by linker + ${FSP_RA}/src/bsp/mcu/all/bsp_rom_registers.c ) target_include_directories(${TARGET} PUBLIC # family, hw, board ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ ) + target_compile_options(${TARGET} PUBLIC + -Wno-error=undef + -Wno-error=strict-prototypes + ) # # RA has custom freertos port # if (NOT TARGET freertos_kernel_port) @@ -112,22 +147,21 @@ function(family_configure_example TARGET RTOS) # endif () # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_RAXXX ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_RAXXX) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c ${TOP}/src/portable/renesas/rusb2/rusb2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_flash_jlink(${TARGET}) + family_add_bin_hex(${TARGET}) if (DEFINED DFU_UTIL_VID_PID) - family_add_bin_hex(${TARGET}) family_flash_dfu_util(${TARGET} ${DFU_UTIL_VID_PID}) endif () endfunction() diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index 4447e8499..6ac7c262f 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -1,42 +1,67 @@ -DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5 - FSP_RA = hw/mcu/renesas/fsp/ra/fsp include $(TOP)/$(BOARD_PATH)/board.mk # Don't include options setting in .bin file since it create unnecessary large file due to padding OBJCOPY_BIN_OPTION = --only-section .text --only-section .data --only-section .rodata --only-section .bss -# Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk -PORT ?= 0 +# ---------------------- +# Port & Speed Selection +# ---------------------- +RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 0 +RHPORT_HOST ?= 0 + +# Determine RHPORT_DEVICE_SPEED if not defined +ifndef RHPORT_DEVICE_SPEED +ifeq ($(RHPORT_DEVICE), 0) + RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif +# Determine RHPORT_HOST_SPEED if not defined +ifndef RHPORT_HOST_SPEED +ifeq ($(RHPORT_HOST), 0) + RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# -------------- +# Compiler Flags +# -------------- CFLAGS += \ - -flto \ -DCFG_TUSB_MCU=OPT_MCU_RAXXX \ - -DBOARD_TUD_RHPORT=$(PORT) \ + -DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \ + -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \ + -DBOARD_TUH_RHPORT=${RHPORT_HOST} \ + -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + +CFLAGS_GCC += \ + -flto \ -Wno-error=undef \ -Wno-error=strict-prototypes \ -Wno-error=cast-align \ -Wno-error=cast-qual \ -Wno-error=unused-but-set-variable \ -Wno-error=unused-variable \ - -nostdlib \ - -nostartfiles \ -ffreestanding -ifeq ($(PORT), 1) - CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - $(info "Using PORT 1 HighSpeed") -else - CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED - $(info "Using PORT 0 FullSpeed") -endif - -LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs +LDFLAGS_GCC += \ + -nostartfiles -nostdlib \ + -specs=nosys.specs -specs=nano.specs +# ----------------- +# Sources & Include +# ----------------- SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ src/portable/renesas/rusb2/rusb2_common.c \ + ${BOARD_PATH}/ra_gen/common_data.c \ + ${BOARD_PATH}/ra_gen/pin_data.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \ $(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \ @@ -53,10 +78,11 @@ SRC_C += \ $(FSP_RA)/src/r_ioport/r_ioport.c \ INC += \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(BOARD_PATH)/fsp_cfg \ - $(TOP)/$(BOARD_PATH)/fsp_cfg/bsp \ + $(TOP)/$(BOARD_PATH)/ra_cfg/fsp_cfg \ + $(TOP)/$(BOARD_PATH)/ra_cfg/fsp_cfg/bsp \ + $(TOP)/$(BOARD_PATH)/ra_gen \ + $(TOP)/lib/CMSIS_6/CMSIS/Core/Include \ $(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \ $(TOP)/$(FSP_RA)/inc \ $(TOP)/$(FSP_RA)/inc/api \ @@ -65,10 +91,11 @@ INC += \ $(TOP)/$(FSP_RA)/src/bsp/mcu/$(MCU_VARIANT) \ ifndef LD_FILE -LD_FILE = $(FAMILY_PATH)/linker/gcc/$(MCU_VARIANT).ld +LD_FILE = $(BOARD_PATH)/script/fsp.ld endif -LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc +LDFLAGS += -L$(TOP)/$(BOARD_PATH)/script +LDFLAGS += -Wl,--defsym=end=__bss_end__ # For freeRTOS port source # hack to use the port provided by renesas diff --git a/hw/bsp/ra/linker/gcc/ra2a1.ld b/hw/bsp/ra/linker/gcc/ra2a1.ld deleted file mode 100644 index 218acbb2a..000000000 --- a/hw/bsp/ra/linker/gcc/ra2a1.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x8000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x40000; -DATA_FLASH_START = 0x40100000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x00000000; -OPTION_SETTING_LENGTH = 0x0; -OPTION_SETTING_S_START = 0x80000000; -OPTION_SETTING_S_LENGTH = 0x0; -ID_CODE_START = 0x01010018; -ID_CODE_LENGTH = 0x20; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x0; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra4m1.ld b/hw/bsp/ra/linker/gcc/ra4m1.ld deleted file mode 100644 index 218acbb2a..000000000 --- a/hw/bsp/ra/linker/gcc/ra4m1.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x8000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x40000; -DATA_FLASH_START = 0x40100000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x00000000; -OPTION_SETTING_LENGTH = 0x0; -OPTION_SETTING_S_START = 0x80000000; -OPTION_SETTING_S_LENGTH = 0x0; -ID_CODE_START = 0x01010018; -ID_CODE_LENGTH = 0x20; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x0; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra4m3.ld b/hw/bsp/ra/linker/gcc/ra4m3.ld deleted file mode 100644 index 7b3a63fbe..000000000 --- a/hw/bsp/ra/linker/gcc/ra4m3.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x20000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x100000; -DATA_FLASH_START = 0x08000000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x0100A100; -OPTION_SETTING_LENGTH = 0x100; -OPTION_SETTING_S_START = 0x0100A200; -OPTION_SETTING_S_LENGTH = 0x100; -ID_CODE_START = 0x00000000; -ID_CODE_LENGTH = 0x0; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra6m1.ld b/hw/bsp/ra/linker/gcc/ra6m1.ld deleted file mode 100644 index 91d27f74c..000000000 --- a/hw/bsp/ra/linker/gcc/ra6m1.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x1FFE0000; -RAM_LENGTH = 0x40000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x80000; -DATA_FLASH_START = 0x40100000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x00000000; -OPTION_SETTING_LENGTH = 0x0; -OPTION_SETTING_S_START = 0x80000000; -OPTION_SETTING_S_LENGTH = 0x0; -ID_CODE_START = 0x0100A150; -ID_CODE_LENGTH = 0x10; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra6m5.ld b/hw/bsp/ra/linker/gcc/ra6m5.ld deleted file mode 100644 index af747fd9b..000000000 --- a/hw/bsp/ra/linker/gcc/ra6m5.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x80000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x200000; -DATA_FLASH_START = 0x08000000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x0100A100; -OPTION_SETTING_LENGTH = 0x100; -OPTION_SETTING_S_START = 0x0100A200; -OPTION_SETTING_S_LENGTH = 0x100; -ID_CODE_START = 0x00000000; -ID_CODE_LENGTH = 0x0; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x68000000; -OSPI_DEVICE_0_LENGTH = 0x8000000; -OSPI_DEVICE_1_START = 0x70000000; -OSPI_DEVICE_1_LENGTH = 0x10000000; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/vector_data.h b/hw/bsp/ra/vector_data.h index 2b3b7d837..a85d064bd 100644 --- a/hw/bsp/ra/vector_data.h +++ b/hw/bsp/ra/vector_data.h @@ -6,6 +6,10 @@ extern "C" { #endif +#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) +#define BOARD_HAS_USB_HIGHSPEED +#endif + /* ISR prototypes */ void usbfs_interrupt_handler(void); void usbfs_resume_handler(void); diff --git a/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.cmake b/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.cmake new file mode 100644 index 000000000..41897f644 --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.cmake @@ -0,0 +1,2 @@ +set(PICO_PLATFORM rp2040) +set(PICO_BOARD adafruit_feather_rp2040_usb_host) diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.h index 733e93797..d003ae828 100644 --- a/hw/bsp/rp2040/board.h +++ b/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.h @@ -1,7 +1,7 @@ /* * The MIT License (MIT) * - * Copyright (c) 2021, Ha Thach (tinyusb.org) + * Copyright (c) 2025 Ha Thach (tinyusb.org) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -24,55 +24,27 @@ * This file is part of the TinyUSB stack. */ -#ifndef BOARD_H_ -#define BOARD_H_ +/* metadata: + name: Adafruit Feather RP2040 with USB Type A Host + url: https://www.adafruit.com/product/5723 +*/ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H #ifdef __cplusplus extern "C" { #endif -// LED -#ifdef PICO_DEFAULT_LED_PIN -#define LED_PIN PICO_DEFAULT_LED_PIN -#define LED_STATE_ON (!(PICO_DEFAULT_LED_PIN_INVERTED)) -#endif - -// Button pin is BOOTSEL which is flash CS pin -#define BUTTON_BOOTSEL -#define BUTTON_STATE_ACTIVE 0 - -// UART -#if defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) && \ - defined(PICO_DEFAULT_UART) && defined(LIB_PICO_STDIO_UART) -#define UART_DEV PICO_DEFAULT_UART -#define UART_TX_PIN PICO_DEFAULT_UART_TX_PIN -#define UART_RX_PIN PICO_DEFAULT_UART_RX_PIN -#endif +// UART and LED are already defined in pico-sdk board //--------------------------------------------------------------------+ // PIO_USB -// default to pin on Adafruit Feather rp2040 USB Host or Tester if defined //--------------------------------------------------------------------+ -// #define USE_ADAFRUIT_FEATHER_RP2040_USBHOST -#ifdef USE_ADAFRUIT_FEATHER_RP2040_USBHOST #define PICO_DEFAULT_PIO_USB_DP_PIN 16 #define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 18 -#endif - -#ifndef PICO_DEFAULT_PIO_USB_DP_PIN -#define PICO_DEFAULT_PIO_USB_DP_PIN 20 -#endif - -// VBUS enable pin and its active state -#ifndef PICO_DEFAULT_PIO_USB_VBUSEN_PIN -#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 -#endif - -// VBUS enable state -#ifndef PICO_DEFAULT_PIO_USB_VBUSEN_STATE #define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 -#endif //-------------------------------------------------------------------- // USB Host MAX3421E @@ -94,4 +66,4 @@ } #endif -#endif /* BOARD_H_ */ +#endif diff --git a/hw/bsp/rp2040/boards/adafruit_fruit_jam/adafruit_fruit_jam.h b/hw/bsp/rp2040/boards/adafruit_fruit_jam/adafruit_fruit_jam.h new file mode 100644 index 000000000..2d4c689de --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_fruit_jam/adafruit_fruit_jam.h @@ -0,0 +1,113 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ +#ifndef BOARDS_ADAFRUIT_FRUIT_JAM_H +#define BOARDS_ADAFRUIT_FRUIT_JAM_H + +// required for board that is not part of pico-sdk + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +// For board detection +#define ADAFRUIT_FRUIT_JAM + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 8 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 9 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 29 +#endif + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 32 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 20 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 21 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 30 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 31 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 28 +#endif + +// --- FLASH --- + +// FruitJam use w25q128 but sdk does not have .s for it, use q080 instead +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// pico_cmake_set_default PICO_RP2350_A2_SUPPORTED = 1 +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.cmake b/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.cmake new file mode 100644 index 000000000..4ab8a5477 --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.cmake @@ -0,0 +1,4 @@ +set(PICO_PLATFORM rp2350-arm-s) +set(PICO_BOARD adafruit_fruit_jam) +set(PICO_BOARD_HEADER_DIRS ${CMAKE_CURRENT_LIST_DIR}) +#set(OPENOCD_SERIAL E6614103E78E8324) diff --git a/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h b/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h new file mode 100644 index 000000000..0f53fd96f --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h @@ -0,0 +1,57 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Adafruit Fruit Jam - Mini RP2350 + url: https://www.adafruit.com/product/6200 +*/ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ +// default to pico brain tester +#define PICO_DEFAULT_PIO_USB_DP_PIN 1 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 11 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/adafruit_metro_rp2350/adafruit_metro_rp2350.h b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/adafruit_metro_rp2350.h new file mode 100644 index 000000000..9fb9658a5 --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/adafruit_metro_rp2350.h @@ -0,0 +1,113 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ +#ifndef BOARDS_ADAFRUIT_METRO_RP2350_H +#define BOARDS_ADAFRUIT_METRO_RP2350_H + +// required for board that is not part of pico-sdk + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +// For board detection +#define ADAFRUIT_METRO_RP2350 + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 23 +#endif + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 25 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 20 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 21 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 30 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 31 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 28 +#endif + +// --- FLASH --- + +// FruitJam use w25q128 but sdk does not have .s for it, use q080 instead +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// pico_cmake_set_default PICO_RP2350_A2_SUPPORTED = 1 +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.cmake b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.cmake new file mode 100644 index 000000000..9a58821a5 --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.cmake @@ -0,0 +1,4 @@ +set(PICO_PLATFORM rp2350-arm-s) +set(PICO_BOARD adafruit_metro_rp2350) +set(PICO_BOARD_HEADER_DIRS ${CMAKE_CURRENT_LIST_DIR}) +#set(OPENOCD_SERIAL E6614103E78E8324) diff --git a/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.h b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.h new file mode 100644 index 000000000..0b8515d1f --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.h @@ -0,0 +1,57 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Adafruit Metro RP2350 + url: https://www.adafruit.com/product/6003 +*/ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ +// default to pico brain tester +#define PICO_DEFAULT_PIO_USB_DP_PIN 32 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 29 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.h b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.h new file mode 100644 index 000000000..f36ca14c9 --- /dev/null +++ b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.h @@ -0,0 +1,64 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ + +#define PICO_DEFAULT_PIO_USB_DP_PIN 16 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 18 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef PICO_DEFAULT_SPI +#define MAX3421_SPI PICO_DEFAULT_SPI // sdk v2 +#else +#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE // sdk v1 +#endif + +#define MAX3421_SCK_PIN PICO_DEFAULT_SPI_SCK_PIN +#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN +#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN +#define MAX3421_CS_PIN 10 +#define MAX3421_INTR_PIN 9 + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/pico_sdk/board.h b/hw/bsp/rp2040/boards/pico_sdk/board.h new file mode 100644 index 000000000..284edac7d --- /dev/null +++ b/hw/bsp/rp2040/boards/pico_sdk/board.h @@ -0,0 +1,40 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake index 804cdb50a..2d739291c 100644 --- a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake @@ -1,2 +1,3 @@ set(PICO_PLATFORM rp2040) set(PICO_BOARD pico) +#set(OPENOCD_SERIAL E6614103E719612F) diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.h b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.h new file mode 100644 index 000000000..88f8793f4 --- /dev/null +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.h @@ -0,0 +1,69 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Pico + url: https://www.raspberrypi.com/products/raspberry-pi-pico/ +*/ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ +// default to pico brain tester +#define PICO_DEFAULT_PIO_USB_DP_PIN 20 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef PICO_DEFAULT_SPI +#define MAX3421_SPI PICO_DEFAULT_SPI // sdk v2 +#else +#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE // sdk v1 +#endif + +#define MAX3421_SCK_PIN PICO_DEFAULT_SPI_SCK_PIN +#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN +#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN +#define MAX3421_CS_PIN 10 +#define MAX3421_INTR_PIN 9 + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake index 3482e2674..0a7dd4d23 100644 --- a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake @@ -1,2 +1,3 @@ set(PICO_PLATFORM rp2350-arm-s) set(PICO_BOARD pico2) +#set(OPENOCD_SERIAL E6614103E77C5A24) diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h new file mode 100644 index 000000000..b5ce8b7e1 --- /dev/null +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h @@ -0,0 +1,69 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Pico2 + url: https://www.raspberrypi.com/products/raspberry-pi-pico-2/ +*/ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ +// default to pico brain tester +#define PICO_DEFAULT_PIO_USB_DP_PIN 20 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef PICO_DEFAULT_SPI +#define MAX3421_SPI PICO_DEFAULT_SPI // sdk v2 +#else +#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE // sdk v1 +#endif + +#define MAX3421_SCK_PIN PICO_DEFAULT_SPI_SCK_PIN +#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN +#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN +#define MAX3421_CS_PIN 10 +#define MAX3421_INTR_PIN 9 + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.cmake new file mode 100644 index 000000000..97621d855 --- /dev/null +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.cmake @@ -0,0 +1,2 @@ +set(PICO_PLATFORM rp2040) +set(PICO_BOARD pico_w) diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.h b/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.h new file mode 100644 index 000000000..8af32fc9e --- /dev/null +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.h @@ -0,0 +1,70 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Pico + url: https://www.raspberrypi.com/products/raspberry-pi-pico/ +*/ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ +// default to pico brain tester +#define PICO_DEFAULT_PIO_USB_DP_PIN 20 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef PICO_DEFAULT_SPI +#define MAX3421_SPI PICO_DEFAULT_SPI // sdk v2 +#else +#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE // sdk v1 +#endif + +#define MAX3421_SCK_PIN PICO_DEFAULT_SPI_SCK_PIN +#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN +#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN +#define MAX3421_CS_PIN 10 +#define MAX3421_INTR_PIN 9 + + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 452a5568f..a22924131 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -25,6 +25,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Raspberry Pi +*/ + #include "pico/stdlib.h" #include "pico/binary_info.h" #include "pico/unique_id.h" @@ -38,10 +42,6 @@ #include "bsp/board_api.h" #include "board.h" -#ifdef UART_DEV -static uart_inst_t *uart_inst; -#endif - #if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB) #include "pio_usb.h" #endif @@ -51,6 +51,36 @@ static uart_inst_t *uart_inst; static void max3421_init(void); #endif +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ +// LED +#if !defined(LED_PIN) && defined(PICO_DEFAULT_LED_PIN) +#define LED_PIN PICO_DEFAULT_LED_PIN +#define LED_STATE_ON (!(PICO_DEFAULT_LED_PIN_INVERTED)) +#endif + +// Button, if not defined use BOOTSEL button +#ifndef BUTTON_PIN +#define BUTTON_BOOTSEL +#define BUTTON_STATE_ACTIVE 0 +#endif + +// UART +#if !defined(UART_DEV) && defined(PICO_DEFAULT_UART) && defined(LIB_PICO_STDIO_UART) && \ + defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) +#define UART_DEV PICO_DEFAULT_UART +#define UART_TX_PIN PICO_DEFAULT_UART_TX_PIN +#define UART_RX_PIN PICO_DEFAULT_UART_RX_PIN +#endif + +#ifdef UART_DEV +static uart_inst_t *uart_inst; +#endif + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ #ifdef BUTTON_BOOTSEL // This example blinks the Picoboard LED when the BOOTSEL button is pressed. // @@ -75,7 +105,7 @@ bool __no_inline_not_in_flash_func(get_bootsel_button)(void) { IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS); // Note we can't call into any sleep functions in flash right now - for (volatile int i = 0; i < 1000; ++i); + for (volatile int i = 0; i < 1000; ++i) {} // The HI GPIO registers in SIO can observe and control the 6 QSPI pins. // Note the button pulls the pin *low* when pressed. @@ -129,12 +159,15 @@ void stdio_rtt_init(void) { //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ - void board_init(void) { #if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB) - // Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb + // Set the system clock to a multiple of 12mhz for bit-banging USB with pico-usb set_sys_clock_khz(120000, true); + // set_sys_clock_khz(180000, true); + // set_sys_clock_khz(192000, true); + // set_sys_clock_khz(240000, true); + // set_sys_clock_khz(264000, true); #ifdef PICO_DEFAULT_PIO_USB_VBUSEN_PIN gpio_init(PICO_DEFAULT_PIO_USB_VBUSEN_PIN); @@ -189,7 +222,6 @@ void board_init(void) //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ - void board_led_write(bool state) { (void) state; @@ -222,7 +254,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) { int board_uart_read(uint8_t *buf, int len) { #ifdef UART_DEV int count = 0; - while ( (count < len) && uart_is_readable(uart_inst) ) { + while ((count < len) && uart_is_readable(uart_inst)) { buf[count] = uart_getc(uart_inst); count++; } @@ -250,6 +282,10 @@ int board_getchar(void) { return getchar_timeout_us(0); } +void board_putchar(int c) { + stdio_putchar(c); +} + //--------------------------------------------------------------------+ // USB Interrupt Handler // rp2040 implementation will install appropriate handler when initializing @@ -262,7 +298,9 @@ int board_getchar(void) { #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 void max3421_int_handler(uint gpio, uint32_t event_mask) { - if (!(gpio == MAX3421_INTR_PIN && event_mask & GPIO_IRQ_EDGE_FALL)) return; + if (!(gpio == MAX3421_INTR_PIN && event_mask & GPIO_IRQ_EDGE_FALL)) { + return; + } tuh_int_handler(BOARD_TUH_RHPORT, true); } diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index b2b01b1cf..2182e9ad1 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -31,7 +31,9 @@ elseif (PICO_PLATFORM STREQUAL "rp2350-riscv") set(OPENOCD_TARGET rp2350-riscv) endif() -set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/${OPENOCD_TARGET}.cfg -c \"adapter speed 5000\"") +if (NOT OPENOCD_OPTION) + set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/${OPENOCD_TARGET}.cfg -c \"adapter speed 5000\"") +endif() if (NOT PICO_TINYUSB_PATH) set(PICO_TINYUSB_PATH ${TOP}) @@ -111,6 +113,7 @@ target_sources(tinyusb_host_base INTERFACE ${TOP}/src/host/hub.c ${TOP}/src/class/cdc/cdc_host.c ${TOP}/src/class/hid/hid_host.c + ${TOP}/src/class/midi/midi_host.c ${TOP}/src/class/msc/msc_host.c ${TOP}/src/class/vendor/vendor_host.c ) @@ -143,6 +146,7 @@ target_sources(tinyusb_bsp INTERFACE ) target_include_directories(tinyusb_bsp INTERFACE ${TOP}/hw + ${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD} ) target_link_libraries(tinyusb_bsp INTERFACE pico_unique_id diff --git a/hw/bsp/rp2040/family.mk b/hw/bsp/rp2040/family.mk deleted file mode 100644 index 25d1ad9c5..000000000 --- a/hw/bsp/rp2040/family.mk +++ /dev/null @@ -1,18 +0,0 @@ -JLINK_DEVICE = rp2040_m0_0 -PYOCD_TARGET = rp2040 - -DEPS_SUBMODULES += hw/mcu/raspberry_pi/Pico-PIO-USB - -ifeq ($(DEBUG), 1) -CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug -endif - -$(BUILD): - cmake -S . -B $(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) -DPICO_BUILD_DOCS=0 $(CMAKE_DEFSYM) - -all: $(BUILD) - $(MAKE) -C $(BUILD) - -flash: flash-pyocd -flash-uf2: - @$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2 diff --git a/hw/bsp/rp2040/rp2350-openocd.cfg b/hw/bsp/rp2040/rp2350-openocd.cfg new file mode 100644 index 000000000..52c71cd99 --- /dev/null +++ b/hw/bsp/rp2040/rp2350-openocd.cfg @@ -0,0 +1,3 @@ +source [find interface/cmsis-dap.cfg] +adapter speed 5000 +source [find target/rp2350.cfg] diff --git a/hw/bsp/rp2040/skip_ci.txt b/hw/bsp/rp2040/skip_ci.txt new file mode 100644 index 000000000..fe99c9f65 --- /dev/null +++ b/hw/bsp/rp2040/skip_ci.txt @@ -0,0 +1,7 @@ +# boards in this files are skipped when running CI with this family +adafruit_feather_rp2040_usb_host +adafruit_fruit_jam +adafruit_metro_rp2350 +feather_rp2040_max3421 +pico_sdk +raspberry_pi_pico_w diff --git a/hw/bsp/rx/boards/gr_citrus/board.h b/hw/bsp/rx/boards/gr_citrus/board.h new file mode 100644 index 000000000..617d309c3 --- /dev/null +++ b/hw/bsp/rx/boards/gr_citrus/board.h @@ -0,0 +1,43 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: GR Citrus + url: https://www.renesas.com/en/products/gadget-renesas/boards/gr-citrus +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/rx/boards/rx65n_target/board.h b/hw/bsp/rx/boards/rx65n_target/board.h new file mode 100644 index 000000000..8c8e7b95f --- /dev/null +++ b/hw/bsp/rx/boards/rx65n_target/board.h @@ -0,0 +1,43 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: RX65N Target Board + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk5rx65n0c00000br-target-board-rx65n +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk index 02ea0dfa4..4ecf80409 100644 --- a/hw/bsp/rx/family.mk +++ b/hw/bsp/rx/family.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/renesas/rx - # Cross Compiler for RX CROSS_COMPILE = rx-elf- diff --git a/hw/bsp/samd11/boards/cynthion_d11/board.h b/hw/bsp/samd11/boards/cynthion_d11/board.h index b13c8eeea..8916e9b83 100644 --- a/hw/bsp/samd11/boards/cynthion_d11/board.h +++ b/hw/bsp/samd11/boards/cynthion_d11/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Great Scott Gadgets Cynthion + url: https://greatscottgadgets.com/cynthion/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd11/boards/samd11_xplained/board.h b/hw/bsp/samd11/boards/samd11_xplained/board.h index 2bbec4958..13045ac1d 100644 --- a/hw/bsp/samd11/boards/samd11_xplained/board.h +++ b/hw/bsp/samd11/boards/samd11_xplained/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAMD11 Xplained Pro + url: https://www.microchip.com/en-us/development-tool/ATSAMD11-XPRO +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd11/family.c b/hw/bsp/samd11/family.c index a6588805a..79ca9de02 100644 --- a/hw/bsp/samd11/family.c +++ b/hw/bsp/samd11/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Microchip +*/ + #include "sam.h" // Suppress warning caused by mcu driver diff --git a/hw/bsp/samd11/family.cmake b/hw/bsp/samd11/family.cmake index c9ccc86f8..965b1cfb5 100644 --- a/hw/bsp/samd11/family.cmake +++ b/hw/bsp/samd11/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAMD11 CACHE INTERNAL "") @@ -100,14 +100,13 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_SAMD11 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_SAMD11) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/board.h b/hw/bsp/samd21/boards/atsamd21_xpro/board.h index 315e40c78..6d2e40c56 100644 --- a/hw/bsp/samd21/boards/atsamd21_xpro/board.h +++ b/hw/bsp/samd21/boards/atsamd21_xpro/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAMD21 Xplained Pro + url: https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMD21-XPRO +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/circuitplayground_express/board.h b/hw/bsp/samd21/boards/circuitplayground_express/board.h index 0037db00d..6a4ec32a9 100644 --- a/hw/bsp/samd21/boards/circuitplayground_express/board.h +++ b/hw/bsp/samd21/boards/circuitplayground_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Circuit Playground Express + url: https://www.adafruit.com/product/3333 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.h b/hw/bsp/samd21/boards/curiosity_nano/board.h index 1a4a833a3..78d701ec9 100644 --- a/hw/bsp/samd21/boards/curiosity_nano/board.h +++ b/hw/bsp/samd21/boards/curiosity_nano/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAMD21 Curiosty Nano + url: https://www.microchip.com/en-us/development-tool/dm320119 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/cynthion_d21/board.h b/hw/bsp/samd21/boards/cynthion_d21/board.h index 776063636..6a2b8c5c6 100644 --- a/hw/bsp/samd21/boards/cynthion_d21/board.h +++ b/hw/bsp/samd21/boards/cynthion_d21/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Great Scott Gadgets Cynthion + url: https://greatscottgadgets.com/cynthion/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/feather_m0_express/board.h b/hw/bsp/samd21/boards/feather_m0_express/board.h index 56ae3230d..a7f9122ee 100644 --- a/hw/bsp/samd21/boards/feather_m0_express/board.h +++ b/hw/bsp/samd21/boards/feather_m0_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather M0 Express + url: https://www.adafruit.com/product/3403 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/board.h b/hw/bsp/samd21/boards/itsybitsy_m0/board.h index 6ee814da5..15a0afb15 100644 --- a/hw/bsp/samd21/boards/itsybitsy_m0/board.h +++ b/hw/bsp/samd21/boards/itsybitsy_m0/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit ItsyBitsy M0 + url: https://www.adafruit.com/product/3727 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.h b/hw/bsp/samd21/boards/metro_m0_express/board.h index 6dd53e901..405c92b02 100644 --- a/hw/bsp/samd21/boards/metro_m0_express/board.h +++ b/hw/bsp/samd21/boards/metro_m0_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Metro M0 Express + url: https://www.adafruit.com/product/3505 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/qtpy/board.h b/hw/bsp/samd21/boards/qtpy/board.h index 9ba39e966..29a9f727f 100644 --- a/hw/bsp/samd21/boards/qtpy/board.h +++ b/hw/bsp/samd21/boards/qtpy/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit QT Py + url: https://www.adafruit.com/product/4600 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/board.h b/hw/bsp/samd21/boards/seeeduino_xiao/board.h index 1bd63d6d9..0a6d1fc7d 100644 --- a/hw/bsp/samd21/boards/seeeduino_xiao/board.h +++ b/hw/bsp/samd21/boards/seeeduino_xiao/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Seeeduino XIAO + url: https://wiki.seeedstudio.com/Seeeduino-XIAO/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h index 60a86d743..85be34008 100644 --- a/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h +++ b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SparkFun SAMD21 Mini + url: https://www.sparkfun.com/products/13664 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/trinket_m0/board.h b/hw/bsp/samd21/boards/trinket_m0/board.h index c94a3abb6..22e7cb77f 100644 --- a/hw/bsp/samd21/boards/trinket_m0/board.h +++ b/hw/bsp/samd21/boards/trinket_m0/board.h @@ -23,6 +23,11 @@ * */ +/* metadata: + name: Adafruit Trinket M0 + url: https://www.adafruit.com/product/3500 +*/ + #pragma once // LED diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c index 7ca20c458..c360a4a5a 100644 --- a/hw/bsp/samd21/family.c +++ b/hw/bsp/samd21/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Microchip +*/ + #include "sam.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake index c836b85d9..4a10d6224 100644 --- a/hw/bsp/samd21/family.cmake +++ b/hw/bsp/samd21/family.cmake @@ -6,7 +6,7 @@ set(SDK_DIR ${TOP}/hw/mcu/microchip/samd21) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAMD21 CACHE INTERNAL "") @@ -96,14 +96,11 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_SAMD21 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_SAMD21) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/samd5x_e5x/boards/d5035_01/board.h b/hw/bsp/samd5x_e5x/boards/d5035_01/board.h index 2cf59f5d1..4eb4a4ebe 100644 --- a/hw/bsp/samd5x_e5x/boards/d5035_01/board.h +++ b/hw/bsp/samd5x_e5x/boards/d5035_01/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: D5035-01 + url: https://github.com/RudolphRiedel/USB_CAN-FD +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h index 83de04266..edb965c9d 100644 --- a/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h +++ b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather M4 Express + url: https://www.adafruit.com/product/3857 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h index 272315771..d41ca4ac3 100644 --- a/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h +++ b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit ItsyBitsy M4 + url: https://www.adafruit.com/product/3800 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h index b3b80db89..b2eaaa54d 100644 --- a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h +++ b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Metro M4 Express + url: https://www.adafruit.com/product/3382 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/pybadge/board.h b/hw/bsp/samd5x_e5x/boards/pybadge/board.h index 4629643fd..a5d447db6 100644 --- a/hw/bsp/samd5x_e5x/boards/pybadge/board.h +++ b/hw/bsp/samd5x_e5x/boards/pybadge/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit PyBadge + url: https://www.adafruit.com/product/4200 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/pyportal/board.h b/hw/bsp/samd5x_e5x/boards/pyportal/board.h index ff04c900b..e635e1375 100644 --- a/hw/bsp/samd5x_e5x/boards/pyportal/board.h +++ b/hw/bsp/samd5x_e5x/boards/pyportal/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit PyPortal + url: https://www.adafruit.com/product/4116 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h index faaa52b8e..6c252f9d0 100644 --- a/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h +++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAME54 Xplained Pro + url: https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAME54-XPRO +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/family.c b/hw/bsp/samd5x_e5x/family.c index abaee353b..8ceddb1be 100644 --- a/hw/bsp/samd5x_e5x/family.c +++ b/hw/bsp/samd5x_e5x/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Microchip +*/ + #include "sam.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/samd5x_e5x/family.cmake b/hw/bsp/samd5x_e5x/family.cmake index fd95ce10e..50e0ec66d 100644 --- a/hw/bsp/samd5x_e5x/family.cmake +++ b/hw/bsp/samd5x_e5x/family.cmake @@ -6,7 +6,7 @@ set(SDK_DIR ${TOP}/hw/mcu/microchip/${SAM_FAMILY}) set(CMSIS_5 ${TOP}/lib/CMSIS_5) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAMD51 SAME54 CACHE INTERNAL "") @@ -93,14 +93,11 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_SAMD51 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_SAMD51) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk index 281a947f3..7e949e135 100644 --- a/hw/bsp/same70_qmtech/board.mk +++ b/hw/bsp/same70_qmtech/board.mk @@ -1,4 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/microchip ASF_DIR = hw/mcu/microchip/same70 CFLAGS += \ diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk index 3edc128a5..2d97ecdc1 100644 --- a/hw/bsp/same70_xplained/board.mk +++ b/hw/bsp/same70_xplained/board.mk @@ -1,4 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/microchip ASF_DIR = hw/mcu/microchip/same70 CFLAGS += \ @@ -14,6 +13,14 @@ CFLAGS += \ # suppress following warnings from mcu driver CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=redundant-decls +SPEED ?= high + +ifeq ($(SPEED), high) + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED +else + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED +endif + # SAM driver is flooded with -Wcast-qual which slow down complication significantly CFLAGS_SKIP += -Wcast-qual diff --git a/hw/bsp/samg/boards/samg55_xplained/board.h b/hw/bsp/samg/boards/samg55_xplained/board.h index c94cda198..53c557ef0 100644 --- a/hw/bsp/samg/boards/samg55_xplained/board.h +++ b/hw/bsp/samg/boards/samg55_xplained/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: SAMG55 Xplained Pro + url: https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMG55-XPRO +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/samg/family.c b/hw/bsp/samg/family.c index 63db5739d..8db429e79 100644 --- a/hw/bsp/samg/family.c +++ b/hw/bsp/samg/family.c @@ -23,6 +23,10 @@ * */ +/* metadata: + manufacturer: Microchip +*/ + #include "sam.h" // Suppress warning caused by mcu driver diff --git a/hw/bsp/samg/family.cmake b/hw/bsp/samg/family.cmake index 1cc715ce6..eb00c8c52 100644 --- a/hw/bsp/samg/family.cmake +++ b/hw/bsp/samg/family.cmake @@ -7,7 +7,7 @@ set(SDK_DIR ${TOP}/hw/mcu/microchip/samg55) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAMG CACHE INTERNAL "") @@ -98,14 +98,13 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_SAMG ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_SAMG) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samg/dcd_samg.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h index 315e40c78..b93b4e591 100644 --- a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h +++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAML21 Xplained Pro + url: https://www.microchip.com/en-us/development-tool/atsaml21-xpro-b +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.h b/hw/bsp/saml2x/boards/saml22_feather/board.h index 72e9897b6..f8660c3f8 100644 --- a/hw/bsp/saml2x/boards/saml22_feather/board.h +++ b/hw/bsp/saml2x/boards/saml22_feather/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAML22 Feather + url: https://github.com/joeycastillo/Feather-Projects/tree/main/SAML22%20Feather +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h index 735f6afc8..502c799db 100644 --- a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h +++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SensorWatch + url: https://github.com/joeycastillo/Sensor-Watch +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/saml2x/family.c b/hw/bsp/saml2x/family.c index 11977b036..cdc65baf1 100644 --- a/hw/bsp/saml2x/family.c +++ b/hw/bsp/saml2x/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Microchip +*/ + #include "sam.h" // Suppress warning caused by mcu driver diff --git a/hw/bsp/saml2x/family.cmake b/hw/bsp/saml2x/family.cmake index 2338d1916..49f2e3e75 100644 --- a/hw/bsp/saml2x/family.cmake +++ b/hw/bsp/saml2x/family.cmake @@ -7,7 +7,7 @@ set(SDK_DIR ${TOP}/hw/mcu/microchip/${SAM_FAMILY}) set(CMSIS_5 ${TOP}/lib/CMSIS_5) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAML21 SAML22 CACHE INTERNAL "") @@ -100,14 +100,13 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_SAML22 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_SAML22) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk index 687761364..5dd7a158f 100644 --- a/hw/bsp/sltb009a/board.mk +++ b/hw/bsp/sltb009a/board.mk @@ -16,9 +16,6 @@ CFLAGS += \ SILABS_FAMILY = efm32gg12b SILABS_CMSIS = hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)/Device/SiliconLabs/$(shell echo $(SILABS_FAMILY) | tr a-z A-Z) -DEPS_SUBMODULES += hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY) -DEPS_SUBMODULES += lib/CMSIS_5 - LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs # All source paths should be relative to the top level. diff --git a/hw/bsp/spresense/board.mk b/hw/bsp/spresense/board.mk index 15fa0ff20..24f39d2b6 100644 --- a/hw/bsp/spresense/board.mk +++ b/hw/bsp/spresense/board.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/sony/cxd56/spresense-exported-sdk - # Platforms are: Linux, Darwin, MSYS, CYGWIN PLATFORM := $(firstword $(subst _, ,$(shell uname -s 2>/dev/null))) diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h index f08762736..751df2251 100644 --- a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h +++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32C071 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-g071rb.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -50,9 +55,45 @@ // Enable UART serial communication with the ST-Link #define UART_DEV USART2 +#define UART_CLK_EN __HAL_RCC_USART2_CLK_ENABLE #define UART_GPIO_PORT GPIOA #define UART_GPIO_AF GPIO_AF1_USART2 #define UART_TX_PIN GPIO_PIN_2 #define UART_RX_PIN GPIO_PIN_3 +static inline void board_clock_init(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_CRSInitTypeDef RCC_CRSInitStruct = {0}; + + /* -1- Enable HSIUSB48 Oscillator */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* -2- Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSIUSB48; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1); + + + __HAL_RCC_CRS_CLK_ENABLE(); + + // Configures CRS + RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; + RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; + RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING; + RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000); + RCC_CRSInitStruct.ErrorLimitValue = 34; + RCC_CRSInitStruct.HSI48CalibrationValue = 32; + + HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); +} + #endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32c0/family.c b/hw/bsp/stm32c0/family.c index dba6a8af1..09704b527 100644 --- a/hw/bsp/stm32c0/family.c +++ b/hw/bsp/stm32c0/family.c @@ -25,6 +25,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32c0xx_hal.h" #include "bsp/board_api.h" #include "board.h" @@ -49,31 +53,16 @@ UART_HandleTypeDef UartHandle; void board_init(void) { HAL_Init(); - - // Enable the HSIUSB48 48 MHz oscillator. - RCC->CR |= RCC_CR_HSIUSB48ON; - - // Wait for HSIUSB48 to be ready. - while (!(RCC->CR & RCC_CR_HSIUSB48RDY)) { } - - // Change the SYSCLK source to HSIUSB48. - RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_SYSCLKSOURCE_HSIUSB48; - - // Wait for the SYSCLK source to change. - while ((RCC->CFGR & RCC_CFGR_SWS) >> RCC_CFGR_SWS_Pos != RCC_SYSCLKSOURCE_HSIUSB48) { } - - // Disable HSI48 to save power. - RCC->CR &= ~RCC_CR_HSION; + board_clock_init(); // Enable peripheral clocks. - RCC->APBENR1 = RCC_APBENR1_USBEN | RCC_APBENR1_CRSEN | RCC_APBENR1_USART2EN; - RCC->APBENR2 = RCC_APBENR2_USART1EN; - - // Enable all GPIO clocks. - RCC->IOPENR = 0x2F; - - // Turn on CRS to make the HSIUSB48 clock more precise when USB is connected. - CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; + __HAL_RCC_USB_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer @@ -105,6 +94,7 @@ void board_init(void) { } #ifdef UART_DEV + UART_CLK_EN(); // UART { GPIO_InitTypeDef gpio_init = { 0 }; diff --git a/hw/bsp/stm32c0/family.cmake b/hw/bsp/stm32c0/family.cmake index ed237838d..c6a90fff6 100644 --- a/hw/bsp/stm32c0/family.cmake +++ b/hw/bsp/stm32c0/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32C0 CACHE INTERNAL "") @@ -102,17 +102,17 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32C0 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32C0) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) family_flash_stlink(${TARGET}) #family_flash_openocd(${TARGET}) diff --git a/hw/bsp/stm32c0/family.mk b/hw/bsp/stm32c0/family.mk index 9ff3a2fdf..bdb34454e 100644 --- a/hw/bsp/stm32c0/family.mk +++ b/hw/bsp/stm32c0/family.mk @@ -1,6 +1,4 @@ ST_FAMILY = c0 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver - ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h index 9af81e63c..82ad309a3 100644 --- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h +++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F070 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f070rb.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.h b/hw/bsp/stm32f0/boards/stm32f072disco/board.h index 1febd01e8..3ca1b3641 100644 --- a/hw/bsp/stm32f0/boards/stm32f072disco/board.h +++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F072 Discovery + url: https://www.st.com/en/evaluation-tools/32f072bdiscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.h b/hw/bsp/stm32f0/boards/stm32f072eval/board.h index 7dcfa3e85..2828000b9 100644 --- a/hw/bsp/stm32f0/boards/stm32f072eval/board.h +++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F072 Eval + url: https://www.st.com/en/evaluation-tools/stm32072b-eval.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c index 3079a1ed3..ea1373e6c 100644 --- a/hw/bsp/stm32f0/family.c +++ b/hw/bsp/stm32f0/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f0xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake index 0af200dd5..12c7b592c 100644 --- a/hw/bsp/stm32f0/family.cmake +++ b/hw/bsp/stm32f0/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F0 CACHE INTERNAL "") @@ -100,16 +100,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F0 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32F0) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk index 431709de0..9b8305874 100644 --- a/hw/bsp/stm32f0/family.mk +++ b/hw/bsp/stm32f0/family.mk @@ -1,7 +1,5 @@ UF2_FAMILY_ID = 0x647824b6 ST_FAMILY = f0 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver - ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h index 2f30a09d4..c8a74337f 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h +++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F103 Bluepill + url: https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h index c8dba4268..d4824686f 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h +++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F103 Mini v2 + url: https://stm32-base.org/boards/STM32F103RCT6-STM32-Mini-V2.0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h index d31102d32..1253c5a48 100644 --- a/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h +++ b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: IAR STM32 F103ze starter kit + url: n/a +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c index 600fc28c0..29785397f 100644 --- a/hw/bsp/stm32f1/family.c +++ b/hw/bsp/stm32f1/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f1xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake index e8cc4db1f..cbb9c3568 100644 --- a/hw/bsp/stm32f1/family.cmake +++ b/hw/bsp/stm32f1/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F1 CACHE INTERNAL "") @@ -99,16 +99,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F1 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32F1) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk index 364616304..ca95f2315 100644 --- a/hw/bsp/stm32f1/family.mk +++ b/hw/bsp/stm32f1/family.mk @@ -1,6 +1,4 @@ ST_FAMILY = f1 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_${ST_FAMILY} hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver - ST_CMSIS = hw/mcu/st/cmsis_device_${ST_FAMILY} ST_HAL_DRIVER = hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h index 3301ede27..8d8c52f60 100644 --- a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h +++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h @@ -1,3 +1,9 @@ + +/* metadata: + name: STM32 F207 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f207zg.html +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk index ba185d199..6e681ef57 100644 --- a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk +++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk @@ -1,12 +1,9 @@ -CFLAGS += \ - -DSTM32F207xx \ +MCU_VARIANT = stm32f207xx +CFLAGS += -DSTM32F207xx # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/STM32F207ZGTx_FLASH.ld -SRC_S += \ - $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f207xx.s - # For flash-jlink target JLINK_DEVICE = stm32f207zg diff --git a/hw/bsp/stm32f2/family.c b/hw/bsp/stm32f2/family.c index 62cca327b..c1333382a 100644 --- a/hw/bsp/stm32f2/family.c +++ b/hw/bsp/stm32f2/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f2xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32f2/family.cmake b/hw/bsp/stm32f2/family.cmake index 538a6cd66..dc6bc2885 100644 --- a/hw/bsp/stm32f2/family.cmake +++ b/hw/bsp/stm32f2/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F2 CACHE INTERNAL "") @@ -99,18 +99,18 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F2 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32F2) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32f2/family.mk b/hw/bsp/stm32f2/family.mk index 7af9a76a0..ef14a9d67 100644 --- a/hw/bsp/stm32f2/family.mk +++ b/hw/bsp/stm32f2/family.mk @@ -1,24 +1,17 @@ ST_FAMILY = f2 - ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver -DEPS_SUBMODULES += \ - lib/CMSIS_5 \ - $(ST_CMSIS) \ - $(ST_HAL_DRIVER) - include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m3 CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_STM32F2 +# mcu driver cause following warnings CFLAGS_GCC += \ -flto \ - -# mcu driver cause following warnings -CFLAGS_GCC += -Wno-error=sign-compare + -Wno-error=sign-compare LDFLAGS_GCC += \ -nostdlib -nostartfiles \ @@ -40,3 +33,10 @@ INC += \ $(TOP)/$(ST_CMSIS)/Include \ $(TOP)/$(ST_HAL_DRIVER)/Inc \ $(TOP)/$(BOARD_PATH) + +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_${MCU_VARIANT}.s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_${MCU_VARIANT}.s + +# Linker +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/board.h b/hw/bsp/stm32f3/boards/stm32f303disco/board.h index 706149b49..c79dea945 100644 --- a/hw/bsp/stm32f3/boards/stm32f303disco/board.h +++ b/hw/bsp/stm32f3/boards/stm32f303disco/board.h @@ -1,3 +1,9 @@ + +/* metadata: + name: STM32 F303 Discovery + url: https://www.st.com/en/evaluation-tools/stm32f3discovery.html +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/board.mk b/hw/bsp/stm32f3/boards/stm32f303disco/board.mk index e387f2d54..6b9a3e283 100644 --- a/hw/bsp/stm32f3/boards/stm32f303disco/board.mk +++ b/hw/bsp/stm32f3/boards/stm32f303disco/board.mk @@ -1,12 +1,10 @@ +MCU_VARIANT = stm32f303xc CFLAGS += \ -DSTM32F303xC \ # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/STM32F303VCTx_FLASH.ld -SRC_S += \ - $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f303xc.s - # For flash-jlink target JLINK_DEVICE = stm32f303vc diff --git a/hw/bsp/stm32f3/family.c b/hw/bsp/stm32f3/family.c index f94dd95cf..84612d416 100644 --- a/hw/bsp/stm32f3/family.c +++ b/hw/bsp/stm32f3/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f3xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32f3/family.cmake b/hw/bsp/stm32f3/family.cmake index dbba1e658..0ba2920d5 100644 --- a/hw/bsp/stm32f3/family.cmake +++ b/hw/bsp/stm32f3/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F3 CACHE INTERNAL "") @@ -97,16 +97,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F3 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32F3) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32f3/family.mk b/hw/bsp/stm32f3/family.mk index 4fe3aa99d..13734583a 100644 --- a/hw/bsp/stm32f3/family.mk +++ b/hw/bsp/stm32f3/family.mk @@ -1,22 +1,17 @@ ST_FAMILY = f3 - ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver -DEPS_SUBMODULES += \ - lib/CMSIS_5 \ - $(ST_CMSIS) \ - $(ST_HAL_DRIVER) - include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m4 CFLAGS += \ - -flto \ -DCFG_TUSB_MCU=OPT_MCU_STM32F3 # mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter +CFLAGS_GCC += \ + -flto \ + -Wno-error=unused-parameter LDFLAGS_GCC += \ -nostdlib -nostartfiles \ @@ -36,3 +31,10 @@ INC += \ $(TOP)/$(ST_CMSIS)/Include \ $(TOP)/$(ST_HAL_DRIVER)/Inc \ $(TOP)/$(BOARD_PATH) + +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_${MCU_VARIANT}.s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_${MCU_VARIANT}.s + +# Linker +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h index 670ce8012..11e976a42 100644 --- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h +++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather STM32F405 + url: https://www.adafruit.com/product/4382 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.h b/hw/bsp/stm32f4/boards/pyboardv11/board.h index 077313518..9583a924b 100644 --- a/hw/bsp/stm32f4/boards/pyboardv11/board.h +++ b/hw/bsp/stm32f4/boards/pyboardv11/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Pyboard v1.1 + url: https://www.adafruit.com/product/2390 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h index ef40089c9..8a3fe8409 100644 --- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h +++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F401 Blackpill + url: https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h index 6879d066b..effbf2be8 100644 --- a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h +++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F407 Blackvet + url: https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk index 2593978ec..c46a78f81 100644 --- a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk +++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk @@ -1,12 +1,12 @@ CFLAGS += -DSTM32F407xx # GCC -GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s -GCC_LD_FILE = $(BOARD_PATH)/STM32F407VETX_FLASH.ld +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s +LD_FILE_GCC = $(BOARD_PATH)/STM32F407VETx_FLASH.ld # IAR -IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f407xx.s -IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f407xx_flash.icf +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f407xx.s +LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f407xx_flash.icf # For flash-jlink target diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.h b/hw/bsp/stm32f4/boards/stm32f407disco/board.h index 380f8e391..19a029768 100644 --- a/hw/bsp/stm32f4/boards/stm32f407disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F407 Discovery + url: https://www.st.com/en/evaluation-tools/stm32f4discovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h index efa618b72..61e5de70d 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F411 Blackpill + url: https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.h b/hw/bsp/stm32f4/boards/stm32f411disco/board.h index d4bad8e40..d7b02e79d 100644 --- a/hw/bsp/stm32f4/boards/stm32f411disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F411 Discovery + url: https://www.st.com/en/evaluation-tools/32f411ediscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.h b/hw/bsp/stm32f4/boards/stm32f412disco/board.h index 74e664418..d5146ae3c 100644 --- a/hw/bsp/stm32f4/boards/stm32f412disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F412 Discovery + url: https://www.st.com/en/evaluation-tools/32f412gdiscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h index 8900a1e6b..f7026ce61 100644 --- a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h +++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F412 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f412zg.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h index aa9de4073..9a348f33f 100644 --- a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h +++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F439 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f439zi.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c index 866a09d6f..3a1507dbf 100644 --- a/hw/bsp/stm32f4/family.c +++ b/hw/bsp/stm32f4/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f4xx_hal.h" #include "bsp/board_api.h" diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake index c0c9fe902..db5736192 100644 --- a/hw/bsp/stm32f4/family.cmake +++ b/hw/bsp/stm32f4/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F4 CACHE INTERNAL "") @@ -125,18 +125,18 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F4 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32F4) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk index 51ff43a60..c3c41dc3f 100644 --- a/hw/bsp/stm32f4/family.mk +++ b/hw/bsp/stm32f4/family.mk @@ -1,6 +1,5 @@ UF2_FAMILY_ID = 0x57755a57 ST_FAMILY = f4 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h index 632fd99ed..06adb79ad 100644 --- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h +++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Stlink-v3 mini + url: https://www.st.com/en/development-tools/stlink-v3mini.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.h b/hw/bsp/stm32f7/boards/stm32f723disco/board.h index d45ceec5c..35102c1f2 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F723 Discovery + url: https://www.st.com/en/evaluation-tools/32f723ediscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.h b/hw/bsp/stm32f7/boards/stm32f746disco/board.h index d8e92931e..2964ebada 100644 --- a/hw/bsp/stm32f7/boards/stm32f746disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F746 Discovery + url: https://www.st.com/en/evaluation-tools/32f746gdiscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h index 55e77fe5f..b039f5543 100644 --- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h +++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F746 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f746zg.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h index 81cb60aeb..b5b3841f1 100644 --- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h +++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F767 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f767zi.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.h b/hw/bsp/stm32f7/boards/stm32f769disco/board.h index 268919b61..8ac520619 100644 --- a/hw/bsp/stm32f7/boards/stm32f769disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F769 Discovery + url: https://www.st.com/en/evaluation-tools/32f769idiscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index 527fbfe5c..5f63834d0 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -26,6 +26,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f7xx_hal.h" #include "bsp/board_api.h" diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index dc134e9c0..1a3365332 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m7-fpsp CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m7-fpsp CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F7 CACHE INTERNAL "") @@ -127,18 +127,18 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F7 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32F7) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk index abeea784c..d3422e03c 100644 --- a/hw/bsp/stm32f7/family.mk +++ b/hw/bsp/stm32f7/family.mk @@ -1,6 +1,5 @@ UF2_FAMILY_ID = 0x53b80f00 ST_FAMILY = f7 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h index 9ebaf73f0..14d309da1 100644 --- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h +++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 G0B1 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c index d1635be12..67b0b3f1c 100644 --- a/hw/bsp/stm32g0/family.c +++ b/hw/bsp/stm32g0/family.c @@ -25,6 +25,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32g0xx_hal.h" #include "bsp/board_api.h" #include "board.h" @@ -39,7 +43,9 @@ void USB_UCPD1_2_IRQHandler(void) { //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ +#ifdef UART_DEV UART_HandleTypeDef UartHandle; +#endif void board_init(void) { HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS @@ -55,8 +61,6 @@ void board_init(void) { __HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE(); - UART_CLK_EN(); - #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -87,6 +91,8 @@ void board_init(void) { HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); #ifdef UART_DEV + UART_CLK_EN(); + // UART GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -163,7 +169,6 @@ int board_uart_write(void const *buf, int len) { #else (void) buf; (void) len; - (void) UartHandle; return 0; #endif } diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake index 0dafa9c0a..4da26f27e 100644 --- a/hw/bsp/stm32g0/family.cmake +++ b/hw/bsp/stm32g0/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32G0 CACHE INTERNAL "") @@ -101,17 +101,17 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32G0 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32G0) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) family_flash_stlink(${TARGET}) #family_flash_openocd(${TARGET}) diff --git a/hw/bsp/stm32g0/family.mk b/hw/bsp/stm32g0/family.mk index 95b8e537d..d735ca92d 100644 --- a/hw/bsp/stm32g0/family.mk +++ b/hw/bsp/stm32g0/family.mk @@ -1,5 +1,4 @@ ST_FAMILY = g0 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h index e61b13170..d569783fc 100644 --- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h +++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 B-G474E-DPOW1 Discovery kit + url: https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h index aa2bf20bb..cfef1c09f 100644 --- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h +++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 G474 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-g474re.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32g4/boards/stm32g491nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g491nucleo/board.h index 7dd4ed9ae..be3d44645 100644 --- a/hw/bsp/stm32g4/boards/stm32g491nucleo/board.h +++ b/hw/bsp/stm32g4/boards/stm32g491nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 G491 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-g491re.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index 2259cb9e2..49ef86db9 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32g4xx_hal.h" #include "stm32g4xx_ll_bus.h" @@ -53,7 +57,9 @@ void UCPD1_IRQHandler(void) { //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ +#ifdef UART_DEV UART_HandleTypeDef UartHandle; +#endif void board_init(void) { HAL_Init(); @@ -67,8 +73,6 @@ void board_init(void) { __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - UART_CLK_EN(); - #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -103,6 +107,8 @@ void board_init(void) { HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); #ifdef UART_DEV + UART_CLK_EN(); + // UART memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct)); GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; @@ -193,7 +199,6 @@ int board_uart_write(void const *buf, int len) { #else (void) buf; (void) len; - (void) UartHandle; return 0; #endif } diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake index 4217e4be6..5ec9926fe 100644 --- a/hw/bsp/stm32g4/family.cmake +++ b/hw/bsp/stm32g4/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32G4 CACHE INTERNAL "") @@ -97,17 +97,17 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32G4 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32G4) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake index f0fb1d809..1a44c3f1d 100644 --- a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake +++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake @@ -4,5 +4,6 @@ set(JLINK_DEVICE stm32h503rb) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32H503xx + HSE_VALUE=24000000 ) endfunction() diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h index da20cfa3a..c8b5e31f5 100644 --- a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h +++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H503 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-h503rb.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk index cf60098af..0292353ae 100644 --- a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk +++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk @@ -1,7 +1,8 @@ MCU_VARIANT = stm32h503xx CFLAGS += \ - -DSTM32H503xx + -DSTM32H503xx \ + -DHSE_VALUE=24000000 \ # For flash-jlink target JLINK_DEVICE = stm32h503rb diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake index 694ea41cd..0077bf235 100644 --- a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake +++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake @@ -4,5 +4,6 @@ set(JLINK_DEVICE stm32h563zi) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32H563xx + HSE_VALUE=8000000 ) endfunction() diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h index 8e849f5c8..adc3d751a 100644 --- a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h +++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H563 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-h563zi.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -67,9 +72,8 @@ static inline void SystemClock_Config(void) { /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 4; @@ -88,8 +92,8 @@ static inline void SystemClock_Config(void) { /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 - |RCC_CLOCKTYPE_PCLK3; + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; @@ -101,25 +105,27 @@ static inline void SystemClock_Config(void) { Error_Handler(); } - // Configure CRS clock source - __HAL_RCC_CRS_CLK_ENABLE(); - RCC_CRSInitTypeDef RCC_CRSInitStruct = {0}; - RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; - RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; - RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING; - RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000); - RCC_CRSInitStruct.ErrorLimitValue = 34; - RCC_CRSInitStruct.HSI48CalibrationValue = 32; - HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); - - /* Select HSI48 as USB clock source */ - RCC_PeriphCLKInitTypeDef usb_clk = {0 }; - usb_clk.PeriphClockSelection = RCC_PERIPHCLK_USB; - usb_clk.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - HAL_RCCEx_PeriphCLKConfig(&usb_clk); + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); - /* Peripheral clock enable */ - __HAL_RCC_USB_CLK_ENABLE(); + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; + PeriphClkInitStruct.PLL3.PLL3M = 1; + PeriphClkInitStruct.PLL3.PLL3N = 18; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 3; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0; + PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } } #ifdef __cplusplus diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk index 091d1e5e3..a7ccbdf39 100644 --- a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk +++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk @@ -1,7 +1,8 @@ MCU_VARIANT = stm32h563xx CFLAGS += \ - -DSTM32H563xx + -DSTM32H563xx \ + -DHSE_VALUE=8000000 \ # For flash-jlink target JLINK_DEVICE = stm32h563zi diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/cubemx/stm32h563nucleo.ioc b/hw/bsp/stm32h5/boards/stm32h563nucleo/cubemx/stm32h563nucleo.ioc index 3c83d136d..b9b9605c1 100644 --- a/hw/bsp/stm32h5/boards/stm32h563nucleo/cubemx/stm32h563nucleo.ioc +++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/cubemx/stm32h563nucleo.ioc @@ -2,6 +2,7 @@ BOOTPATH.BootPathName=LEGACY BOOTPATH.IPParameters=BootPathName BOOTPATH.UserSelectedBootPath=LEGACY +BSP_IP_NAME=NUCLEO-H563ZI CAD.formats= CAD.pinconfig= CAD.provider= @@ -16,6 +17,7 @@ Mcu.ContextProject=TrustZoneDisabled Mcu.Family=STM32H5 Mcu.IP0=BOOTPATH Mcu.IP1=CORTEX_M33_NS +Mcu.IP10=NUCLEO-H563ZI Mcu.IP2=DEBUG Mcu.IP3=ICACHE Mcu.IP4=MEMORYMAP @@ -24,7 +26,7 @@ Mcu.IP6=PWR Mcu.IP7=RCC Mcu.IP8=SYS Mcu.IP9=USB -Mcu.IPNb=10 +Mcu.IPNb=11 Mcu.Name=STM32H563ZITx Mcu.Package=LQFP144 Mcu.Pin0=PE2 @@ -74,8 +76,8 @@ Mcu.PinsNb=43 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32H563ZITx -MxCube.Version=6.10.0 -MxDb.Version=DB.6.0.100 +MxCube.Version=6.12.1 +MxDb.Version=DB.6.0.121 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.EXTI13_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true @@ -267,7 +269,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32H563ZITx -ProjectManager.FirmwarePackage=STM32Cube FW_H5 V1.1.1 +ProjectManager.FirmwarePackage=STM32Cube FW_H5 V1.3.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 @@ -317,7 +319,7 @@ RCC.I2C2Freq_Value=250000000 RCC.I2C3Freq_Value=250000000 RCC.I2C4Freq_Value=250000000 RCC.I3C1Freq_Value=250000000 -RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CECFreq_Value,CKPERFreq_Value,CRSFreq_Value,CSI_VALUE,CortexFreq_Value,DACFreq_Value,EPOD_VALUE,ETHFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSIDiv,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPTIM6Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSIRC_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,OCTOSPIMFreq_Value,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5Freq_Value,SPI6Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART12Freq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,UCPD1outputFreq_Value,USART10Freq_Value,USART11Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CECFreq_Value,CKPERFreq_Value,CRSFreq_Value,CSI_VALUE,CortexFreq_Value,DACFreq_Value,EPOD_VALUE,ETHFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSIDiv,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPTIM6Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSIRC_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,OCTOSPIMFreq_Value,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL2Source,PLL3FRACN,PLL3N,PLL3PoutputFreq_Value,PLL3Q,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLL3Source,PLLFRACN,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5Freq_Value,SPI6Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART12Freq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,UCPD1outputFreq_Value,USART10Freq_Value,USART11Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBCLockSelection,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value RCC.LPTIM1Freq_Value=250000000 RCC.LPTIM2Freq_Value=250000000 RCC.LPTIM3Freq_Value=250000000 @@ -330,12 +332,18 @@ RCC.LSIRC_VALUE=32000 RCC.MCO1PinFreq_Value=64000000 RCC.MCO2PinFreq_Value=250000000 RCC.OCTOSPIMFreq_Value=250000000 -RCC.PLL2PoutputFreq_Value=258000000 -RCC.PLL2QoutputFreq_Value=258000000 -RCC.PLL2RoutputFreq_Value=258000000 -RCC.PLL3PoutputFreq_Value=258000000 -RCC.PLL3QoutputFreq_Value=258000000 -RCC.PLL3RoutputFreq_Value=258000000 +RCC.PLL2PoutputFreq_Value=516000000 +RCC.PLL2QoutputFreq_Value=516000000 +RCC.PLL2RoutputFreq_Value=516000000 +RCC.PLL2Source=RCC_PLL2_SOURCE_HSE +RCC.PLL3FRACN=0 +RCC.PLL3N=18 +RCC.PLL3PoutputFreq_Value=72000000 +RCC.PLL3Q=3 +RCC.PLL3QoutputFreq_Value=48000000 +RCC.PLL3RoutputFreq_Value=72000000 +RCC.PLL3Source=RCC_PLL3_SOURCE_HSE +RCC.PLLFRACN=0 RCC.PLLM=4 RCC.PLLN=250 RCC.PLLPoutputFreq_Value=250000000 @@ -343,8 +351,8 @@ RCC.PLLQoutputFreq_Value=250000000 RCC.PLLSourceVirtual=RCC_PLL1_SOURCE_HSE RCC.PWRFreq_Value=250000000 RCC.RNGFreq_Value=48000000 -RCC.SAI1Freq_Value=258000000 -RCC.SAI2Freq_Value=258000000 +RCC.SAI1Freq_Value=516000000 +RCC.SAI2Freq_Value=516000000 RCC.SDMMC1Freq_Value=250000000 RCC.SDMMC2Freq_Value=250000000 RCC.SPI1Freq_Value=250000000 @@ -368,13 +376,14 @@ RCC.USART1Freq_Value=250000000 RCC.USART2Freq_Value=250000000 RCC.USART3Freq_Value=250000000 RCC.USART6Freq_Value=250000000 +RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3Q RCC.USBFreq_Value=48000000 -RCC.VCOInput2Freq_Value=4000000 -RCC.VCOInput3Freq_Value=4000000 +RCC.VCOInput2Freq_Value=8000000 +RCC.VCOInput3Freq_Value=8000000 RCC.VCOInputFreq_Value=2000000 RCC.VCOOutputFreq_Value=500000000 -RCC.VCOPLL2OutputFreq_Value=516000000 -RCC.VCOPLL3OutputFreq_Value=516000000 +RCC.VCOPLL2OutputFreq_Value=1032000000 +RCC.VCOPLL3OutputFreq_Value=144000000 SH.ADCx_INP18.0=ADC1_INP18 SH.ADCx_INP18.ConfNb=1 SH.GPXTI13.0=GPIO_EXTI13 diff --git a/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h index 7baef6ca6..d75114397 100644 --- a/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h +++ b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H573i Discovery + url: https://www.st.com/en/evaluation-tools/stm32h573i-dk.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h5/family.c b/hw/bsp/stm32h5/family.c index 02500db4e..26ba34ac3 100644 --- a/hw/bsp/stm32h5/family.c +++ b/hw/bsp/stm32h5/family.c @@ -25,6 +25,9 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ // Suppress warning caused by mcu driver #ifdef __GNUC__ @@ -55,7 +58,9 @@ void USB_DRD_FS_IRQHandler(void) { //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ +#ifdef UART_DEV UART_HandleTypeDef UartHandle; +#endif void board_init(void) { HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS @@ -79,8 +84,6 @@ void board_init(void) { __HAL_RCC_GPIOI_CLK_ENABLE(); #endif - UART_CLK_EN(); - #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -111,6 +114,8 @@ void board_init(void) { HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); #ifdef UART_DEV + UART_CLK_EN(); + // UART GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -189,7 +194,6 @@ int board_uart_write(void const* buf, int len) { #else (void) buf; (void) len; - (void) UartHandle; return 0; #endif } diff --git a/hw/bsp/stm32h5/family.cmake b/hw/bsp/stm32h5/family.cmake index 94900f416..1df6bcb90 100644 --- a/hw/bsp/stm32h5/family.cmake +++ b/hw/bsp/stm32h5/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32H5 CACHE INTERNAL "") @@ -101,17 +101,17 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32H5 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32H5) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.h b/hw/bsp/stm32h7/boards/daisyseed/board.h index 2d681d640..300ecb8b2 100644 --- a/hw/bsp/stm32h7/boards/daisyseed/board.h +++ b/hw/bsp/stm32h7/boards/daisyseed/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Daisy Seed + url: https://electro-smith.com/products/daisy-seed +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h index c5257901d..f623149bd 100644 --- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h +++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H723 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-h723zg.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h index fa9721be3..7c3f6414a 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H743 Eval + url: https://www.st.com/en/evaluation-tools/stm32h743i-eval.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ @@ -179,7 +184,7 @@ static MFXSTM32L152_Object_t mfx_obj = { 0 }; static MFXSTM32L152_IO_Mode_t* mfx_io = NULL; static uint32_t mfx_vbus_pin[2] = { MFXSTM32L152_GPIO_PIN_7, MFXSTM32L152_GPIO_PIN_9 }; -int32_t board_i2c_init(void) { +static int32_t board_i2c_init(void) { __HAL_RCC_I2C1_CLK_ENABLE(); __HAL_RCC_I2C1_FORCE_RESET(); __HAL_RCC_I2C1_RELEASE_RESET(); @@ -195,16 +200,16 @@ int32_t board_i2c_init(void) { return 0; } -int32_t board_i2c_deinit(void) { +static int32_t board_i2c_deinit(void) { return 0; } -int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { +static int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { TU_ASSERT (HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); return 0; } -int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { +static int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); return 0; } @@ -244,7 +249,7 @@ static inline void board_init2(void) { } // VBUS1 is actually controlled by USB3320C PHY (using dwc2 drivebus signal) -void board_vbus_set(uint8_t rhport, bool state) { +static void TU_ATTR_UNUSED board_vbus_set(uint8_t rhport, bool state) { if (mfx_io) { mfx_io->IO_WritePin(&mfx_obj, mfx_vbus_pin[rhport], state); } diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h index 0606f395a..0277d05c7 100644 --- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H743 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-h743zi.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.h b/hw/bsp/stm32h7/boards/stm32h745disco/board.h index b9d9cdea4..ebdd5a17a 100644 --- a/hw/bsp/stm32h7/boards/stm32h745disco/board.h +++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H745 Discovery + url: https://www.st.com/en/evaluation-tools/stm32h745i-disco.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.h b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h index f1c363082..e11a55103 100644 --- a/hw/bsp/stm32h7/boards/stm32h750_weact/board.h +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H750 WeAct + url: https://www.adafruit.com/product/5032 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.h b/hw/bsp/stm32h7/boards/stm32h750bdk/board.h index 2895f0973..ac417601b 100644 --- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.h +++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H750b Discovery Kit + url: https://www.st.com/en/evaluation-tools/stm32h750b-dk.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h index 625c6a137..bfaf42784 100644 --- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h +++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h @@ -26,6 +26,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Waveshare Open H743i + url: https://www.waveshare.com/openh743i-c-standard.htm +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index 0be18350c..f8723b0c7 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -27,6 +27,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32h7xx_hal.h" #include "bsp/board_api.h" @@ -76,7 +80,7 @@ void OTG_HS_IRQHandler(void) { } #ifdef TRACE_ETM -void trace_etm_init(void) { +static void trace_etm_init(void) { // H7 trace pin is PE2 to PE6 GPIO_InitTypeDef gpio_init; gpio_init.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6; @@ -90,7 +94,7 @@ void trace_etm_init(void) { DBGMCU->CR |= DBGMCU_CR_DBG_TRACECKEN | DBGMCU_CR_DBG_CKD1EN | DBGMCU_CR_DBG_CKD3EN; } #else - #define trace_etm_init() +#define trace_etm_init() #endif void board_init(void) { diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index 3e246faed..b4f0bebbf 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -12,7 +12,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m7 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32H7 CACHE INTERNAL "") @@ -132,18 +132,18 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32H7 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32H7) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk index 29b83cf7d..19a085424 100644 --- a/hw/bsp/stm32h7/family.mk +++ b/hw/bsp/stm32h7/family.mk @@ -45,11 +45,9 @@ CFLAGS += \ -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \ # GCC Flags -CFLAGS_GCC += \ - -flto \ - # suppress warning caused by vendor mcu driver CFLAGS_GCC += \ + -flto \ -Wno-error=cast-align \ -Wno-error=unused-parameter \ diff --git a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h7rs/FreeRTOSConfig/FreeRTOSConfig.h index e5a76af85..9fd3f6c50 100644 --- a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/stm32h7rs/FreeRTOSConfig/FreeRTOSConfig.h @@ -44,7 +44,7 @@ // skip if included from IAR assembler #ifndef __IASMARM__ - #include "mxc_device.h" + #include "stm32h7rsxx.h" #endif /* Cortex M23/M33 port configuration. */ @@ -59,7 +59,7 @@ #define configTICK_RATE_HZ ( 1000 ) #define configMAX_PRIORITIES ( 5 ) #define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 ) #define configMAX_TASK_NAME_LEN 16 #define configUSE_16_BIT_TICKS 0 #define configIDLE_SHOULD_YIELD 1 @@ -127,7 +127,7 @@ //--------------------------------------------------------------------+ // For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header -#define configPRIO_BITS __NVIC_PRIO_BITS +#define configPRIO_BITS 4 /* The lowest interrupt priority that can be used in a call to a "set priority" function. */ #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1) diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake new file mode 100644 index 000000000..f52b70408 --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake @@ -0,0 +1,19 @@ +set(MCU_VARIANT stm32h7s3xx) +set(JLINK_DEVICE stm32h7s3xx) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.ld) +set(LD_FILE_Clang ${LD_FILE_GNU}) +set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.icf) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + STM32H7S3xx + ) + target_sources(${TARGET} PUBLIC + ${ST_TCPP0203}/tcpp0203.c + ${ST_TCPP0203}/tcpp0203_reg.c + ) + target_include_directories(${TARGET} PUBLIC + ${ST_TCPP0203} + ) +endfunction() diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h new file mode 100644 index 000000000..dfa77a8fb --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h @@ -0,0 +1,262 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: STM32 H7S3L8 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-h7s3l8.html +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "tcpp0203.h" +#include "stm32h7rsxx_ll_exti.h" +#include "stm32h7rsxx_ll_system.h" + +#define UART_DEV USART3 +#define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE + +// VBUS Sense detection +#define OTG_FS_VBUS_SENSE 1 +#define OTG_HS_VBUS_SENSE 0 + +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_TCPP0203_EN 4 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // VBUS input pin used for TCPP0203 EN + .port = GPIOM, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0 }, + .active_state = 0 + }, + { // I2C SCL for TCPP0203 + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = GPIO_AF4_I2C3 }, + }, + { // I2C SDA for TCPP0203 + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = GPIO_AF4_I2C3 }, + }, + { // INT for TCPP0203 + .port = GPIOM, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0 }, + }, +}; + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ +static inline void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE0) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL1.PLLM = 12; + RCC_OscInitStruct.PLL1.PLLN = 300; + RCC_OscInitStruct.PLL1.PLLP = 1; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLR = 2; + RCC_OscInitStruct.PLL1.PLLS = 2; + RCC_OscInitStruct.PLL1.PLLT = 2; + RCC_OscInitStruct.PLL1.PLLFractional = 0; + RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL2.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL2.PLLM = 12; + RCC_OscInitStruct.PLL2.PLLN = 200; + RCC_OscInitStruct.PLL2.PLLP = 2; + RCC_OscInitStruct.PLL2.PLLQ = 2; + RCC_OscInitStruct.PLL2.PLLR = 2; + RCC_OscInitStruct.PLL2.PLLS = 2; + RCC_OscInitStruct.PLL2.PLLT = 2; + RCC_OscInitStruct.PLL2.PLLFractional = 0; + RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_PCLK4|RCC_CLOCKTYPE_PCLK5; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + Error_Handler(); + } + + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHYC; + PeriphClkInit.UsbPhycClockSelection = RCC_USBPHYCCLKSOURCE_HSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + __HAL_RCC_SBS_CLK_ENABLE(); +} + +//--------------------------------------------------------------------+ +// USB PD +//--------------------------------------------------------------------+ +static I2C_HandleTypeDef i2c_handle = { + .Instance = I2C3, + .Init = { + .Timing = 0x20C0EDFF, + .OwnAddress1 = 0, + .AddressingMode = I2C_ADDRESSINGMODE_7BIT, + .DualAddressMode = I2C_DUALADDRESS_DISABLE, + .OwnAddress2 = 0, + .OwnAddress2Masks = I2C_OA2_NOMASK, + .GeneralCallMode = I2C_GENERALCALL_DISABLE, + .NoStretchMode = I2C_NOSTRETCH_DISABLE, + } +}; +static TCPP0203_Object_t tcpp0203_obj = { 0 }; + +int32_t board_tcpp0203_init(void) { + board_pindef_t* pindef = &board_pindef[PINID_TCPP0203_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, GPIO_PIN_SET); + + __HAL_RCC_I2C3_CLK_ENABLE(); + __HAL_RCC_I2C3_FORCE_RESET(); + __HAL_RCC_I2C3_RELEASE_RESET(); + if (HAL_I2C_Init(&i2c_handle) != HAL_OK) { + return HAL_ERROR; + } + + NVIC_SetPriority(EXTI8_IRQn, 12); + NVIC_EnableIRQ(EXTI8_IRQn); + + return 0; +} + +int32_t board_tcpp0203_deinit(void) { + return 0; +} + +int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT (HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); + return 0; +} + +int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); + return 0; +} + +static inline void board_init2(void) { + TCPP0203_IO_t io_ctx; + + io_ctx.Address = TCPP0203_I2C_ADDRESS_X68; + io_ctx.Init = board_tcpp0203_init; + io_ctx.DeInit = board_tcpp0203_deinit; + io_ctx.ReadReg = i2c_readreg; + io_ctx.WriteReg = i2c_writereg; + + TU_ASSERT(TCPP0203_RegisterBusIO(&tcpp0203_obj, &io_ctx) == TCPP0203_OK, ); + + TU_ASSERT(TCPP0203_Init(&tcpp0203_obj) == TCPP0203_OK, ); + + TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, ); +} + +void board_vbus_set(uint8_t rhport, bool state) { + (void) state; + if (rhport == 1) { + TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, ); + } +} + +void EXTI8_IRQHandler(void) { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_8); + if (tcpp0203_obj.IsInitialized) { + TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, ); + TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, ); + } +} + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk new file mode 100644 index 000000000..cf0c2ff54 --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk @@ -0,0 +1,19 @@ +MCU_VARIANT = stm32h7s3xx +CFLAGS += -DSTM32H7S3xx + +# For flash-jlink target +JLINK_DEVICE = stm32h7s3xx + +# flash target using on-board stlink +flash: flash-stlink + +# Linker +LD_FILE_GCC = $(BOARD_PATH)/stm32h7s3xx_flash.ld +LD_FILE_IAR = $(BOARD_PATH)/stm32h7s3xx_flash.icf + +SRC_C += \ + $(ST_TCPP0203)/tcpp0203.c \ + $(ST_TCPP0203)/tcpp0203_reg.c \ + +INC += \ + $(TOP)/$(ST_TCPP0203) \ diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.icf b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.icf new file mode 100644 index 000000000..8ffaa74a7 --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.icf @@ -0,0 +1,55 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol NONCACHEABLEBUFFER_size = 0x4000; +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.ld b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.ld new file mode 100644 index 000000000..3bd7f0b89 --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.ld @@ -0,0 +1,208 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H7S3xx Device from STM32H7RS series +** 64Kbytes FLASH +** 456Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +__FLASH_BEGIN = 0x08000000; +__FLASH_SIZE = 0x00010000; + +__RAM_BEGIN = 0x24000000; +__RAM_SIZE = 0x4FC00; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x4000; + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000 + + FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE +} + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } > RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32h7rs/family.c b/hw/bsp/stm32h7rs/family.c new file mode 100644 index 000000000..4b81deea0 --- /dev/null +++ b/hw/bsp/stm32h7rs/family.c @@ -0,0 +1,340 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 + * William D. Jones ([email protected]), + * Ha Thach (tinyusb.org) + * Uwe Bonnes ([email protected] + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + manufacturer: STMicroelectronics +*/ + +#include "stm32h7rsxx_hal.h" +#include "bsp/board_api.h" + +TU_ATTR_UNUSED static void Error_Handler(void) { } + +typedef struct { + GPIO_TypeDef* port; + GPIO_InitTypeDef pin_init; + uint8_t active_state; +} board_pindef_t; + +#include "board.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +#ifdef UART_DEV +UART_HandleTypeDef UartHandle = { + .Instance = UART_DEV, + .Init = { + .BaudRate = CFG_BOARD_UART_BAUDRATE, + .WordLength = UART_WORDLENGTH_8B, + .StopBits = UART_STOPBITS_1, + .Parity = UART_PARITY_NONE, + .HwFlowCtl = UART_HWCONTROL_NONE, + .Mode = UART_MODE_TX_RX, + .OverSampling = UART_OVERSAMPLING_16, + } +}; +#endif + +#ifndef SWO_FREQ +#define SWO_FREQ 4000000 +#endif + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ + +// Despite being call USB2_OTG_FS on some MCUs +// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port +void OTG_FS_IRQHandler(void) { + tusb_int_handler(0, true); +} + +// Despite being call USB1_OTG_HS on some MCUs +// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port +void OTG_HS_IRQHandler(void) { + tusb_int_handler(1, true); +} + +#ifdef TRACE_ETM +void trace_etm_init(void) { + // H7 trace pin is PE2 to PE6 + GPIO_InitTypeDef gpio_init; + gpio_init.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6; + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + gpio_init.Alternate = GPIO_AF0_TRACE; + HAL_GPIO_Init(GPIOE, &gpio_init); + + // Enable trace clk, also in D1 and D3 domain + DBGMCU->CR |= DBGMCU_CR_DBG_TRACECKEN | DBGMCU_CR_DBG_CKD1EN | DBGMCU_CR_DBG_CKD3EN; +} +#else + #define trace_etm_init() +#endif + +#ifdef LOGGER_SWO +void log_swo_init(void) +{ + //UNLOCK FUNNEL + *(volatile uint32_t*)(0x5C004FB0) = 0xC5ACCE55; // SWTF_LAR + *(volatile uint32_t*)(0x5C003FB0) = 0xC5ACCE55; // SWO_LAR + + //SWO current output divisor register + //To change it, you can use the following rule + // value = (CPU_Freq / 3 / SWO_Freq) - 1 + *(volatile uint32_t*)(0x5C003010) = ((SystemCoreClock / 3 / SWO_FREQ) - 1); // SWO_CODR + + //SWO selected pin protocol register + *(volatile uint32_t*)(0x5C0030F0) = 0x00000002; // SWO_SPPR + + //Enable ITM input of SWO trace funnel + *(volatile uint32_t*)(0x5C004000) |= 0x00000001; // SWFT_CTRL +} +#else + #define log_swo_init() +#endif + +void board_init(void) { + HAL_Init(); + + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + // Implemented in board.h + SystemClock_Config(); + + // Enable All GPIOs clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOM_CLK_ENABLE(); + __HAL_RCC_GPION_CLK_ENABLE(); + __HAL_RCC_GPIOO_CLK_ENABLE(); + __HAL_RCC_GPIOP_CLK_ENABLE(); + + log_swo_init(); + trace_etm_init(); + + for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) { + HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init); + } + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); + +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + #ifdef USB_OTG_FS_PERIPH_BASE + NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + #endif + + NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + + +#ifdef UART_DEV + UART_CLK_EN(); + HAL_UART_Init(&UartHandle); +#endif + + //------------- USB FS -------------// +#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0) + // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port + + HAL_PWREx_EnableUSBVoltageDetector(); + HAL_PWREx_EnableUSBReg(); + + __HAL_RCC_USB2_OTG_FS_CLK_ENABLE(); + + // PM14 VUSB, PM10 ID, PM11 DM, PM12 DP + // Configure DM DP Pins + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOM, &GPIO_InitStruct); + + // This for ID line debug + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOM, &GPIO_InitStruct); + +#if OTG_FS_VBUS_SENSE + // Configure VBUS Pin + GPIO_InitStruct.Pin = GPIO_PIN_14; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOM, &GPIO_InitStruct); + + // Enable VBUS sense (B device) via pin PM14 + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; +#else + // Disable VBUS sense (B device) + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + // B-peripheral session valid override enable + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; +#endif // vbus sense +#endif + + //------------- USB HS -------------// +#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1) + + // Enable USB HS & ULPI Clocks + __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); + __HAL_RCC_USBPHYC_CLK_ENABLE(); + + // Enable USB power + HAL_PWREx_EnableUSBVoltageDetector(); + HAL_PWREx_EnableUSBHSregulator(); + +#if OTG_HS_VBUS_SENSE + // Configure VBUS Pin + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS; + HAL_GPIO_Init(GPIOM, &GPIO_InitStruct); + + // Enable VBUS sense (B device) via pin PM9 + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN; +#else + // Disable VBUS sense (B device) + USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + +#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1 + // B-peripheral session valid override enable + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN; + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL; +#else + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN; +#endif + +#endif +#endif + + board_init2(); + +#if CFG_TUH_ENABLED + board_vbus_set(BOARD_TUH_RHPORT, 1); +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { +#ifdef PINID_LED + board_pindef_t* pindef = &board_pindef[PINID_LED]; + GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state); +#else + (void) state; +#endif +} + +uint32_t board_button_read(void) { +#ifdef PINID_BUTTON + board_pindef_t* pindef = &board_pindef[PINID_BUTTON]; + return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin); +#else + return 0; +#endif +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE; + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = stm32_uuid[0]; + id32[1] = stm32_uuid[1]; + id32[2] = stm32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) { +#ifdef UART_DEV + HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t) + buf, len, 0xffff); + return len; +#else + (void) buf; (void) len; + return -1; +#endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + HAL_IncTick(); + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} + +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/stm32h7rs/family.cmake b/hw/bsp/stm32h7rs/family.cmake new file mode 100644 index 000000000..e5e98f914 --- /dev/null +++ b/hw/bsp/stm32h7rs/family.cmake @@ -0,0 +1,150 @@ +include_guard() + +set(ST_FAMILY h7rs) +set(ST_PREFIX stm32${ST_FAMILY}xx) + +set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) +set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) +set(ST_TCPP0203 ${TOP}/hw/mcu/st/stm32-tcpp0203) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m7 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS STM32H7RS CACHE INTERNAL "") + +# ---------------------- +# Port & Speed Selection +# ---------------------- +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 1) +endif () + +if (NOT DEFINED RHPORT_SPEED) + set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) +endif () +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () + +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif() + + # Startup & Linker script + set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) + + if(NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld) + endif() + set(LD_FILE_Clang ${LD_FILE_GNU}) + if(NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) + endif() + + add_library(${BOARD_TARGET} STATIC + ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${ST_CMSIS}/Include + ${ST_HAL_DRIVER}/Inc + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + SEGGER_RTT_SECTION="noncacheable_buffer" + BUFFER_SIZE_UP=0x3000 + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_STM32H7RS ${RTOS}) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_stlink(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/stm32h7rs/family.mk b/hw/bsp/stm32h7rs/family.mk new file mode 100644 index 000000000..9970059f8 --- /dev/null +++ b/hw/bsp/stm32h7rs/family.mk @@ -0,0 +1,95 @@ +ST_FAMILY = h7rs +ST_PREFIX = stm32${ST_FAMILY}xx +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver +ST_TCPP0203 = hw/mcu/st/stm32-tcpp0203 + +UF2_FAMILY_ID = 0x6db66083 + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m7 + +# ---------------------- +# Port & Speed Selection +# ---------------------- +RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 1 + +# Determine RHPORT_DEVICE_SPEED if not defined +ifndef RHPORT_DEVICE_SPEED +ifeq ($(RHPORT_DEVICE), 0) + RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# Determine RHPORT_HOST_SPEED if not defined +ifndef RHPORT_HOST_SPEED +ifeq ($(RHPORT_HOST), 0) + RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# -------------- +# Compiler Flags +# -------------- +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32H7RS \ + -DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \ + -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \ + -DBOARD_TUH_RHPORT=${RHPORT_HOST} \ + -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \ + -DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \ + -DBUFFER_SIZE_UP=0x3000 \ + +# GCC Flags +CFLAGS_GCC += \ + -flto \ + +# suppress warning caused by vendor mcu driver +CFLAGS_GCC += \ + -Wno-error=cast-align \ + -Wno-error=unused-parameter \ + +LDFLAGS_GCC += \ + -nostdlib -nostartfiles \ + --specs=nosys.specs --specs=nano.specs + +# ----------------- +# Sources & Include +# ----------------- + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_dma.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_i2c.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart_ex.c \ + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc + +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s + +# Linker +LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(MCU_VARIANT)_flash.ld +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf diff --git a/hw/bsp/stm32h7rs/stm32h7rsxx_hal_conf.h b/hw/bsp/stm32h7rs/stm32h7rsxx_hal_conf.h new file mode 100644 index 000000000..6fd90abde --- /dev/null +++ b/hw/bsp/stm32h7rs/stm32h7rsxx_hal_conf.h @@ -0,0 +1,500 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32h7rsxx_hal_conf.h. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CONF_H +#define STM32H7RSxx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CORDIC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DCMIPP_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_GFXMMU_MODULE_ENABLED */ +/* #define HAL_GFXTIM_MODULE_ENABLED */ +/* #define HAL_GPU2D_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_I3C_MODULE_ENABLED */ +/* #define HAL_ICACHE_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_MCE_MODULE_ENABLED */ +/* #define HAL_MDF_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_PKA_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_RAMECC_MODULE_ENABLED */ +/* #define HAL_RCC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_XSPI_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up (in ms) */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low-power oscillator (CSI) default value. + * This value is the default CSI range value after Reset. + */ +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB OTG FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ + #if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB OTG FS/RNG in Hz. + The real value my vary depending on manufacturing process variations. */ + #endif /* HSI48_VALUE */ + +/** +* @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz. + Value of the Internal Low Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* LSI_VALUE */ + +/** +* @brief External Low Speed oscillator (LSE) value. +*/ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up (in ms) */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for digital audio interfaces: SPI/I2S, SAI and ADF + * This value is used by the RCC HAL module to provide the digital audio interfaces + * frequency. This clock source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000UL /*!< Value of the external clock source in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL)/*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** +* @brief Uncomment the line below to expanse the "assert_param" macro in the +* HAL drivers code +*/ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** +* @brief Set below the peripheral configuration to "1U" to add the support +* of HAL callback registration/unregistration feature for the HAL +* driver(s). This allows user application to provide specific callback +* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting +* the default weak callback functions (see each stm32h7rsxx_hal_ppp.h file +* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef +* for each PPP peripheral). +*/ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 0U + +/* ################## HASH peripheral configuration ########################## */ + +#define USE_HAL_HASH_SUSPEND_RESUME 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h7rsxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h7rsxx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h7rsxx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h7rsxx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h7rsxx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h7rsxx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32h7rsxx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h7rsxx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h7rsxx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED + #include "stm32h7rsxx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32h7rsxx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7rsxx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32h7rsxx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h7rsxx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h7rsxx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h7rsxx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7rsxx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED + #include "stm32h7rsxx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h7rsxx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h7rsxx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h7rsxx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h7rsxx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED + #include "stm32h7rsxx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED + #include "stm32h7rsxx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h7rsxx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h7rsxx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32h7rsxx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32h7rsxx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED + #include "stm32h7rsxx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED + #include "stm32h7rsxx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h7rsxx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h7rsxx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h7rsxx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h7rsxx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED + #include "stm32h7rsxx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7rsxx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h7rsxx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + #include "stm32h7rsxx_hal_ramecc.h" +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h7rsxx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h7rsxx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32h7rsxx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h7rsxx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32h7rsxx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h7rsxx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h7rsxx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32h7rsxx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h7rsxx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h7rsxx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h7rsxx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h7rsxx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h7rsxx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED + #include "stm32h7rsxx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_CONF_H */ diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h index ee83bbcbc..50bbafadb 100644 --- a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h +++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L052 DAP + url: n/a +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk b/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk index 0b1348474..e63b41f12 100644 --- a/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk +++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk @@ -1,10 +1,9 @@ +MCU_VARIANT = stm32l052xx CFLAGS += \ -DSTM32L052xx LD_FILE = $(BOARD_PATH)/STM32L052K8Ux_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l052xx.s - # For flash-jlink target JLINK_DEVICE = stm32l052k8 diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.h b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h index 5cda1c15a..29402f00a 100644 --- a/hw/bsp/stm32l0/boards/stm32l0538disco/board.h +++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L0538 Discovery + url: https://www.st.com/en/evaluation-tools/32l0538discovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk b/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk index deed519ba..f3e6978b0 100644 --- a/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk +++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk @@ -1,12 +1,10 @@ +MCU_VARIANT = stm32l053xx CFLAGS += \ -DSTM32L053xx # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/STM32L053C8Tx_FLASH.ld -SRC_S += \ - $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l053xx.s - # For flash-jlink target JLINK_DEVICE = STM32L053R8 diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c index c8c88d687..b28903e00 100644 --- a/hw/bsp/stm32l0/family.c +++ b/hw/bsp/stm32l0/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32l0xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32l0/family.cmake b/hw/bsp/stm32l0/family.cmake index c04927585..954bdb158 100644 --- a/hw/bsp/stm32l0/family.cmake +++ b/hw/bsp/stm32l0/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32L0 CACHE INTERNAL "") @@ -101,16 +101,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32L0 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32L0) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32l0/family.mk b/hw/bsp/stm32l0/family.mk index fe7561fc2..921b1b413 100644 --- a/hw/bsp/stm32l0/family.mk +++ b/hw/bsp/stm32l0/family.mk @@ -1,9 +1,4 @@ ST_FAMILY = l0 -DEPS_SUBMODULES += \ - lib/CMSIS_5 \ - hw/mcu/st/cmsis_device_$(ST_FAMILY) \ - hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver - ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver @@ -11,20 +6,17 @@ include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m0plus CFLAGS += \ - -flto \ -DCFG_EXAMPLE_MSC_READONLY \ -DCFG_EXAMPLE_VIDEO_READONLY \ -DCFG_TUSB_MCU=OPT_MCU_STM32L0 # mcu driver cause following warnings CFLAGS_GCC += \ + -flto \ -Wno-error=unused-parameter \ -Wno-error=redundant-decls \ -Wno-error=cast-align \ - -ifeq ($(TOOLCHAIN),gcc) -CFLAGS_GCC += -Wno-error=maybe-uninitialized -endif + -Wno-error=maybe-uninitialized \ CFLAGS_CLANG += \ -Wno-error=parentheses-equality @@ -48,3 +40,10 @@ INC += \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(ST_CMSIS)/Include \ $(TOP)/$(ST_HAL_DRIVER)/Inc + +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_${MCU_VARIANT}.s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_${MCU_VARIANT}.s + +# Linker +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h index 72d17b760..980e1e321 100644 --- a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h +++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L412 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-l412kb.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.h b/hw/bsp/stm32l4/boards/stm32l476disco/board.h index 9d4351b39..8c766d8ea 100644 --- a/hw/bsp/stm32l4/boards/stm32l476disco/board.h +++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L476 Disco + url: https://www.st.com/en/evaluation-tools/32l476gdiscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h index 47ada6bb9..f522e7522 100644 --- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h +++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L4P5 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h index 47ada6bb9..c181f5d4a 100644 --- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h +++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L4R5 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c index 965c4810a..2b555b5c2 100644 --- a/hw/bsp/stm32l4/family.c +++ b/hw/bsp/stm32l4/family.c @@ -26,6 +26,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32l4xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake index 77876cb8b..eebcff4f3 100644 --- a/hw/bsp/stm32l4/family.cmake +++ b/hw/bsp/stm32l4/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32L4 CACHE INTERNAL "") @@ -101,19 +101,19 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS} ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS}) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk index 950b6f9cb..01d059236 100644 --- a/hw/bsp/stm32l4/family.mk +++ b/hw/bsp/stm32l4/family.mk @@ -1,5 +1,4 @@ ST_FAMILY = l4 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver diff --git a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h index e5a76af85..a1b83c802 100644 --- a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h @@ -44,10 +44,11 @@ // skip if included from IAR assembler #ifndef __IASMARM__ - #include "mxc_device.h" + #include "stm32n6xx.h" #endif -/* Cortex M23/M33 port configuration. */ +/* Cortex M55 port configuration. */ +#define configENABLE_MVE 0 #define configENABLE_MPU 0 #define configENABLE_FPU 1 #define configENABLE_TRUSTZONE 0 @@ -59,7 +60,7 @@ #define configTICK_RATE_HZ ( 1000 ) #define configMAX_PRIORITIES ( 5 ) #define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 ) #define configMAX_TASK_NAME_LEN 16 #define configUSE_16_BIT_TICKS 0 #define configIDLE_SHOULD_YIELD 1 @@ -127,7 +128,7 @@ //--------------------------------------------------------------------+ // For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header -#define configPRIO_BITS __NVIC_PRIO_BITS +#define configPRIO_BITS 4 /* The lowest interrupt priority that can be used in a call to a "set priority" function. */ #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1) diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/STM32N657XX_AXISRAM2_fsbl.ld b/hw/bsp/stm32n6/boards/stm32n657nucleo/STM32N657XX_AXISRAM2_fsbl.ld new file mode 100644 index 000000000..e4c792cd8 --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/STM32N657XX_AXISRAM2_fsbl.ld @@ -0,0 +1,203 @@ +/* +****************************************************************************** +** +** @file : STM32N657XX_AXISRAM2_fsbl.ld +** +** @author : GPM Application Team +** +** @brief : Linker script for STM32N657XX Device from STM32N6 series +** 512 KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x800; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + ROM (xrw) : ORIGIN = 0x34180400, LENGTH = 255K + RAM (xrw) : ORIGIN = 0x341C0000, LENGTH = 256K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> ROM + + .noncacheable : + { + . = ALIGN(8); + __snoncacheable = .;/* create symbol for start of section */ + KEEP(*(.noncacheable)) + . = ALIGN(8); + __enoncacheable = .; /* create symbol for end of section */ + } > RAM + + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >ROM + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake new file mode 100644 index 000000000..e88efefb9 --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake @@ -0,0 +1,17 @@ +set(MCU_VARIANT stm32n657xx) +set(JLINK_DEVICE stm32n6xx) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + STM32N657xx + ) + target_sources(${TARGET} PUBLIC + ${ST_TCPP0203}/tcpp0203.c + ${ST_TCPP0203}/tcpp0203_reg.c + ) + target_include_directories(${TARGET} PUBLIC + ${ST_TCPP0203} + ) +endfunction() diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h new file mode 100644 index 000000000..963ecad61 --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h @@ -0,0 +1,283 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: STM32 N657X0-Q Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stm32n657xx.h" +#include "stm32n6xx_ll_exti.h" +#include "stm32n6xx_ll_system.h" +#include "tcpp0203.h" + +#define UART_DEV USART1 +#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE + +#define BOARD_TUD_RHPORT 1 + +// VBUS Sense detection +#define OTG_FS_VBUS_SENSE 1 +#define OTG_HS_VBUS_SENSE 1 + +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_TCPP0203_EN 4 + +static board_pindef_t board_pindef[] = { + {// LED + .port = GPIOG, + .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + .active_state = 1}, + {// Button + .port = GPIOC, + .pin_init = {.Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + .active_state = 1}, + {// UART TX + .port = GPIOE, + .pin_init = {.Pin = GPIO_PIN_5, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1}, + .active_state = 0}, + {// UART RX + .port = GPIOE, + .pin_init = {.Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1}, + .active_state = 0}, + {// VBUS input pin used for TCPP0203 EN + .port = GPIOA, + .pin_init = {.Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + .active_state = 0}, + { + // I2C SCL for TCPP0203 + .port = GPIOB, + .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2}, + }, + { + // I2C SDA for TCPP0203 + .port = GPIOB, + .pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2}, + }, + { + // INT for TCPP0203 + .port = GPIOD, + .pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + }, +}; + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ +void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + /* Configure the power domain */ + if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY) != HAL_OK) { + Error_Handler(); + } + + /* Get current CPU/System buses clocks configuration */ + /* and if necessary switch to intermediate HSI clock */ + /* to ensure target clock can be set */ + HAL_RCC_GetClockConfig(&RCC_ClkInitStruct); + if ((RCC_ClkInitStruct.CPUCLKSource == RCC_CPUCLKSOURCE_IC1) || + (RCC_ClkInitStruct.SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11)) { + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK); + RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) { + Error_Handler(); + } + } + + /* HSE selected as source (stable clock on Level 0 samples */ + /* PLL1 output = ((HSE/PLLM)*PLLN)/PLLP1/PLLP2 */ + /* = ((48000000/3)*75)/1/1 */ + /* = (16000000*75)/1/1 */ + /* = 1200000000 (1200 MHz) */ + /* PLL2 off */ + /* PLL3 off */ + /* PLL4 off */ + + /* Enable HSE && HSI */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* 48 MHz */ + + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL1.PLLM = 3; + RCC_OscInitStruct.PLL1.PLLN = 75; /* PLL1 VCO = 48/3 * 75 = 1200MHz */ + RCC_OscInitStruct.PLL1.PLLP1 = 1; /* PLL output = PLL VCO frequency / (PLLP1 * PLLP2) */ + RCC_OscInitStruct.PLL1.PLLP2 = 1; /* PLL output = 1200 MHz */ + RCC_OscInitStruct.PLL1.PLLFractional = 0; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + /* Initialization error */ + Error_Handler(); + } + + /* Select PLL1 outputs as CPU and System bus clock source */ + /* CPUCLK = ic1_ck = PLL1 output/ic1_divider = 600 MHz */ + /* SYSCLK = ic2_ck = PLL1 output/ic2_divider = 400 MHz */ + /* Configure the HCLK clock divider */ + /* HCLK = PLL1 SYSCLK/HCLK divider = 200 MHz */ + /* PCLKx = HCLK / PCLKx divider = 200 MHz */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK4 | RCC_CLOCKTYPE_PCLK5); + RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1; + RCC_ClkInitStruct.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC1Selection.ClockDivider = 2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11; + RCC_ClkInitStruct.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC2Selection.ClockDivider = 3; + RCC_ClkInitStruct.IC6Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC6Selection.ClockDivider = 3; + RCC_ClkInitStruct.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC11Selection.ClockDivider = 3; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; + RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) { + /* Initialization Error */ + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1; + PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + /* Initialization Error */ + Error_Handler(); + } + + /** Set USB OTG HS PHY1 Reference Clock Source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBPHY1; + PeriphClkInitStruct.UsbPhy1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + /* Initialization Error */ + Error_Handler(); + } +} + +//--------------------------------------------------------------------+ +// USB PD +//--------------------------------------------------------------------+ +static I2C_HandleTypeDef i2c_handle = { + .Instance = I2C2, + .Init = { + .Timing = 0x20C0EDFF, + .OwnAddress1 = 0, + .AddressingMode = I2C_ADDRESSINGMODE_7BIT, + .DualAddressMode = I2C_DUALADDRESS_DISABLE, + .OwnAddress2 = 0, + .OwnAddress2Masks = I2C_OA2_NOMASK, + .GeneralCallMode = I2C_GENERALCALL_DISABLE, + .NoStretchMode = I2C_NOSTRETCH_DISABLE, + }}; +static TCPP0203_Object_t tcpp0203_obj = {0}; + +int32_t board_tcpp0203_init(void) { + board_pindef_t *pindef = &board_pindef[PINID_TCPP0203_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, GPIO_PIN_SET); + + __HAL_RCC_I2C2_CLK_ENABLE(); + __HAL_RCC_I2C2_FORCE_RESET(); + __HAL_RCC_I2C2_RELEASE_RESET(); + if (HAL_I2C_Init(&i2c_handle) != HAL_OK) { + return HAL_ERROR; + } + + NVIC_SetPriority(EXTI8_IRQn, 12); + NVIC_EnableIRQ(EXTI8_IRQn); + + return 0; +} + +int32_t board_tcpp0203_deinit(void) { + return 0; +} + +int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT(HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); + return 0; +} + +int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); + return 0; +} + +static inline void board_init2(void) { + TCPP0203_IO_t io_ctx; + + io_ctx.Address = TCPP0203_I2C_ADDRESS_X68; + io_ctx.Init = board_tcpp0203_init; + io_ctx.DeInit = board_tcpp0203_deinit; + io_ctx.ReadReg = i2c_readreg; + io_ctx.WriteReg = i2c_writereg; + + TU_ASSERT(TCPP0203_RegisterBusIO(&tcpp0203_obj, &io_ctx) == TCPP0203_OK, ); + + TU_ASSERT(TCPP0203_Init(&tcpp0203_obj) == TCPP0203_OK, ); + + TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, ); +} + +void board_vbus_set(uint8_t rhport, bool state) { + (void) state; + if (rhport == 1) { + TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, ); + } +} + +void EXTI8_IRQHandler(void) { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_8); + if (tcpp0203_obj.IsInitialized) { + TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, ); + TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, ); + } +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk new file mode 100644 index 000000000..05717699c --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk @@ -0,0 +1,17 @@ +MCU_VARIANT = stm32n657xx +CFLAGS += -DSTM32N657xx +JLINK_DEVICE = stm32n6xx + +LD_FILE_GCC = $(BOARD_PATH)/STM32N657XX_AXISRAM2_fsbl.ld + +# flash target using on-board stlink +flash: flash-stlink + +PORT = 1 + +SRC_C += \ + $(ST_TCPP0203)/tcpp0203.c \ + $(ST_TCPP0203)/tcpp0203_reg.c \ + +INC += \ + $(TOP)/$(ST_TCPP0203) \ diff --git a/hw/bsp/stm32n6/family.c b/hw/bsp/stm32n6/family.c new file mode 100644 index 000000000..1d0616d8e --- /dev/null +++ b/hw/bsp/stm32n6/family.c @@ -0,0 +1,280 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 + * William D. Jones ([email protected]), + * Ha Thach (tinyusb.org) + * Uwe Bonnes ([email protected] + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + manufacturer: STMicroelectronics +*/ + +// Suppress warning caused by mcu driver +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wcast-align" +#endif + +#include "stm32n6xx_hal.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "bsp/board_api.h" + +TU_ATTR_UNUSED static void Error_Handler(void) { } + +void HardFault_Handler(void); + +typedef struct { + GPIO_TypeDef* port; + GPIO_InitTypeDef pin_init; + uint8_t active_state; +} board_pindef_t; + +#include "board.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +#ifdef UART_DEV +UART_HandleTypeDef UartHandle = { + .Instance = UART_DEV, + .Init = { + .BaudRate = CFG_BOARD_UART_BAUDRATE, + .WordLength = UART_WORDLENGTH_8B, + .StopBits = UART_STOPBITS_1, + .Parity = UART_PARITY_NONE, + .HwFlowCtl = UART_HWCONTROL_NONE, + .Mode = UART_MODE_TX_RX, + .OverSampling = UART_OVERSAMPLING_16, + } +}; +#endif + +#ifndef SWO_FREQ +#define SWO_FREQ 4000000 +#endif + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ + +// Despite being call USB2_OTG_FS on some MCUs +// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port +void USB2_OTG_HS_IRQHandler(void) { + tusb_int_handler(0, true); +} + +// Despite being call USB1_OTG_HS on some MCUs +// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port +void USB1_OTG_HS_IRQHandler(void) { + tusb_int_handler(1, true); +} + +void board_init(void) { + + /* Enable BusFault and SecureFault handlers (HardFault is default) */ + SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk); + + HAL_PWREx_EnableVddA(); + HAL_PWREx_EnableVddIO2(); + HAL_PWREx_EnableVddIO3(); + HAL_PWREx_EnableVddIO4(); + HAL_PWREx_EnableVddIO5(); + + HAL_Init(); + + // Implemented in board.h + SystemClock_Config(); + + // Enable All GPIOs clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPION_CLK_ENABLE(); + __HAL_RCC_GPIOO_CLK_ENABLE(); + __HAL_RCC_GPIOP_CLK_ENABLE(); + __HAL_RCC_GPIOQ_CLK_ENABLE(); + + // HAL_ICACHE_Enable(); + + for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) { + HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init); + } + + NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0)); + NVIC_EnableIRQ(UCPD1_IRQn); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); + +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + + NVIC_SetPriority(USB1_OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + + +#ifdef UART_DEV + UART_CLK_EN(); + HAL_UART_Init(&UartHandle); +#endif + + + __HAL_RCC_USB1_OTG_HS_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWREx_EnableVddUSBVMEN(); + while(__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY)); + HAL_PWREx_EnableVddUSB(); + + LL_AHB5_GRP1_ForceReset(0x00800000); + __HAL_RCC_USB1_OTG_HS_FORCE_RESET(); + __HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET(); + + LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock(); + LL_AHB5_GRP1_ReleaseReset(0x00800000); + + /* Peripheral clock enable */ + __HAL_RCC_USB1_OTG_HS_CLK_ENABLE(); + + /* Required few clock cycles before accessing USB PHY Controller Registers */ + for (volatile uint32_t i = 0; i < 10; i++) { + __NOP(); // No Operation instruction to create a delay + } + + USB1_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4); + + USB1_HS_PHYC->USBPHYC_CR |= (0x1 << 16) | + (0x2 << 4) | + (0x1 << 2) | + 0x1U; + + __HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET(); + + /* Required few clock cycles before Releasing Reset */ + for (volatile uint32_t i = 0; i < 10; i++) { + __NOP(); // No Operation instruction to create a delay + } + + __HAL_RCC_USB1_OTG_HS_RELEASE_RESET(); + + /* Peripheral PHY clock enable */ + __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE(); + + board_init2(); + +#if CFG_TUH_ENABLED + board_vbus_set(BOARD_TUH_RHPORT, 1); +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { +#ifdef PINID_LED + board_pindef_t* pindef = &board_pindef[PINID_LED]; + GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state); +#else + (void) state; +#endif +} + +uint32_t board_button_read(void) { +#ifdef PINID_BUTTON + board_pindef_t* pindef = &board_pindef[PINID_BUTTON]; + return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin); +#else + return 0; +#endif +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE; + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = stm32_uuid[0]; + id32[1] = stm32_uuid[1]; + id32[2] = stm32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) { +#ifdef UART_DEV + HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t) + buf, len, 0xffff); + return len; +#else + (void) buf; (void) len; + return -1; +#endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + HAL_IncTick(); + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} + +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/stm32n6/family.cmake b/hw/bsp/stm32n6/family.cmake new file mode 100644 index 000000000..76763937e --- /dev/null +++ b/hw/bsp/stm32n6/family.cmake @@ -0,0 +1,148 @@ +include_guard() + +set(ST_FAMILY n6) +set(ST_PREFIX stm32${ST_FAMILY}xx) + +set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) +set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) +set(ST_TCPP0203 ${TOP}/hw/mcu/st/stm32-tcpp0203) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m55 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS STM32N6 CACHE INTERNAL "") + +# ---------------------- +# Port & Speed Selection +# ---------------------- +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 1) +endif () + +# N6 are all high speed +if (NOT DEFINED RHPORT_DEVICE_SPEED) + set(RHPORT_DEVICE_SPEED OPT_MODE_HIGH_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + set(RHPORT_HOST_SPEED OPT_MODE_HIGH_SPEED) +endif () + +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif() + + # Startup & Linker script + set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) + + if(NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld) + endif() + set(LD_FILE_Clang ${LD_FILE_GNU}) + if(NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) + endif() + + add_library(${BOARD_TARGET} STATIC + ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}_fsbl.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${ST_CMSIS}/Include + ${ST_HAL_DRIVER}/Inc + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + SEGGER_RTT_SECTION="noncacheable_buffer" + BUFFER_SIZE_UP=0x3000 + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_STM32N6 ${RTOS}) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_stlink(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/stm32n6/family.mk b/hw/bsp/stm32n6/family.mk new file mode 100644 index 000000000..37087ed42 --- /dev/null +++ b/hw/bsp/stm32n6/family.mk @@ -0,0 +1,89 @@ +ST_FAMILY = n6 +ST_PREFIX = stm32${ST_FAMILY}xx +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver +ST_TCPP0203 = hw/mcu/st/stm32-tcpp0203 + +UF2_FAMILY_ID = 0x6db66083 + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m55 + +# ---------------------- +# Port & Speed Selection +# ---------------------- +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 1 + +ifndef RHPORT_DEVICE_SPEED + RHPORT_DEVICE_SPEED = OPT_MODE_HIGH_SPEED +endif + +ifndef RHPORT_HOST_SPEED + RHPORT_HOST_SPEED = OPT_MODE_HIGH_SPEED +endif + +# -------------- +# Compiler Flags +# -------------- +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32N6 \ + -DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \ + -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \ + -DBOARD_TUH_RHPORT=${RHPORT_HOST} \ + -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \ + -DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \ + -DBUFFER_SIZE_UP=0x3000 \ + +# GCC Flags +CFLAGS_GCC += \ + -flto \ + +# suppress warning caused by vendor mcu driver +CFLAGS_GCC += \ + -Wno-error=cast-align \ + -Wno-error=unused-parameter \ + +LDFLAGS_GCC += \ + -nostdlib -nostartfiles \ + --specs=nosys.specs --specs=nano.specs + +# ----------------- +# Sources & Include +# ----------------- + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}_fsbl.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_dma.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_hcd.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_i2c.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rif.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_ll_usb.c \ + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc + +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT)_fsbl.s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s + +# Linker +LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(MCU_VARIANT)_flash.ld +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf diff --git a/hw/bsp/stm32n6/partition_stm32n657xx.h b/hw/bsp/stm32n6/partition_stm32n657xx.h new file mode 100644 index 000000000..4efdc5668 --- /dev/null +++ b/hw/bsp/stm32n6/partition_stm32n657xx.h @@ -0,0 +1,792 @@ +/** + ****************************************************************************** + * @file partition_stm32n657xx.h + * @author MCD Application Team + * @brief CMSIS STM32N657xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_STM32N657XX_H +#define PARTITION_STM32N657XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// <e>Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 0 + +/* +// <q> Enable SAU +// <i> Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// <o> When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// <i> Value for SAU->CTRL register bit ALLNS +// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// </e> +*/ + +/* +// <h>Initialize Security Attribution Unit (SAU) Address Regions +// <i>SAU configuration specifies regions to be one of: +// <i> - Secure and Non-Secure Callable +// <i> - Non-Secure +// <i>Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// <e>Initialize SAU Region 0 +// <i> Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// <o>Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// <o>End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */ + +/* +// <o>Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// </e> +*/ + +/* +// <e>Initialize SAU Region 1 +// <i> Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// <o>Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */ + +/* +// <o>End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */ + +/* +// <o>Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// </e> +*/ + +/* +// <e>Initialize SAU Region 2 +// <i> Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// <o>Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */ + +/* +// <o>End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */ + +/* +// <o>Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// </e> +*/ + +/* +// <e>Initialize SAU Region 3 +// <i> Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// <o>Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */ + +/* +// <o>End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */ + +/* +// <o>Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// </e> +*/ + +/* +// <e>Initialize SAU Region 4 +// <i> Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// <o>Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// <o>End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// <o>Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// </e> +*/ + +/* +// <e>Initialize SAU Region 5 +// <i> Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// <o>Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// <o>End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// <o>Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// </e> +*/ + +/* +// <e>Initialize SAU Region 6 +// <i> Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// <o>Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// <o>End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// <o>Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// </e> +*/ + +/* +// <e>Initialize SAU Region 7 +// <i> Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// <o>Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// <o>End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// <o>Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// </e> +*/ + +/* +// </h> +*/ + +/* +// <e>Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// <o> Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// <i> Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// <o>System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// <i> Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// <o>Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// <i> Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// <o>BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// <i> Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// </e> +*/ + +/* +// <e>Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// <o>Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// <i> Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// <o>Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// <i> Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// <o>Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// <i> Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// <o>Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// <i> Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// </e> +*/ + +/* +// <h>Setup Interrupt Target +*/ + +/* +// <e>Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// <o.0> PVD_IRQn <0=> Secure state <1=> Non-Secure state +// <o.1> Reserved <0=> Secure state <1=> Non-Secure state +// <o.2> DTS_IRQn <0=> Secure state <1=> Non-Secure state +// <o.3> RCC_IRQn <0=> Secure state <1=> Non-Secure state +// <o.4> LOCKUP_IRQn <0=> Secure state <1=> Non-Secure state +// <o.5> CACHE_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// <o.6> TCM_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// <o.7> BKP_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// <o.8> FPU_IRQn <0=> Secure state <1=> Non-Secure state +// <o.9> Reserved <0=> Secure state <1=> Non-Secure state +// <o.10> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// <o.11> TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// <o.12> RIFSC_TAMPER_IRQn <0=> Secure state <1=> Non-Secure state +// <o.13> IAC_IRQn <0=> Secure state <1=> Non-Secure state +// <o.14> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// <o.15> Reserved <0=> Secure state <1=> Non-Secure state +// <o.16> RTC_IRQn <0=> Secure state <1=> Non-Secure state +// <o.17> Reserved <0=> Secure state <1=> Non-Secure state +// <o.18> IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// <o.19> WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// <o.20> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// <o.21> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.22> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.23> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// <o.24> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// <o.25> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// <o.26> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// <o.27> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// <o.28> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// <o.29> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// <o.30> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// <o.31> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// </e> +*/ + +/* +// <e>Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// <o.0> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// <o.1> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// <o.2> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// <o.3> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// <o.4> SAES_IRQn <0=> Secure state <1=> Non-Secure state +// <o.5> CRYP_IRQn <0=> Secure state <1=> Non-Secure state +// <o.6> PKA_IRQn <0=> Secure state <1=> Non-Secure state +// <o.7> HASH_IRQn <0=> Secure state <1=> Non-Secure state +// <o.8> RNG_IRQn <0=> Secure state <1=> Non-Secure state +// <o.9> Reserved <0=> Secure state <1=> Non-Secure state +// <o.10> MCE1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.11> MCE2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.12> MCE3_IRQn <0=> Secure state <1=> Non-Secure state +// <o.13> MCE4_IRQn <0=> Secure state <1=> Non-Secure state +// <o.14> ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.15> CSI_IRQn <0=> Secure state <1=> Non-Secure state +// <o.16> DCMIPP_IRQn <0=> Secure state <1=> Non-Secure state +// <o.17> Reserved <0=> Secure state <1=> Non-Secure state +// <o.18> Reserved <0=> Secure state <1=> Non-Secure state +// <o.19> Reserved <0=> Secure state <1=> Non-Secure state +// <o.20> PAHB_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// <o.21> NPU0_IRQn <0=> Secure state <1=> Non-Secure state +// <o.22> NPU1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.23> NPU2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.24> NPU3_IRQn <0=> Secure state <1=> Non-Secure state +// <o.25> CACHEAXI_IRQn <0=> Secure state <1=> Non-Secure state +// <o.26> LTDC_LO_IRQn <0=> Secure state <1=> Non-Secure state +// <o.27> LTDC_LO_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// <o.28> DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// <o.29> JPEG_IRQn <0=> Secure state <1=> Non-Secure state +// <o.30> VENC_IRQn <0=> Secure state <1=> Non-Secure state +// <o.31> GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// </e> +*/ + +/* +// <e>Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// <o.0> GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state +// <o.1> GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// <o.2> GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// <o.3> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// <o.4> HPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// <o.5> HPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.6> HPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.7> HPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// <o.8> HPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// <o.9> HPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// <o.10> HPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// <o.11> HPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// <o.12> HPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// <o.13> HPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// <o.14> HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// <o.15> HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// <o.16> HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// <o.17> HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// <o.18> HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// <o.19> HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// <o.20> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// <o.21> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.22> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.23> GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// <o.24> GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// <o.25> GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// <o.26> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// <o.27> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// <o.28> GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// <o.29> GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// <o.30> GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// <o.31> GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// </e> +*/ + +/* +// <e>Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// <o.0> GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// <o.1> GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// <o.2> GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// <o.3> GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// <o.4> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// <o.5> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// <o.6> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// <o.7> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// <o.8> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// <o.9> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// <o.10> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// <o.11> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// <o.12> I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// <o.13> I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// <o.14> I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// <o.15> I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// <o.16> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// <o.17> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// <o.18> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// <o.19> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// <o.20> TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.21> TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// <o.22> TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// <o.23> TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// <o.24> TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// <o.25> TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// <o.26> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// <o.27> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// <o.28> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// <o.29> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// <o.30> TIM9_IRQn <0=> Secure state <1=> Non-Secure state +// <o.31> TIM10_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// </e> +*/ + +/* +// <e>Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..159 +// <o.0> TIM11_IRQn <0=> Secure state <1=> Non-Secure state +// <o.1> TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// <o.2> TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// <o.3> TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// <o.4> TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// <o.5> TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// <o.6> TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// <o.7> TIM18_IRQn <0=> Secure state <1=> Non-Secure state +// <o.8> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.9> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.10> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// <o.11> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// <o.12> LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// <o.13> ADF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// <o.14> MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// <o.15> MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.16> MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.17> MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// <o.18> MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// <o.19> MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// <o.20> SAI1_A_IRQn <0=> Secure state <1=> Non-Secure state +// <o.21> SAI1_B_IRQn <0=> Secure state <1=> Non-Secure state +// <o.22> SAI2_A_IRQn <0=> Secure state <1=> Non-Secure state +// <o.23> SAI2_B_IRQn <0=> Secure state <1=> Non-Secure state +// <o.24> SPDIFRX1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.25> SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.26> SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.27> SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// <o.28> SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// <o.29> SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// <o.30> SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// <o.31> USART1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// </e> +*/ + +/* +// <e>Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 1 + +/* +// Interrupts 160..191 +// <o.0> USART2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.1> USART3_IRQn <0=> Secure state <1=> Non-Secure state +// <o.2> UART4_IRQn <0=> Secure state <1=> Non-Secure state +// <o.3> UART5_IRQn <0=> Secure state <1=> Non-Secure state +// <o.4> USART6_IRQn <0=> Secure state <1=> Non-Secure state +// <o.5> UART7_IRQn <0=> Secure state <1=> Non-Secure state +// <o.6> UART8_IRQn <0=> Secure state <1=> Non-Secure state +// <o.7> UART9_IRQn <0=> Secure state <1=> Non-Secure state +// <o.8> USART10_IRQn <0=> Secure state <1=> Non-Secure state +// <o.9> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.10> XSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.11> XSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.12> XSPI3_IRQn <0=> Secure state <1=> Non-Secure state +// <o.13> FMC_IRQn <0=> Secure state <1=> Non-Secure state +// <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.15> SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// <o.16> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.17> USB1_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// <o.18> USB2_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// <o.19> ETH1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.20> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// <o.21> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.22> FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// <o.23> FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.24> FDCAN3_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// <o.25> FDCAN3_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// <o.26> FDCAN_CU_IRQn <0=> Secure state <1=> Non-Secure state +// <o.27> MDIOS_IRQn <0=> Secure state <1=> Non-Secure state +// <o.28> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// <o.29> WAKEUP_PIN_IRQn <0=> Secure state <1=> Non-Secure state +// <o.30> CTI_INT0_IRQn <0=> Secure state <1=> Non-Secure state +// <o.31> CTI_INT1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// </e> +*/ + +/* +// <e>Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 1 + +/* +// Interrupts 192..223 +// <o.0> Reserved <0=> Secure state <1=> Non-Secure state +// <o.1> LTDC_UP_IRQn <0=> Secure state <1=> Non-Secure state +// <o.2> LTDC_UP_ERR_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// </e> +*/ + +/* +// </h> +*/ + + + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + +} + +#endif /* PARTITION_STM32N657XX_H */ diff --git a/hw/bsp/stm32n6/stm32n6xx_hal_conf.h b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h new file mode 100644 index 000000000..00cb31159 --- /dev/null +++ b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h @@ -0,0 +1,504 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32n6xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_CONF_H +#define STM32N6xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_BSEC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DCMIPP_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DTS_MODULE_ENABLED */ +/*#define HAL_ETH_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_GFXTIM_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_I3C_MODULE_ENABLED */ +/*#define HAL_ICACHE_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_JPEG_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_MCE_MODULE_ENABLED */ +/*#define HAL_MDF_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ +/*#define HAL_RAMCFG_MODULE_ENABLED */ +/*#define HAL_RIF_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SDIO_MODULE_ENABLED */ +/*#define HAL_SDRAM_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED*/ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPDIFRX_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_XSPI_MODULE_ENABLED */ +/*#define HAL_CACHEAXI_MODULE_ENABLED */ +/*#define HAL_MDIOS_MODULE_ENABLED */ +/*#define HAL_GPU2D_MODULE_ENABLED */ +/*#define HAL_CACHEAXI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 48000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) +#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz */ +/* The real value may vary depending on the variations in voltage and temperature.*/ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32n6xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CACHEAXI_REGISTER_CALLBACKS 0U /* CACHEAXI register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U /* DCMIPP register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_GFXTIM_REGISTER_CALLBACKS 0U /* GFXTIM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MCE_REGISTER_CALLBACKS 0U /* MCE register callback disabled */ +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U /* PSSI register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* ################## SDIO peripheral configuration ########################## */ +#define USE_SDIO_TRANSCEIVER 1U +#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32n6xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_RIF_MODULE_ENABLED +#include "stm32n6xx_hal_rif.h" +#endif /* HAL_RIF_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32n6xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CACHEAXI_MODULE_ENABLED +#include "stm32n6xx_hal_cacheaxi.h" +#endif /* HAL_CACHEAXI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32n6xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32n6xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_BSEC_MODULE_ENABLED +#include "stm32n6xx_hal_bsec.h" +#endif /* HAL_BSEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32n6xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32n6xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED +#include "stm32n6xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED +#include "stm32n6xx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED +#include "stm32n6xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED +#include "stm32n6xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32n6xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32n6xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32n6xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED +#include "stm32n6xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED +#include "stm32n6xx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED +#include "stm32n6xx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32n6xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32n6xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32n6xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32n6xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED +#include "stm32n6xx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32n6xx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32n6xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32n6xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED +#include "stm32n6xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32n6xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32n6xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED +#include "stm32n6xx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED +#include "stm32n6xx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED +#include "stm32n6xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32n6xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32n6xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32n6xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32n6xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED +#include "stm32n6xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32n6xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32n6xx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32n6xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32n6xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32n6xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32n6xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32n6xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32n6xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32n6xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED +#include "stm32n6xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32n6xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32n6xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32n6xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32n6xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32n6xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32n6xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macros -----------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_CONF_H */ diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h index 2f1c451db..cf3f63ea5 100644 --- a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h +++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 B-U585i IOT2A Discovery kit + url: https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk index ae63afef3..0a2c47030 100644 --- a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk +++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk @@ -1,11 +1,9 @@ +MCU_VARIANT = stm32u585xx CFLAGS += \ -DSTM32U585xx \ # All source paths should be relative to the top level. LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s - -MCU_VARIANT = stm32u585xx # For flash-jlink target JLINK_DEVICE = stm32u585zi diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h index 7f3bf462c..0c3439b2c 100644 --- a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h +++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 U545 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-u545re-q.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk index 072c595fb..0aba57ce4 100644 --- a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk +++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk @@ -1,11 +1,9 @@ +MCU_VARIANT = stm32u545xx CFLAGS += \ -DSTM32U545xx \ # All source paths should be relative to the top level. LD_FILE = ${FAMILY_PATH}/linker/STM32U545xx_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u545xx.s - -MCU_VARIANT = stm32u545xx # For flash-jlink target JLINK_DEVICE = stm32u545re diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.h b/hw/bsp/stm32u5/boards/stm32u575eval/board.h index bd91502af..b11f6a747 100644 --- a/hw/bsp/stm32u5/boards/stm32u575eval/board.h +++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 U575 Eval + url: https://www.st.com/en/evaluation-tools/stm32u575i-ev.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk index fee56f2ba..4bc9fea10 100644 --- a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk +++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk @@ -1,11 +1,9 @@ +MCU_VARIANT = stm32u575xx CFLAGS += \ -DSTM32U575xx \ # All source paths should be relative to the top level. LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s - -MCU_VARIANT = stm32u575xx # For flash-jlink target JLINK_DEVICE = stm32u575ai diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h index 6d244d418..be037b68a 100644 --- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h +++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 U575 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk index c83ec3999..d09dc5c46 100644 --- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk +++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk @@ -1,11 +1,9 @@ +MCU_VARIANT = stm32u575xx CFLAGS += \ -DSTM32U575xx \ # All source paths should be relative to the top level. LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s - -MCU_VARIANT = stm32u575xx # For flash-jlink target JLINK_DEVICE = stm32u575zi diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h index 062fb807f..0785fb36b 100644 --- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 U5a5 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk index 4bebe3330..c9fdbac1a 100644 --- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk @@ -1,3 +1,4 @@ +MCU_VARIANT = stm32u5a5xx CFLAGS += \ -DSTM32U5A5xx \ -DHSE_VALUE=16000000UL \ @@ -5,8 +6,5 @@ CFLAGS += \ # All source paths should be relative to the top level. LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u5a5xx.s - -MCU_VARIANT = stm32u5a5xx # For flash-jlink target JLINK_DEVICE = stm32u575zi diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c index 3cc7cc511..032c01f34 100644 --- a/hw/bsp/stm32u5/family.c +++ b/hw/bsp/stm32u5/family.c @@ -25,6 +25,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + // Suppress warning caused by mcu driver #ifdef __GNUC__ #pragma GCC diagnostic push diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake index 3ab7cdf8b..7a5935961 100644 --- a/hw/bsp/stm32u5/family.cmake +++ b/hw/bsp/stm32u5/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32U5 CACHE INTERNAL "") @@ -101,20 +101,20 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32U5 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_STM32U5) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c #${TOP}/src/portable/st/typec/typec_stm32.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk index 05fe4608a..3694b1ca0 100644 --- a/hw/bsp/stm32u5/family.mk +++ b/hw/bsp/stm32u5/family.mk @@ -1,5 +1,4 @@ ST_FAMILY = u5 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver @@ -57,5 +56,12 @@ INC += \ $(TOP)/$(ST_HAL_DRIVER)/Inc \ $(TOP)/$(BOARD_PATH) +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s + +# Linker +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf + # flash target using on-board stlink flash: flash-stlink diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h index ea975df03..704592506 100644 --- a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h +++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 P-NUCLEO-WB55 + url: https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld index 916f11866..c16235586 100644 --- a/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld +++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld @@ -3,21 +3,26 @@ ** ** File : stm32wb55xx_flash_cm4.ld ** -** Abstract : System Workbench Minimal System calls file +** Author : STM32CubeIDE ** -** For more information about which c-functions -** need which of these lowlevel functions -** please consult the Newlib libc-manual +** Abstract : Linker script for STM32WB55xx Device +** 1024Kbytes FLASH +** 128Kbytes RAM ** -** Environment : System Workbench for MCU +** Set heap size, stack size and stack location according +** to application requirements. ** -** Distribution: The file is distributed “as is,” without any warranty +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty ** of any kind. ** ***************************************************************************** ** @attention ** -** Copyright (c) 2019 STMicroelectronics. +** Copyright (c) 2019-2022 STMicroelectronics. ** All rights reserved. ** ** This software is licensed under terms that can be found in the LICENSE file @@ -33,7 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = 0x20030000; /* end of RAM */ /* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Heap_Size = 0x400; /* required amount of heap */ _Min_Stack_Size = 0x1000; /* required amount of stack */ /* Specify the memory areas */ @@ -81,14 +86,17 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH .ARM : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) @@ -124,7 +132,6 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM1 AT> FLASH - /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -152,8 +159,6 @@ SECTIONS . = ALIGN(8); } >RAM1 - - /* Remove information from the standard libraries */ /DISCARD/ : { @@ -163,7 +168,15 @@ SECTIONS } .ARM.attributes 0 : { *(.ARM.attributes) } - MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED - MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED - MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED + MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED + MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED + + /* used by the startup to initialize .MB_MEM2 data */ + _siMB_MEM2 = LOADADDR(.MB_MEM2); + .MB_MEM2 : + { + _sMB_MEM2 = . ; + *(MB_MEM2) ; + _eMB_MEM2 = . ; + } >RAM_SHARED AT> FLASH } diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c index 6051388a7..93aba02fa 100644 --- a/hw/bsp/stm32wb/family.c +++ b/hw/bsp/stm32wb/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32wbxx_hal.h" #include "bsp/board_api.h" #include "board.h" @@ -42,7 +46,9 @@ void USB_LP_IRQHandler(void) { //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ +#ifdef UART_DEV UART_HandleTypeDef UartHandle; +#endif void board_init(void) { board_clock_init(); @@ -54,8 +60,6 @@ void board_init(void) { __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOE_CLK_ENABLE(); - UART_CLK_EN(); - #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -98,6 +102,8 @@ void board_init(void) { HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); #ifdef UART_DEV + UART_CLK_EN(); + // UART GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -155,7 +161,7 @@ int board_uart_write(void const* buf, int len) { HAL_UART_Transmit(&UartHandle, (uint8_t*) (uintptr_t) buf, len, 0xffff); return len; #else - (void) buf; (void) len; (void) UartHandle; + (void) buf; (void) len; return 0; #endif } @@ -178,8 +184,7 @@ void HardFault_Handler(void) { asm("bkpt 1"); } -// Required by __libc_init_array in startup code if we are compiling using -// -nostdlib/-nostartfiles. +// Required by __libc_init_array in startup code if we are compiling using -nostdlib/-nostartfiles. +void _init(void); void _init(void) { - } diff --git a/hw/bsp/stm32wb/family.cmake b/hw/bsp/stm32wb/family.cmake index 071797c20..0ea937257 100644 --- a/hw/bsp/stm32wb/family.cmake +++ b/hw/bsp/stm32wb/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32WB CACHE INTERNAL "") @@ -104,16 +104,16 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS} ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS}) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32wb/family.mk b/hw/bsp/stm32wb/family.mk index de8372eea..a80ff6f5b 100644 --- a/hw/bsp/stm32wb/family.mk +++ b/hw/bsp/stm32wb/family.mk @@ -9,14 +9,12 @@ include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m4 CFLAGS += \ - -flto \ - -nostdlib -nostartfiles \ -DCFG_TUSB_MCU=OPT_MCU_STM32WB -# suppress warning caused by vendor mcu driver -CFLAGS += -Wno-error=cast-align -Wno-unused-parameter - -LD_FILE ?= ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_cm4.ld +CFLAGS_GCC += \ + -flto \ + -nostdlib -nostartfiles \ + -Wno-error=cast-align -Wno-unused-parameter LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs @@ -25,19 +23,26 @@ SRC_C += \ $(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_${MCU_VARIANT}_cm4.s - INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(ST_CMSIS)/Include \ $(TOP)/$(ST_HAL_DRIVER)/Inc +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT)_cm4.s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT)_cm4.s + +# Linker +LD_FILE_GCC ?= ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_cm4.ld +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash_cm4.icf + # flash target using on-board stlink flash: flash-stlink diff --git a/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h index 5732056ae..c0ceb4cd8 100644 --- a/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h +++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: TM4C123G LaunchPad + url: https://www.ti.com/tool/EK-TM4C123GXL +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/hw/bsp/tm4c/family.c b/hw/bsp/tm4c/family.c index 5e1f6d3ff..4e5491005 100644 --- a/hw/bsp/tm4c/family.c +++ b/hw/bsp/tm4c/family.c @@ -1,3 +1,7 @@ +/* metadata: + manufacturer: Texas Instruments +*/ + #include "TM4C123.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/tm4c/family.cmake b/hw/bsp/tm4c/family.cmake index 9c083759b..e1cf94e96 100644 --- a/hw/bsp/tm4c/family.cmake +++ b/hw/bsp/tm4c/family.cmake @@ -9,7 +9,7 @@ set(SDK_DIR ${TOP}/hw/mcu/ti/${MCU_VARIANT}xx) set(CMSIS_DIR ${TOP}/lib/CMSIS_5) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS TM4C123 CACHE INTERNAL "") @@ -79,15 +79,14 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_TM4C123 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_TM4C123) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ${TOP}/src/portable/mentor/musb/hcd_musb.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h index 2d4764f40..3d0e92b2c 100644 --- a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h +++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: XMC4500 relax kit + url: https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc45_relax_v1/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/xmc4000/boards/xmc4700_relax/board.h b/hw/bsp/xmc4000/boards/xmc4700_relax/board.h index aa12fde3b..f3972980c 100644 --- a/hw/bsp/xmc4000/boards/xmc4700_relax/board.h +++ b/hw/bsp/xmc4000/boards/xmc4700_relax/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: XMC4700 relax kit + url: https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc47_relax_v1/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c index c776cb58a..1acce024b 100644 --- a/hw/bsp/xmc4000/family.c +++ b/hw/bsp/xmc4000/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Infineon +*/ + #include "xmc_gpio.h" #include "xmc_scu.h" #include "xmc_uart.h" diff --git a/hw/bsp/xmc4000/family.cmake b/hw/bsp/xmc4000/family.cmake index 85444db28..6edd72caf 100644 --- a/hw/bsp/xmc4000/family.cmake +++ b/hw/bsp/xmc4000/family.cmake @@ -6,7 +6,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS XMC4000 CACHE INTERNAL "") @@ -83,17 +83,17 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_XMC4000 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + family_add_tinyusb(${TARGET} OPT_MCU_XMC4000) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk index a1679a2f0..4eed7360a 100644 --- a/hw/bsp/xmc4000/family.mk +++ b/hw/bsp/xmc4000/family.mk @@ -1,8 +1,6 @@ UF2_FAMILY_ID = 0x00 SDK_DIR = hw/mcu/infineon/mtb-xmclib-cat3 -DEPS_SUBMODULES += ${SDK_DIR} - include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m4 diff --git a/hw/bsp/zephyr_board_aliases.cmake b/hw/bsp/zephyr_board_aliases.cmake new file mode 100644 index 000000000..b60e97ef4 --- /dev/null +++ b/hw/bsp/zephyr_board_aliases.cmake @@ -0,0 +1,2 @@ +set(pca10056_BOARD_ALIAS nrf52840dk/nrf52840) +set(stm32n657nucleo_BOARD_ALIAS nucleo_n657x0_q) |