diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h | 165 | ||||
| -rw-r--r-- | hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake | 9 | ||||
| -rw-r--r-- | hw/bsp/lpc40/boards/ea4088_quickstart/board.h | 74 | ||||
| -rw-r--r-- | hw/bsp/lpc40/boards/ea4088_quickstart/board.mk | 8 | ||||
| -rw-r--r-- | hw/bsp/lpc40/boards/ea4088_quickstart/lpc4088.ld (renamed from hw/bsp/ea4088qs/lpc4088.ld) | 0 | ||||
| -rw-r--r-- | hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug | 238 | ||||
| -rw-r--r-- | hw/bsp/lpc40/family.c (renamed from hw/bsp/ea4088qs/ea4088qs.c) | 115 | ||||
| -rw-r--r-- | hw/bsp/lpc40/family.cmake | 102 | ||||
| -rw-r--r-- | hw/bsp/lpc40/family.mk (renamed from hw/bsp/ea4088qs/board.mk) | 30 | ||||
| -rw-r--r-- | hw/bsp/xmc4000/boards/xmc4500_relax/board.mk | 2 | ||||
| -rw-r--r-- | hw/bsp/xmc4000/boards/xmc4700_relax/board.h | 81 | ||||
| -rw-r--r-- | hw/bsp/xmc4000/boards/xmc4700_relax/board.mk | 12 | ||||
| -rw-r--r-- | hw/bsp/xmc4000/family.c | 26 | ||||
| -rw-r--r-- | hw/bsp/xmc4000/family.mk | 5 |
14 files changed, 765 insertions, 102 deletions
diff --git a/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..96611ca1c --- /dev/null +++ b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,165 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "chip.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 2 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Define to trap errors during development. */ +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) + #define configASSERT(_exp) \ + do {\ + if ( !(_exp) ) { \ + volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ + taskDISABLE_INTERRUPTS(); \ + __asm("BKPT #0\n"); \ + }\ + }\ + } while(0) +#else + #define configASSERT( x ) +#endif + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 5 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +#endif diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake b/hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake new file mode 100644 index 000000000..7f281d5f6 --- /dev/null +++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake @@ -0,0 +1,9 @@ +set(JLINK_DEVICE LPC4088) +set(PYOCD_TARGET LPC4088) +set(NXPLINK_DEVICE LPC4088:LPC4088) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc4088.ld) + +function(update_board TARGET) + # nothing to do +endfunction() diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.h b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h new file mode 100644 index 000000000..d5489c154 --- /dev/null +++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h @@ -0,0 +1,74 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef EA4088QS__BOARD_H +#define EA4088QS__BOARD_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define LED_PORT 2 +#define LED_PIN 19 + +#define BUTTON_PORT 2 +#define BUTTON_PIN 10 +#define BUTTON_ACTIV_STATE 0 + +/* System oscillator rate and RTC oscillator rate */ +const uint32_t OscRateIn = 12000000; +const uint32_t RTCOscRateIn = 32768; + +/* Pin muxing configuration */ +static const PINMUX_GRP_T pinmuxing[] = { + // LED + { 2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT) }, + + // Button + { 2, 10, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_MODE_PULLUP) }, + + // USB1 as Host + { 0, 29, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // D+1 + { 0, 30, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // D-1 + { 1, 18, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // UP LED1 + { 1, 19, (IOCON_FUNC2 | IOCON_MODE_INACT) }, // PPWR1 +// {2, 14, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // VBUS1 +// {2, 15, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // OVRCR1 + + // USB2 as Device + { 0, 31, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // D+2 + { 0, 13, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // UP LED + { 0, 14, (IOCON_FUNC3 | IOCON_MODE_INACT) }, // CONNECT2 + + /* VBUS is not connected on this board, so leave the pin at default setting. */ + /*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */ +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.mk b/hw/bsp/lpc40/boards/ea4088_quickstart/board.mk new file mode 100644 index 000000000..d0bb4fe8c --- /dev/null +++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.mk @@ -0,0 +1,8 @@ + +LD_FILE = $(BOARD_PATH)/lpc4088.ld + +# For flash-jlink target +JLINK_DEVICE = LPC4088 + +# flash using jlink +flash: flash-jlink diff --git a/hw/bsp/ea4088qs/lpc4088.ld b/hw/bsp/lpc40/boards/ea4088_quickstart/lpc4088.ld index 5897707f6..5897707f6 100644 --- a/hw/bsp/ea4088qs/lpc4088.ld +++ b/hw/bsp/lpc40/boards/ea4088_quickstart/lpc4088.ld diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug b/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug new file mode 100644 index 000000000..6aaf1076d --- /dev/null +++ b/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug @@ -0,0 +1,238 @@ + +/********************************************************************* +* +* OnProjectLoad +* +* Function description +* Project load routine. Required. +* +********************************************************************** +*/ +void OnProjectLoad (void) { + Edit.SysVar (VAR_POWER_SAMPLING_SPEED, FREQ_100_KHZ); + Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M4F.svd"); + Project.AddSvdFile ("../../../../../../../cmsis-svd/data/NXP/LPC408x_7x_v0.7.svd"); + + Project.SetDevice ("LPC4088"); + Project.SetHostIF ("USB", ""); + Project.SetTargetIF ("SWD"); + Project.SetTIFSpeed ("50 MHz"); + Project.SetTraceSource ("Trace Pins"); + Project.SetTracePortWidth (4); + + // User settings + File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ea4088-quickstart/cdc_msc.elf"); +} + +/********************************************************************* +* +* TargetReset +* +* Function description +* Replaces the default target device reset routine. Optional. +* +* Notes +* This example demonstrates the usage when +* debugging a RAM program on a Cortex-M target device +* +********************************************************************** +*/ +//void TargetReset (void) { +// +// unsigned int SP; +// unsigned int PC; +// unsigned int VectorTableAddr; +// +// Exec.Reset(); +// +// VectorTableAddr = Elf.GetBaseAddr(); +// +// if (VectorTableAddr != 0xFFFFFFFF) { +// +// Util.Log("Resetting Program."); +// +// SP = Target.ReadU32(VectorTableAddr); +// Target.SetReg("SP", SP); +// +// PC = Target.ReadU32(VectorTableAddr + 4); +// Target.SetReg("PC", PC); +// } +//} + +/********************************************************************* +* +* BeforeTargetReset +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetReset (void) { +//} + +/********************************************************************* +* +* AfterTargetReset +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetReset (void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + + if (VectorTableAddr == 0xFFFFFFFF) { + Util.Log("Project file error: failed to get program base"); + } else { + SP = Target.ReadU32(VectorTableAddr); + Target.SetReg("SP", SP); + + PC = Target.ReadU32(VectorTableAddr + 4); + Target.SetReg("PC", PC); + } +} + +/********************************************************************* +* +* DebugStart +* +* Function description +* Replaces the default debug session startup routine. Optional. +* +********************************************************************** +*/ +//void DebugStart (void) { +//} + +/********************************************************************* +* +* TargetConnect +* +* Function description +* Replaces the default target IF connection routine. Optional. +* +********************************************************************** +*/ +//void TargetConnect (void) { +//} + +/********************************************************************* +* +* BeforeTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +void BeforeTargetConnect (void) { +} + +/********************************************************************* +* +* AfterTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetConnect (void) { +//} + +/********************************************************************* +* +* TargetDownload +* +* Function description +* Replaces the default program download routine. Optional. +* +********************************************************************** +*/ +//void TargetDownload (void) { +//} + +/********************************************************************* +* +* BeforeTargetDownload +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDownload (void) { +//} + +/********************************************************************* +* +* AfterTargetDownload +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetDownload (void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + + if (VectorTableAddr == 0xFFFFFFFF) { + Util.Log("Project file error: failed to get program base"); + } else { + SP = Target.ReadU32(VectorTableAddr); + Target.SetReg("SP", SP); + + PC = Target.ReadU32(VectorTableAddr + 4); + Target.SetReg("PC", PC); + } +} + +/********************************************************************* +* +* BeforeTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetHalt +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetHalt (void) { +//} diff --git a/hw/bsp/ea4088qs/ea4088qs.c b/hw/bsp/lpc40/family.c index ace72fef0..829df4ac7 100644 --- a/hw/bsp/ea4088qs/ea4088qs.c +++ b/hw/bsp/lpc40/family.c @@ -25,89 +25,60 @@ */ #include "chip.h" -#include "../board.h" +#include "bsp/board.h" +#include "board.h" //--------------------------------------------------------------------+ // USB Interrupt Handler //--------------------------------------------------------------------+ -void USB_IRQHandler(void) -{ +void USB_IRQHandler(void) { #if CFG_TUD_ENABLED - tud_int_handler(0); + tud_int_handler(0); #endif #if CFG_TUH_ENABLED - tuh_int_handler(0); + tuh_int_handler(0); #endif } //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ -#define LED_PORT 2 -#define LED_PIN 19 - -#define BUTTON_PORT 2 -#define BUTTON_PIN 10 - -/* System oscillator rate and RTC oscillator rate */ -const uint32_t OscRateIn = 12000000; -const uint32_t RTCOscRateIn = 32768; - -/* Pin muxing configuration */ -static const PINMUX_GRP_T pinmuxing[] = -{ - // LED - {2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT)}, - - // Button - {2, 10, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_MODE_PULLUP)}, -}; - -static const PINMUX_GRP_T pin_usb_mux[] = -{ - // USB1 as Host - {0, 29, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+1 - {0, 30, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D-1 - {1, 18, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED1 - {1, 19, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // PPWR1 -// {2, 14, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // VBUS1 -// {2, 15, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // OVRCR1 - - // USB2 as Device - {0, 31, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+2 - {0, 13, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED - {0, 14, (IOCON_FUNC3 | IOCON_MODE_INACT)}, // CONNECT2 - - /* VBUS is not connected on this board, so leave the pin at default setting. */ - /*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */ -}; // Invoked by startup code -void SystemInit(void) -{ +void SystemInit(void) { #ifdef __USE_LPCOPEN - extern void (* const g_pfnVectors[])(void); + extern void (*const g_pfnVectors[])(void); unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08; - *pSCB_VTOR = (unsigned int) g_pfnVectors; + *pSCB_VTOR = (unsigned int) g_pfnVectors; -#if __FPU_USED == 1 - fpuInit(); -#endif + #if __FPU_USED == 1 + fpuInit(); + #endif #endif // __USE_LPCOPEN Chip_IOCON_Init(LPC_IOCON); Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); - /* CPU clock source starts with IRC */ - /* Enable PBOOST for CPU clock over 100MHz */ - Chip_SYSCTL_EnableBoost(); +#ifdef TRACE_ETM + const PINMUX_GRP_T trace_pinmux[] = { + {2, 2, IOCON_FUNC5 | IOCON_FASTSLEW_EN }, + {2, 3, IOCON_FUNC5 | IOCON_FASTSLEW_EN }, + {2, 4, IOCON_FUNC5 | IOCON_FASTSLEW_EN }, + {2, 5, IOCON_FUNC5 | IOCON_FASTSLEW_EN }, + {2, 6, IOCON_FUNC5 | IOCON_FASTSLEW_EN }, + }; + Chip_IOCON_SetPinMuxing(LPC_IOCON, trace_pinmux, sizeof(trace_pinmux) / sizeof(PINMUX_GRP_T)); +#endif + + /* CPU clock source starts with IRC */ + /* Enable PBOOST for CPU clock over 100MHz */ + Chip_SYSCTL_EnableBoost(); Chip_SetupXtalClocking(); } -void board_init(void) -{ +void board_init(void) { SystemCoreClockUpdate(); #if CFG_TUSB_OS == OPT_OS_NONE @@ -129,15 +100,14 @@ void board_init(void) // UART //------------- USB -------------// - Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T)); // Port1 as Host, Port2: Device Chip_USB_Init(); enum { USBCLK_DEVCIE = 0x12, // AHB + Device - USBCLK_HOST = 0x19 , // AHB + OTG + Host - USBCLK_ALL = 0x1B // Host + Device + OTG + AHB + USBCLK_HOST = 0x19, // AHB + OTG + Host + USBCLK_ALL = 0x1B // Host + Device + OTG + AHB }; LPC_USB->OTGClkCtrl = USBCLK_ALL; @@ -151,40 +121,37 @@ void board_init(void) // Board porting API //--------------------------------------------------------------------+ -void board_led_write(bool state) -{ +void board_led_write(bool state) { Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state); } -uint32_t board_button_read(void) -{ - // active low - return Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN) ? 0 : 1; +uint32_t board_button_read(void) { + return BUTTON_ACTIV_STATE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN); } -int board_uart_read(uint8_t* buf, int len) -{ +int board_uart_read(uint8_t *buf, int len) { //return UART_ReceiveByte(BOARD_UART_PORT); - (void) buf; (void) len; + (void) buf; + (void) len; return 0; } -int board_uart_write(void const * buf, int len) -{ +int board_uart_write(void const *buf, int len) { //UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING); - (void) buf; (void) len; + (void) buf; + (void) len; return 0; } #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; -void SysTick_Handler (void) -{ + +void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) -{ +uint32_t board_millis(void) { return system_ticks; } + #endif diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake new file mode 100644 index 000000000..56eb37a2f --- /dev/null +++ b/hw/bsp/lpc40/family.cmake @@ -0,0 +1,102 @@ +include_guard() + +set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS LPC18XX CACHE INTERNAL "") + + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + add_library(${BOARD_TARGET} STATIC + ${SDK_DIR}/../gcc/cr_startup_lpc40xx.c + ${SDK_DIR}/src/chip_17xx_40xx.c + ${SDK_DIR}/src/clock_17xx_40xx.c + ${SDK_DIR}/src/fpu_init.c + ${SDK_DIR}/src/gpio_17xx_40xx.c + ${SDK_DIR}/src/iocon_17xx_40xx.c + ${SDK_DIR}/src/sysctl_17xx_40xx.c + ${SDK_DIR}/src/sysinit_17xx_40xx.c + ${SDK_DIR}/src/uart_17xx_40xx.c + ) + target_compile_options(${BOARD_TARGET} PUBLIC + -nostdlib + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + __USE_LPCOPEN + CORE_M4 + CFG_TUSB_MEM_SECTION=__attribute__\(\(section\(\".data.$RAM2\"\)\)\) + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${SDK_DIR}/inc + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + # nanolib + --specs=nosys.specs + --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_LPC40XX ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + ${TOP}/src/portable/ohci/ohci.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_jlink(${TARGET}) + #family_flash_nxplink(${TARGET}) +endfunction() diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/lpc40/family.mk index e1e14b717..c11325890 100644 --- a/hw/bsp/ea4088qs/board.mk +++ b/hw/bsp/lpc40/family.mk @@ -1,47 +1,33 @@ DEPS_SUBMODULES += hw/mcu/nxp/lpcopen +MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m4 + CFLAGS += \ -flto \ - -mthumb \ - -mabi=aapcs \ - -mcpu=cortex-m4 \ - -mfloat-abi=hard \ - -mfpu=fpv4-sp-d16 \ -nostdlib \ -DCORE_M4 \ -D__USE_LPCOPEN \ - -DCFG_TUD_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ - -DCFG_TUH_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ + -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ -DCFG_TUSB_MCU=OPT_MCU_LPC40XX # mcu driver cause following warnings CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual -MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx - # All source paths should be relative to the top level. -LD_FILE = hw/bsp/$(BOARD)/lpc4088.ld - SRC_C += \ src/portable/nxp/lpc17_40/dcd_lpc17_40.c \ $(MCU_DIR)/../gcc/cr_startup_lpc40xx.c \ $(MCU_DIR)/src/chip_17xx_40xx.c \ $(MCU_DIR)/src/clock_17xx_40xx.c \ + $(MCU_DIR)/src/fpu_init.c \ $(MCU_DIR)/src/gpio_17xx_40xx.c \ $(MCU_DIR)/src/iocon_17xx_40xx.c \ $(MCU_DIR)/src/sysctl_17xx_40xx.c \ $(MCU_DIR)/src/sysinit_17xx_40xx.c \ $(MCU_DIR)/src/uart_17xx_40xx.c \ - $(MCU_DIR)/src/fpu_init.c INC += \ - $(TOP)/$(MCU_DIR)/inc - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F - -# For flash-jlink target -JLINK_DEVICE = LPC4088 - -# flash using jlink -flash: flash-jlink + $(TOP)/$(MCU_DIR)/inc \ + $(TOP)/$(BOARD_PATH) diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk index 371adff91..2b8f7bc57 100644 --- a/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk +++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk @@ -3,7 +3,7 @@ CFLAGS += \ -DXMC4500_F100x1024 \ # mcu driver cause following warnings -CFLAGS += -Wno-error=stringop-overread +CFLAGS += -Wno-stringop-overread LD_FILE = $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld diff --git a/hw/bsp/xmc4000/boards/xmc4700_relax/board.h b/hw/bsp/xmc4000/boards/xmc4700_relax/board.h new file mode 100644 index 000000000..aa12fde3b --- /dev/null +++ b/hw/bsp/xmc4000/boards/xmc4700_relax/board.h @@ -0,0 +1,81 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PIN P5_9 +#define LED_STATE_ON 1 + +#define BUTTON_PIN P15_13 +#define BUTTON_STATE_ACTIVE 0 + +#define UART_DEV XMC_UART0_CH0 +#define UART_TX_PIN P1_5 +#define UART_TX_PIN_AF P1_5_AF_U0C0_DOUT0 +#define UART_RX_PIN P1_4 +#define UART_RX_INPUT USIC0_C0_DX0_P1_4 + +static inline void board_clock_init(void) +{ + /* Clock configuration */ + /* fPLL = 144MHz */ + /* fSYS = 144MHz */ + /* fUSB = 48MHz */ + const XMC_SCU_CLOCK_CONFIG_t clock_config = + { + .syspll_config.p_div = 2, + .syspll_config.n_div = 48, + .syspll_config.k_div = 1, + .syspll_config.mode = XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL, + .syspll_config.clksrc = XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP, + .enable_oschp = true, + .calibration_mode = XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY, + .fsys_clksrc = XMC_SCU_CLOCK_SYSCLKSRC_PLL, + .fsys_clkdiv = 2, + .fcpu_clkdiv = 1, + .fccu_clkdiv = 1, + .fperipheral_clkdiv = 1 + }; + + /* Setup settings for USB clock */ + XMC_SCU_CLOCK_Init(&clock_config); + + XMC_SCU_CLOCK_SetUsbClockDivider(6); + XMC_SCU_CLOCK_SetUsbClockSource(XMC_SCU_CLOCK_USBCLKSRC_SYSPLL); + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_USB); +} + + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/xmc4000/boards/xmc4700_relax/board.mk b/hw/bsp/xmc4000/boards/xmc4700_relax/board.mk new file mode 100644 index 000000000..28fadf8f4 --- /dev/null +++ b/hw/bsp/xmc4000/boards/xmc4700_relax/board.mk @@ -0,0 +1,12 @@ +MCU_VARIANT = XMC4700 +CFLAGS += \ + -DXMC4700_F144x2048 \ + +# mcu driver cause following warnings +CFLAGS += -Wno-stringop-overread + +LD_FILE = $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/XMC4700x2048.ld + +JLINK_DEVICE = XMC4700-2048 + +flash: flash-jlink diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c index bf6684736..146bef373 100644 --- a/hw/bsp/xmc4000/family.c +++ b/hw/bsp/xmc4000/family.c @@ -26,6 +26,7 @@ #include "xmc_gpio.h" #include "xmc_scu.h" +#include "xmc_uart.h" #include "bsp/board.h" #include "board.h" @@ -45,17 +46,31 @@ void board_init(void) SystemCoreClockUpdate(); // LED - XMC_GPIO_CONFIG_t led_cfg; + XMC_GPIO_CONFIG_t led_cfg = {0}; led_cfg.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; led_cfg.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; led_cfg.output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM; XMC_GPIO_Init(LED_PIN, &led_cfg); // Button - XMC_GPIO_CONFIG_t button_cfg; + XMC_GPIO_CONFIG_t button_cfg = {0}; button_cfg.mode = XMC_GPIO_MODE_INPUT_TRISTATE; XMC_GPIO_Init(BUTTON_PIN, &button_cfg); +#ifdef UART_DEV + XMC_UART_CH_CONFIG_t uart_cfg = {0}; + uart_cfg.baudrate = CFG_BOARD_UART_BAUDRATE; + uart_cfg.data_bits = 8; + uart_cfg.stop_bits = 1; + XMC_UART_CH_Init(UART_DEV, &uart_cfg); + + XMC_GPIO_SetMode(UART_RX_PIN, XMC_GPIO_MODE_INPUT_PULL_UP); + XMC_UART_CH_SetInputSource(UART_DEV, XMC_UART_CH_INPUT_RXD, UART_RX_INPUT); + + XMC_UART_CH_Start(UART_DEV); + XMC_GPIO_SetMode(UART_TX_PIN, (XMC_GPIO_MODE_t)(XMC_GPIO_MODE_OUTPUT_PUSH_PULL | UART_TX_PIN_AF)); +#endif + #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -69,6 +84,9 @@ void board_init(void) #endif // USB Power Enable +#if(UC_SERIES != XMC45) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); +#endif XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0); XMC_SCU_POWER_EnableUsb(); } @@ -93,7 +111,7 @@ int board_uart_read(uint8_t* buf, int len) { #ifdef UART_DEV for(int i=0;i<len;i++) { - buf[i] = uart_getc(uart_inst); + buf[i] = XMC_UART_CH_GetReceivedData(UART_DEV); } return len; #else @@ -107,7 +125,7 @@ int board_uart_write(void const * buf, int len) #ifdef UART_DEV char const* bufch = (char const*) buf; for(int i=0;i<len;i++) { - uart_putc(uart_inst, bufch[i]); + XMC_UART_CH_Transmit(UART_DEV, bufch[i]); } return len; #else diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk index 35c3a58b7..6c460c93b 100644 --- a/hw/bsp/xmc4000/family.mk +++ b/hw/bsp/xmc4000/family.mk @@ -20,8 +20,11 @@ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ $(MCU_DIR)/Newlib/syscalls.c \ $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/system_$(MCU_VARIANT).c \ + $(MCU_DIR)/XMCLib/src/xmc_gpio.c \ $(MCU_DIR)/XMCLib/src/xmc4_gpio.c \ - $(MCU_DIR)/XMCLib/src/xmc4_scu.c + $(MCU_DIR)/XMCLib/src/xmc4_scu.c \ + $(MCU_DIR)/XMCLib/src/xmc_usic.c \ + $(MCU_DIR)/XMCLib/src/xmc_uart.c SRC_S += $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/startup_$(MCU_VARIANT).S |