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A zero-length OUT read (e.g. the MTP driver's read for the host's
terminating data ZLP) could never complete when the ZLP's EPDATA
arrived after the read was armed: actual_len < total_len is always
false for total_len == 0, so the handler only set data_received and the
armed transfer hung forever, wedging both bulk endpoints (host sees
pure NAK; EP0 stays alive). Run the 0-byte DMA in that case to drain
the endpoint and complete the transfer, matching what the arm path
already does when the ZLP arrives first.
Found via usbmon on the HIL rig: device/mtp on feather_nrf52840_express
wedged after SendObject's terminating ZLP whenever the class armed the
read before the host's (NAK-delayed) ZLP retry landed - deterministic
under CI load, which is why PR CI only passed this test on a re-flash
retry (21.4 s vs the normal 2.2 s).
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fs_send_object() copied every received payload to f->data using only
the running offset, so a host sending more data than its SendObjectInfo
declared wrote past the object and overflowed fs_buf. Clamp each copy to
what remains of f->size.
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The data-out phase ended before its terminating ZLP and before the
application had seen the final payload, and several transaction states
had no way back to idle. Reworked as one state machine:
- Add MTP_PHASE_DATA_COMPLETE, entered once the data phase has fully
finished - for an exact buffer-multiple data-out, only after the
host's terminating ZLP - and deliver tud_mtp_data_complete_cb() from
there. tud_mtp_response_send() now refuses while the phase is still
MTP_PHASE_DATA: ep_out still owes the host a read at that point and
re-arming it for a new command would race that read.
- Arm the terminating-ZLP read before handing the final payload to the
application, as the IN path already does. The 0-length read passes a
NULL buffer so the payload is untouched, and claiming ep_out first
means a late tud_mtp_data_receive() fails its own claim instead of
breaking the driver's next step.
- Honor the documented negative return of tud_mtp_data_xfer_cb() and
tud_mtp_data_complete_cb() by entering MTP_PHASE_ERROR, which stalls
both endpoints. This is the application's way out of a data phase now
that a response cannot be sent from one. Their weak stubs return 0 so
an application that does not implement them is unaffected.
- Take total_len from the container header the host sends on the first
OUT packet. The application can only set it up front when it knows
the size (SendObject); SendObjectInfo cannot, so total_len kept the
12-byte header default and the phase ended on the first packet.
- Reject a runt or misdirected container in both the command and data
phases: a short packet was matched against stale buffer contents, and
the failed TU_VERIFY left ep_out neither armed nor stalled. The
first data-out packet previously underflowed payload_bytes instead.
- Restore the previous phase when tud_mtp_data_send()/_receive() cannot
claim their endpoint, so the application's fallback response is not
refused by a phase the driver never actually entered.
- Re-arm ep_out after MTP_REQ_CANCEL of a data phase, and defer the
new-command read when ep_out is still busy with the ZLP read of an
abandoned transaction: usbd_edpt_xfer() asserts on a busy endpoint,
so MTP_REQ_RESET could not recover.
The MTP example follows the same contract: a handler error raised mid
data phase (fs_send_object_info validates the received ObjectInfo, so
STORE_FULL and INVALID_PARENT_OBJECT can only be raised there) is kept
and answered from tud_mtp_data_complete_cb() once the phase completes.
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hil, ci: scope HIL builds and tests to the boards a PR affects
Add test/hil/hil_select.py, a stdlib-only selector that maps a PR diff to the
rig boards, tests and BSP families a change can affect, and wire it into CI so
pull requests build and run only those. A port change picks its families' boards,
a class change picks the examples enabling that class, and device/host changes
prune the other role. Anything unclassified — infra, an unmapped port, a selector
error — falls back to the full matrix, and push/schedule runs are untouched.
Move the shared example lists to hil_examples.py; 54 hardware-free tests cover
the rules.
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rp2xxx: added rp2usb_deinit() to fix 'No spinlocks are available'
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probes (#3794)
test/hil: add board-pool health check, split hil_test into focused modules (#3794)
Add test/hil/hil_pool_check.py: per-board rig health scan — probe presence,
light-example flash (dfu_runtime; device_info + serial check for host-only
boards), uid re-enumeration, safe recovery (probe authorized-toggle, board
reset), verified board_test re-park, USB topology report, and a markdown
summary table. Missing firmware is built on the spot (tools/build.py, idf.py
for espressif, one get_deps retry); row statuses: ok, flash-failed, failed,
locked. Board locks are always respected, never bypassed.
Refactor hil_test.py into hil_lock.py (flock protocol, controller permits,
hold/release/status CLI; replaces board_lock.py) and hil_flash.py (flashers,
find_firmware, run_cmd). Update WCH probe uids and the board roster in
tinyusb.json; add the hil-pool-check skill.
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Add More HID Usage Page enums
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This reverts commit 80ffbff6e98a9c5053bba008ae2c5087f0351300.
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Signed-off-by: Zixun LI <[email protected]>
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docs: add the unified OpenOCD plan, note worktree dep symlinks
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The plan doc records why the fork exists and how each vendor source was
ported; the interim handoff it superseded is dropped.
CLAUDE.md: a new worktree should symlink the dependency dirs to the
primary checkout rather than re-fetching them, replacing a single
symlink only when the branch needs a different dep revision. Also allow
'linke' in codespell - WCH-LinkE is a product name.
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bsp, hil: flash with the unified OpenOCD fork
https://github.com/hathach/openocd (branch tinyusb) is mainline plus every
config these boards need: RPi RP2350, ADI max32/max78, the MounRiver WCH
configs, and the wlinke adapter on mainline's riscv target. It is a superset
of the vendor forks, so one 'openocd' covers all boards; -DOPENOCD=/OPENOCD=
still select another, msdk's when MAXIM_PATH is set.
Drops family_flash_openocd_wch and the OPENOCD_WCH pair, dedups
family_flash_openocd_adi, aligns ch583's work area, and points hil at the
flasher's own config instead of generating one per probe.
Verified: HIL green on all four WCH boards and max32666fthr.
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(#3789)
test/hil: replace PCI reset with root-port VBUS cycle for D-state recovery
pci-reset was documented as an FLR, but no controller on either rig has FLR, so
it issued a PCIe secondary bus reset on a live, driver-bound xHCI -- halting the
card until the PVE host was power-cycled, and returning success so the caller
could not tell. It destroyed the ci controller twice.
Replace it with root-cycle, which cuts VBUS at the xHCI root port and touches
only the root hub, so it never takes the per-device lock the wedged ioctl holds.
uhubctl needs -S, or its sysfs backend disconnects the child before cutting
power and blocks on that same lock. Success is proven by the device's sysfs
directory inode changing: node existence proves nothing, and devnum is reused
once the per-bus map wraps.
usbtest.py's hang path invokes it, then confirms via /proc that nothing still
holds the device node. Skill scripts now run from the repo; the drifted
/usr/local/sbin copies are deleted.
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Cast BMaxPower in TUD_CONFIG_DESCRIPTOR to uint8_t
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Enable APM32F0 dependency fetching and CI
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Signed-off-by: Zixun LI <[email protected]>
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Add etm-trace skill: unattended ETM instruction trace + per-board TRACE_ETM support
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Coverage rows now resolve the de-collided module-qualified key introduced
for same-named statics. RA boards: document that --attach requires a
debugger-booted target - the C_DEBUGEN gate exists because an unguarded
TRCKCR write bricks standalone boots (hardware-proven), so the limitation
is documented rather than the guard weakened; a debugger-side TRCKCR hook
can lift it later once re-verified on hardware. The stm32n6 board-gating
suggestion is not taken: N6 trace pins are AF0-fixed chip-level, the same
family-wide pattern as stm32h7.
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The board-specific PHY-reset nets move behind a board.h opt-in
(TRACE_ETM_QUIET_ENET_PHY on same70_xplained and mimxrt1170_evkb) so other
boards of those families cannot inherit a foreign GPIO write; the
chip-level trace pin muxes stay family-wide by design (same pattern as
stm32h7). same70 reference: width 1 is the validated default until the
J403.16 rework, and the hooks now wait (bounded) for PCKRDY3 before Ozone
arms trace. ra8m1 reference caches the boot ROM in AfterTargetConnect so
--attach sessions decode ROM execution too. etm_capture rejects an
unexpanded CMake JLINK_DEVICE with a clear error; PIO-USB + TRACE_ETM on
RP2350 is now a compile error (48 MHz trace clock is too slow for PIO-USB
and a runtime switch would desync the stream); etm_profile keeps
same-named statics from different modules as distinct rows.
Build-verified: same70_xplained, mimxrt1170_evkb, raspberry_pi_pico2.
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Bot findings (Copilot/Codex): no-op board_trace_pinmux stubs for
lpcxpresso18s37/43s67 (TRACE_ETM otherwise broke their build), SAME70
ID_PIOD clock enable, capture-script duplicate BeforeTargetConnect on the
RA references, profile-script support for --no-timestamps itraces.
Deep review (whole branch): same70_xplained board row + caveat restored,
stale pico2 72 MHz claim corrected to the shipped 48, explicit
SetTracePortWidth(4) in the three references that relied on Ozone's
default, coverage-cell guard, median-based SysTick calibration, dead
session flag removed, stale RA8M1 divider comment fixed (0x02 = /4 is the
validated chip max) and the debugger guard indented.
EVKB bench findings: only R1884/D3 remains open (D1/D2 meter-verified);
RT1176 trace width is 1 or 4 only - J-Link arms the CSSYS TPIU and its
own sampler at 4-bit for any width>=2 request; a powered MCU-Link USB
breaks the external probe even with JP4 shorted.
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Fresh bring-up pass on mimxrt1170_evkb: holding the 100M RTL8201 in reset
(ENET_RST_B = GPIO_LPSR_04) stops its RMII lines driving against the
shared trace pads and doubles the clean trace-pin rate to 50 MHz
(100 MHz CSTRACE root; 133 MHz root is marginal, stock 132 corrupts).
Validated 3x 8 s TinyUSB captures at 11.46M fetches. D1-D3 remain silent
in every configuration - the welded R1882-R1884 are electrically open;
reflow is the remaining step to width 4. Board notes gain JP4 (must be
shorted for an external probe on J58).
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Fifth capture view alongside usbmon/kernel/target/wire: exact execution
history via J-Trace, existing only where the trace header is wired -
confirm with the user before reaching for it.
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Instruction-level trace outranks PC-sampling when samples cannot resolve a
mechanism, but the J-Trace is exclusive per-board hardware: the agent uses
it only when its prompt says the board is trace-wired or the user asked,
and otherwise proposes it in notes - mirroring the lock-force consent rule.
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target-debug replaced usb-target-debug in the debug-skill overhaul; update
the cross-skill table and PC-sampling pointer. Add the consent gate: the
J-Trace is a single probe moved between boards, so captures on a board the
user did not just ask about need explicit confirmation that it is wired.
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J403 (bottom-side Cortex Debug+ETM footprint, header required):
TRACECLK=PD8 peripheral D, TRACED0-3=PD4-7 peripheral C. TRACE_ETM builds
hold the KSZ8081 PHY in reset (PD4-7 are its RMII receive outputs and it
drives against the trace stream), clock the TPIU from PCK3 (MCK/2) and
mux the pins; the ozone reference starts PCK3 in the post-reset/download
hooks - TPIU programming while PCK3 is stopped is silently lost. Width-1
validated at the stock 300 MHz core; width 4 blocked on a dead D1 line
(suspect probe channel, h743eval crosscheck pending).
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The populated 20-pin Cortex Debug+ETM header carries 4-bit trace
(TRACECLK=PC27, D0-3=PC28/PC26/PC25/PC24, mux H). TRACE_ETM builds mux
the pins and enable GCLK channel 47 (GCLK_CM4_TRACE) from GCLK0 - without
that gate the port stays silent with pins and TPIU armed. Chip-max
120 MHz core / 60 MHz TRACECLK validated (3x 280M-fetch captures).
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J-Link's built-in RP2350 script owns the whole chip-side path (component
map is not ROM-table-discoverable; a custom JLinkScript replaces the
built-in one and kills pin trace), re-arming at every resume - firmware
does no trace setup. TRACE_ETM builds pin clk_sys to 48 MHz from crt0
(fly-wire seating-proof; the port is DDR at clk_sys/2 and the J-Trace PRO
V2 cliff sits just above 40 MHz TRACECLK - SEGGER requires V3.0+ for this
chip), clear TIMER0/1 DBGPAUSE (default freezes the us-timer while any
core is debug-halted and sleep_ms spins forever), and run the UART console
TX-only (GPIO1 = default UART0 RX = TRACECLK).
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