| Age | Commit message (Collapse) | Author |
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HWFIFO access-mode refactor and stride-aware FIFO fixes across FSDEV/RUSB2/MUSB
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Co-authored-by: Copilot <[email protected]>
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Co-authored-by: Copilot <[email protected]>
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delay for stable speed detection
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read/write
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rusb use custom write
enable all hil test for ra4m1
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duplicated packet write/read for fsdev
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Fix compilation v2
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'idx' is not used if CFG_TUH_CDC_LINE_CODING_ON_ENUM is not defined.
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Enable D-Cache unless we're compiling for the M4 core of a dual-core H7 mcu by directly testing CORE_CM4
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Added tud_vendor_write_clear() which forcefully clears TX buffer
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SCB_EnableDCache() is required for rt1011
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remove the usage snprintf
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Add support for NXP RW61x
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Feature/support hpmicro chips
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Signed-off-by: Zixun LI <[email protected]>
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Signed-off-by: Zixun LI <[email protected]>
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Signed-off-by: Zixun LI <[email protected]>
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Signed-off-by: Zixun LI <[email protected]>
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Signed-off-by: Zixun LI <[email protected]>
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Signed-off-by: Zixun LI <[email protected]>
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Signed-off-by: Zixun LI <[email protected]>
Signed-off-by: HiFiPhile <[email protected]>
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