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2026-07-07Enable 4-packet bursts on CH569 SuperSpeed bulk endpointshathach
- Default CFG_TUD_WCH_USB30_MAX_BURST to 4 (tusb_mcu.h): matches the link layer's header-packet buffer count (NUM_HP_BUF). Burst 8 fails to configure; the TeenyUSB-reported burst corruption quirk did not reproduce with per-burst DMA re-arm (50x MSC write/read-back and 256KB CDC echo integrity all clean at burst 4) - Bounce slots stay one max packet regardless of burst (bounced transfers cap their burst to the slot; zero-copy uses the full burst) so the RAMX pool no longer scales with burst size - cdc_msc/cdc_msc_throughput SS descriptors advertise bMaxBurst = CFG_TUD_WCH_USB30_MAX_BURST-1 via the CFG_EXAMPLE_SS_BULK_MAXBURST knob (0 for non-WCH SuperSpeed ports) Measured on HydraUSB3 v1 at 5 Gbps (HIL cdc_msc_throughput): MSC read 147 MBps write 127 MBps - about 2x the single-packet figures (raw dd: up to 163 MB/s read at 1M blocks). Co-Authored-By: Claude Fable 5 <[email protected]>
2026-07-07Add SuperSpeed support to cdc_msc_throughput examplehathach
- SS device/config/BOS descriptors with endpoint companions, speed-aware EP0/CDC/MSC buffer sizes (same pattern as cdc_msc) - Lengthen the CH569 SuperSpeed-training fallback timeout to 1 s per phase: training from a host port settled in another connection state can exceed the previous 0.5 s window Measured on HydraUSB3 v1 at 5 Gbps (NUMP=1): MSC sequential read 70-79 MB/s, write 55 MB/s via dd direct IO - about 3.5x the USB2 high-speed fallback figures on the same setup. Burst support (CFG_TUD_WCH_USB30_MAX_BURST > 1) remains the main headroom. Co-Authored-By: Claude Fable 5 <[email protected]>
2026-06-29docs: add build-doc tooling and a README for every examplehathach
Documentation tooling: - Add the `build-doc` skill and `tools/build_doc.py` wrapper for local Sphinx builds (clean / -W / open). - Enable Markdown (MyST) in conf.py and auto-collect examples/{device,host,dual}/*/README.md into a 3-level Examples nav (Examples > Device/Host/Dual > example), noting each page's source location and normalizing headings to a single H1. - Remove the stale `.claude/commands/build-doc.md`; point the AGENTS.md Documentation section at the skill. Example docs: - Add a README.md for every device/host/dual example: what it does, USB interface table, notable tusb_config.h settings, generic CMake + Make build steps, and how to try it. - Fold each *_freertos variant into its base README, noting the FreeRTOS source path and any RTOS-specific behavior. Generated docs/examples/ output is git-ignored. Builds clean with `sphinx-build -W`. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
2026-05-23tweak examplesHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-04-28fix warning, change hil jlink for feather nrf52840hathach
2026-04-26shrink cdc_msc_throughput MSC buffer for FS targetshathach
CFG_TUD_MSC_EP_BUFSIZE: 4096 → (HS ? 4096 : 1024). Keep the big buffer for HS where it actually amortises CBW overhead at iperf-class throughput; FS peaks around ~830 kBps so 1 KB is plenty and the example now fits on small-RAM MCUs (lpc11/13, samd11, kinetis_kl, stm32f0/l0, stm32f1, etc.). Also dedupe CDC_TX_BUFSIZE = CDC_RX_BUFSIZE. Drops the previously-needed skip.txt — verified builds locally on lpcxpresso1347, cynthion_d11, lpcxpresso11u37/u68, stm32f072disco/eval, frdm_kl25z, stm32l052dap52. Co-Authored-By: Claude Opus 4.7 (1M context) <[email protected]>
2026-04-26skip cdc_msc_throughput on small-RAM MCUshathach
The example uses 4 KB MSC bulk buffer + 2-4 KB CDC buffers to push USB throughput, which overflows on lpcxpresso1347 (RamUsb2) and cynthion_d11. Skip the same MCU set as net_lwip_webserver — these targets don't have the RAM headroom to benefit from throughput tuning anyway. Co-Authored-By: Claude Opus 4.7 (1M context) <[email protected]>
2026-04-23add cdc msc throughput examplehathach