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Cortex-M0/M0+, the WCH RISC-V parts and MAX3266x have no usable DWT cycle
counter, so their family.c provides SEGGER_SYSVIEW_X_GetTimestamp() from a
free-running hardware timer: a 32-bit general-purpose timer on ST parts
(sysview_stm32_tim2.h), SysTick-extended sources on the M0 families, the
core's SysTick-equivalent on WCH with the documented ordered read of the
split count registers (sysview_wch_timestamp.h), and a TMR on MAX3266x
(sysview_max32_tmr.h).
max32666fthr's DWT implements only watchpoint comparators (DWT_CTRL.NOCYCCNT=1
read live; UG6971 documents no DWT/trace at all), so SystemView's ARMv7-M
default read 0xE0001004 as a frozen 0 and every duration decoded as zero. The
TMR runs at 48 MHz (f_PCLK = f_SYS_CLK/2; Continuous mode, CMP=0xFFFFFFFF,
prescaler 1 - UG6971 15.2 guarantees TMRn_CNT readable while counting); TMR0
by default - present on every MAX32 part, unused by the examples, FreeRTOS
ticks on SysTick - overridable with -DSYSVIEW_MAX32_TMR=n. The family builds
SystemView with SEGGER_SYSVIEW_CORE_OTHER and sets CFG_TUSB_SYSVIEW_TIMESTAMP_BSP,
a tusb_sysview.c opt-in for ARMv7-M parts without CYCCNT where the BSP also
reports the rate via SEGGER_SYSVIEW_X_GetTimestampFreq(); the fixed-1MHz
microsecond contract is unreachable on a powers-of-two-only prescaler.
SEGGER_SYSVIEW_X_GetInterruptId() gains the ICSR.VECTACTIVE read for
CORE_OTHER builds. MAX32650/32690 use different GCR clock-gate names and stay
unported. Measured on the rig: seven host-timed 1.000 s gaps at
1.00044-1.00091 (median +0.05%).
stm32f0 refuses to configure SYSVIEW for stm32f070xb at CMake time: that
variant has no TIM2 at all, and the alternative was an undefined-reference
link error with no hint.
The shared hw/bsp/sysview_*.h join ci_select rule 16's hw/bsp file list
(cross-family build files, compiled only under -DSYSVIEW which no CI leg
enables), mirrored in the spec's rule table, so master's classification
guard resolves them on both axes.
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family_support.cmake/.mk translate -DSYSVIEW=<level> (CMake) / SYSVIEW=<level>
(Make) into CFG_TUD_SYSVIEW/CFG_TUH_SYSVIEW, pull in lib/SystemView sources
and the RTT/SystemView include paths, and refuse levels the family cannot
honour.
The lpc11/13/15/17/40/43 families declare SYSVIEW_RAM_BASE_DEFAULT
0x10000000: their SRAM does not start at the Cortex-M-canonical 0x20000000,
and the recorder needs the real base to find the RTT control block.
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IAR is only supported with CMake. Remove all IAR-specific references
from the Make build system including toolchain files, SRC_S_IAR,
LD_FILE_IAR variables, and IAR toolchain detection.
Also fix GET_SECTOR_COUNT truncation in msc_file_explorer and
broken formatting in stm32f7 board_uart_write.
Co-Authored-By: Claude Opus 4.6 (1M context) <[email protected]>
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across all families
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# Conflicts:
- hw/bsp/lpc17/family.cmake
- hw/bsp/lpc40/family.cmake
- hw/bsp/lpc55/family.cmake
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move it to family_configure_common()
also move startup and linker from board target to actual exe
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with zephyr
- change tinyusb CMakeLists.txt to function tinyusb_target_add() instead of defining tinyusb lib target
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* change concurrency group to ${{ github.workflow }}-${{ github.ref }}
* use argparse for build.py hil_test.py, remove the need to install click
* move ci win/mac to build_cmake.yml
* rename build_family.yml to build_util.yml
* build_util.yml support esp32
* integrate build-espressif into build.yml
* build.py support make with --board option
* add get_deps action
* update hil test to reuse action
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change tuh_int_handler() to take in_isr as optional parameter (default =
true)
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