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path: root/hw/bsp/ra/family.c
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2026-07-24address #3787 reviews: bsp fixes, script hardening, board-note accuracyhathach
Bot findings (Copilot/Codex): no-op board_trace_pinmux stubs for lpcxpresso18s37/43s67 (TRACE_ETM otherwise broke their build), SAME70 ID_PIOD clock enable, capture-script duplicate BeforeTargetConnect on the RA references, profile-script support for --no-timestamps itraces. Deep review (whole branch): same70_xplained board row + caveat restored, stale pico2 72 MHz claim corrected to the shipped 48, explicit SetTracePortWidth(4) in the three references that relied on Ozone's default, coverage-cell guard, median-based SysTick calibration, dead session flag removed, stale RA8M1 divider comment fixed (0x02 = /4 is the validated chip max) and the debugger guard indented. EVKB bench findings: only R1884/D3 remains open (D1/D2 meter-verified); RT1176 trace width is 1 or 4 only - J-Link arms the CSSYS TPIU and its own sampler at 4-bit for any width>=2 request; a powered MCU-Link USB breaks the external probe even with JP4 shorted.
2026-07-24ra: TRACE_ETM for ra6m5_ek and ra8m1_ekhathach
Generic TRCKCR setup gated on DHCSR.C_DEBUGEN (a standalone-boot TRCKCR write wedges the chip un-attachable until power-cycle), two-step write per the hardware manual. ra6m5_ek: div-4 (25 MHz pin) - div-2 is dead on this board at every width/timing; J9 must be closed. ra8m1_ek: chip-max 120 MHz TRCLK / 60 MHz pin via the committed JLinkScript whose empty OnTraceStart defers the trace clock to firmware (J-Link's from-reset enable steps the clock mid-stream at the FSP MOCO-to-PLL switch); ReadIntoTraceCache covers runtime ROM execution. J9 closed on both EKs - open = SWD contention up to apparent bricks.
2026-04-04make board_uart_read()/write() return -1 when unimplemented for consistency ↵hathach
across all families
2026-02-28replace board_millis() with tusb_time_millis_api()hathach
2025-11-25bsp: Disable SysTick ISR if FreeRTOS is enabledZixun LI
2024-12-27embed metadata to family.c and board.h to generate supported boards dochathach
2024-12-13update build for ra8m1: usbfs work, but usbhs not working just yet. Probably ↵hathach
missing configuration or clock setup
2024-12-12rasc ra2a1_ek, but usb does not seem to work. Note fsp.ld need extra 0x100 ↵hathach
byte for ROM registers to work.
2024-12-12used pin generated by raschathach
2024-10-10add new tusb_int_handler(rhport, in_isr) as common irq handlerhathach
update tusb_init() to take rhport and role, defined as macro with optional argument for backward compatible
2024-07-19add ra4m1 ek for hil testhathach
2024-04-10support ra2a1 pipe numbering, fix ra2a1 ek led/button. Though usb not ↵hathach
enumerated yet, probably due to bsp/clock setup
2023-11-15add ra2a1 ekhathach
also make some other changes
2023-09-27change hcd_int_handler(rhport, in_isr) signature: add in_isrhathach
change tuh_int_handler() to take in_isr as optional parameter (default = true)
2023-08-04Merge branch 'master' into enhance-bsphathach
2023-08-03more board_api.h renamehathach
2023-08-01fix build with -fltohathach
2023-07-31enable USBMC for uno r4, add board_init_after_tusb() APIhathach
add BOARD_UPPERCASE for board detection
2023-07-31enable_irq since uno bootloader can disable it. systick triggered, however ↵hathach
usb still not work with uno
2023-07-07correct setting trace clockhathach
2023-07-06add rusb2_module_start(), more update for multiple ports for dcd rusb2hathach
2023-07-05usb hs work with ra 6m5 ekhathach
2023-07-04update fsp to version 4.5, correct RA BSP. Fix ETM Trace with 6m5 by ↵hathach
lowering PLL to 128Mhz.
2023-07-03add jlinkscript for detect rtthathach
2023-07-03Merge branch 'master' into renesas_ra_hs_rebasedhathach
2023-07-03wrap up ra updatehathach
2023-07-03move files aroundhathach
2023-07-02add etm trace for 6m5hathach
2023-07-01update linkerhathach
2023-07-01rework ra buildhathach