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H5 hangs its debug AP if trace CoreSight is touched unclocked (recover =
power-cycle): the reference's AfterTargetConnect clocks the DBGMCU trace
domain but defers IOEN to firmware, or the mid-boot clock switch desyncs
the decoder. Stock solder bridges make the CN5 path marginal: validated
config is 100 MHz core, width 1, +5 ns (board.h selects the reduced clock
for TRACE_ETM builds); width 4 / 250 MHz retest waits on SB removal.
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Signed-off-by: HiFiPhile <[email protected]>
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stm32h533nucleo
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Implemented changes suggested in the review:
- restored original name of SystemClock_Config() function
- some GPIO clocks are only enabled if macros are defined
- moved GPIO clocks init back to family.c
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- added support for STM32H503RB on H503RB-NUCLEO board
- modified H5 family.c file to allow portability between H503 and H565/H573
- redefined USB_DRD_BASE to USB_DRD_FS_BASE if STM32H503xx is used
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Tested on Windows with IAR and gcc toolchain ( via cubeide) Tested only with audio examples, but sould be ok for other examples Cmake pacthed : but not tested Linux build : not tested Added a temporary workaround in make file to support H5 HAL repo ( ARMCC_VERSION=0)
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