| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-11-02 | grouping stm32L4 family in bsp | hathach | |
| 2021-11-02 | add fix for stm32l4 (version 3.10a) which generate transfer complete when ↵ | hathach | |
| setup recieved and control out data complete | |||
| 2021-03-18 | add example specific DEPS_SUBMODULES | hathach | |
| 2021-03-17 | spaces | hathach | |
| 2021-03-17 | explicitly add dcd source file without vendor/family | hathach | |
| 2021-03-05 | update DEPS_SUBMODULES to optimize ci | hathach | |
| 2021-03-04 | rename FAMILY_SUBMODULES to DEPS_SUBMODULES | hathach | |
| 2021-03-04 | merge no-family example build | hathach | |
| specify FAMILY_SUBMODULES for all boards | |||
| 2021-01-26 | change output filename to BOARD-Directory | hathach | |
| 2020-10-30 | use cmsis 5 for all stm32 | hathach | |
| 2020-10-30 | add more stm mcu | hathach | |
| 2020-10-30 | l4 use offical st driver repo | hathach | |
| 2020-10-08 | clean up jlink default interface | hathach | |
| 2020-05-06 | stm32l476disco: Fix system clock setup | Jerzy Kasenberg | |
| Code suggested that PLL with MSI is used resulting in 80MHz clock. When in fact PLL was not configured and system clock was left at MSI 48MHz. This happens because PLL configuration requires that SysTick interrupt has interrupt priority level configured correctly. As it seems ST code intentionally setups variable uwTickPrio to invalid value and later when it is not setup by user code configuration of oscillator will fail before PLL is configured. This simple changes systick priority to some valid value that allows clock to use PLL. | |||
| 2020-05-06 | stm32l476disco: fix uninitialized filed usage | Jerzy Kasenberg | |
| Field PLLState was not initialized in RCC_OscInitStruct.PLL in function SystemClock_Config(). Value is used in HAL_RCC_OscConfig() regardless of oscillator. In lucky case value would be 0 RCC_PLL_NONE and nothing would happen. If value was incorrect following line would end up in assert: assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); If value was valid but no RCC_PLL_NONE pll could be configured with some other random values. Setting PLLState to RCC_PLL_NONE eliminates potential problem. | |||
| 2020-04-17 | mass rename tud/dcd_irq_handler to tud/dcd_init_handler | hathach | |
| 2020-04-08 | move irq for stm32 synopsys | hathach | |
| 2020-03-26 | Modify include of HAL, and remove CMSIS clock configuration code, and ↵ | Nathan Conrad | |
| implement UART for STM32F407Disco | |||
| 2019-12-12 | Merge pull request #234 from hathach/stm32f4-blackpill | Ha Thach | |
| move VBUS sense out of dcd_synosys to bsp | |||
| 2019-12-11 | close #204 define HSE_VALUE in _hal_conf instead of board.mk | hathach | |
| 2019-12-11 | move VBUS sense out of dcd_synosys to bsp | hathach | |
| 2019-11-20 | move -flto to board.mk | hathach | |
| current board that doesn work with flto is spresense and mimxrt10xx (due to xip image_vector_table is optimized out). | |||
| 2019-10-24 | fix missing board uart read/write() | hathach | |
| 2019-10-03 | couldn't get 32L4 running with crystal less mode | hathach | |
| 2019-09-13 | adding stm32l4 support, board test run with stm32l476disco, usb doens't work yet | hathach | |
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index : tinyusb.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
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