| Age | Commit message (Collapse) | Author |
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Add support for stm32u5a5 (highspeed with built-in femtoPHY)
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get passed otg clock reset
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to make sure it is valid
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dwc2 core stuck at reset
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tested working with sam d21 and d51, not tested with nrf52, seem not
working with esp32
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revert change in hcd.h
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change tuh_int_handler() to take in_isr as optional parameter (default =
true)
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bit of issue
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add -Wno-error=format for espressif
wrap up cdc_msc_hid_freertos
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'MAX3421_HOST=1' must be added as part of make/cmake command
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update ci cmake
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- also add usbh_defer_func()
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