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HWFIFO access-mode refactor and stride-aware FIFO fixes across FSDEV/RUSB2/MUSB
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Co-authored-by: Copilot <[email protected]>
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Co-authored-by: Copilot <[email protected]>
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read/write
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rusb use custom write
enable all hil test for ra4m1
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duplicated packet write/read for fsdev
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Enable D-Cache unless we're compiling for the M4 core of a dual-core H7 mcu by directly testing CORE_CM4
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: Zixun LI <[email protected]>
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Signed-off-by: Zhihong Chen <[email protected]>
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of bool. help to simplify parsing configuration
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Signed-off-by: Zixun LI <[email protected]>
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CFG_TUSB_EDPT_STREAM_NO_FIFO_ENABLED
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vendor_write_flush() and write_available() only available when CFG_TUD_VENDOR_TX_BUFSIZE > 0
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CFG_TUD_VENDOR_RX_BUFSIZE = 0
update vendor device to omit ep buf when dedicated hwfifo is supported
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