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2021-01-08fix cihathach
2021-01-08use dcd_event_bus_reset() with speed to replace bus_signalhathach
2021-01-08another renamehathach
2021-01-08remove inline for update_grxfsizhathach
2021-01-08more minor workhathach
2021-01-08minor clean up following pr581hathach
2021-01-04Correct function declarationReinhard Panhuber
2021-01-04Minor corrections for PRReinhard Panhuber
- externerlize code into functions - correct comments
2021-01-04Remove too verbose commentReinhard Panhuber
2021-01-03Clean upReinhard Panhuber
2021-01-03Rework USB FIFO allocation scheme and allow RX FIFO size reductionReinhard Panhuber
2020-11-27fix cihathach
2020-11-27add bus suspend & resume support for esp32s2hathach
2020-10-24Move into if statementJacob Potter
2020-10-24CR feedback: compare CFG_TUSB_RHPORT1_MODE instead of using new macroJacob Potter
2020-10-18Allow use of internal FS PHY on OTG_HS interfaceJacob Potter
Some ST parts (like STM32F74xxx / STM32F75xxx) allow the USB_OTG_HS core to be used with either an external high-speed ULPI PHY or an internal full-speed-only (12mbps) PHY. Currently the code assumes than an ULPI PHY is used unless the chip has an internal high-speed PHY (`#if defined(USB_HS_PHYC)`), with no provision to use the internal FS PHY.
2020-10-11Merge pull request #520 from salkinium/feature/misc_enhancementsHa Thach
STM32F3 IRQ remap option and some minor improvements
2020-10-10Merge pull request #521 from PanRe/uac2Ha Thach
Uac2
2020-10-10Dynamically check STM32F3 IRQ remap optionNiklas Hauser
2020-10-09Revert dcd_alloc_mem_for_conf() but keep changes from @kasjer for ISO EPReinhard Panhuber
Add tud_audio_set_itf_close_EP_cb()
2020-10-06stm32: fix ISTR and CTR_RX/TX race conditionsGavin Li
2020-09-28Fix minor issue.Reinhard Panhuber
- Change set_EP0_max_pkt_size() to set_EP0_max_pkt_size(void).
2020-09-28Cleanup for PR.Reinhard Panhuber
2020-09-28synopsys: Fix odd/even frame handling for ISOJerzy Kasenberg
Current implementation always sets odd/even bit for ISO transactions. This is a good strategy only if interval is 1. For ISO endpoint interval in (micro)frames is computed as 2^(interval-1), which means that odd/frame number should stay same for interval values > 1. With this change only when interval is 1 odd/even bit is modified.
2020-09-28synopsys: Remove compilation warning in dcd_edpt_closeJerzy Kasenberg
dcd_edpt_close() no longer modifies FIFO distribution. Code that that was commented out is removed along with variables that are no longer used. FIFO distribution among endpoints is handled upfront and does not need to be modified in open and close endpoint functions.
2020-09-28synopsys: Fix fifo allocation schemaJerzy Kasenberg
Recommended FIFO allocation schema includes 2 maximum endpoint sizes. Comment suggested that this is the case while it would work according to this description only in checked endpoints were ascending sizes. Also two same size endpoints would be counted as one. That is fixed by way sz is filled. Calculation used too much modulo operation while single division was enough to account for odd FIFO sizes. Extra space that is evenly distributed between Bulk and control endpoints was incorrectly calculated it could prevent allocation of ISO endpoint FIFO when bulk endpoints existed with smaller endpoint numbers. Minimum endpoint FIFO size is 16 32bit words, FIFO space requirement is now observed.
2020-09-06Start of sampling works.Reinhard Panhuber
2020-09-04Merge remote-tracking branch 'upstream/master' into uac2Reinhard Panhuber
2020-08-20Fix formatting, get rid of all tabs.Reinhard Panhuber
2020-08-19Commit before sharing.Reinhard Panhuber
Setup a test example - UNTESTED! Missing: Start transmitting audio data in set_interface.
2020-08-16Merge remote-tracking branch 'upstream/master' into uac2Reinhard Panhuber
Conflicts: src/device/usbd.c src/device/usbd.h src/portable/st/synopsys/dcd_synopsys.c
2020-08-16Add EP close. Fix bug in set_interface within audio.Reinhard Panhuber
2020-08-14Add dcd_edpt_close() to synopsysJerzy Kasenberg
Endpoint close was implemented only in one driver so far. This function is needed for interfaces with several alternate settings. The way FIFO is allocated in dcd_edpt_open() allows to correctly close only one IN endpoint (the one that was opened last).
2020-08-12Fix synopsys fifo flush during stallJerzy Kasenberg
Wrong FIFO was flushed in dcd_edpt_stall(). (epnum - 1) should only be used when accessing DIEPTXF registers. For DIEPCTL and GRSTCTL epnum is correct index.
2020-08-05Merge pull request #476 from kasjer/kasjer/fix-synopsys-fix-iso-frame-bitHa Thach
Fix synopsys odd/even frame bit for IN ISO endpoints
2020-08-04Fix synopsys odd/even frame bit for IN ISO endpointsJerzy Kasenberg
For ISO endpoint driver has to specify when data is to be transmitted (odd or even frame). Currently code was not updating this bit resulting in data being sent every other frame. If interval was 1ms full data packed was sent every 2ms, and ZLP was sent in between.
2020-08-03Implement dynamic FIFO RAM allocation according to configuration desc.Reinhard Panhuber
2020-08-01enable pull-up in dcd_init() instead of usbdhathach
2020-07-31Fix synopsys size check for ISO endpointJerzy Kasenberg
Constraint was incorrect for ISO endpoint as stated in TODO.
2020-07-29fix nested extern declaration of 'SystemCoreClock' [-Werror=nested-externs]hathach
2020-07-27Implement dynamic reallocation of RX and TX fifos for EP0.Reinhard Panhuber
Tested with EP0 size 8/16/32/64.
2020-07-26add 'set_EP0_max_pkt_size(...)' and fix EP0 size to 64 bytes after resetReinhard Panhuber
2020-07-08change REDUCE_SPEED=0/1 to explicitly SPEED=high/fullhathach
update readme, boards.md to add link to new stm boards
2020-07-05Merge pull request #457 from UweBonnes/add-stm-hsHa Thach
Add stm hs
2020-07-03STM32/OTG_HS: Allow OTG_HS port to run at FS speed.Uwe Bonnes
Add "REDUCE_SPEED=1" to the compile options.
2020-07-03update per reviewhathach
2020-07-03fix NVIC disable typohathach
2020-07-02correct HSE_VALUE in hal_confhathach
- although it is define in CFLAGS, it is worth to correct to be consistent with other build - extract set_speed()
2020-07-02change default port some stm bsphathach
- f769disco default port is highspeed port1 - remove PORT0 on stlink since the board only populated HS connector
2020-07-02clean uphathach
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