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(DM=DP=0) in addition to dwc2's dctrl
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- all dwc2 ip seems to support test mode in both fs/hs -> remove TUP_USBIP_DWC2_TEST_MODE
- remove dcd_check_test_mode_support(), all should be supported
- move enum tusb_feature_test_mode_t to tusb_types.h
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highspeed
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- switch unit test back to gcc, since path to clang conflict on local setup (x86 and arm)
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If this interrupt ever hits it will result in an infinite interrupt
loop as it is never cleared.
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get passed otg clock reset
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dwc2 core stuck at reset
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Fixes #1737
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This is needed in order to always be able to fit a packet in the fifo.
Writing to the fifo is done from an interrupts that fires when the fifo is
half-empty, so the fifo must be twice the packet size.
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SOF is not a flag of the GOTGINT register but of the GINTSTS register. Therefore the flag must be written in the GINTSTS register instead of the GOTGINT register to clear the interrupt.
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-Wuninitialized, -Wunused, -Wredundant-decls
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