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path: root/src/portable/synopsys
AgeCommit message (Collapse)Author
2024-05-29Use correct specs.Tinic Uro
2024-05-29Cleaner approach.Tinic Uro
2024-05-29Make it compile for STM32U545.Tinic Uro
2024-05-24wch usbfs/usbhs need to specify which driver to use. for v307 default to ↵hathach
highspeed
2024-05-13Remove dead code.HiFiPhile
2024-05-13Adjust logic.HiFiPhile
2024-05-13Merge branch 'master' into test-mode-supportHiFiPhile
2024-04-25Disable EPs correctly to clear incomplete transfer.HiFiPhile
2024-04-23port clang stm32: f1, f2, f3hathach
2024-04-19- clang h743 build and run cdc_msc okhathach
- switch unit test back to gcc, since path to clang conflict on local setup (x86 and arm)
2024-04-16minor update to sofhathach
2024-04-11separate flush tx/rx fifohathach
2024-04-10flush fifo in dcd_edpt_close_all()HiFiPhile
2024-04-10set txfifo empty level to complete and change back fifo tx to normal sizehathach
2024-04-09Merge branch 'master' into dwc2-interruptshathach
2024-04-05dwc2: remove fifo free code.HiFiPhile
2024-03-31minor clean uphathach
2024-03-30Code refactor.HiFiPhile
2024-03-30Flush FIFO on bus reset.HiFiPhile
2024-03-30dwc2: add endpoint allocation support.HiFiPhile
2024-02-19Opt-out for USB Test-ModeRocky04
2024-02-15Do not enable the Mode mismatch interrupt source, it is not clearedChris Desjardins
If this interrupt ever hits it will result in an infinite interrupt loop as it is never cleared.
2024-02-01Merge branch 'master' into src/portable/synopsys/dwc2/fix_sof_int_handlingHiFiPhile
2024-01-15Merge branch 'master' into test-mode-supportRocky04
2024-01-15Change to control complete cbRocky04
2024-01-15Add DWC2 Test Mode SUpportRocky04
2024-01-10Disable ULPI clock during sleep on stm32f7 when using internal phyAlex Voinea
2023-11-22fix h7 running on fullspeed phy has issue with WFI if not disable ULPI clockhathach
2023-11-22add spec version to dwc2 infohathach
2023-11-19Fix CIHiFiPhile
2023-11-19Add dwc2 info of F429.HiFiPhile
2023-10-31dwc2 flush tx,rx fifo in dcd_init()hathach
2023-10-31usb on u5a5 hs work well with correct VBVALEXTOEN/VBVALOVAL sethathach
2023-10-31minor clean uphathach
2023-10-30minor space format dwc2 driverhathach
2023-10-30addd dwc2_info.py/md update stm32u5a5 board clock & power configure, able to ↵hathach
get passed otg clock reset
2023-10-18adding nulceo stm32u5a5, fix clock configure issuehathach
dwc2 core stuck at reset
2023-09-26Added support for USB2 HS peripheral (with integrated HS PHY) on STM32U59x chipsbac
2023-05-04Use double-sized fifo only for IN endpointsMichiel van Leeuwen
2023-04-28Check correct interrupt flagMichiel van Leeuwen
Fixes #1737
2023-04-28dwc2: configure fifo size to be twice the max_sizeMichiel van Leeuwen
This is needed in order to always be able to fit a packet in the fifo. Writing to the fifo is done from an interrupts that fires when the fifo is half-empty, so the fifo must be twice the packet size.
2023-02-27synopsys/dwc2: fix SOF interrupt handlingGunar Schorcht
SOF is not a flag of the GOTGINT register but of the GINTSTS register. Therefore the flag must be written in the GINTSTS register instead of the GOTGINT register to clear the interrupt.
2023-01-11dwc2: fix IAR warnings.MasterPhi
2022-12-04Fix typosBastien Nocera
2022-10-13Add support for STM32U5 mcuLynnL4
2022-09-13re-added code in pr 1438 to fix compile with h7 with 1 usb otghathach
2022-06-29fix buid_board.py scripthathach
2022-06-24add more warning option, also fix -Wconversion with rp2040hathach
-Wuninitialized, -Wunused, -Wredundant-decls
2022-06-06more ci fixhathach
2022-06-04update all dwc2 ports to support new dynamic controller supporthathach
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