| Age | Commit message (Collapse) | Author |
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If this interrupt ever hits it will result in an infinite interrupt
loop as it is never cleared.
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get passed otg clock reset
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dwc2 core stuck at reset
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Fixes #1737
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This is needed in order to always be able to fit a packet in the fifo.
Writing to the fifo is done from an interrupts that fires when the fifo is
half-empty, so the fifo must be twice the packet size.
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SOF is not a flag of the GOTGINT register but of the GINTSTS register. Therefore the flag must be written in the GINTSTS register instead of the GOTGINT register to clear the interrupt.
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-Wuninitialized, -Wunused, -Wredundant-decls
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overwrite grstctl on edpt_disable
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Update dwc2_stm32.h
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Add missing #endif
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Support STM32H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
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