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2026-06-11Fix stm32f723disco host/cdc_msc_hid HIL: UART RX starvation + DWC2 DMA ↵Ha Thach
split-IN NAK storm (#3677) Fix stm32f723disco host HIL: UART RX starvation + DWC2 split bulk NAK/XactErr handling (#3677) stm32f7 BSP — UART RX starvation - The host console USART shared interrupt priority with the USB OTG ISR, so a long OTG interrupt could starve RXNE and drop received bytes. Raise the USART RX IRQ above OTG_FS/OTG_HS in both the bare-metal and FreeRTOS init paths, guarded by #ifdef UART_ID so boards without a UART console keep the default OTG priority. dwc2 host — split NAK/XactErr handling - Slave mode: a persistently-NAKing split bulk/control IN poll re-armed the start-split immediately, storming the ISR and starving task context. Throttle by disabling the channel and re-arming on the resulting halt (no frame deferral). - Buffer-DMA mode: a pure split bulk-OUT NAK was unhandled, leaving the channel halted and stalling the transfer — the dominant cause of CDC echo truncation. Handle it by rewinding the buffer pointers and retrying the start-split (Programming Guide v4.20a 5.1.4.2). - Buffer-DMA mode: a split bulk-OUT XactErr was retried immediately, exhausting HCD_XFER_ERROR_MAX before the transient cleared. Throttle via channel_disable + re-arm to give the hub TT a recovery gap, mirroring slave mode. - All three are scoped to split transfers (hcsplt.split_en); non-split NAK/XactErr keep the core-handled / immediate-retry behavior. The OUT XactErr throttle also excludes periodic split, where channel_disable() is a no-op and would wedge the channel. The nak_disabled flag is generalized to retry_disabled and honors xfer->closing so an endpoint close during a throttled retry tears down cleanly. Verified on stm32f723disco HIL (slave + CFG_TUH_DWC2_DMA_ENABLE): host/cdc_msc_hid, msc_file_explorer, and device_info all pass on both variants; DMA CDC echo went from ~15-25% raw failure to 10/10 clean.
2026-06-04dwc2: cleanup setup_packet pointer cast (review feedback)hathach
Cast DOEPDMA0 through uintptr_t and use sizeof(tusb_control_request_t) instead of the magic constant 8, matching project convention. Add a reference to Programming Guide v4.20a 9.1.2.1 for the DOEPDMAn-8 rule. Addresses Copilot review comment; no functional change. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
2026-06-04Update setup buffer size definition based on DMA configurationhathach
2026-06-04Merge branch 'master' into dwc2_postfixhathach
2026-06-03dwc2: address Copilot review (comment grammar/typo, tinyusb.json f407 dedup)hathach
Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
2026-06-03dwc2: remove investigation debug logginghathach
Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
2026-06-03dwc2: submit setup packet on SETUP_DONE and drop spurious EP0 RX_COMPLETE on ↵hathach
core v3.10a (STM32L476) DWC2 core rev 3.10a pushes an extra EP0 RX_COMPLETE (RXFLVL PKTSTS 0x3) that is not a real OUT data completion, in two cases flagged on DOEPINT: - STPKTRX (Setup Packet Received): between SETUP_RX and SETUP_DONE - STSPHSRX (Status Phase Received, control write): after the OUT data stage when the host starts the IN status phase
2026-06-02dcd/dwc2: fix back-to-back SETUP reception in DMA modeHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-05-29dwc2: process IN EP before OUTHiFiPhile
To avoid STATUS IN completion of previous control transfer treated as next DATA IN when IRQ latency is high. Signed-off-by: HiFiPhile <[email protected]>
2026-05-29dwc2: move OUT transfer management into RXFLVL IRQHiFiPhile
- GRXSTSP register has internal FIFO, receiving events won't mix up (STATUS OUT & next SETUP) - Improve efficiency, remove 2nd IRQ overhead Signed-off-by: HiFiPhile <[email protected]>
2026-05-27dwc2: fix EP0 DMA setup race conditionHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-05-27dwc2: simplify EP0 ZLP handlingHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-05-22Merge remote-tracking branch 'tinyusb/master' into fix/Dwc2Stm32U5HiFiPhile
2026-05-22dwc2: handle EP0 status OUT in RXFLVL interruptHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-05-12dcd/dwc2: fix ISO IN endpoint become disabled after incomplete transferHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-05-09dwc2: guard EP0 status completion with armed ZLP stateAlex-Schaefer
Track when an EP0 OUT zero-length transfer is actually armed and require that state before synthesizing a status-stage completion ahead of a co-reported SETUP event. This preserves the validated status-before-SETUP ordering fix while avoiding stale zero-length state from producing spurious EP0 OUT completions.
2026-05-09dwc2: preserve EP0 status completion before SETUPAlex-Schaefer
On STM32 DWC2, SETUP phase done and EP0 OUT transfer complete can be reported together. Processing SETUP first can overwrite control state before the previous zero-length OUT status stage is acknowledged, which causes DFU DNLOAD/GETSTATUS traffic to lose the status ACK and stall. Queue the EP0 OUT zero-length transfer completion before queuing the SETUP event when the endpoint has no pending OUT data and total_len is zero. This keeps TinyUSB control-transfer ordering intact for the combined interrupt case.
2026-05-04hcd/dwc2: fix txfifo full checkHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-04-23Merge pull request #3601 from hathach/fix-conversion-warningsHa Thach
Fix some -Wconversion warnings
2026-04-22Add ESP32-S31 as a supported MCU in TinyUSBigor.masar
2026-04-17fix some Wconversion warningshathach
2026-04-10Update src/portable/synopsys/dwc2/dcd_dwc2.cHa Thach
Co-authored-by: Copilot <[email protected]>
2026-04-10clean uphathach
2026-04-10fix DWC2 FIFO depth values for STM32 familieshathach
2026-04-10add dwc2_clock_init() to have nrf54 initial sequence. currently stub for ↵hathach
other ports. add board_uart_read() for nrf
2026-04-09rename ep_fifo_size (bytes) to otg_dfifo_depth (words)hathach
2026-04-09Add initial board support for nRF54LM20 DKgab-k
2026-03-30Revert unintentional removal of commentgab-k
2026-03-30Revert back to simple edpt_disable()/edpt_activate() inside ↵gab-k
dcd_edpt_iso_activate(), Clear active EP bit in edpt_disable()
2026-03-28Clear DOEPCTL_USBAEP instead of setting DOEPCTL = DOEPCTL_SNAKgab-k
2026-03-28Minimize changes in ISO OUT reset fixgab-k
2026-03-28Add nrf54lm20 dwc2 infogab-k
2026-03-28fix ISO OUT stale state on alt-setting switch with different MPSgab-k
2026-03-05add hs_phy_type parameter to dwc2_phy_deinit for selective PHY ↵hathach
deinitialization across all MCUs
2026-03-04add PHY deinitialization support for DWC2 driver across all MCUshathach
2026-03-03Merge branch 'master' into dwc2_deinithathach
2026-03-02fix(dcd/dwc2): Do not modify FS PHY registers on HS PHY ESP32-P4Tomas Rezucha
2026-02-27cleanupHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-02-27Merge remote-tracking branch 'tinyusb/master' into dwc2_deinitHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-02-23refactor: streamline high-speed PHY detection and configuration in DWC2 driverhathach
2026-02-23refactor: improve high-speed PHY handling and FIFO configuration in DWC2 driverhathach
2026-02-22Apply suggestions from code reviewZixun LI
Co-authored-by: Copilot <[email protected]>
2026-02-22refactor speed checkHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-02-21check femtoPHY speedHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-02-21fix ciHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-02-20refactor config optionHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-02-19Fix a couple indentationsCédric Berger
2026-02-19Introduce TUH_CFGID_PHY_SPEED configure optionCédric Berger
2026-02-19Better variable/function namesCédric Berger
2026-02-13use CFG_TUD_CONFIGURE_DWC2_DEFAULT to make it easier to add more valuehathach